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bf40a686 DW |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * GPL LICENSE SUMMARY | |
6 | * | |
7 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms and conditions of the GNU General Public License, | |
11 | * version 2, as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., | |
20 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
21 | * | |
22 | * The full GNU General Public License is included in this distribution in | |
23 | * the file called "COPYING". | |
24 | * | |
25 | * BSD LICENSE | |
26 | * | |
27 | * Copyright(c) 2004-2009 Intel Corporation. All rights reserved. | |
28 | * | |
29 | * Redistribution and use in source and binary forms, with or without | |
30 | * modification, are permitted provided that the following conditions are met: | |
31 | * | |
32 | * * Redistributions of source code must retain the above copyright | |
33 | * notice, this list of conditions and the following disclaimer. | |
34 | * * Redistributions in binary form must reproduce the above copyright | |
35 | * notice, this list of conditions and the following disclaimer in | |
36 | * the documentation and/or other materials provided with the | |
37 | * distribution. | |
38 | * * Neither the name of Intel Corporation nor the names of its | |
39 | * contributors may be used to endorse or promote products derived | |
40 | * from this software without specific prior written permission. | |
41 | * | |
42 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
43 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
44 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
45 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | |
46 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
47 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
48 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
49 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
50 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
51 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
52 | * POSSIBILITY OF SUCH DAMAGE. | |
53 | */ | |
54 | ||
55 | /* | |
56 | * Support routines for v3+ hardware | |
57 | */ | |
58 | ||
59 | #include <linux/pci.h> | |
60 | #include <linux/dmaengine.h> | |
61 | #include <linux/dma-mapping.h> | |
62 | #include "registers.h" | |
63 | #include "hw.h" | |
64 | #include "dma.h" | |
65 | #include "dma_v2.h" | |
66 | ||
b094ad3b DW |
67 | /* ioat hardware assumes at least two sources for raid operations */ |
68 | #define src_cnt_to_sw(x) ((x) + 2) | |
69 | #define src_cnt_to_hw(x) ((x) - 2) | |
70 | ||
71 | /* provide a lookup table for setting the source address in the base or | |
d69d235b | 72 | * extended descriptor of an xor or pq descriptor |
b094ad3b DW |
73 | */ |
74 | static const u8 xor_idx_to_desc __read_mostly = 0xd0; | |
75 | static const u8 xor_idx_to_field[] __read_mostly = { 1, 4, 5, 6, 7, 0, 1, 2 }; | |
d69d235b DW |
76 | static const u8 pq_idx_to_desc __read_mostly = 0xf8; |
77 | static const u8 pq_idx_to_field[] __read_mostly = { 1, 4, 5, 0, 1, 2, 4, 5 }; | |
b094ad3b DW |
78 | |
79 | static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx) | |
80 | { | |
81 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; | |
82 | ||
83 | return raw->field[xor_idx_to_field[idx]]; | |
84 | } | |
85 | ||
86 | static void xor_set_src(struct ioat_raw_descriptor *descs[2], | |
87 | dma_addr_t addr, u32 offset, int idx) | |
88 | { | |
89 | struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; | |
90 | ||
91 | raw->field[xor_idx_to_field[idx]] = addr + offset; | |
92 | } | |
93 | ||
d69d235b DW |
94 | static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx) |
95 | { | |
96 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; | |
97 | ||
98 | return raw->field[pq_idx_to_field[idx]]; | |
99 | } | |
100 | ||
101 | static void pq_set_src(struct ioat_raw_descriptor *descs[2], | |
102 | dma_addr_t addr, u32 offset, u8 coef, int idx) | |
103 | { | |
104 | struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0]; | |
105 | struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; | |
106 | ||
107 | raw->field[pq_idx_to_field[idx]] = addr + offset; | |
108 | pq->coef[idx] = coef; | |
109 | } | |
110 | ||
bf40a686 | 111 | static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat, |
b094ad3b | 112 | struct ioat_ring_ent *desc, int idx) |
bf40a686 DW |
113 | { |
114 | struct ioat_chan_common *chan = &ioat->base; | |
115 | struct pci_dev *pdev = chan->device->pdev; | |
116 | size_t len = desc->len; | |
117 | size_t offset = len - desc->hw->size; | |
118 | struct dma_async_tx_descriptor *tx = &desc->txd; | |
119 | enum dma_ctrl_flags flags = tx->flags; | |
120 | ||
121 | switch (desc->hw->ctl_f.op) { | |
122 | case IOAT_OP_COPY: | |
58c8649e DW |
123 | if (!desc->hw->ctl_f.null) /* skip 'interrupt' ops */ |
124 | ioat_dma_unmap(chan, flags, len, desc->hw); | |
bf40a686 DW |
125 | break; |
126 | case IOAT_OP_FILL: { | |
127 | struct ioat_fill_descriptor *hw = desc->fill; | |
128 | ||
129 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) | |
130 | ioat_unmap(pdev, hw->dst_addr - offset, len, | |
131 | PCI_DMA_FROMDEVICE, flags, 1); | |
132 | break; | |
133 | } | |
b094ad3b DW |
134 | case IOAT_OP_XOR_VAL: |
135 | case IOAT_OP_XOR: { | |
136 | struct ioat_xor_descriptor *xor = desc->xor; | |
137 | struct ioat_ring_ent *ext; | |
138 | struct ioat_xor_ext_descriptor *xor_ex = NULL; | |
139 | int src_cnt = src_cnt_to_sw(xor->ctl_f.src_cnt); | |
140 | struct ioat_raw_descriptor *descs[2]; | |
141 | int i; | |
142 | ||
143 | if (src_cnt > 5) { | |
144 | ext = ioat2_get_ring_ent(ioat, idx + 1); | |
145 | xor_ex = ext->xor_ex; | |
146 | } | |
147 | ||
148 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
149 | descs[0] = (struct ioat_raw_descriptor *) xor; | |
150 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; | |
151 | for (i = 0; i < src_cnt; i++) { | |
152 | dma_addr_t src = xor_get_src(descs, i); | |
153 | ||
154 | ioat_unmap(pdev, src - offset, len, | |
155 | PCI_DMA_TODEVICE, flags, 0); | |
156 | } | |
157 | ||
158 | /* dest is a source in xor validate operations */ | |
159 | if (xor->ctl_f.op == IOAT_OP_XOR_VAL) { | |
160 | ioat_unmap(pdev, xor->dst_addr - offset, len, | |
161 | PCI_DMA_TODEVICE, flags, 1); | |
162 | break; | |
163 | } | |
164 | } | |
165 | ||
166 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) | |
167 | ioat_unmap(pdev, xor->dst_addr - offset, len, | |
168 | PCI_DMA_FROMDEVICE, flags, 1); | |
169 | break; | |
170 | } | |
d69d235b DW |
171 | case IOAT_OP_PQ_VAL: |
172 | case IOAT_OP_PQ: { | |
173 | struct ioat_pq_descriptor *pq = desc->pq; | |
174 | struct ioat_ring_ent *ext; | |
175 | struct ioat_pq_ext_descriptor *pq_ex = NULL; | |
176 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); | |
177 | struct ioat_raw_descriptor *descs[2]; | |
178 | int i; | |
179 | ||
180 | if (src_cnt > 3) { | |
181 | ext = ioat2_get_ring_ent(ioat, idx + 1); | |
182 | pq_ex = ext->pq_ex; | |
183 | } | |
184 | ||
185 | /* in the 'continue' case don't unmap the dests as sources */ | |
186 | if (dmaf_p_disabled_continue(flags)) | |
187 | src_cnt--; | |
188 | else if (dmaf_continue(flags)) | |
189 | src_cnt -= 3; | |
190 | ||
191 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) { | |
192 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
193 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; | |
194 | for (i = 0; i < src_cnt; i++) { | |
195 | dma_addr_t src = pq_get_src(descs, i); | |
196 | ||
197 | ioat_unmap(pdev, src - offset, len, | |
198 | PCI_DMA_TODEVICE, flags, 0); | |
199 | } | |
200 | ||
201 | /* the dests are sources in pq validate operations */ | |
202 | if (pq->ctl_f.op == IOAT_OP_XOR_VAL) { | |
203 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
204 | ioat_unmap(pdev, pq->p_addr - offset, | |
205 | len, PCI_DMA_TODEVICE, flags, 0); | |
206 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
207 | ioat_unmap(pdev, pq->q_addr - offset, | |
208 | len, PCI_DMA_TODEVICE, flags, 0); | |
209 | break; | |
210 | } | |
211 | } | |
212 | ||
213 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) { | |
214 | if (!(flags & DMA_PREP_PQ_DISABLE_P)) | |
215 | ioat_unmap(pdev, pq->p_addr - offset, len, | |
216 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
217 | if (!(flags & DMA_PREP_PQ_DISABLE_Q)) | |
218 | ioat_unmap(pdev, pq->q_addr - offset, len, | |
219 | PCI_DMA_BIDIRECTIONAL, flags, 1); | |
220 | } | |
221 | break; | |
222 | } | |
bf40a686 DW |
223 | default: |
224 | dev_err(&pdev->dev, "%s: unknown op type: %#x\n", | |
225 | __func__, desc->hw->ctl_f.op); | |
226 | } | |
227 | } | |
228 | ||
b094ad3b DW |
229 | static bool desc_has_ext(struct ioat_ring_ent *desc) |
230 | { | |
231 | struct ioat_dma_descriptor *hw = desc->hw; | |
232 | ||
233 | if (hw->ctl_f.op == IOAT_OP_XOR || | |
234 | hw->ctl_f.op == IOAT_OP_XOR_VAL) { | |
235 | struct ioat_xor_descriptor *xor = desc->xor; | |
bf40a686 | 236 | |
b094ad3b DW |
237 | if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5) |
238 | return true; | |
d69d235b DW |
239 | } else if (hw->ctl_f.op == IOAT_OP_PQ || |
240 | hw->ctl_f.op == IOAT_OP_PQ_VAL) { | |
241 | struct ioat_pq_descriptor *pq = desc->pq; | |
242 | ||
243 | if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3) | |
244 | return true; | |
b094ad3b DW |
245 | } |
246 | ||
247 | return false; | |
248 | } | |
249 | ||
250 | /** | |
251 | * __cleanup - reclaim used descriptors | |
252 | * @ioat: channel (ring) to clean | |
253 | * | |
254 | * The difference from the dma_v2.c __cleanup() is that this routine | |
255 | * handles extended descriptors and dma-unmapping raid operations. | |
256 | */ | |
bf40a686 DW |
257 | static void __cleanup(struct ioat2_dma_chan *ioat, unsigned long phys_complete) |
258 | { | |
259 | struct ioat_chan_common *chan = &ioat->base; | |
260 | struct ioat_ring_ent *desc; | |
261 | bool seen_current = false; | |
262 | u16 active; | |
263 | int i; | |
264 | ||
265 | dev_dbg(to_dev(chan), "%s: head: %#x tail: %#x issued: %#x\n", | |
266 | __func__, ioat->head, ioat->tail, ioat->issued); | |
267 | ||
268 | active = ioat2_ring_active(ioat); | |
269 | for (i = 0; i < active && !seen_current; i++) { | |
270 | struct dma_async_tx_descriptor *tx; | |
271 | ||
272 | prefetch(ioat2_get_ring_ent(ioat, ioat->tail + i + 1)); | |
273 | desc = ioat2_get_ring_ent(ioat, ioat->tail + i); | |
274 | dump_desc_dbg(ioat, desc); | |
275 | tx = &desc->txd; | |
276 | if (tx->cookie) { | |
277 | chan->completed_cookie = tx->cookie; | |
b094ad3b | 278 | ioat3_dma_unmap(ioat, desc, ioat->tail + i); |
bf40a686 DW |
279 | tx->cookie = 0; |
280 | if (tx->callback) { | |
281 | tx->callback(tx->callback_param); | |
282 | tx->callback = NULL; | |
283 | } | |
284 | } | |
285 | ||
286 | if (tx->phys == phys_complete) | |
287 | seen_current = true; | |
b094ad3b DW |
288 | |
289 | /* skip extended descriptors */ | |
290 | if (desc_has_ext(desc)) { | |
291 | BUG_ON(i + 1 >= active); | |
292 | i++; | |
293 | } | |
bf40a686 DW |
294 | } |
295 | ioat->tail += i; | |
aa75db00 | 296 | BUG_ON(active && !seen_current); /* no active descs have written a completion? */ |
bf40a686 | 297 | chan->last_completion = phys_complete; |
b9cc9869 DW |
298 | |
299 | active = ioat2_ring_active(ioat); | |
300 | if (active == 0) { | |
bf40a686 DW |
301 | dev_dbg(to_dev(chan), "%s: cancel completion timeout\n", |
302 | __func__); | |
303 | clear_bit(IOAT_COMPLETION_PENDING, &chan->state); | |
304 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
305 | } | |
b9cc9869 DW |
306 | /* 5 microsecond delay per pending descriptor */ |
307 | writew(min((5 * active), IOAT_INTRDELAY_MASK), | |
308 | chan->device->reg_base + IOAT_INTRDELAY_OFFSET); | |
bf40a686 DW |
309 | } |
310 | ||
b9cc9869 DW |
311 | /* try to cleanup, but yield (via spin_trylock) to incoming submissions |
312 | * with the expectation that we will immediately poll again shortly | |
313 | */ | |
314 | static void ioat3_cleanup_poll(struct ioat2_dma_chan *ioat) | |
bf40a686 DW |
315 | { |
316 | struct ioat_chan_common *chan = &ioat->base; | |
317 | unsigned long phys_complete; | |
318 | ||
319 | prefetch(chan->completion); | |
320 | ||
321 | if (!spin_trylock_bh(&chan->cleanup_lock)) | |
322 | return; | |
323 | ||
324 | if (!ioat_cleanup_preamble(chan, &phys_complete)) { | |
325 | spin_unlock_bh(&chan->cleanup_lock); | |
326 | return; | |
327 | } | |
328 | ||
329 | if (!spin_trylock_bh(&ioat->ring_lock)) { | |
330 | spin_unlock_bh(&chan->cleanup_lock); | |
331 | return; | |
332 | } | |
333 | ||
334 | __cleanup(ioat, phys_complete); | |
335 | ||
336 | spin_unlock_bh(&ioat->ring_lock); | |
337 | spin_unlock_bh(&chan->cleanup_lock); | |
338 | } | |
339 | ||
b9cc9869 DW |
340 | /* run cleanup now because we already delayed the interrupt via INTRDELAY */ |
341 | static void ioat3_cleanup_sync(struct ioat2_dma_chan *ioat) | |
342 | { | |
343 | struct ioat_chan_common *chan = &ioat->base; | |
344 | unsigned long phys_complete; | |
345 | ||
346 | prefetch(chan->completion); | |
347 | ||
348 | spin_lock_bh(&chan->cleanup_lock); | |
349 | if (!ioat_cleanup_preamble(chan, &phys_complete)) { | |
350 | spin_unlock_bh(&chan->cleanup_lock); | |
351 | return; | |
352 | } | |
353 | spin_lock_bh(&ioat->ring_lock); | |
354 | ||
355 | __cleanup(ioat, phys_complete); | |
356 | ||
357 | spin_unlock_bh(&ioat->ring_lock); | |
358 | spin_unlock_bh(&chan->cleanup_lock); | |
359 | } | |
360 | ||
bf40a686 DW |
361 | static void ioat3_cleanup_tasklet(unsigned long data) |
362 | { | |
363 | struct ioat2_dma_chan *ioat = (void *) data; | |
364 | ||
b9cc9869 | 365 | ioat3_cleanup_sync(ioat); |
773d9e2d | 366 | writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET); |
bf40a686 DW |
367 | } |
368 | ||
369 | static void ioat3_restart_channel(struct ioat2_dma_chan *ioat) | |
370 | { | |
371 | struct ioat_chan_common *chan = &ioat->base; | |
372 | unsigned long phys_complete; | |
bf40a686 | 373 | |
b372ec2d | 374 | ioat2_quiesce(chan, 0); |
bf40a686 DW |
375 | if (ioat_cleanup_preamble(chan, &phys_complete)) |
376 | __cleanup(ioat, phys_complete); | |
377 | ||
378 | __ioat2_restart_chan(ioat); | |
379 | } | |
380 | ||
381 | static void ioat3_timer_event(unsigned long data) | |
382 | { | |
383 | struct ioat2_dma_chan *ioat = (void *) data; | |
384 | struct ioat_chan_common *chan = &ioat->base; | |
385 | ||
386 | spin_lock_bh(&chan->cleanup_lock); | |
387 | if (test_bit(IOAT_COMPLETION_PENDING, &chan->state)) { | |
388 | unsigned long phys_complete; | |
389 | u64 status; | |
390 | ||
391 | spin_lock_bh(&ioat->ring_lock); | |
392 | status = ioat_chansts(chan); | |
393 | ||
394 | /* when halted due to errors check for channel | |
395 | * programming errors before advancing the completion state | |
396 | */ | |
397 | if (is_ioat_halted(status)) { | |
398 | u32 chanerr; | |
399 | ||
400 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
b57014de DW |
401 | dev_err(to_dev(chan), "%s: Channel halted (%x)\n", |
402 | __func__, chanerr); | |
bf40a686 DW |
403 | BUG_ON(is_ioat_bug(chanerr)); |
404 | } | |
405 | ||
406 | /* if we haven't made progress and we have already | |
407 | * acknowledged a pending completion once, then be more | |
408 | * forceful with a restart | |
409 | */ | |
410 | if (ioat_cleanup_preamble(chan, &phys_complete)) | |
411 | __cleanup(ioat, phys_complete); | |
412 | else if (test_bit(IOAT_COMPLETION_ACK, &chan->state)) | |
413 | ioat3_restart_channel(ioat); | |
414 | else { | |
415 | set_bit(IOAT_COMPLETION_ACK, &chan->state); | |
416 | mod_timer(&chan->timer, jiffies + COMPLETION_TIMEOUT); | |
417 | } | |
418 | spin_unlock_bh(&ioat->ring_lock); | |
419 | } else { | |
420 | u16 active; | |
421 | ||
422 | /* if the ring is idle, empty, and oversized try to step | |
423 | * down the size | |
424 | */ | |
425 | spin_lock_bh(&ioat->ring_lock); | |
426 | active = ioat2_ring_active(ioat); | |
427 | if (active == 0 && ioat->alloc_order > ioat_get_alloc_order()) | |
428 | reshape_ring(ioat, ioat->alloc_order-1); | |
429 | spin_unlock_bh(&ioat->ring_lock); | |
430 | ||
431 | /* keep shrinking until we get back to our minimum | |
432 | * default size | |
433 | */ | |
434 | if (ioat->alloc_order > ioat_get_alloc_order()) | |
435 | mod_timer(&chan->timer, jiffies + IDLE_TIMEOUT); | |
436 | } | |
437 | spin_unlock_bh(&chan->cleanup_lock); | |
438 | } | |
439 | ||
440 | static enum dma_status | |
441 | ioat3_is_complete(struct dma_chan *c, dma_cookie_t cookie, | |
442 | dma_cookie_t *done, dma_cookie_t *used) | |
443 | { | |
444 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
445 | ||
446 | if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS) | |
447 | return DMA_SUCCESS; | |
448 | ||
b9cc9869 | 449 | ioat3_cleanup_poll(ioat); |
bf40a686 DW |
450 | |
451 | return ioat_is_complete(c, cookie, done, used); | |
452 | } | |
453 | ||
454 | static struct dma_async_tx_descriptor * | |
455 | ioat3_prep_memset_lock(struct dma_chan *c, dma_addr_t dest, int value, | |
456 | size_t len, unsigned long flags) | |
457 | { | |
458 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
459 | struct ioat_ring_ent *desc; | |
460 | size_t total_len = len; | |
461 | struct ioat_fill_descriptor *fill; | |
462 | int num_descs; | |
463 | u64 src_data = (0x0101010101010101ULL) * (value & 0xff); | |
464 | u16 idx; | |
465 | int i; | |
466 | ||
467 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
468 | if (likely(num_descs) && | |
469 | ioat2_alloc_and_lock(&idx, ioat, num_descs) == 0) | |
470 | /* pass */; | |
471 | else | |
472 | return NULL; | |
cdef57db DW |
473 | i = 0; |
474 | do { | |
bf40a686 DW |
475 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); |
476 | ||
477 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
478 | fill = desc->fill; | |
479 | ||
480 | fill->size = xfer_size; | |
481 | fill->src_data = src_data; | |
482 | fill->dst_addr = dest; | |
483 | fill->ctl = 0; | |
484 | fill->ctl_f.op = IOAT_OP_FILL; | |
485 | ||
486 | len -= xfer_size; | |
487 | dest += xfer_size; | |
488 | dump_desc_dbg(ioat, desc); | |
cdef57db | 489 | } while (++i < num_descs); |
bf40a686 DW |
490 | |
491 | desc->txd.flags = flags; | |
492 | desc->len = total_len; | |
493 | fill->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
494 | fill->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
495 | fill->ctl_f.compl_write = 1; | |
496 | dump_desc_dbg(ioat, desc); | |
497 | ||
498 | /* we leave the channel locked to ensure in order submission */ | |
499 | return &desc->txd; | |
500 | } | |
501 | ||
b094ad3b DW |
502 | static struct dma_async_tx_descriptor * |
503 | __ioat3_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result, | |
504 | dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt, | |
505 | size_t len, unsigned long flags) | |
506 | { | |
507 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
508 | struct ioat_ring_ent *compl_desc; | |
509 | struct ioat_ring_ent *desc; | |
510 | struct ioat_ring_ent *ext; | |
511 | size_t total_len = len; | |
512 | struct ioat_xor_descriptor *xor; | |
513 | struct ioat_xor_ext_descriptor *xor_ex = NULL; | |
514 | struct ioat_dma_descriptor *hw; | |
515 | u32 offset = 0; | |
516 | int num_descs; | |
517 | int with_ext; | |
518 | int i; | |
519 | u16 idx; | |
520 | u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR; | |
521 | ||
522 | BUG_ON(src_cnt < 2); | |
523 | ||
524 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
525 | /* we need 2x the number of descriptors to cover greater than 5 | |
526 | * sources | |
527 | */ | |
528 | if (src_cnt > 5) { | |
529 | with_ext = 1; | |
530 | num_descs *= 2; | |
531 | } else | |
532 | with_ext = 0; | |
533 | ||
534 | /* completion writes from the raid engine may pass completion | |
535 | * writes from the legacy engine, so we need one extra null | |
536 | * (legacy) descriptor to ensure all completion writes arrive in | |
537 | * order. | |
538 | */ | |
539 | if (likely(num_descs) && | |
540 | ioat2_alloc_and_lock(&idx, ioat, num_descs+1) == 0) | |
541 | /* pass */; | |
542 | else | |
543 | return NULL; | |
cdef57db DW |
544 | i = 0; |
545 | do { | |
b094ad3b DW |
546 | struct ioat_raw_descriptor *descs[2]; |
547 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
548 | int s; | |
549 | ||
550 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
551 | xor = desc->xor; | |
552 | ||
553 | /* save a branch by unconditionally retrieving the | |
554 | * extended descriptor xor_set_src() knows to not write | |
555 | * to it in the single descriptor case | |
556 | */ | |
557 | ext = ioat2_get_ring_ent(ioat, idx + i + 1); | |
558 | xor_ex = ext->xor_ex; | |
559 | ||
560 | descs[0] = (struct ioat_raw_descriptor *) xor; | |
561 | descs[1] = (struct ioat_raw_descriptor *) xor_ex; | |
562 | for (s = 0; s < src_cnt; s++) | |
563 | xor_set_src(descs, src[s], offset, s); | |
564 | xor->size = xfer_size; | |
565 | xor->dst_addr = dest + offset; | |
566 | xor->ctl = 0; | |
567 | xor->ctl_f.op = op; | |
568 | xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt); | |
569 | ||
570 | len -= xfer_size; | |
571 | offset += xfer_size; | |
572 | dump_desc_dbg(ioat, desc); | |
cdef57db | 573 | } while ((i += 1 + with_ext) < num_descs); |
b094ad3b DW |
574 | |
575 | /* last xor descriptor carries the unmap parameters and fence bit */ | |
576 | desc->txd.flags = flags; | |
577 | desc->len = total_len; | |
578 | if (result) | |
579 | desc->result = result; | |
580 | xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
581 | ||
582 | /* completion descriptor carries interrupt bit */ | |
583 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); | |
584 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; | |
585 | hw = compl_desc->hw; | |
586 | hw->ctl = 0; | |
587 | hw->ctl_f.null = 1; | |
588 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
589 | hw->ctl_f.compl_write = 1; | |
590 | hw->size = NULL_DESC_BUFFER_SIZE; | |
591 | dump_desc_dbg(ioat, compl_desc); | |
592 | ||
593 | /* we leave the channel locked to ensure in order submission */ | |
49954c15 | 594 | return &compl_desc->txd; |
b094ad3b DW |
595 | } |
596 | ||
597 | static struct dma_async_tx_descriptor * | |
598 | ioat3_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, | |
599 | unsigned int src_cnt, size_t len, unsigned long flags) | |
600 | { | |
601 | return __ioat3_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags); | |
602 | } | |
603 | ||
604 | struct dma_async_tx_descriptor * | |
605 | ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, | |
606 | unsigned int src_cnt, size_t len, | |
607 | enum sum_check_flags *result, unsigned long flags) | |
608 | { | |
609 | /* the cleanup routine only sets bits on validate failure, it | |
610 | * does not clear bits on validate success... so clear it here | |
611 | */ | |
612 | *result = 0; | |
613 | ||
614 | return __ioat3_prep_xor_lock(chan, result, src[0], &src[1], | |
615 | src_cnt - 1, len, flags); | |
616 | } | |
617 | ||
d69d235b DW |
618 | static void |
619 | dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext) | |
620 | { | |
621 | struct device *dev = to_dev(&ioat->base); | |
622 | struct ioat_pq_descriptor *pq = desc->pq; | |
623 | struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL; | |
624 | struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex }; | |
625 | int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); | |
626 | int i; | |
627 | ||
628 | dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x" | |
629 | " sz: %#x ctl: %#x (op: %d int: %d compl: %d pq: '%s%s' src_cnt: %d)\n", | |
630 | desc_id(desc), (unsigned long long) desc->txd.phys, | |
631 | (unsigned long long) (pq_ex ? pq_ex->next : pq->next), | |
632 | desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en, | |
633 | pq->ctl_f.compl_write, | |
634 | pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q", | |
635 | pq->ctl_f.src_cnt); | |
636 | for (i = 0; i < src_cnt; i++) | |
637 | dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i, | |
638 | (unsigned long long) pq_get_src(descs, i), pq->coef[i]); | |
639 | dev_dbg(dev, "\tP: %#llx\n", pq->p_addr); | |
640 | dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr); | |
641 | } | |
642 | ||
643 | static struct dma_async_tx_descriptor * | |
644 | __ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result, | |
645 | const dma_addr_t *dst, const dma_addr_t *src, | |
646 | unsigned int src_cnt, const unsigned char *scf, | |
647 | size_t len, unsigned long flags) | |
648 | { | |
649 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
650 | struct ioat_chan_common *chan = &ioat->base; | |
651 | struct ioat_ring_ent *compl_desc; | |
652 | struct ioat_ring_ent *desc; | |
653 | struct ioat_ring_ent *ext; | |
654 | size_t total_len = len; | |
655 | struct ioat_pq_descriptor *pq; | |
656 | struct ioat_pq_ext_descriptor *pq_ex = NULL; | |
657 | struct ioat_dma_descriptor *hw; | |
658 | u32 offset = 0; | |
659 | int num_descs; | |
660 | int with_ext; | |
661 | int i, s; | |
662 | u16 idx; | |
663 | u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ; | |
664 | ||
665 | dev_dbg(to_dev(chan), "%s\n", __func__); | |
666 | /* the engine requires at least two sources (we provide | |
667 | * at least 1 implied source in the DMA_PREP_CONTINUE case) | |
668 | */ | |
669 | BUG_ON(src_cnt + dmaf_continue(flags) < 2); | |
670 | ||
671 | num_descs = ioat2_xferlen_to_descs(ioat, len); | |
672 | /* we need 2x the number of descriptors to cover greater than 3 | |
cd78809f DW |
673 | * sources (we need 1 extra source in the q-only continuation |
674 | * case and 3 extra sources in the p+q continuation case. | |
d69d235b | 675 | */ |
cd78809f DW |
676 | if (src_cnt + dmaf_p_disabled_continue(flags) > 3 || |
677 | (dmaf_continue(flags) && !dmaf_p_disabled_continue(flags))) { | |
d69d235b DW |
678 | with_ext = 1; |
679 | num_descs *= 2; | |
680 | } else | |
681 | with_ext = 0; | |
682 | ||
683 | /* completion writes from the raid engine may pass completion | |
684 | * writes from the legacy engine, so we need one extra null | |
685 | * (legacy) descriptor to ensure all completion writes arrive in | |
686 | * order. | |
687 | */ | |
688 | if (likely(num_descs) && | |
689 | ioat2_alloc_and_lock(&idx, ioat, num_descs+1) == 0) | |
690 | /* pass */; | |
691 | else | |
692 | return NULL; | |
cdef57db DW |
693 | i = 0; |
694 | do { | |
d69d235b DW |
695 | struct ioat_raw_descriptor *descs[2]; |
696 | size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log); | |
697 | ||
698 | desc = ioat2_get_ring_ent(ioat, idx + i); | |
699 | pq = desc->pq; | |
700 | ||
701 | /* save a branch by unconditionally retrieving the | |
702 | * extended descriptor pq_set_src() knows to not write | |
703 | * to it in the single descriptor case | |
704 | */ | |
705 | ext = ioat2_get_ring_ent(ioat, idx + i + with_ext); | |
706 | pq_ex = ext->pq_ex; | |
707 | ||
708 | descs[0] = (struct ioat_raw_descriptor *) pq; | |
709 | descs[1] = (struct ioat_raw_descriptor *) pq_ex; | |
710 | ||
711 | for (s = 0; s < src_cnt; s++) | |
712 | pq_set_src(descs, src[s], offset, scf[s], s); | |
713 | ||
714 | /* see the comment for dma_maxpq in include/linux/dmaengine.h */ | |
715 | if (dmaf_p_disabled_continue(flags)) | |
716 | pq_set_src(descs, dst[1], offset, 1, s++); | |
717 | else if (dmaf_continue(flags)) { | |
718 | pq_set_src(descs, dst[0], offset, 0, s++); | |
719 | pq_set_src(descs, dst[1], offset, 1, s++); | |
720 | pq_set_src(descs, dst[1], offset, 0, s++); | |
721 | } | |
722 | pq->size = xfer_size; | |
723 | pq->p_addr = dst[0] + offset; | |
724 | pq->q_addr = dst[1] + offset; | |
725 | pq->ctl = 0; | |
726 | pq->ctl_f.op = op; | |
727 | pq->ctl_f.src_cnt = src_cnt_to_hw(s); | |
728 | pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P); | |
729 | pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q); | |
730 | ||
731 | len -= xfer_size; | |
732 | offset += xfer_size; | |
cdef57db | 733 | } while ((i += 1 + with_ext) < num_descs); |
d69d235b DW |
734 | |
735 | /* last pq descriptor carries the unmap parameters and fence bit */ | |
736 | desc->txd.flags = flags; | |
737 | desc->len = total_len; | |
738 | if (result) | |
739 | desc->result = result; | |
740 | pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
741 | dump_pq_desc_dbg(ioat, desc, ext); | |
742 | ||
743 | /* completion descriptor carries interrupt bit */ | |
744 | compl_desc = ioat2_get_ring_ent(ioat, idx + i); | |
745 | compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; | |
746 | hw = compl_desc->hw; | |
747 | hw->ctl = 0; | |
748 | hw->ctl_f.null = 1; | |
749 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
750 | hw->ctl_f.compl_write = 1; | |
751 | hw->size = NULL_DESC_BUFFER_SIZE; | |
752 | dump_desc_dbg(ioat, compl_desc); | |
753 | ||
754 | /* we leave the channel locked to ensure in order submission */ | |
49954c15 | 755 | return &compl_desc->txd; |
d69d235b DW |
756 | } |
757 | ||
758 | static struct dma_async_tx_descriptor * | |
759 | ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, | |
760 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
761 | unsigned long flags) | |
762 | { | |
de581b65 DW |
763 | /* specify valid address for disabled result */ |
764 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
765 | dst[0] = dst[1]; | |
766 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
767 | dst[1] = dst[0]; | |
768 | ||
d69d235b DW |
769 | /* handle the single source multiply case from the raid6 |
770 | * recovery path | |
771 | */ | |
de581b65 | 772 | if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) { |
d69d235b DW |
773 | dma_addr_t single_source[2]; |
774 | unsigned char single_source_coef[2]; | |
775 | ||
776 | BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q); | |
777 | single_source[0] = src[0]; | |
778 | single_source[1] = src[0]; | |
779 | single_source_coef[0] = scf[0]; | |
780 | single_source_coef[1] = 0; | |
781 | ||
782 | return __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2, | |
783 | single_source_coef, len, flags); | |
784 | } else | |
785 | return __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt, scf, | |
786 | len, flags); | |
787 | } | |
788 | ||
789 | struct dma_async_tx_descriptor * | |
790 | ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, | |
791 | unsigned int src_cnt, const unsigned char *scf, size_t len, | |
792 | enum sum_check_flags *pqres, unsigned long flags) | |
793 | { | |
de581b65 DW |
794 | /* specify valid address for disabled result */ |
795 | if (flags & DMA_PREP_PQ_DISABLE_P) | |
796 | pq[0] = pq[1]; | |
797 | if (flags & DMA_PREP_PQ_DISABLE_Q) | |
798 | pq[1] = pq[0]; | |
799 | ||
d69d235b DW |
800 | /* the cleanup routine only sets bits on validate failure, it |
801 | * does not clear bits on validate success... so clear it here | |
802 | */ | |
803 | *pqres = 0; | |
804 | ||
805 | return __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len, | |
806 | flags); | |
807 | } | |
808 | ||
ae786624 DW |
809 | static struct dma_async_tx_descriptor * |
810 | ioat3_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, | |
811 | unsigned int src_cnt, size_t len, unsigned long flags) | |
812 | { | |
813 | unsigned char scf[src_cnt]; | |
814 | dma_addr_t pq[2]; | |
815 | ||
816 | memset(scf, 0, src_cnt); | |
ae786624 | 817 | pq[0] = dst; |
de581b65 DW |
818 | flags |= DMA_PREP_PQ_DISABLE_Q; |
819 | pq[1] = dst; /* specify valid address for disabled result */ | |
ae786624 DW |
820 | |
821 | return __ioat3_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len, | |
822 | flags); | |
823 | } | |
824 | ||
825 | struct dma_async_tx_descriptor * | |
826 | ioat3_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, | |
827 | unsigned int src_cnt, size_t len, | |
828 | enum sum_check_flags *result, unsigned long flags) | |
829 | { | |
830 | unsigned char scf[src_cnt]; | |
831 | dma_addr_t pq[2]; | |
832 | ||
833 | /* the cleanup routine only sets bits on validate failure, it | |
834 | * does not clear bits on validate success... so clear it here | |
835 | */ | |
836 | *result = 0; | |
837 | ||
838 | memset(scf, 0, src_cnt); | |
ae786624 | 839 | pq[0] = src[0]; |
de581b65 DW |
840 | flags |= DMA_PREP_PQ_DISABLE_Q; |
841 | pq[1] = pq[0]; /* specify valid address for disabled result */ | |
ae786624 DW |
842 | |
843 | return __ioat3_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1, scf, | |
844 | len, flags); | |
845 | } | |
846 | ||
58c8649e DW |
847 | static struct dma_async_tx_descriptor * |
848 | ioat3_prep_interrupt_lock(struct dma_chan *c, unsigned long flags) | |
849 | { | |
850 | struct ioat2_dma_chan *ioat = to_ioat2_chan(c); | |
851 | struct ioat_ring_ent *desc; | |
852 | struct ioat_dma_descriptor *hw; | |
853 | u16 idx; | |
854 | ||
855 | if (ioat2_alloc_and_lock(&idx, ioat, 1) == 0) | |
856 | desc = ioat2_get_ring_ent(ioat, idx); | |
857 | else | |
858 | return NULL; | |
859 | ||
860 | hw = desc->hw; | |
861 | hw->ctl = 0; | |
862 | hw->ctl_f.null = 1; | |
863 | hw->ctl_f.int_en = 1; | |
864 | hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE); | |
865 | hw->ctl_f.compl_write = 1; | |
866 | hw->size = NULL_DESC_BUFFER_SIZE; | |
867 | hw->src_addr = 0; | |
868 | hw->dst_addr = 0; | |
869 | ||
870 | desc->txd.flags = flags; | |
871 | desc->len = 1; | |
872 | ||
873 | dump_desc_dbg(ioat, desc); | |
874 | ||
875 | /* we leave the channel locked to ensure in order submission */ | |
876 | return &desc->txd; | |
877 | } | |
878 | ||
9de6fc71 DW |
879 | static void __devinit ioat3_dma_test_callback(void *dma_async_param) |
880 | { | |
881 | struct completion *cmp = dma_async_param; | |
882 | ||
883 | complete(cmp); | |
884 | } | |
885 | ||
886 | #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */ | |
887 | static int __devinit ioat_xor_val_self_test(struct ioatdma_device *device) | |
888 | { | |
889 | int i, src_idx; | |
890 | struct page *dest; | |
891 | struct page *xor_srcs[IOAT_NUM_SRC_TEST]; | |
892 | struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1]; | |
893 | dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1]; | |
894 | dma_addr_t dma_addr, dest_dma; | |
895 | struct dma_async_tx_descriptor *tx; | |
896 | struct dma_chan *dma_chan; | |
897 | dma_cookie_t cookie; | |
898 | u8 cmp_byte = 0; | |
899 | u32 cmp_word; | |
900 | u32 xor_val_result; | |
901 | int err = 0; | |
902 | struct completion cmp; | |
903 | unsigned long tmo; | |
904 | struct device *dev = &device->pdev->dev; | |
905 | struct dma_device *dma = &device->common; | |
906 | ||
907 | dev_dbg(dev, "%s\n", __func__); | |
908 | ||
909 | if (!dma_has_cap(DMA_XOR, dma->cap_mask)) | |
910 | return 0; | |
911 | ||
912 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { | |
913 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); | |
914 | if (!xor_srcs[src_idx]) { | |
915 | while (src_idx--) | |
916 | __free_page(xor_srcs[src_idx]); | |
917 | return -ENOMEM; | |
918 | } | |
919 | } | |
920 | ||
921 | dest = alloc_page(GFP_KERNEL); | |
922 | if (!dest) { | |
923 | while (src_idx--) | |
924 | __free_page(xor_srcs[src_idx]); | |
925 | return -ENOMEM; | |
926 | } | |
927 | ||
928 | /* Fill in src buffers */ | |
929 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) { | |
930 | u8 *ptr = page_address(xor_srcs[src_idx]); | |
931 | for (i = 0; i < PAGE_SIZE; i++) | |
932 | ptr[i] = (1 << src_idx); | |
933 | } | |
934 | ||
935 | for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) | |
936 | cmp_byte ^= (u8) (1 << src_idx); | |
937 | ||
938 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
939 | (cmp_byte << 8) | cmp_byte; | |
940 | ||
941 | memset(page_address(dest), 0, PAGE_SIZE); | |
942 | ||
943 | dma_chan = container_of(dma->channels.next, struct dma_chan, | |
944 | device_node); | |
945 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { | |
946 | err = -ENODEV; | |
947 | goto out; | |
948 | } | |
949 | ||
950 | /* test xor */ | |
951 | dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
952 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
953 | dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE, | |
954 | DMA_TO_DEVICE); | |
955 | tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
956 | IOAT_NUM_SRC_TEST, PAGE_SIZE, | |
957 | DMA_PREP_INTERRUPT); | |
958 | ||
959 | if (!tx) { | |
960 | dev_err(dev, "Self-test xor prep failed\n"); | |
961 | err = -ENODEV; | |
962 | goto free_resources; | |
963 | } | |
964 | ||
965 | async_tx_ack(tx); | |
966 | init_completion(&cmp); | |
967 | tx->callback = ioat3_dma_test_callback; | |
968 | tx->callback_param = &cmp; | |
969 | cookie = tx->tx_submit(tx); | |
970 | if (cookie < 0) { | |
971 | dev_err(dev, "Self-test xor setup failed\n"); | |
972 | err = -ENODEV; | |
973 | goto free_resources; | |
974 | } | |
975 | dma->device_issue_pending(dma_chan); | |
976 | ||
977 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
978 | ||
979 | if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
980 | dev_err(dev, "Self-test xor timed out\n"); | |
981 | err = -ENODEV; | |
982 | goto free_resources; | |
983 | } | |
984 | ||
985 | dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE); | |
986 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
987 | u32 *ptr = page_address(dest); | |
988 | if (ptr[i] != cmp_word) { | |
989 | dev_err(dev, "Self-test xor failed compare\n"); | |
990 | err = -ENODEV; | |
991 | goto free_resources; | |
992 | } | |
993 | } | |
994 | dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_TO_DEVICE); | |
995 | ||
996 | /* skip validate if the capability is not present */ | |
997 | if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) | |
998 | goto free_resources; | |
999 | ||
1000 | /* validate the sources with the destintation page */ | |
1001 | for (i = 0; i < IOAT_NUM_SRC_TEST; i++) | |
1002 | xor_val_srcs[i] = xor_srcs[i]; | |
1003 | xor_val_srcs[i] = dest; | |
1004 | ||
1005 | xor_val_result = 1; | |
1006 | ||
1007 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1008 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, | |
1009 | DMA_TO_DEVICE); | |
1010 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, | |
1011 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, | |
1012 | &xor_val_result, DMA_PREP_INTERRUPT); | |
1013 | if (!tx) { | |
1014 | dev_err(dev, "Self-test zero prep failed\n"); | |
1015 | err = -ENODEV; | |
1016 | goto free_resources; | |
1017 | } | |
1018 | ||
1019 | async_tx_ack(tx); | |
1020 | init_completion(&cmp); | |
1021 | tx->callback = ioat3_dma_test_callback; | |
1022 | tx->callback_param = &cmp; | |
1023 | cookie = tx->tx_submit(tx); | |
1024 | if (cookie < 0) { | |
1025 | dev_err(dev, "Self-test zero setup failed\n"); | |
1026 | err = -ENODEV; | |
1027 | goto free_resources; | |
1028 | } | |
1029 | dma->device_issue_pending(dma_chan); | |
1030 | ||
1031 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1032 | ||
1033 | if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
1034 | dev_err(dev, "Self-test validate timed out\n"); | |
1035 | err = -ENODEV; | |
1036 | goto free_resources; | |
1037 | } | |
1038 | ||
1039 | if (xor_val_result != 0) { | |
1040 | dev_err(dev, "Self-test validate failed compare\n"); | |
1041 | err = -ENODEV; | |
1042 | goto free_resources; | |
1043 | } | |
1044 | ||
1045 | /* skip memset if the capability is not present */ | |
1046 | if (!dma_has_cap(DMA_MEMSET, dma_chan->device->cap_mask)) | |
1047 | goto free_resources; | |
1048 | ||
1049 | /* test memset */ | |
1050 | dma_addr = dma_map_page(dev, dest, 0, | |
1051 | PAGE_SIZE, DMA_FROM_DEVICE); | |
1052 | tx = dma->device_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, | |
1053 | DMA_PREP_INTERRUPT); | |
1054 | if (!tx) { | |
1055 | dev_err(dev, "Self-test memset prep failed\n"); | |
1056 | err = -ENODEV; | |
1057 | goto free_resources; | |
1058 | } | |
1059 | ||
1060 | async_tx_ack(tx); | |
1061 | init_completion(&cmp); | |
1062 | tx->callback = ioat3_dma_test_callback; | |
1063 | tx->callback_param = &cmp; | |
1064 | cookie = tx->tx_submit(tx); | |
1065 | if (cookie < 0) { | |
1066 | dev_err(dev, "Self-test memset setup failed\n"); | |
1067 | err = -ENODEV; | |
1068 | goto free_resources; | |
1069 | } | |
1070 | dma->device_issue_pending(dma_chan); | |
1071 | ||
1072 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1073 | ||
1074 | if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
1075 | dev_err(dev, "Self-test memset timed out\n"); | |
1076 | err = -ENODEV; | |
1077 | goto free_resources; | |
1078 | } | |
1079 | ||
1080 | for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) { | |
1081 | u32 *ptr = page_address(dest); | |
1082 | if (ptr[i]) { | |
1083 | dev_err(dev, "Self-test memset failed compare\n"); | |
1084 | err = -ENODEV; | |
1085 | goto free_resources; | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | /* test for non-zero parity sum */ | |
1090 | xor_val_result = 0; | |
1091 | for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) | |
1092 | dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE, | |
1093 | DMA_TO_DEVICE); | |
1094 | tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs, | |
1095 | IOAT_NUM_SRC_TEST + 1, PAGE_SIZE, | |
1096 | &xor_val_result, DMA_PREP_INTERRUPT); | |
1097 | if (!tx) { | |
1098 | dev_err(dev, "Self-test 2nd zero prep failed\n"); | |
1099 | err = -ENODEV; | |
1100 | goto free_resources; | |
1101 | } | |
1102 | ||
1103 | async_tx_ack(tx); | |
1104 | init_completion(&cmp); | |
1105 | tx->callback = ioat3_dma_test_callback; | |
1106 | tx->callback_param = &cmp; | |
1107 | cookie = tx->tx_submit(tx); | |
1108 | if (cookie < 0) { | |
1109 | dev_err(dev, "Self-test 2nd zero setup failed\n"); | |
1110 | err = -ENODEV; | |
1111 | goto free_resources; | |
1112 | } | |
1113 | dma->device_issue_pending(dma_chan); | |
1114 | ||
1115 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | |
1116 | ||
1117 | if (dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) { | |
1118 | dev_err(dev, "Self-test 2nd validate timed out\n"); | |
1119 | err = -ENODEV; | |
1120 | goto free_resources; | |
1121 | } | |
1122 | ||
1123 | if (xor_val_result != SUM_CHECK_P_RESULT) { | |
1124 | dev_err(dev, "Self-test validate failed compare\n"); | |
1125 | err = -ENODEV; | |
1126 | goto free_resources; | |
1127 | } | |
1128 | ||
1129 | free_resources: | |
1130 | dma->device_free_chan_resources(dma_chan); | |
1131 | out: | |
1132 | src_idx = IOAT_NUM_SRC_TEST; | |
1133 | while (src_idx--) | |
1134 | __free_page(xor_srcs[src_idx]); | |
1135 | __free_page(dest); | |
1136 | return err; | |
1137 | } | |
1138 | ||
1139 | static int __devinit ioat3_dma_self_test(struct ioatdma_device *device) | |
1140 | { | |
1141 | int rc = ioat_dma_self_test(device); | |
1142 | ||
1143 | if (rc) | |
1144 | return rc; | |
1145 | ||
1146 | rc = ioat_xor_val_self_test(device); | |
1147 | if (rc) | |
1148 | return rc; | |
1149 | ||
1150 | return 0; | |
1151 | } | |
1152 | ||
a6d52d70 DW |
1153 | static int ioat3_reset_hw(struct ioat_chan_common *chan) |
1154 | { | |
1155 | /* throw away whatever the channel was doing and get it | |
1156 | * initialized, with ioat3 specific workarounds | |
1157 | */ | |
1158 | struct ioatdma_device *device = chan->device; | |
1159 | struct pci_dev *pdev = device->pdev; | |
1160 | u32 chanerr; | |
1161 | u16 dev_id; | |
1162 | int err; | |
1163 | ||
1164 | ioat2_quiesce(chan, msecs_to_jiffies(100)); | |
1165 | ||
1166 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); | |
1167 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); | |
1168 | ||
1169 | /* -= IOAT ver.3 workarounds =- */ | |
1170 | /* Write CHANERRMSK_INT with 3E07h to mask out the errors | |
1171 | * that can cause stability issues for IOAT ver.3, and clear any | |
1172 | * pending errors | |
1173 | */ | |
1174 | pci_write_config_dword(pdev, IOAT_PCI_CHANERRMASK_INT_OFFSET, 0x3e07); | |
1175 | err = pci_read_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, &chanerr); | |
1176 | if (err) { | |
1177 | dev_err(&pdev->dev, "channel error register unreachable\n"); | |
1178 | return err; | |
1179 | } | |
1180 | pci_write_config_dword(pdev, IOAT_PCI_CHANERR_INT_OFFSET, chanerr); | |
1181 | ||
1182 | /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit | |
1183 | * (workaround for spurious config parity error after restart) | |
1184 | */ | |
1185 | pci_read_config_word(pdev, IOAT_PCI_DEVICE_ID_OFFSET, &dev_id); | |
1186 | if (dev_id == PCI_DEVICE_ID_INTEL_IOAT_TBG0) | |
1187 | pci_write_config_dword(pdev, IOAT_PCI_DMAUNCERRSTS_OFFSET, 0x10); | |
1188 | ||
1189 | return ioat2_reset_sync(chan, msecs_to_jiffies(200)); | |
1190 | } | |
1191 | ||
bf40a686 DW |
1192 | int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca) |
1193 | { | |
1194 | struct pci_dev *pdev = device->pdev; | |
228c4f5c | 1195 | int dca_en = system_has_dca_enabled(pdev); |
bf40a686 DW |
1196 | struct dma_device *dma; |
1197 | struct dma_chan *c; | |
1198 | struct ioat_chan_common *chan; | |
e3232714 | 1199 | bool is_raid_device = false; |
bf40a686 | 1200 | int err; |
bf40a686 DW |
1201 | u32 cap; |
1202 | ||
1203 | device->enumerate_channels = ioat2_enumerate_channels; | |
a6d52d70 | 1204 | device->reset_hw = ioat3_reset_hw; |
9de6fc71 | 1205 | device->self_test = ioat3_dma_self_test; |
bf40a686 DW |
1206 | dma = &device->common; |
1207 | dma->device_prep_dma_memcpy = ioat2_dma_prep_memcpy_lock; | |
1208 | dma->device_issue_pending = ioat2_issue_pending; | |
1209 | dma->device_alloc_chan_resources = ioat2_alloc_chan_resources; | |
1210 | dma->device_free_chan_resources = ioat2_free_chan_resources; | |
58c8649e DW |
1211 | |
1212 | dma_cap_set(DMA_INTERRUPT, dma->cap_mask); | |
1213 | dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock; | |
1214 | ||
bf40a686 | 1215 | cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET); |
228c4f5c DW |
1216 | |
1217 | /* dca is incompatible with raid operations */ | |
1218 | if (dca_en && (cap & (IOAT_CAP_XOR|IOAT_CAP_PQ))) | |
1219 | cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ); | |
1220 | ||
b094ad3b | 1221 | if (cap & IOAT_CAP_XOR) { |
e3232714 | 1222 | is_raid_device = true; |
b094ad3b DW |
1223 | dma->max_xor = 8; |
1224 | dma->xor_align = 2; | |
1225 | ||
1226 | dma_cap_set(DMA_XOR, dma->cap_mask); | |
1227 | dma->device_prep_dma_xor = ioat3_prep_xor; | |
1228 | ||
1229 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); | |
1230 | dma->device_prep_dma_xor_val = ioat3_prep_xor_val; | |
1231 | } | |
d69d235b | 1232 | if (cap & IOAT_CAP_PQ) { |
e3232714 | 1233 | is_raid_device = true; |
d69d235b DW |
1234 | dma_set_maxpq(dma, 8, 0); |
1235 | dma->pq_align = 2; | |
1236 | ||
1237 | dma_cap_set(DMA_PQ, dma->cap_mask); | |
1238 | dma->device_prep_dma_pq = ioat3_prep_pq; | |
1239 | ||
1240 | dma_cap_set(DMA_PQ_VAL, dma->cap_mask); | |
1241 | dma->device_prep_dma_pq_val = ioat3_prep_pq_val; | |
ae786624 DW |
1242 | |
1243 | if (!(cap & IOAT_CAP_XOR)) { | |
1244 | dma->max_xor = 8; | |
1245 | dma->xor_align = 2; | |
1246 | ||
1247 | dma_cap_set(DMA_XOR, dma->cap_mask); | |
1248 | dma->device_prep_dma_xor = ioat3_prep_pqxor; | |
1249 | ||
1250 | dma_cap_set(DMA_XOR_VAL, dma->cap_mask); | |
1251 | dma->device_prep_dma_xor_val = ioat3_prep_pqxor_val; | |
1252 | } | |
d69d235b | 1253 | } |
e3232714 DW |
1254 | if (is_raid_device && (cap & IOAT_CAP_FILL_BLOCK)) { |
1255 | dma_cap_set(DMA_MEMSET, dma->cap_mask); | |
1256 | dma->device_prep_dma_memset = ioat3_prep_memset_lock; | |
1257 | } | |
1258 | ||
1259 | ||
1260 | if (is_raid_device) { | |
1261 | dma->device_is_tx_complete = ioat3_is_complete; | |
1262 | device->cleanup_tasklet = ioat3_cleanup_tasklet; | |
1263 | device->timer_fn = ioat3_timer_event; | |
1264 | } else { | |
1265 | dma->device_is_tx_complete = ioat2_is_complete; | |
1266 | device->cleanup_tasklet = ioat2_cleanup_tasklet; | |
1267 | device->timer_fn = ioat2_timer_event; | |
1268 | } | |
bf40a686 | 1269 | |
7b3cc2b1 DW |
1270 | #ifdef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA |
1271 | dma_cap_clear(DMA_PQ_VAL, dma->cap_mask); | |
1272 | dma->device_prep_dma_pq_val = NULL; | |
1273 | #endif | |
1274 | ||
1275 | #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA | |
1276 | dma_cap_clear(DMA_XOR_VAL, dma->cap_mask); | |
1277 | dma->device_prep_dma_xor_val = NULL; | |
1278 | #endif | |
1279 | ||
bf40a686 DW |
1280 | err = ioat_probe(device); |
1281 | if (err) | |
1282 | return err; | |
1283 | ioat_set_tcp_copy_break(262144); | |
1284 | ||
1285 | list_for_each_entry(c, &dma->channels, device_node) { | |
1286 | chan = to_chan_common(c); | |
1287 | writel(IOAT_DMA_DCA_ANY_CPU, | |
1288 | chan->reg_base + IOAT_DCACTRL_OFFSET); | |
1289 | } | |
1290 | ||
1291 | err = ioat_register(device); | |
1292 | if (err) | |
1293 | return err; | |
5669e31c DW |
1294 | |
1295 | ioat_kobject_add(device, &ioat2_ktype); | |
1296 | ||
bf40a686 DW |
1297 | if (dca) |
1298 | device->dca = ioat3_dca_init(pdev, device->reg_base); | |
1299 | ||
1300 | return 0; | |
1301 | } |