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dmaengine: ensure all DMA engine drivers initialize their cookies
[deliverable/linux.git] / drivers / dma / iop-adma.c
CommitLineData
c2110923
DW		 1/*
2 * offload engine driver for the Intel Xscale series of i/o processors
3 * Copyright © 2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20/*
21 * This driver supports the asynchrounous DMA copy and RAID engines available
22 * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
23 */
24
25#include <linux/init.h>
26#include <linux/module.h>
c2110923
DW		 27#include <linux/delay.h>
28#include <linux/dma-mapping.h>
29#include <linux/spinlock.h>
30#include <linux/interrupt.h>
31#include <linux/platform_device.h>
32#include <linux/memory.h>
33#include <linux/ioport.h>
f6dbf651 34#include <linux/raid/pq.h>
5a0e3ad6 35#include <linux/slab.h>
c2110923 36
a09e64fb 37#include <mach/adma.h>
c2110923 38
d2ebfb33
RKAL		 39#include "dmaengine.h"
40
c2110923
DW		 41#define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
42#define to_iop_adma_device(dev) \
43 container_of(dev, struct iop_adma_device, common)
44#define tx_to_iop_adma_slot(tx) \
45 container_of(tx, struct iop_adma_desc_slot, async_tx)
46
47/**
48 * iop_adma_free_slots - flags descriptor slots for reuse
49 * @slot: Slot to free
50 * Caller must hold &iop_chan->lock while calling this function
51 */
52static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
53{
54 int stride = slot->slots_per_op;
55
56 while (stride--) {
57 slot->slots_per_op = 0;
58 slot = list_entry(slot->slot_node.next,
59 struct iop_adma_desc_slot,
60 slot_node);
61 }
62}
63
7bf649ae
DW		 64static void
65iop_desc_unmap(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc)
66{
67 struct dma_async_tx_descriptor *tx = &desc->async_tx;
68 struct iop_adma_desc_slot *unmap = desc->group_head;
69 struct device *dev = &iop_chan->device->pdev->dev;
70 u32 len = unmap->unmap_len;
71 enum dma_ctrl_flags flags = tx->flags;
72 u32 src_cnt;
73 dma_addr_t addr;
74 dma_addr_t dest;
75
76 src_cnt = unmap->unmap_src_cnt;
77 dest = iop_desc_get_dest_addr(unmap, iop_chan);
78 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
79 enum dma_data_direction dir;
80
81 if (src_cnt > 1) /* is xor? */
82 dir = DMA_BIDIRECTIONAL;
83 else
84 dir = DMA_FROM_DEVICE;
85
86 dma_unmap_page(dev, dest, len, dir);
87 }
88
89 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
90 while (src_cnt--) {
91 addr = iop_desc_get_src_addr(unmap, iop_chan, src_cnt);
92 if (addr == dest)
93 continue;
94 dma_unmap_page(dev, addr, len, DMA_TO_DEVICE);
95 }
96 }
97 desc->group_head = NULL;
98}
99
100static void
101iop_desc_unmap_pq(struct iop_adma_chan *iop_chan, struct iop_adma_desc_slot *desc)
102{
103 struct dma_async_tx_descriptor *tx = &desc->async_tx;
104 struct iop_adma_desc_slot *unmap = desc->group_head;
105 struct device *dev = &iop_chan->device->pdev->dev;
106 u32 len = unmap->unmap_len;
107 enum dma_ctrl_flags flags = tx->flags;
108 u32 src_cnt = unmap->unmap_src_cnt;
109 dma_addr_t pdest = iop_desc_get_dest_addr(unmap, iop_chan);
110 dma_addr_t qdest = iop_desc_get_qdest_addr(unmap, iop_chan);
111 int i;
112
113 if (tx->flags & DMA_PREP_CONTINUE)
114 src_cnt -= 3;
115
116 if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP) && !desc->pq_check_result) {
117 dma_unmap_page(dev, pdest, len, DMA_BIDIRECTIONAL);
118 dma_unmap_page(dev, qdest, len, DMA_BIDIRECTIONAL);
119 }
120
121 if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
122 dma_addr_t addr;
123
124 for (i = 0; i < src_cnt; i++) {
125 addr = iop_desc_get_src_addr(unmap, iop_chan, i);
126 dma_unmap_page(dev, addr, len, DMA_TO_DEVICE);
127 }
128 if (desc->pq_check_result) {
129 dma_unmap_page(dev, pdest, len, DMA_TO_DEVICE);
130 dma_unmap_page(dev, qdest, len, DMA_TO_DEVICE);
131 }
132 }
133
134 desc->group_head = NULL;
135}
136
137
c2110923
DW		 138static dma_cookie_t
139iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
140 struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
141{
507fbec4
DW		 142 struct dma_async_tx_descriptor *tx = &desc->async_tx;
143
144 BUG_ON(tx->cookie < 0);
145 if (tx->cookie > 0) {
146 cookie = tx->cookie;
147 tx->cookie = 0;
c2110923
DW		 148
149 /* call the callback (must not sleep or submit new
150 * operations to this channel)
151 */
507fbec4
DW		 152 if (tx->callback)
153 tx->callback(tx->callback_param);
c2110923
DW		 154
155 /* unmap dma addresses
156 * (unmap_single vs unmap_page?)
157 */
158 if (desc->group_head && desc->unmap_len) {
7bf649ae
DW		 159 if (iop_desc_is_pq(desc))
160 iop_desc_unmap_pq(iop_chan, desc);
161 else
162 iop_desc_unmap(iop_chan, desc);
c2110923
DW		 163 }
164 }
165
166 /* run dependent operations */
507fbec4 167 dma_run_dependencies(tx);
c2110923
DW		 168
169 return cookie;
170}
171
172static int
173iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
174 struct iop_adma_chan *iop_chan)
175{
176 /* the client is allowed to attach dependent operations
177 * until 'ack' is set
178 */
636bdeaa 179 if (!async_tx_test_ack(&desc->async_tx))
c2110923
DW		 180 return 0;
181
182 /* leave the last descriptor in the chain
183 * so we can append to it
184 */
185 if (desc->chain_node.next == &iop_chan->chain)
186 return 1;
187
188 dev_dbg(iop_chan->device->common.dev,
189 "\tfree slot: %d slots_per_op: %d\n",
190 desc->idx, desc->slots_per_op);
191
192 list_del(&desc->chain_node);
193 iop_adma_free_slots(desc);
194
195 return 0;
196}
197
198static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
199{
200 struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
201 dma_cookie_t cookie = 0;
202 u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
203 int busy = iop_chan_is_busy(iop_chan);
204 int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
205
3d9b525b 206 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
c2110923
DW		 207 /* free completed slots from the chain starting with
208 * the oldest descriptor
209 */
210 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
211 chain_node) {
212 pr_debug("\tcookie: %d slot: %d busy: %d "
213 "this_desc: %#x next_desc: %#x ack: %d\n",
214 iter->async_tx.cookie, iter->idx, busy,
215 iter->async_tx.phys, iop_desc_get_next_desc(iter),
636bdeaa 216 async_tx_test_ack(&iter->async_tx));
c2110923
DW		 217 prefetch(_iter);
218 prefetch(&_iter->async_tx);
219
220 /* do not advance past the current descriptor loaded into the
221 * hardware channel, subsequent descriptors are either in
222 * process or have not been submitted
223 */
224 if (seen_current)
225 break;
226
227 /* stop the search if we reach the current descriptor and the
228 * channel is busy, or if it appears that the current descriptor
229 * needs to be re-read (i.e. has been appended to)
230 */
231 if (iter->async_tx.phys == current_desc) {
232 BUG_ON(seen_current++);
233 if (busy || iop_desc_get_next_desc(iter))
234 break;
235 }
236
237 /* detect the start of a group transaction */
238 if (!slot_cnt && !slots_per_op) {
239 slot_cnt = iter->slot_cnt;
240 slots_per_op = iter->slots_per_op;
241 if (slot_cnt <= slots_per_op) {
242 slot_cnt = 0;
243 slots_per_op = 0;
244 }
245 }
246
247 if (slot_cnt) {
248 pr_debug("\tgroup++\n");
249 if (!grp_start)
250 grp_start = iter;
251 slot_cnt -= slots_per_op;
252 }
253
254 /* all the members of a group are complete */
255 if (slots_per_op != 0 && slot_cnt == 0) {
256 struct iop_adma_desc_slot *grp_iter, *_grp_iter;
257 int end_of_chain = 0;
258 pr_debug("\tgroup end\n");
259
260 /* collect the total results */
261 if (grp_start->xor_check_result) {
262 u32 zero_sum_result = 0;
263 slot_cnt = grp_start->slot_cnt;
264 grp_iter = grp_start;
265
266 list_for_each_entry_from(grp_iter,
267 &iop_chan->chain, chain_node) {
268 zero_sum_result |=
269 iop_desc_get_zero_result(grp_iter);
270 pr_debug("\titer%d result: %d\n",
271 grp_iter->idx, zero_sum_result);
272 slot_cnt -= slots_per_op;
273 if (slot_cnt == 0)
274 break;
275 }
276 pr_debug("\tgrp_start->xor_check_result: %p\n",
277 grp_start->xor_check_result);
278 *grp_start->xor_check_result = zero_sum_result;
279 }
280
281 /* clean up the group */
282 slot_cnt = grp_start->slot_cnt;
283 grp_iter = grp_start;
284 list_for_each_entry_safe_from(grp_iter, _grp_iter,
285 &iop_chan->chain, chain_node) {
286 cookie = iop_adma_run_tx_complete_actions(
287 grp_iter, iop_chan, cookie);
288
289 slot_cnt -= slots_per_op;
290 end_of_chain = iop_adma_clean_slot(grp_iter,
291 iop_chan);
292
293 if (slot_cnt == 0 || end_of_chain)
294 break;
295 }
296
297 /* the group should be complete at this point */
298 BUG_ON(slot_cnt);
299
300 slots_per_op = 0;
301 grp_start = NULL;
302 if (end_of_chain)
303 break;
304 else
305 continue;
306 } else if (slots_per_op) /* wait for group completion */
307 continue;
308
309 /* write back zero sum results (single descriptor case) */
310 if (iter->xor_check_result && iter->async_tx.cookie)
311 *iter->xor_check_result =
312 iop_desc_get_zero_result(iter);
313
314 cookie = iop_adma_run_tx_complete_actions(
315 iter, iop_chan, cookie);
316
317 if (iop_adma_clean_slot(iter, iop_chan))
318 break;
319 }
320
c2110923 321 if (cookie > 0) {
4d4e58de 322 iop_chan->common.completed_cookie = cookie;
c2110923
DW		 323 pr_debug("\tcompleted cookie %d\n", cookie);
324 }
325}
326
327static void
328iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
329{
330 spin_lock_bh(&iop_chan->lock);
331 __iop_adma_slot_cleanup(iop_chan);
332 spin_unlock_bh(&iop_chan->lock);
333}
334
335static void iop_adma_tasklet(unsigned long data)
336{
19242d72
DW		 337 struct iop_adma_chan *iop_chan = (struct iop_adma_chan *) data;
338
72be12f0
DW		 339 /* lockdep will flag depedency submissions as potentially
340 * recursive locking, this is not the case as a dependency
341 * submission will never recurse a channels submit routine.
342 * There are checks in async_tx.c to prevent this.
343 */
344 spin_lock_nested(&iop_chan->lock, SINGLE_DEPTH_NESTING);
19242d72
DW		 345 __iop_adma_slot_cleanup(iop_chan);
346 spin_unlock(&iop_chan->lock);
c2110923
DW		 347}
348
349static struct iop_adma_desc_slot *
350iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
351 int slots_per_op)
352{
353 struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
e73ef9ac 354 LIST_HEAD(chain);
c2110923
DW		 355 int slots_found, retry = 0;
356
357 /* start search from the last allocated descrtiptor
358 * if a contiguous allocation can not be found start searching
359 * from the beginning of the list
360 */
361retry:
362 slots_found = 0;
363 if (retry == 0)
364 iter = iop_chan->last_used;
365 else
366 iter = list_entry(&iop_chan->all_slots,
367 struct iop_adma_desc_slot,
368 slot_node);
369
370 list_for_each_entry_safe_continue(
371 iter, _iter, &iop_chan->all_slots, slot_node) {
372 prefetch(_iter);
373 prefetch(&_iter->async_tx);
374 if (iter->slots_per_op) {
375 /* give up after finding the first busy slot
376 * on the second pass through the list
377 */
378 if (retry)
379 break;
380
381 slots_found = 0;
382 continue;
383 }
384
385 /* start the allocation if the slot is correctly aligned */
386 if (!slots_found++) {
387 if (iop_desc_is_aligned(iter, slots_per_op))
388 alloc_start = iter;
389 else {
390 slots_found = 0;
391 continue;
392 }
393 }
394
395 if (slots_found == num_slots) {
396 struct iop_adma_desc_slot *alloc_tail = NULL;
397 struct iop_adma_desc_slot *last_used = NULL;
398 iter = alloc_start;
399 while (num_slots) {
400 int i;
401 dev_dbg(iop_chan->device->common.dev,
402 "allocated slot: %d "
403 "(desc %p phys: %#x) slots_per_op %d\n",
404 iter->idx, iter->hw_desc,
405 iter->async_tx.phys, slots_per_op);
406
407 /* pre-ack all but the last descriptor */
408 if (num_slots != slots_per_op)
636bdeaa 409 async_tx_ack(&iter->async_tx);
c2110923
DW		 410
411 list_add_tail(&iter->chain_node, &chain);
412 alloc_tail = iter;
413 iter->async_tx.cookie = 0;
414 iter->slot_cnt = num_slots;
415 iter->xor_check_result = NULL;
416 for (i = 0; i < slots_per_op; i++) {
417 iter->slots_per_op = slots_per_op - i;
418 last_used = iter;
419 iter = list_entry(iter->slot_node.next,
420 struct iop_adma_desc_slot,
421 slot_node);
422 }
423 num_slots -= slots_per_op;
424 }
425 alloc_tail->group_head = alloc_start;
426 alloc_tail->async_tx.cookie = -EBUSY;
308136d1 427 list_splice(&chain, &alloc_tail->tx_list);
c2110923
DW		 428 iop_chan->last_used = last_used;
429 iop_desc_clear_next_desc(alloc_start);
430 iop_desc_clear_next_desc(alloc_tail);
431 return alloc_tail;
432 }
433 }
434 if (!retry++)
435 goto retry;
436
c7141d00
DW		 437 /* perform direct reclaim if the allocation fails */
438 __iop_adma_slot_cleanup(iop_chan);
c2110923
DW		 439
440 return NULL;
441}
442
c2110923
DW		 443static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
444{
445 dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
446 iop_chan->pending);
447
448 if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
449 iop_chan->pending = 0;
450 iop_chan_append(iop_chan);
451 }
452}
453
454static dma_cookie_t
455iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
456{
457 struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
458 struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
459 struct iop_adma_desc_slot *grp_start, *old_chain_tail;
460 int slot_cnt;
461 int slots_per_op;
462 dma_cookie_t cookie;
137cb55c 463 dma_addr_t next_dma;
c2110923
DW		 464
465 grp_start = sw_desc->group_head;
466 slot_cnt = grp_start->slot_cnt;
467 slots_per_op = grp_start->slots_per_op;
468
469 spin_lock_bh(&iop_chan->lock);
884485e1 470 cookie = dma_cookie_assign(tx);
c2110923
DW		 471
472 old_chain_tail = list_entry(iop_chan->chain.prev,
473 struct iop_adma_desc_slot, chain_node);
308136d1 474 list_splice_init(&sw_desc->tx_list,
c2110923
DW		 475 &old_chain_tail->chain_node);
476
477 /* fix up the hardware chain */
137cb55c
DW		 478 next_dma = grp_start->async_tx.phys;
479 iop_desc_set_next_desc(old_chain_tail, next_dma);
480 BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */
c2110923 481
137cb55c 482 /* check for pre-chained descriptors */
65e50381 483 iop_paranoia(iop_desc_get_next_desc(sw_desc));
c2110923
DW		 484
485 /* increment the pending count by the number of slots
486 * memcpy operations have a 1:1 (slot:operation) relation
487 * other operations are heavier and will pop the threshold
488 * more often.
489 */
490 iop_chan->pending += slot_cnt;
491 iop_adma_check_threshold(iop_chan);
492 spin_unlock_bh(&iop_chan->lock);
493
494 dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
3d9b525b 495 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
c2110923
DW		 496
497 return cookie;
498}
499
c2110923
DW		 500static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
501static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
502
5eb907aa
DW		 503/**
504 * iop_adma_alloc_chan_resources - returns the number of allocated descriptors
505 * @chan - allocate descriptor resources for this channel
506 * @client - current client requesting the channel be ready for requests
507 *
508 * Note: We keep the slots for 1 operation on iop_chan->chain at all times. To
509 * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be
510 * greater than 2x the number slots needed to satisfy a device->max_xor
511 * request.
512 * */
aa1e6f1a 513static int iop_adma_alloc_chan_resources(struct dma_chan *chan)
c2110923
DW		 514{
515 char *hw_desc;
516 int idx;
517 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
518 struct iop_adma_desc_slot *slot = NULL;
519 int init = iop_chan->slots_allocated ? 0 : 1;
520 struct iop_adma_platform_data *plat_data =
521 iop_chan->device->pdev->dev.platform_data;
522 int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
523
524 /* Allocate descriptor slots */
525 do {
526 idx = iop_chan->slots_allocated;
527 if (idx == num_descs_in_pool)
528 break;
529
530 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
531 if (!slot) {
532 printk(KERN_INFO "IOP ADMA Channel only initialized"
533 " %d descriptor slots", idx);
534 break;
535 }
536 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
537 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
538
539 dma_async_tx_descriptor_init(&slot->async_tx, chan);
540 slot->async_tx.tx_submit = iop_adma_tx_submit;
308136d1 541 INIT_LIST_HEAD(&slot->tx_list);
c2110923
DW		 542 INIT_LIST_HEAD(&slot->chain_node);
543 INIT_LIST_HEAD(&slot->slot_node);
c2110923
DW		 544 hw_desc = (char *) iop_chan->device->dma_desc_pool;
545 slot->async_tx.phys =
546 (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
547 slot->idx = idx;
548
549 spin_lock_bh(&iop_chan->lock);
550 iop_chan->slots_allocated++;
551 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
552 spin_unlock_bh(&iop_chan->lock);
553 } while (iop_chan->slots_allocated < num_descs_in_pool);
554
555 if (idx && !iop_chan->last_used)
556 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
557 struct iop_adma_desc_slot,
558 slot_node);
559
560 dev_dbg(iop_chan->device->common.dev,
561 "allocated %d descriptor slots last_used: %p\n",
562 iop_chan->slots_allocated, iop_chan->last_used);
563
564 /* initialize the channel and the chain with a null operation */
565 if (init) {
566 if (dma_has_cap(DMA_MEMCPY,
567 iop_chan->device->common.cap_mask))
568 iop_chan_start_null_memcpy(iop_chan);
569 else if (dma_has_cap(DMA_XOR,
570 iop_chan->device->common.cap_mask))
571 iop_chan_start_null_xor(iop_chan);
572 else
573 BUG();
574 }
575
576 return (idx > 0) ? idx : -ENOMEM;
577}
578
579static struct dma_async_tx_descriptor *
636bdeaa 580iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags)
c2110923
DW		 581{
582 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
583 struct iop_adma_desc_slot *sw_desc, *grp_start;
584 int slot_cnt, slots_per_op;
585
3d9b525b 586 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
c2110923
DW		 587
588 spin_lock_bh(&iop_chan->lock);
589 slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
590 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
591 if (sw_desc) {
592 grp_start = sw_desc->group_head;
593 iop_desc_init_interrupt(grp_start, iop_chan);
594 grp_start->unmap_len = 0;
636bdeaa 595 sw_desc->async_tx.flags = flags;
c2110923
DW		 596 }
597 spin_unlock_bh(&iop_chan->lock);
598
599 return sw_desc ? &sw_desc->async_tx : NULL;
600}
601
c2110923 602static struct dma_async_tx_descriptor *
0036731c 603iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
d4c56f97 604 dma_addr_t dma_src, size_t len, unsigned long flags)
c2110923
DW		 605{
606 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
607 struct iop_adma_desc_slot *sw_desc, *grp_start;
608 int slot_cnt, slots_per_op;
609
610 if (unlikely(!len))
611 return NULL;
e2ec771a 612 BUG_ON(len > IOP_ADMA_MAX_BYTE_COUNT);
c2110923
DW		 613
614 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
3d9b525b 615 __func__, len);
c2110923
DW		 616
617 spin_lock_bh(&iop_chan->lock);
618 slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
619 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
620 if (sw_desc) {
621 grp_start = sw_desc->group_head;
d4c56f97 622 iop_desc_init_memcpy(grp_start, flags);
c2110923 623 iop_desc_set_byte_count(grp_start, iop_chan, len);
0036731c
DW		 624 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
625 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
c2110923
DW		 626 sw_desc->unmap_src_cnt = 1;
627 sw_desc->unmap_len = len;
636bdeaa 628 sw_desc->async_tx.flags = flags;
c2110923
DW		 629 }
630 spin_unlock_bh(&iop_chan->lock);
631
632 return sw_desc ? &sw_desc->async_tx : NULL;
633}
634
635static struct dma_async_tx_descriptor *
0036731c 636iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
d4c56f97 637 int value, size_t len, unsigned long flags)
c2110923
DW		 638{
639 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
640 struct iop_adma_desc_slot *sw_desc, *grp_start;
641 int slot_cnt, slots_per_op;
642
643 if (unlikely(!len))
644 return NULL;
e2ec771a 645 BUG_ON(len > IOP_ADMA_MAX_BYTE_COUNT);
c2110923
DW		 646
647 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
3d9b525b 648 __func__, len);
c2110923
DW		 649
650 spin_lock_bh(&iop_chan->lock);
651 slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
652 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
653 if (sw_desc) {
654 grp_start = sw_desc->group_head;
d4c56f97 655 iop_desc_init_memset(grp_start, flags);
c2110923
DW		 656 iop_desc_set_byte_count(grp_start, iop_chan, len);
657 iop_desc_set_block_fill_val(grp_start, value);
0036731c 658 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
c2110923
DW		 659 sw_desc->unmap_src_cnt = 1;
660 sw_desc->unmap_len = len;
636bdeaa 661 sw_desc->async_tx.flags = flags;
c2110923
DW		 662 }
663 spin_unlock_bh(&iop_chan->lock);
664
665 return sw_desc ? &sw_desc->async_tx : NULL;
666}
667
c2110923 668static struct dma_async_tx_descriptor *
0036731c
DW		 669iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
670 dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
d4c56f97 671 unsigned long flags)
c2110923
DW		 672{
673 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
674 struct iop_adma_desc_slot *sw_desc, *grp_start;
675 int slot_cnt, slots_per_op;
676
677 if (unlikely(!len))
678 return NULL;
e2ec771a 679 BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
c2110923
DW		 680
681 dev_dbg(iop_chan->device->common.dev,
d4c56f97 682 "%s src_cnt: %d len: %u flags: %lx\n",
3d9b525b 683 __func__, src_cnt, len, flags);
c2110923
DW		 684
685 spin_lock_bh(&iop_chan->lock);
686 slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
687 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
688 if (sw_desc) {
689 grp_start = sw_desc->group_head;
d4c56f97 690 iop_desc_init_xor(grp_start, src_cnt, flags);
c2110923 691 iop_desc_set_byte_count(grp_start, iop_chan, len);
0036731c 692 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
c2110923
DW		 693 sw_desc->unmap_src_cnt = src_cnt;
694 sw_desc->unmap_len = len;
636bdeaa 695 sw_desc->async_tx.flags = flags;
0036731c
DW		 696 while (src_cnt--)
697 iop_desc_set_xor_src_addr(grp_start, src_cnt,
698 dma_src[src_cnt]);
c2110923
DW		 699 }
700 spin_unlock_bh(&iop_chan->lock);
701
702 return sw_desc ? &sw_desc->async_tx : NULL;
703}
704
c2110923 705static struct dma_async_tx_descriptor *
099f53cb
DW		 706iop_adma_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *dma_src,
707 unsigned int src_cnt, size_t len, u32 *result,
708 unsigned long flags)
c2110923
DW		 709{
710 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
711 struct iop_adma_desc_slot *sw_desc, *grp_start;
712 int slot_cnt, slots_per_op;
713
714 if (unlikely(!len))
715 return NULL;
716
717 dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
3d9b525b 718 __func__, src_cnt, len);
c2110923
DW		 719
720 spin_lock_bh(&iop_chan->lock);
721 slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
722 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
723 if (sw_desc) {
724 grp_start = sw_desc->group_head;
d4c56f97 725 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
c2110923
DW		 726 iop_desc_set_zero_sum_byte_count(grp_start, len);
727 grp_start->xor_check_result = result;
728 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
3d9b525b 729 __func__, grp_start->xor_check_result);
c2110923
DW		 730 sw_desc->unmap_src_cnt = src_cnt;
731 sw_desc->unmap_len = len;
636bdeaa 732 sw_desc->async_tx.flags = flags;
0036731c
DW		 733 while (src_cnt--)
734 iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
735 dma_src[src_cnt]);
c2110923
DW		 736 }
737 spin_unlock_bh(&iop_chan->lock);
738
739 return sw_desc ? &sw_desc->async_tx : NULL;
740}
741
7bf649ae
DW		 742static struct dma_async_tx_descriptor *
743iop_adma_prep_dma_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
744 unsigned int src_cnt, const unsigned char *scf, size_t len,
745 unsigned long flags)
746{
747 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
748 struct iop_adma_desc_slot *sw_desc, *g;
749 int slot_cnt, slots_per_op;
750 int continue_srcs;
751
752 if (unlikely(!len))
753 return NULL;
754 BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
755
756 dev_dbg(iop_chan->device->common.dev,
757 "%s src_cnt: %d len: %u flags: %lx\n",
758 __func__, src_cnt, len, flags);
759
760 if (dmaf_p_disabled_continue(flags))
761 continue_srcs = 1+src_cnt;
762 else if (dmaf_continue(flags))
763 continue_srcs = 3+src_cnt;
764 else
765 continue_srcs = 0+src_cnt;
766
767 spin_lock_bh(&iop_chan->lock);
768 slot_cnt = iop_chan_pq_slot_count(len, continue_srcs, &slots_per_op);
769 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
770 if (sw_desc) {
771 int i;
772
773 g = sw_desc->group_head;
774 iop_desc_set_byte_count(g, iop_chan, len);
775
776 /* even if P is disabled its destination address (bits
777 * [3:0]) must match Q. It is ok if P points to an
778 * invalid address, it won't be written.
779 */
780 if (flags & DMA_PREP_PQ_DISABLE_P)
781 dst[0] = dst[1] & 0x7;
782
783 iop_desc_set_pq_addr(g, dst);
784 sw_desc->unmap_src_cnt = src_cnt;
785 sw_desc->unmap_len = len;
786 sw_desc->async_tx.flags = flags;
787 for (i = 0; i < src_cnt; i++)
788 iop_desc_set_pq_src_addr(g, i, src[i], scf[i]);
789
790 /* if we are continuing a previous operation factor in
791 * the old p and q values, see the comment for dma_maxpq
792 * in include/linux/dmaengine.h
793 */
794 if (dmaf_p_disabled_continue(flags))
795 iop_desc_set_pq_src_addr(g, i++, dst[1], 1);
796 else if (dmaf_continue(flags)) {
797 iop_desc_set_pq_src_addr(g, i++, dst[0], 0);
798 iop_desc_set_pq_src_addr(g, i++, dst[1], 1);
799 iop_desc_set_pq_src_addr(g, i++, dst[1], 0);
800 }
801 iop_desc_init_pq(g, i, flags);
802 }
803 spin_unlock_bh(&iop_chan->lock);
804
805 return sw_desc ? &sw_desc->async_tx : NULL;
806}
807
808static struct dma_async_tx_descriptor *
809iop_adma_prep_dma_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
810 unsigned int src_cnt, const unsigned char *scf,
811 size_t len, enum sum_check_flags *pqres,
812 unsigned long flags)
813{
814 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
815 struct iop_adma_desc_slot *sw_desc, *g;
816 int slot_cnt, slots_per_op;
817
818 if (unlikely(!len))
819 return NULL;
820 BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT);
821
822 dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
823 __func__, src_cnt, len);
824
825 spin_lock_bh(&iop_chan->lock);
826 slot_cnt = iop_chan_pq_zero_sum_slot_count(len, src_cnt + 2, &slots_per_op);
827 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
828 if (sw_desc) {
829 /* for validate operations p and q are tagged onto the
830 * end of the source list
831 */
832 int pq_idx = src_cnt;
833
834 g = sw_desc->group_head;
835 iop_desc_init_pq_zero_sum(g, src_cnt+2, flags);
836 iop_desc_set_pq_zero_sum_byte_count(g, len);
837 g->pq_check_result = pqres;
838 pr_debug("\t%s: g->pq_check_result: %p\n",
839 __func__, g->pq_check_result);
840 sw_desc->unmap_src_cnt = src_cnt+2;
841 sw_desc->unmap_len = len;
842 sw_desc->async_tx.flags = flags;
843 while (src_cnt--)
844 iop_desc_set_pq_zero_sum_src_addr(g, src_cnt,
845 src[src_cnt],
846 scf[src_cnt]);
847 iop_desc_set_pq_zero_sum_addr(g, pq_idx, src);
848 }
849 spin_unlock_bh(&iop_chan->lock);
850
851 return sw_desc ? &sw_desc->async_tx : NULL;
852}
853
c2110923
DW		 854static void iop_adma_free_chan_resources(struct dma_chan *chan)
855{
856 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
857 struct iop_adma_desc_slot *iter, *_iter;
858 int in_use_descs = 0;
859
860 iop_adma_slot_cleanup(iop_chan);
861
862 spin_lock_bh(&iop_chan->lock);
863 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
864 chain_node) {
865 in_use_descs++;
866 list_del(&iter->chain_node);
867 }
868 list_for_each_entry_safe_reverse(
869 iter, _iter, &iop_chan->all_slots, slot_node) {
870 list_del(&iter->slot_node);
871 kfree(iter);
872 iop_chan->slots_allocated--;
873 }
874 iop_chan->last_used = NULL;
875
876 dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
3d9b525b 877 __func__, iop_chan->slots_allocated);
c2110923
DW		 878 spin_unlock_bh(&iop_chan->lock);
879
880 /* one is ok since we left it on there on purpose */
881 if (in_use_descs > 1)
882 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
883 in_use_descs - 1);
884}
885
886/**
07934481 887 * iop_adma_status - poll the status of an ADMA transaction
c2110923
DW		 888 * @chan: ADMA channel handle
889 * @cookie: ADMA transaction identifier
07934481 890 * @txstate: a holder for the current state of the channel or NULL
c2110923 891 */
07934481 892static enum dma_status iop_adma_status(struct dma_chan *chan,
c2110923 893 dma_cookie_t cookie,
07934481 894 struct dma_tx_state *txstate)
c2110923
DW		 895{
896 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
96a2af41
RKAL		 897
898 ret = dma_cookie_status(chan, cookie, txstate);
c2110923
DW		 899 if (ret == DMA_SUCCESS)
900 return ret;
901
902 iop_adma_slot_cleanup(iop_chan);
903
96a2af41 904 return dma_cookie_status(chan, cookie, txstate);
c2110923
DW		 905}
906
907static irqreturn_t iop_adma_eot_handler(int irq, void *data)
908{
909 struct iop_adma_chan *chan = data;
910
3d9b525b 911 dev_dbg(chan->device->common.dev, "%s\n", __func__);
c2110923
DW		 912
913 tasklet_schedule(&chan->irq_tasklet);
914
915 iop_adma_device_clear_eot_status(chan);
916
917 return IRQ_HANDLED;
918}
919
920static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
921{
922 struct iop_adma_chan *chan = data;
923
3d9b525b 924 dev_dbg(chan->device->common.dev, "%s\n", __func__);
c2110923
DW		 925
926 tasklet_schedule(&chan->irq_tasklet);
927
928 iop_adma_device_clear_eoc_status(chan);
929
930 return IRQ_HANDLED;
931}
932
933static irqreturn_t iop_adma_err_handler(int irq, void *data)
934{
935 struct iop_adma_chan *chan = data;
936 unsigned long status = iop_chan_get_status(chan);
937
938 dev_printk(KERN_ERR, chan->device->common.dev,
939 "error ( %s%s%s%s%s%s%s)\n",
940 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
941 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
942 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
943 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
944 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
945 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
946 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
947
948 iop_adma_device_clear_err_status(chan);
949
950 BUG();
951
952 return IRQ_HANDLED;
953}
954
955static void iop_adma_issue_pending(struct dma_chan *chan)
956{
957 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
958
959 if (iop_chan->pending) {
960 iop_chan->pending = 0;
961 iop_chan_append(iop_chan);
962 }
963}
964
965/*
966 * Perform a transaction to verify the HW works.
967 */
968#define IOP_ADMA_TEST_SIZE 2000
969
970static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
971{
972 int i;
973 void *src, *dest;
974 dma_addr_t src_dma, dest_dma;
975 struct dma_chan *dma_chan;
976 dma_cookie_t cookie;
977 struct dma_async_tx_descriptor *tx;
978 int err = 0;
979 struct iop_adma_chan *iop_chan;
980
3d9b525b 981 dev_dbg(device->common.dev, "%s\n", __func__);
c2110923 982
eccf2144 983 src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
c2110923
DW		 984 if (!src)
985 return -ENOMEM;
eccf2144 986 dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL);
c2110923
DW		 987 if (!dest) {
988 kfree(src);
989 return -ENOMEM;
990 }
991
992 /* Fill in src buffer */
993 for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
994 ((u8 *) src)[i] = (u8)i;
995
c2110923
DW		 996 /* Start copy, using first DMA channel */
997 dma_chan = container_of(device->common.channels.next,
998 struct dma_chan,
999 device_node);
aa1e6f1a 1000 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
c2110923
DW		 1001 err = -ENODEV;
1002 goto out;
1003 }
1004
c2110923
DW		 1005 dest_dma = dma_map_single(dma_chan->device->dev, dest,
1006 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
c2110923
DW		 1007 src_dma = dma_map_single(dma_chan->device->dev, src,
1008 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
0036731c 1009 tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
636bdeaa
DW		 1010 IOP_ADMA_TEST_SIZE,
1011 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
c2110923
DW		 1012
1013 cookie = iop_adma_tx_submit(tx);
1014 iop_adma_issue_pending(dma_chan);
c2110923
DW		 1015 msleep(1);
1016
07934481 1017 if (iop_adma_status(dma_chan, cookie, NULL) !=
c2110923
DW		 1018 DMA_SUCCESS) {
1019 dev_printk(KERN_ERR, dma_chan->device->dev,
1020 "Self-test copy timed out, disabling\n");
1021 err = -ENODEV;
1022 goto free_resources;
1023 }
1024
1025 iop_chan = to_iop_adma_chan(dma_chan);
1026 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
1027 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
1028 if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
1029 dev_printk(KERN_ERR, dma_chan->device->dev,
1030 "Self-test copy failed compare, disabling\n");
1031 err = -ENODEV;
1032 goto free_resources;
1033 }
1034
1035free_resources:
1036 iop_adma_free_chan_resources(dma_chan);
1037out:
1038 kfree(src);
1039 kfree(dest);
1040 return err;
1041}
1042
1043#define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
1044static int __devinit
099f53cb 1045iop_adma_xor_val_self_test(struct iop_adma_device *device)
c2110923
DW		 1046{
1047 int i, src_idx;
1048 struct page *dest;
1049 struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
1050 struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
0036731c 1051 dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
c2110923
DW		 1052 dma_addr_t dma_addr, dest_dma;
1053 struct dma_async_tx_descriptor *tx;
1054 struct dma_chan *dma_chan;
1055 dma_cookie_t cookie;
1056 u8 cmp_byte = 0;
1057 u32 cmp_word;
1058 u32 zero_sum_result;
1059 int err = 0;
1060 struct iop_adma_chan *iop_chan;
1061
3d9b525b 1062 dev_dbg(device->common.dev, "%s\n", __func__);
c2110923
DW		 1063
1064 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
1065 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
a09b09ae
RK		 1066 if (!xor_srcs[src_idx]) {
1067 while (src_idx--)
c2110923 1068 __free_page(xor_srcs[src_idx]);
a09b09ae
RK		 1069 return -ENOMEM;
1070 }
c2110923
DW		 1071 }
1072
1073 dest = alloc_page(GFP_KERNEL);
a09b09ae
RK		 1074 if (!dest) {
1075 while (src_idx--)
c2110923 1076 __free_page(xor_srcs[src_idx]);
a09b09ae
RK		 1077 return -ENOMEM;
1078 }
c2110923
DW		 1079
1080 /* Fill in src buffers */
1081 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
1082 u8 *ptr = page_address(xor_srcs[src_idx]);
1083 for (i = 0; i < PAGE_SIZE; i++)
1084 ptr[i] = (1 << src_idx);
1085 }
1086
1087 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
1088 cmp_byte ^= (u8) (1 << src_idx);
1089
1090 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
1091 (cmp_byte << 8) | cmp_byte;
1092
1093 memset(page_address(dest), 0, PAGE_SIZE);
1094
1095 dma_chan = container_of(device->common.channels.next,
1096 struct dma_chan,
1097 device_node);
aa1e6f1a 1098 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
c2110923
DW		 1099 err = -ENODEV;
1100 goto out;
1101 }
1102
1103 /* test xor */
c2110923
DW		 1104 dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
1105 PAGE_SIZE, DMA_FROM_DEVICE);
0036731c
DW		 1106 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1107 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
1108 0, PAGE_SIZE, DMA_TO_DEVICE);
1109 tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
636bdeaa
DW		 1110 IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE,
1111 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
c2110923
DW		 1112
1113 cookie = iop_adma_tx_submit(tx);
1114 iop_adma_issue_pending(dma_chan);
c2110923
DW		 1115 msleep(8);
1116
07934481 1117 if (iop_adma_status(dma_chan, cookie, NULL) !=
c2110923
DW		 1118 DMA_SUCCESS) {
1119 dev_printk(KERN_ERR, dma_chan->device->dev,
1120 "Self-test xor timed out, disabling\n");
1121 err = -ENODEV;
1122 goto free_resources;
1123 }
1124
1125 iop_chan = to_iop_adma_chan(dma_chan);
1126 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
1127 PAGE_SIZE, DMA_FROM_DEVICE);
1128 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
1129 u32 *ptr = page_address(dest);
1130 if (ptr[i] != cmp_word) {
1131 dev_printk(KERN_ERR, dma_chan->device->dev,
1132 "Self-test xor failed compare, disabling\n");
1133 err = -ENODEV;
1134 goto free_resources;
1135 }
1136 }
1137 dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
1138 PAGE_SIZE, DMA_TO_DEVICE);
1139
1140 /* skip zero sum if the capability is not present */
099f53cb 1141 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
c2110923
DW		 1142 goto free_resources;
1143
1144 /* zero sum the sources with the destintation page */
1145 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1146 zero_sum_srcs[i] = xor_srcs[i];
1147 zero_sum_srcs[i] = dest;
1148
1149 zero_sum_result = 1;
1150
0036731c
DW		 1151 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1152 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1153 zero_sum_srcs[i], 0, PAGE_SIZE,
1154 DMA_TO_DEVICE);
099f53cb
DW		 1155 tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs,
1156 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1157 &zero_sum_result,
1158 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
c2110923
DW		 1159
1160 cookie = iop_adma_tx_submit(tx);
1161 iop_adma_issue_pending(dma_chan);
c2110923
DW		 1162 msleep(8);
1163
07934481 1164 if (iop_adma_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
c2110923
DW		 1165 dev_printk(KERN_ERR, dma_chan->device->dev,
1166 "Self-test zero sum timed out, disabling\n");
1167 err = -ENODEV;
1168 goto free_resources;
1169 }
1170
1171 if (zero_sum_result != 0) {
1172 dev_printk(KERN_ERR, dma_chan->device->dev,
1173 "Self-test zero sum failed compare, disabling\n");
1174 err = -ENODEV;
1175 goto free_resources;
1176 }
1177
1178 /* test memset */
c2110923
DW		 1179 dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1180 PAGE_SIZE, DMA_FROM_DEVICE);
636bdeaa
DW		 1181 tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE,
1182 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
c2110923
DW		 1183
1184 cookie = iop_adma_tx_submit(tx);
1185 iop_adma_issue_pending(dma_chan);
c2110923
DW		 1186 msleep(8);
1187
07934481 1188 if (iop_adma_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
c2110923
DW		 1189 dev_printk(KERN_ERR, dma_chan->device->dev,
1190 "Self-test memset timed out, disabling\n");
1191 err = -ENODEV;
1192 goto free_resources;
1193 }
1194
1195 for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1196 u32 *ptr = page_address(dest);
1197 if (ptr[i]) {
1198 dev_printk(KERN_ERR, dma_chan->device->dev,
1199 "Self-test memset failed compare, disabling\n");
1200 err = -ENODEV;
1201 goto free_resources;
1202 }
1203 }
1204
1205 /* test for non-zero parity sum */
1206 zero_sum_result = 0;
0036731c
DW		 1207 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1208 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1209 zero_sum_srcs[i], 0, PAGE_SIZE,
1210 DMA_TO_DEVICE);
099f53cb
DW		 1211 tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs,
1212 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1213 &zero_sum_result,
1214 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
c2110923
DW		 1215
1216 cookie = iop_adma_tx_submit(tx);
1217 iop_adma_issue_pending(dma_chan);
c2110923
DW		 1218 msleep(8);
1219
07934481 1220 if (iop_adma_status(dma_chan, cookie, NULL) != DMA_SUCCESS) {
c2110923
DW		 1221 dev_printk(KERN_ERR, dma_chan->device->dev,
1222 "Self-test non-zero sum timed out, disabling\n");
1223 err = -ENODEV;
1224 goto free_resources;
1225 }
1226
1227 if (zero_sum_result != 1) {
1228 dev_printk(KERN_ERR, dma_chan->device->dev,
1229 "Self-test non-zero sum failed compare, disabling\n");
1230 err = -ENODEV;
1231 goto free_resources;
1232 }
1233
1234free_resources:
1235 iop_adma_free_chan_resources(dma_chan);
1236out:
1237 src_idx = IOP_ADMA_NUM_SRC_TEST;
1238 while (src_idx--)
1239 __free_page(xor_srcs[src_idx]);
1240 __free_page(dest);
1241 return err;
1242}
1243
0261f741 1244#ifdef CONFIG_RAID6_PQ
f6dbf651
DW		 1245static int __devinit
1246iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device)
1247{
1248 /* combined sources, software pq results, and extra hw pq results */
1249 struct page *pq[IOP_ADMA_NUM_SRC_TEST+2+2];
1250 /* ptr to the extra hw pq buffers defined above */
1251 struct page **pq_hw = &pq[IOP_ADMA_NUM_SRC_TEST+2];
1252 /* address conversion buffers (dma_map / page_address) */
1253 void *pq_sw[IOP_ADMA_NUM_SRC_TEST+2];
1254 dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST];
1255 dma_addr_t pq_dest[2];
1256
1257 int i;
1258 struct dma_async_tx_descriptor *tx;
1259 struct dma_chan *dma_chan;
1260 dma_cookie_t cookie;
1261 u32 zero_sum_result;
1262 int err = 0;
1263 struct device *dev;
1264
1265 dev_dbg(device->common.dev, "%s\n", __func__);
1266
1267 for (i = 0; i < ARRAY_SIZE(pq); i++) {
1268 pq[i] = alloc_page(GFP_KERNEL);
1269 if (!pq[i]) {
1270 while (i--)
1271 __free_page(pq[i]);
1272 return -ENOMEM;
1273 }
1274 }
1275
1276 /* Fill in src buffers */
1277 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) {
1278 pq_sw[i] = page_address(pq[i]);
1279 memset(pq_sw[i], 0x11111111 * (1<<i), PAGE_SIZE);
1280 }
1281 pq_sw[i] = page_address(pq[i]);
1282 pq_sw[i+1] = page_address(pq[i+1]);
1283
1284 dma_chan = container_of(device->common.channels.next,
1285 struct dma_chan,
1286 device_node);
1287 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
1288 err = -ENODEV;
1289 goto out;
1290 }
1291
1292 dev = dma_chan->device->dev;
1293
1294 /* initialize the dests */
1295 memset(page_address(pq_hw[0]), 0 , PAGE_SIZE);
1296 memset(page_address(pq_hw[1]), 0 , PAGE_SIZE);
1297
1298 /* test pq */
1299 pq_dest[0] = dma_map_page(dev, pq_hw[0], 0, PAGE_SIZE, DMA_FROM_DEVICE);
1300 pq_dest[1] = dma_map_page(dev, pq_hw[1], 0, PAGE_SIZE, DMA_FROM_DEVICE);
1301 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1302 pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
1303 DMA_TO_DEVICE);
1304
1305 tx = iop_adma_prep_dma_pq(dma_chan, pq_dest, pq_src,
1306 IOP_ADMA_NUM_SRC_TEST, (u8 *)raid6_gfexp,
1307 PAGE_SIZE,
1308 DMA_PREP_INTERRUPT |
1309 DMA_CTRL_ACK);
1310
1311 cookie = iop_adma_tx_submit(tx);
1312 iop_adma_issue_pending(dma_chan);
1313 msleep(8);
1314
07934481 1315 if (iop_adma_status(dma_chan, cookie, NULL) !=
f6dbf651
DW		 1316 DMA_SUCCESS) {
1317 dev_err(dev, "Self-test pq timed out, disabling\n");
1318 err = -ENODEV;
1319 goto free_resources;
1320 }
1321
1322 raid6_call.gen_syndrome(IOP_ADMA_NUM_SRC_TEST+2, PAGE_SIZE, pq_sw);
1323
1324 if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST],
1325 page_address(pq_hw[0]), PAGE_SIZE) != 0) {
1326 dev_err(dev, "Self-test p failed compare, disabling\n");
1327 err = -ENODEV;
1328 goto free_resources;
1329 }
1330 if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST+1],
1331 page_address(pq_hw[1]), PAGE_SIZE) != 0) {
1332 dev_err(dev, "Self-test q failed compare, disabling\n");
1333 err = -ENODEV;
1334 goto free_resources;
1335 }
1336
1337 /* test correct zero sum using the software generated pq values */
1338 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++)
1339 pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
1340 DMA_TO_DEVICE);
1341
1342 zero_sum_result = ~0;
1343 tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST],
1344 pq_src, IOP_ADMA_NUM_SRC_TEST,
1345 raid6_gfexp, PAGE_SIZE, &zero_sum_result,
1346 DMA_PREP_INTERRUPT|DMA_CTRL_ACK);
1347
1348 cookie = iop_adma_tx_submit(tx);
1349 iop_adma_issue_pending(dma_chan);
1350 msleep(8);
1351
07934481 1352 if (iop_adma_status(dma_chan, cookie, NULL) !=
f6dbf651
DW		 1353 DMA_SUCCESS) {
1354 dev_err(dev, "Self-test pq-zero-sum timed out, disabling\n");
1355 err = -ENODEV;
1356 goto free_resources;
1357 }
1358
1359 if (zero_sum_result != 0) {
1360 dev_err(dev, "Self-test pq-zero-sum failed to validate: %x\n",
1361 zero_sum_result);
1362 err = -ENODEV;
1363 goto free_resources;
1364 }
1365
1366 /* test incorrect zero sum */
1367 i = IOP_ADMA_NUM_SRC_TEST;
1368 memset(pq_sw[i] + 100, 0, 100);
1369 memset(pq_sw[i+1] + 200, 0, 200);
1370 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++)
1371 pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE,
1372 DMA_TO_DEVICE);
1373
1374 zero_sum_result = 0;
1375 tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST],
1376 pq_src, IOP_ADMA_NUM_SRC_TEST,
1377 raid6_gfexp, PAGE_SIZE, &zero_sum_result,
1378 DMA_PREP_INTERRUPT|DMA_CTRL_ACK);
1379
1380 cookie = iop_adma_tx_submit(tx);
1381 iop_adma_issue_pending(dma_chan);
1382 msleep(8);
1383
07934481 1384 if (iop_adma_status(dma_chan, cookie, NULL) !=
f6dbf651
DW		 1385 DMA_SUCCESS) {
1386 dev_err(dev, "Self-test !pq-zero-sum timed out, disabling\n");
1387 err = -ENODEV;
1388 goto free_resources;
1389 }
1390
1391 if (zero_sum_result != (SUM_CHECK_P_RESULT | SUM_CHECK_Q_RESULT)) {
1392 dev_err(dev, "Self-test !pq-zero-sum failed to validate: %x\n",
1393 zero_sum_result);
1394 err = -ENODEV;
1395 goto free_resources;
1396 }
1397
1398free_resources:
1399 iop_adma_free_chan_resources(dma_chan);
1400out:
1401 i = ARRAY_SIZE(pq);
1402 while (i--)
1403 __free_page(pq[i]);
1404 return err;
1405}
1406#endif
1407
c2110923
DW		 1408static int __devexit iop_adma_remove(struct platform_device *dev)
1409{
1410 struct iop_adma_device *device = platform_get_drvdata(dev);
1411 struct dma_chan *chan, *_chan;
1412 struct iop_adma_chan *iop_chan;
c2110923
DW		 1413 struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1414
1415 dma_async_device_unregister(&device->common);
1416
c2110923
DW		 1417 dma_free_coherent(&dev->dev, plat_data->pool_size,
1418 device->dma_desc_pool_virt, device->dma_desc_pool);
1419
c2110923
DW		 1420 list_for_each_entry_safe(chan, _chan, &device->common.channels,
1421 device_node) {
1422 iop_chan = to_iop_adma_chan(chan);
1423 list_del(&chan->device_node);
1424 kfree(iop_chan);
1425 }
1426 kfree(device);
1427
1428 return 0;
1429}
1430
1431static int __devinit iop_adma_probe(struct platform_device *pdev)
1432{
1433 struct resource *res;
1434 int ret = 0, i;
1435 struct iop_adma_device *adev;
1436 struct iop_adma_chan *iop_chan;
1437 struct dma_device *dma_dev;
1438 struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1439
1440 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1441 if (!res)
1442 return -ENODEV;
1443
1444 if (!devm_request_mem_region(&pdev->dev, res->start,
2e032b62 1445 resource_size(res), pdev->name))
c2110923
DW		 1446 return -EBUSY;
1447
1448 adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1449 if (!adev)
1450 return -ENOMEM;
1451 dma_dev = &adev->common;
1452
1453 /* allocate coherent memory for hardware descriptors
1454 * note: writecombine gives slightly better performance, but
1455 * requires that we explicitly flush the writes
1456 */
1457 if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1458 plat_data->pool_size,
1459 &adev->dma_desc_pool,
1460 GFP_KERNEL)) == NULL) {
1461 ret = -ENOMEM;
1462 goto err_free_adev;
1463 }
1464
1465 dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
3d9b525b 1466 __func__, adev->dma_desc_pool_virt,
c2110923
DW		 1467 (void *) adev->dma_desc_pool);
1468
1469 adev->id = plat_data->hw_id;
1470
1471 /* discover transaction capabilites from the platform data */
1472 dma_dev->cap_mask = plat_data->cap_mask;
1473
1474 adev->pdev = pdev;
1475 platform_set_drvdata(pdev, adev);
1476
1477 INIT_LIST_HEAD(&dma_dev->channels);
1478
1479 /* set base routines */
1480 dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1481 dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
07934481 1482 dma_dev->device_tx_status = iop_adma_status;
c2110923 1483 dma_dev->device_issue_pending = iop_adma_issue_pending;
c2110923
DW		 1484 dma_dev->dev = &pdev->dev;
1485
1486 /* set prep routines based on capability */
1487 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1488 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1489 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1490 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1491 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1492 dma_dev->max_xor = iop_adma_get_max_xor();
1493 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1494 }
099f53cb
DW		 1495 if (dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask))
1496 dma_dev->device_prep_dma_xor_val =
1497 iop_adma_prep_dma_xor_val;
7bf649ae
DW		 1498 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1499 dma_set_maxpq(dma_dev, iop_adma_get_max_pq(), 0);
1500 dma_dev->device_prep_dma_pq = iop_adma_prep_dma_pq;
1501 }
1502 if (dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask))
1503 dma_dev->device_prep_dma_pq_val =
1504 iop_adma_prep_dma_pq_val;
c2110923
DW		 1505 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1506 dma_dev->device_prep_dma_interrupt =
1507 iop_adma_prep_dma_interrupt;
1508
1509 iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1510 if (!iop_chan) {
1511 ret = -ENOMEM;
1512 goto err_free_dma;
1513 }
1514 iop_chan->device = adev;
1515
1516 iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
2e032b62 1517 resource_size(res));
c2110923
DW		 1518 if (!iop_chan->mmr_base) {
1519 ret = -ENOMEM;
1520 goto err_free_iop_chan;
1521 }
1522 tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1523 iop_chan);
1524
1525 /* clear errors before enabling interrupts */
1526 iop_adma_device_clear_err_status(iop_chan);
1527
1528 for (i = 0; i < 3; i++) {
1529 irq_handler_t handler[] = { iop_adma_eot_handler,
1530 iop_adma_eoc_handler,
1531 iop_adma_err_handler };
1532 int irq = platform_get_irq(pdev, i);
1533 if (irq < 0) {
1534 ret = -ENXIO;
1535 goto err_free_iop_chan;
1536 } else {
1537 ret = devm_request_irq(&pdev->dev, irq,
1538 handler[i], 0, pdev->name, iop_chan);
1539 if (ret)
1540 goto err_free_iop_chan;
1541 }
1542 }
1543
1544 spin_lock_init(&iop_chan->lock);
c2110923
DW		 1545 INIT_LIST_HEAD(&iop_chan->chain);
1546 INIT_LIST_HEAD(&iop_chan->all_slots);
c2110923 1547 iop_chan->common.device = dma_dev;
8ac69546 1548 dma_cookie_init(&iop_chan->common);
c2110923
DW		 1549 list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1550
1551 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1552 ret = iop_adma_memcpy_self_test(adev);
1553 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1554 if (ret)
1555 goto err_free_iop_chan;
1556 }
1557
1558 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
f6dbf651 1559 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
099f53cb 1560 ret = iop_adma_xor_val_self_test(adev);
c2110923
DW		 1561 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1562 if (ret)
1563 goto err_free_iop_chan;
1564 }
1565
f6dbf651
DW		 1566 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask) &&
1567 dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) {
0261f741 1568 #ifdef CONFIG_RAID6_PQ
f6dbf651
DW		 1569 ret = iop_adma_pq_zero_sum_self_test(adev);
1570 dev_dbg(&pdev->dev, "pq self test returned %d\n", ret);
1571 #else
1572 /* can not test raid6, so do not publish capability */
1573 dma_cap_clear(DMA_PQ, dma_dev->cap_mask);
1574 dma_cap_clear(DMA_PQ_VAL, dma_dev->cap_mask);
1575 ret = 0;
1576 #endif
1577 if (ret)
1578 goto err_free_iop_chan;
1579 }
1580
c2110923 1581 dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
9308add6 1582 "( %s%s%s%s%s%s%s)\n",
b2f46fd8 1583 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "",
099f53cb 1584 dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask) ? "pq_val " : "",
c2110923 1585 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
099f53cb 1586 dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask) ? "xor_val " : "",
c2110923 1587 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "",
c2110923
DW		 1588 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1589 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1590
1591 dma_async_device_register(dma_dev);
1592 goto out;
1593
1594 err_free_iop_chan:
1595 kfree(iop_chan);
1596 err_free_dma:
1597 dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1598 adev->dma_desc_pool_virt, adev->dma_desc_pool);
1599 err_free_adev:
1600 kfree(adev);
1601 out:
1602 return ret;
1603}
1604
1605static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1606{
1607 struct iop_adma_desc_slot *sw_desc, *grp_start;
1608 dma_cookie_t cookie;
1609 int slot_cnt, slots_per_op;
1610
3d9b525b 1611 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
c2110923
DW		 1612
1613 spin_lock_bh(&iop_chan->lock);
1614 slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1615 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1616 if (sw_desc) {
1617 grp_start = sw_desc->group_head;
1618
308136d1 1619 list_splice_init(&sw_desc->tx_list, &iop_chan->chain);
636bdeaa 1620 async_tx_ack(&sw_desc->async_tx);
c2110923
DW		 1621 iop_desc_init_memcpy(grp_start, 0);
1622 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1623 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1624 iop_desc_set_memcpy_src_addr(grp_start, 0);
1625
2a926e46 1626 cookie = dma_cookie_assign(&sw_desc->async_tx);
c2110923
DW		 1627
1628 /* initialize the completed cookie to be less than
1629 * the most recently used cookie
1630 */
4d4e58de 1631 iop_chan->common.completed_cookie = cookie - 1;
c2110923
DW		 1632
1633 /* channel should not be busy */
1634 BUG_ON(iop_chan_is_busy(iop_chan));
1635
1636 /* clear any prior error-status bits */
1637 iop_adma_device_clear_err_status(iop_chan);
1638
1639 /* disable operation */
1640 iop_chan_disable(iop_chan);
1641
1642 /* set the descriptor address */
1643 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1644
1645 /* 1/ don't add pre-chained descriptors
1646 * 2/ dummy read to flush next_desc write
1647 */
1648 BUG_ON(iop_desc_get_next_desc(sw_desc));
1649
1650 /* run the descriptor */
1651 iop_chan_enable(iop_chan);
1652 } else
1653 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1654 "failed to allocate null descriptor\n");
1655 spin_unlock_bh(&iop_chan->lock);
1656}
1657
1658static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1659{
1660 struct iop_adma_desc_slot *sw_desc, *grp_start;
1661 dma_cookie_t cookie;
1662 int slot_cnt, slots_per_op;
1663
3d9b525b 1664 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
c2110923
DW		 1665
1666 spin_lock_bh(&iop_chan->lock);
1667 slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1668 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1669 if (sw_desc) {
1670 grp_start = sw_desc->group_head;
308136d1 1671 list_splice_init(&sw_desc->tx_list, &iop_chan->chain);
636bdeaa 1672 async_tx_ack(&sw_desc->async_tx);
c2110923
DW		 1673 iop_desc_init_null_xor(grp_start, 2, 0);
1674 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1675 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1676 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1677 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1678
2a926e46 1679 cookie = dma_cookie_assign(&sw_desc->async_tx);
c2110923
DW		 1680
1681 /* initialize the completed cookie to be less than
1682 * the most recently used cookie
1683 */
4d4e58de 1684 iop_chan->common.completed_cookie = cookie - 1;
c2110923
DW		 1685
1686 /* channel should not be busy */
1687 BUG_ON(iop_chan_is_busy(iop_chan));
1688
1689 /* clear any prior error-status bits */
1690 iop_adma_device_clear_err_status(iop_chan);
1691
1692 /* disable operation */
1693 iop_chan_disable(iop_chan);
1694
1695 /* set the descriptor address */
1696 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1697
1698 /* 1/ don't add pre-chained descriptors
1699 * 2/ dummy read to flush next_desc write
1700 */
1701 BUG_ON(iop_desc_get_next_desc(sw_desc));
1702
1703 /* run the descriptor */
1704 iop_chan_enable(iop_chan);
1705 } else
1706 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1707 "failed to allocate null descriptor\n");
1708 spin_unlock_bh(&iop_chan->lock);
1709}
1710
1711static struct platform_driver iop_adma_driver = {
1712 .probe = iop_adma_probe,
bdf602bd 1713 .remove = __devexit_p(iop_adma_remove),
c2110923
DW		 1714 .driver = {
1715 .owner = THIS_MODULE,
1716 .name = "iop-adma",
1717 },
1718};
1719
c94e9105 1720module_platform_driver(iop_adma_driver);
c2110923
DW		 1721
1722MODULE_AUTHOR("Intel Corporation");
1723MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1724MODULE_LICENSE("GPL");
c94e9105 1725MODULE_ALIAS("platform:iop-adma");
Linux kernel - Deliverables
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