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8e6152bc ZG |
1 | /* |
2 | * Copyright (c) 2013 Linaro Ltd. | |
3 | * Copyright (c) 2013 Hisilicon Limited. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | #include <linux/sched.h> | |
10 | #include <linux/device.h> | |
11 | #include <linux/dmaengine.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/of_device.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/of_dma.h> | |
23 | ||
24 | #include "virt-dma.h" | |
25 | ||
26 | #define DRIVER_NAME "k3-dma" | |
27 | #define DMA_ALIGN 3 | |
28 | #define DMA_MAX_SIZE 0x1ffc | |
29 | ||
30 | #define INT_STAT 0x00 | |
31 | #define INT_TC1 0x04 | |
32 | #define INT_ERR1 0x0c | |
33 | #define INT_ERR2 0x10 | |
34 | #define INT_TC1_MASK 0x18 | |
35 | #define INT_ERR1_MASK 0x20 | |
36 | #define INT_ERR2_MASK 0x24 | |
37 | #define INT_TC1_RAW 0x600 | |
38 | #define INT_ERR1_RAW 0x608 | |
39 | #define INT_ERR2_RAW 0x610 | |
40 | #define CH_PRI 0x688 | |
41 | #define CH_STAT 0x690 | |
42 | #define CX_CUR_CNT 0x704 | |
43 | #define CX_LLI 0x800 | |
44 | #define CX_CNT 0x810 | |
45 | #define CX_SRC 0x814 | |
46 | #define CX_DST 0x818 | |
47 | #define CX_CFG 0x81c | |
48 | #define AXI_CFG 0x820 | |
49 | #define AXI_CFG_DEFAULT 0x201201 | |
50 | ||
51 | #define CX_LLI_CHAIN_EN 0x2 | |
52 | #define CX_CFG_EN 0x1 | |
53 | #define CX_CFG_MEM2PER (0x1 << 2) | |
54 | #define CX_CFG_PER2MEM (0x2 << 2) | |
55 | #define CX_CFG_SRCINCR (0x1 << 31) | |
56 | #define CX_CFG_DSTINCR (0x1 << 30) | |
57 | ||
58 | struct k3_desc_hw { | |
59 | u32 lli; | |
60 | u32 reserved[3]; | |
61 | u32 count; | |
62 | u32 saddr; | |
63 | u32 daddr; | |
64 | u32 config; | |
65 | } __aligned(32); | |
66 | ||
67 | struct k3_dma_desc_sw { | |
68 | struct virt_dma_desc vd; | |
69 | dma_addr_t desc_hw_lli; | |
70 | size_t desc_num; | |
71 | size_t size; | |
72 | struct k3_desc_hw desc_hw[0]; | |
73 | }; | |
74 | ||
75 | struct k3_dma_phy; | |
76 | ||
77 | struct k3_dma_chan { | |
78 | u32 ccfg; | |
79 | struct virt_dma_chan vc; | |
80 | struct k3_dma_phy *phy; | |
81 | struct list_head node; | |
82 | enum dma_transfer_direction dir; | |
83 | dma_addr_t dev_addr; | |
84 | enum dma_status status; | |
85 | }; | |
86 | ||
87 | struct k3_dma_phy { | |
88 | u32 idx; | |
89 | void __iomem *base; | |
90 | struct k3_dma_chan *vchan; | |
91 | struct k3_dma_desc_sw *ds_run; | |
92 | struct k3_dma_desc_sw *ds_done; | |
93 | }; | |
94 | ||
95 | struct k3_dma_dev { | |
96 | struct dma_device slave; | |
97 | void __iomem *base; | |
98 | struct tasklet_struct task; | |
99 | spinlock_t lock; | |
100 | struct list_head chan_pending; | |
101 | struct k3_dma_phy *phy; | |
102 | struct k3_dma_chan *chans; | |
103 | struct clk *clk; | |
104 | u32 dma_channels; | |
105 | u32 dma_requests; | |
106 | }; | |
107 | ||
108 | #define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave) | |
109 | ||
110 | static struct k3_dma_chan *to_k3_chan(struct dma_chan *chan) | |
111 | { | |
112 | return container_of(chan, struct k3_dma_chan, vc.chan); | |
113 | } | |
114 | ||
115 | static void k3_dma_pause_dma(struct k3_dma_phy *phy, bool on) | |
116 | { | |
117 | u32 val = 0; | |
118 | ||
119 | if (on) { | |
120 | val = readl_relaxed(phy->base + CX_CFG); | |
121 | val |= CX_CFG_EN; | |
122 | writel_relaxed(val, phy->base + CX_CFG); | |
123 | } else { | |
124 | val = readl_relaxed(phy->base + CX_CFG); | |
125 | val &= ~CX_CFG_EN; | |
126 | writel_relaxed(val, phy->base + CX_CFG); | |
127 | } | |
128 | } | |
129 | ||
130 | static void k3_dma_terminate_chan(struct k3_dma_phy *phy, struct k3_dma_dev *d) | |
131 | { | |
132 | u32 val = 0; | |
133 | ||
134 | k3_dma_pause_dma(phy, false); | |
135 | ||
136 | val = 0x1 << phy->idx; | |
137 | writel_relaxed(val, d->base + INT_TC1_RAW); | |
138 | writel_relaxed(val, d->base + INT_ERR1_RAW); | |
139 | writel_relaxed(val, d->base + INT_ERR2_RAW); | |
140 | } | |
141 | ||
142 | static void k3_dma_set_desc(struct k3_dma_phy *phy, struct k3_desc_hw *hw) | |
143 | { | |
144 | writel_relaxed(hw->lli, phy->base + CX_LLI); | |
145 | writel_relaxed(hw->count, phy->base + CX_CNT); | |
146 | writel_relaxed(hw->saddr, phy->base + CX_SRC); | |
147 | writel_relaxed(hw->daddr, phy->base + CX_DST); | |
148 | writel_relaxed(AXI_CFG_DEFAULT, phy->base + AXI_CFG); | |
149 | writel_relaxed(hw->config, phy->base + CX_CFG); | |
150 | } | |
151 | ||
152 | static u32 k3_dma_get_curr_cnt(struct k3_dma_dev *d, struct k3_dma_phy *phy) | |
153 | { | |
154 | u32 cnt = 0; | |
155 | ||
156 | cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10); | |
157 | cnt &= 0xffff; | |
158 | return cnt; | |
159 | } | |
160 | ||
161 | static u32 k3_dma_get_curr_lli(struct k3_dma_phy *phy) | |
162 | { | |
163 | return readl_relaxed(phy->base + CX_LLI); | |
164 | } | |
165 | ||
166 | static u32 k3_dma_get_chan_stat(struct k3_dma_dev *d) | |
167 | { | |
168 | return readl_relaxed(d->base + CH_STAT); | |
169 | } | |
170 | ||
171 | static void k3_dma_enable_dma(struct k3_dma_dev *d, bool on) | |
172 | { | |
173 | if (on) { | |
174 | /* set same priority */ | |
175 | writel_relaxed(0x0, d->base + CH_PRI); | |
176 | ||
177 | /* unmask irq */ | |
178 | writel_relaxed(0xffff, d->base + INT_TC1_MASK); | |
179 | writel_relaxed(0xffff, d->base + INT_ERR1_MASK); | |
180 | writel_relaxed(0xffff, d->base + INT_ERR2_MASK); | |
181 | } else { | |
182 | /* mask irq */ | |
183 | writel_relaxed(0x0, d->base + INT_TC1_MASK); | |
184 | writel_relaxed(0x0, d->base + INT_ERR1_MASK); | |
185 | writel_relaxed(0x0, d->base + INT_ERR2_MASK); | |
186 | } | |
187 | } | |
188 | ||
189 | static irqreturn_t k3_dma_int_handler(int irq, void *dev_id) | |
190 | { | |
191 | struct k3_dma_dev *d = (struct k3_dma_dev *)dev_id; | |
192 | struct k3_dma_phy *p; | |
193 | struct k3_dma_chan *c; | |
194 | u32 stat = readl_relaxed(d->base + INT_STAT); | |
195 | u32 tc1 = readl_relaxed(d->base + INT_TC1); | |
196 | u32 err1 = readl_relaxed(d->base + INT_ERR1); | |
197 | u32 err2 = readl_relaxed(d->base + INT_ERR2); | |
198 | u32 i, irq_chan = 0; | |
199 | ||
200 | while (stat) { | |
201 | i = __ffs(stat); | |
202 | stat &= (stat - 1); | |
203 | if (likely(tc1 & BIT(i))) { | |
204 | p = &d->phy[i]; | |
205 | c = p->vchan; | |
206 | if (c) { | |
207 | unsigned long flags; | |
208 | ||
209 | spin_lock_irqsave(&c->vc.lock, flags); | |
210 | vchan_cookie_complete(&p->ds_run->vd); | |
211 | p->ds_done = p->ds_run; | |
212 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
213 | } | |
214 | irq_chan |= BIT(i); | |
215 | } | |
216 | if (unlikely((err1 & BIT(i)) || (err2 & BIT(i)))) | |
217 | dev_warn(d->slave.dev, "DMA ERR\n"); | |
218 | } | |
219 | ||
220 | writel_relaxed(irq_chan, d->base + INT_TC1_RAW); | |
221 | writel_relaxed(err1, d->base + INT_ERR1_RAW); | |
222 | writel_relaxed(err2, d->base + INT_ERR2_RAW); | |
223 | ||
224 | if (irq_chan) { | |
225 | tasklet_schedule(&d->task); | |
226 | return IRQ_HANDLED; | |
227 | } else | |
228 | return IRQ_NONE; | |
229 | } | |
230 | ||
231 | static int k3_dma_start_txd(struct k3_dma_chan *c) | |
232 | { | |
233 | struct k3_dma_dev *d = to_k3_dma(c->vc.chan.device); | |
234 | struct virt_dma_desc *vd = vchan_next_desc(&c->vc); | |
235 | ||
236 | if (!c->phy) | |
237 | return -EAGAIN; | |
238 | ||
239 | if (BIT(c->phy->idx) & k3_dma_get_chan_stat(d)) | |
240 | return -EAGAIN; | |
241 | ||
242 | if (vd) { | |
243 | struct k3_dma_desc_sw *ds = | |
244 | container_of(vd, struct k3_dma_desc_sw, vd); | |
245 | /* | |
246 | * fetch and remove request from vc->desc_issued | |
247 | * so vc->desc_issued only contains desc pending | |
248 | */ | |
249 | list_del(&ds->vd.node); | |
250 | c->phy->ds_run = ds; | |
251 | c->phy->ds_done = NULL; | |
252 | /* start dma */ | |
253 | k3_dma_set_desc(c->phy, &ds->desc_hw[0]); | |
254 | return 0; | |
255 | } | |
256 | c->phy->ds_done = NULL; | |
257 | c->phy->ds_run = NULL; | |
258 | return -EAGAIN; | |
259 | } | |
260 | ||
261 | static void k3_dma_tasklet(unsigned long arg) | |
262 | { | |
263 | struct k3_dma_dev *d = (struct k3_dma_dev *)arg; | |
264 | struct k3_dma_phy *p; | |
265 | struct k3_dma_chan *c, *cn; | |
266 | unsigned pch, pch_alloc = 0; | |
267 | ||
268 | /* check new dma request of running channel in vc->desc_issued */ | |
269 | list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) { | |
270 | spin_lock_irq(&c->vc.lock); | |
271 | p = c->phy; | |
272 | if (p && p->ds_done) { | |
273 | if (k3_dma_start_txd(c)) { | |
274 | /* No current txd associated with this channel */ | |
275 | dev_dbg(d->slave.dev, "pchan %u: free\n", p->idx); | |
276 | /* Mark this channel free */ | |
277 | c->phy = NULL; | |
278 | p->vchan = NULL; | |
279 | } | |
280 | } | |
281 | spin_unlock_irq(&c->vc.lock); | |
282 | } | |
283 | ||
284 | /* check new channel request in d->chan_pending */ | |
285 | spin_lock_irq(&d->lock); | |
286 | for (pch = 0; pch < d->dma_channels; pch++) { | |
287 | p = &d->phy[pch]; | |
288 | ||
289 | if (p->vchan == NULL && !list_empty(&d->chan_pending)) { | |
290 | c = list_first_entry(&d->chan_pending, | |
291 | struct k3_dma_chan, node); | |
292 | /* remove from d->chan_pending */ | |
293 | list_del_init(&c->node); | |
294 | pch_alloc |= 1 << pch; | |
295 | /* Mark this channel allocated */ | |
296 | p->vchan = c; | |
297 | c->phy = p; | |
298 | dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc); | |
299 | } | |
300 | } | |
301 | spin_unlock_irq(&d->lock); | |
302 | ||
303 | for (pch = 0; pch < d->dma_channels; pch++) { | |
304 | if (pch_alloc & (1 << pch)) { | |
305 | p = &d->phy[pch]; | |
306 | c = p->vchan; | |
307 | if (c) { | |
308 | spin_lock_irq(&c->vc.lock); | |
309 | k3_dma_start_txd(c); | |
310 | spin_unlock_irq(&c->vc.lock); | |
311 | } | |
312 | } | |
313 | } | |
314 | } | |
315 | ||
8e6152bc ZG |
316 | static void k3_dma_free_chan_resources(struct dma_chan *chan) |
317 | { | |
318 | struct k3_dma_chan *c = to_k3_chan(chan); | |
319 | struct k3_dma_dev *d = to_k3_dma(chan->device); | |
320 | unsigned long flags; | |
321 | ||
322 | spin_lock_irqsave(&d->lock, flags); | |
323 | list_del_init(&c->node); | |
324 | spin_unlock_irqrestore(&d->lock, flags); | |
325 | ||
326 | vchan_free_chan_resources(&c->vc); | |
327 | c->ccfg = 0; | |
328 | } | |
329 | ||
330 | static enum dma_status k3_dma_tx_status(struct dma_chan *chan, | |
331 | dma_cookie_t cookie, struct dma_tx_state *state) | |
332 | { | |
333 | struct k3_dma_chan *c = to_k3_chan(chan); | |
334 | struct k3_dma_dev *d = to_k3_dma(chan->device); | |
335 | struct k3_dma_phy *p; | |
336 | struct virt_dma_desc *vd; | |
337 | unsigned long flags; | |
338 | enum dma_status ret; | |
339 | size_t bytes = 0; | |
340 | ||
341 | ret = dma_cookie_status(&c->vc.chan, cookie, state); | |
bd2c348e | 342 | if (ret == DMA_COMPLETE) |
8e6152bc ZG |
343 | return ret; |
344 | ||
345 | spin_lock_irqsave(&c->vc.lock, flags); | |
346 | p = c->phy; | |
347 | ret = c->status; | |
348 | ||
349 | /* | |
350 | * If the cookie is on our issue queue, then the residue is | |
351 | * its total size. | |
352 | */ | |
353 | vd = vchan_find_desc(&c->vc, cookie); | |
354 | if (vd) { | |
355 | bytes = container_of(vd, struct k3_dma_desc_sw, vd)->size; | |
356 | } else if ((!p) || (!p->ds_run)) { | |
357 | bytes = 0; | |
358 | } else { | |
359 | struct k3_dma_desc_sw *ds = p->ds_run; | |
360 | u32 clli = 0, index = 0; | |
361 | ||
362 | bytes = k3_dma_get_curr_cnt(d, p); | |
363 | clli = k3_dma_get_curr_lli(p); | |
364 | index = (clli - ds->desc_hw_lli) / sizeof(struct k3_desc_hw); | |
365 | for (; index < ds->desc_num; index++) { | |
366 | bytes += ds->desc_hw[index].count; | |
367 | /* end of lli */ | |
368 | if (!ds->desc_hw[index].lli) | |
369 | break; | |
370 | } | |
371 | } | |
372 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
373 | dma_set_residue(state, bytes); | |
374 | return ret; | |
375 | } | |
376 | ||
377 | static void k3_dma_issue_pending(struct dma_chan *chan) | |
378 | { | |
379 | struct k3_dma_chan *c = to_k3_chan(chan); | |
380 | struct k3_dma_dev *d = to_k3_dma(chan->device); | |
381 | unsigned long flags; | |
382 | ||
383 | spin_lock_irqsave(&c->vc.lock, flags); | |
384 | /* add request to vc->desc_issued */ | |
385 | if (vchan_issue_pending(&c->vc)) { | |
386 | spin_lock(&d->lock); | |
387 | if (!c->phy) { | |
388 | if (list_empty(&c->node)) { | |
389 | /* if new channel, add chan_pending */ | |
390 | list_add_tail(&c->node, &d->chan_pending); | |
391 | /* check in tasklet */ | |
392 | tasklet_schedule(&d->task); | |
393 | dev_dbg(d->slave.dev, "vchan %p: issued\n", &c->vc); | |
394 | } | |
395 | } | |
396 | spin_unlock(&d->lock); | |
397 | } else | |
398 | dev_dbg(d->slave.dev, "vchan %p: nothing to issue\n", &c->vc); | |
399 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
400 | } | |
401 | ||
402 | static void k3_dma_fill_desc(struct k3_dma_desc_sw *ds, dma_addr_t dst, | |
403 | dma_addr_t src, size_t len, u32 num, u32 ccfg) | |
404 | { | |
405 | if ((num + 1) < ds->desc_num) | |
406 | ds->desc_hw[num].lli = ds->desc_hw_lli + (num + 1) * | |
407 | sizeof(struct k3_desc_hw); | |
408 | ds->desc_hw[num].lli |= CX_LLI_CHAIN_EN; | |
409 | ds->desc_hw[num].count = len; | |
410 | ds->desc_hw[num].saddr = src; | |
411 | ds->desc_hw[num].daddr = dst; | |
412 | ds->desc_hw[num].config = ccfg; | |
413 | } | |
414 | ||
415 | static struct dma_async_tx_descriptor *k3_dma_prep_memcpy( | |
416 | struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, | |
417 | size_t len, unsigned long flags) | |
418 | { | |
419 | struct k3_dma_chan *c = to_k3_chan(chan); | |
420 | struct k3_dma_desc_sw *ds; | |
421 | size_t copy = 0; | |
422 | int num = 0; | |
423 | ||
424 | if (!len) | |
425 | return NULL; | |
426 | ||
427 | num = DIV_ROUND_UP(len, DMA_MAX_SIZE); | |
428 | ds = kzalloc(sizeof(*ds) + num * sizeof(ds->desc_hw[0]), GFP_ATOMIC); | |
429 | if (!ds) { | |
430 | dev_dbg(chan->device->dev, "vchan %p: kzalloc fail\n", &c->vc); | |
431 | return NULL; | |
432 | } | |
433 | ds->desc_hw_lli = __virt_to_phys((unsigned long)&ds->desc_hw[0]); | |
434 | ds->size = len; | |
435 | ds->desc_num = num; | |
436 | num = 0; | |
437 | ||
438 | if (!c->ccfg) { | |
db08425e | 439 | /* default is memtomem, without calling device_config */ |
8e6152bc ZG |
440 | c->ccfg = CX_CFG_SRCINCR | CX_CFG_DSTINCR | CX_CFG_EN; |
441 | c->ccfg |= (0xf << 20) | (0xf << 24); /* burst = 16 */ | |
442 | c->ccfg |= (0x3 << 12) | (0x3 << 16); /* width = 64 bit */ | |
443 | } | |
444 | ||
445 | do { | |
446 | copy = min_t(size_t, len, DMA_MAX_SIZE); | |
447 | k3_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg); | |
448 | ||
449 | if (c->dir == DMA_MEM_TO_DEV) { | |
450 | src += copy; | |
451 | } else if (c->dir == DMA_DEV_TO_MEM) { | |
452 | dst += copy; | |
453 | } else { | |
454 | src += copy; | |
455 | dst += copy; | |
456 | } | |
457 | len -= copy; | |
458 | } while (len); | |
459 | ||
460 | ds->desc_hw[num-1].lli = 0; /* end of link */ | |
461 | return vchan_tx_prep(&c->vc, &ds->vd, flags); | |
462 | } | |
463 | ||
464 | static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg( | |
465 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sglen, | |
466 | enum dma_transfer_direction dir, unsigned long flags, void *context) | |
467 | { | |
468 | struct k3_dma_chan *c = to_k3_chan(chan); | |
469 | struct k3_dma_desc_sw *ds; | |
470 | size_t len, avail, total = 0; | |
471 | struct scatterlist *sg; | |
472 | dma_addr_t addr, src = 0, dst = 0; | |
473 | int num = sglen, i; | |
474 | ||
c61177c5 | 475 | if (sgl == NULL) |
8e6152bc ZG |
476 | return NULL; |
477 | ||
478 | for_each_sg(sgl, sg, sglen, i) { | |
479 | avail = sg_dma_len(sg); | |
480 | if (avail > DMA_MAX_SIZE) | |
481 | num += DIV_ROUND_UP(avail, DMA_MAX_SIZE) - 1; | |
482 | } | |
483 | ||
484 | ds = kzalloc(sizeof(*ds) + num * sizeof(ds->desc_hw[0]), GFP_ATOMIC); | |
485 | if (!ds) { | |
486 | dev_dbg(chan->device->dev, "vchan %p: kzalloc fail\n", &c->vc); | |
487 | return NULL; | |
488 | } | |
489 | ds->desc_hw_lli = __virt_to_phys((unsigned long)&ds->desc_hw[0]); | |
490 | ds->desc_num = num; | |
491 | num = 0; | |
492 | ||
493 | for_each_sg(sgl, sg, sglen, i) { | |
494 | addr = sg_dma_address(sg); | |
495 | avail = sg_dma_len(sg); | |
496 | total += avail; | |
497 | ||
498 | do { | |
499 | len = min_t(size_t, avail, DMA_MAX_SIZE); | |
500 | ||
501 | if (dir == DMA_MEM_TO_DEV) { | |
502 | src = addr; | |
503 | dst = c->dev_addr; | |
504 | } else if (dir == DMA_DEV_TO_MEM) { | |
505 | src = c->dev_addr; | |
506 | dst = addr; | |
507 | } | |
508 | ||
509 | k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg); | |
510 | ||
511 | addr += len; | |
512 | avail -= len; | |
513 | } while (avail); | |
514 | } | |
515 | ||
516 | ds->desc_hw[num-1].lli = 0; /* end of link */ | |
517 | ds->size = total; | |
518 | return vchan_tx_prep(&c->vc, &ds->vd, flags); | |
519 | } | |
520 | ||
db08425e MR |
521 | static int k3_dma_config(struct dma_chan *chan, |
522 | struct dma_slave_config *cfg) | |
523 | { | |
524 | struct k3_dma_chan *c = to_k3_chan(chan); | |
525 | u32 maxburst = 0, val = 0; | |
526 | enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED; | |
527 | ||
528 | if (cfg == NULL) | |
529 | return -EINVAL; | |
530 | c->dir = cfg->direction; | |
531 | if (c->dir == DMA_DEV_TO_MEM) { | |
532 | c->ccfg = CX_CFG_DSTINCR; | |
533 | c->dev_addr = cfg->src_addr; | |
534 | maxburst = cfg->src_maxburst; | |
535 | width = cfg->src_addr_width; | |
536 | } else if (c->dir == DMA_MEM_TO_DEV) { | |
537 | c->ccfg = CX_CFG_SRCINCR; | |
538 | c->dev_addr = cfg->dst_addr; | |
539 | maxburst = cfg->dst_maxburst; | |
540 | width = cfg->dst_addr_width; | |
541 | } | |
542 | switch (width) { | |
543 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
544 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
545 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
546 | case DMA_SLAVE_BUSWIDTH_8_BYTES: | |
547 | val = __ffs(width); | |
548 | break; | |
549 | default: | |
550 | val = 3; | |
551 | break; | |
552 | } | |
553 | c->ccfg |= (val << 12) | (val << 16); | |
554 | ||
555 | if ((maxburst == 0) || (maxburst > 16)) | |
556 | val = 16; | |
557 | else | |
558 | val = maxburst - 1; | |
559 | c->ccfg |= (val << 20) | (val << 24); | |
560 | c->ccfg |= CX_CFG_MEM2PER | CX_CFG_EN; | |
561 | ||
562 | /* specific request line */ | |
563 | c->ccfg |= c->vc.chan.chan_id << 4; | |
564 | ||
565 | return 0; | |
566 | } | |
567 | ||
568 | static int k3_dma_terminate_all(struct dma_chan *chan) | |
8e6152bc ZG |
569 | { |
570 | struct k3_dma_chan *c = to_k3_chan(chan); | |
571 | struct k3_dma_dev *d = to_k3_dma(chan->device); | |
8e6152bc ZG |
572 | struct k3_dma_phy *p = c->phy; |
573 | unsigned long flags; | |
8e6152bc ZG |
574 | LIST_HEAD(head); |
575 | ||
db08425e | 576 | dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc); |
8e6152bc | 577 | |
db08425e MR |
578 | /* Prevent this channel being scheduled */ |
579 | spin_lock(&d->lock); | |
580 | list_del_init(&c->node); | |
581 | spin_unlock(&d->lock); | |
8e6152bc | 582 | |
db08425e MR |
583 | /* Clear the tx descriptor lists */ |
584 | spin_lock_irqsave(&c->vc.lock, flags); | |
585 | vchan_get_all_descriptors(&c->vc, &head); | |
586 | if (p) { | |
587 | /* vchan is assigned to a pchan - stop the channel */ | |
588 | k3_dma_terminate_chan(p, d); | |
589 | c->phy = NULL; | |
590 | p->vchan = NULL; | |
591 | p->ds_run = p->ds_done = NULL; | |
592 | } | |
593 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
594 | vchan_dma_desc_free_list(&c->vc, &head); | |
8e6152bc | 595 | |
db08425e MR |
596 | return 0; |
597 | } | |
8e6152bc | 598 | |
a1a9becb | 599 | static int k3_dma_transfer_pause(struct dma_chan *chan) |
db08425e MR |
600 | { |
601 | struct k3_dma_chan *c = to_k3_chan(chan); | |
602 | struct k3_dma_dev *d = to_k3_dma(chan->device); | |
603 | struct k3_dma_phy *p = c->phy; | |
8e6152bc | 604 | |
db08425e MR |
605 | dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc); |
606 | if (c->status == DMA_IN_PROGRESS) { | |
607 | c->status = DMA_PAUSED; | |
8e6152bc | 608 | if (p) { |
db08425e MR |
609 | k3_dma_pause_dma(p, false); |
610 | } else { | |
611 | spin_lock(&d->lock); | |
612 | list_del_init(&c->node); | |
613 | spin_unlock(&d->lock); | |
8e6152bc | 614 | } |
db08425e | 615 | } |
8e6152bc | 616 | |
db08425e MR |
617 | return 0; |
618 | } | |
8e6152bc | 619 | |
a1a9becb | 620 | static int k3_dma_transfer_resume(struct dma_chan *chan) |
db08425e MR |
621 | { |
622 | struct k3_dma_chan *c = to_k3_chan(chan); | |
623 | struct k3_dma_dev *d = to_k3_dma(chan->device); | |
624 | struct k3_dma_phy *p = c->phy; | |
625 | unsigned long flags; | |
626 | ||
627 | dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc); | |
628 | spin_lock_irqsave(&c->vc.lock, flags); | |
629 | if (c->status == DMA_PAUSED) { | |
630 | c->status = DMA_IN_PROGRESS; | |
631 | if (p) { | |
632 | k3_dma_pause_dma(p, true); | |
633 | } else if (!list_empty(&c->vc.desc_issued)) { | |
634 | spin_lock(&d->lock); | |
635 | list_add_tail(&c->node, &d->chan_pending); | |
636 | spin_unlock(&d->lock); | |
8e6152bc | 637 | } |
8e6152bc | 638 | } |
db08425e MR |
639 | spin_unlock_irqrestore(&c->vc.lock, flags); |
640 | ||
8e6152bc ZG |
641 | return 0; |
642 | } | |
643 | ||
644 | static void k3_dma_free_desc(struct virt_dma_desc *vd) | |
645 | { | |
646 | struct k3_dma_desc_sw *ds = | |
647 | container_of(vd, struct k3_dma_desc_sw, vd); | |
648 | ||
649 | kfree(ds); | |
650 | } | |
651 | ||
57c03422 | 652 | static const struct of_device_id k3_pdma_dt_ids[] = { |
8e6152bc ZG |
653 | { .compatible = "hisilicon,k3-dma-1.0", }, |
654 | {} | |
655 | }; | |
656 | MODULE_DEVICE_TABLE(of, k3_pdma_dt_ids); | |
657 | ||
658 | static struct dma_chan *k3_of_dma_simple_xlate(struct of_phandle_args *dma_spec, | |
659 | struct of_dma *ofdma) | |
660 | { | |
661 | struct k3_dma_dev *d = ofdma->of_dma_data; | |
662 | unsigned int request = dma_spec->args[0]; | |
663 | ||
664 | if (request > d->dma_requests) | |
665 | return NULL; | |
666 | ||
667 | return dma_get_slave_channel(&(d->chans[request].vc.chan)); | |
668 | } | |
669 | ||
670 | static int k3_dma_probe(struct platform_device *op) | |
671 | { | |
672 | struct k3_dma_dev *d; | |
673 | const struct of_device_id *of_id; | |
674 | struct resource *iores; | |
675 | int i, ret, irq = 0; | |
676 | ||
677 | iores = platform_get_resource(op, IORESOURCE_MEM, 0); | |
678 | if (!iores) | |
679 | return -EINVAL; | |
680 | ||
681 | d = devm_kzalloc(&op->dev, sizeof(*d), GFP_KERNEL); | |
682 | if (!d) | |
683 | return -ENOMEM; | |
684 | ||
a576b7fe JH |
685 | d->base = devm_ioremap_resource(&op->dev, iores); |
686 | if (IS_ERR(d->base)) | |
687 | return PTR_ERR(d->base); | |
8e6152bc ZG |
688 | |
689 | of_id = of_match_device(k3_pdma_dt_ids, &op->dev); | |
690 | if (of_id) { | |
691 | of_property_read_u32((&op->dev)->of_node, | |
692 | "dma-channels", &d->dma_channels); | |
693 | of_property_read_u32((&op->dev)->of_node, | |
694 | "dma-requests", &d->dma_requests); | |
695 | } | |
696 | ||
697 | d->clk = devm_clk_get(&op->dev, NULL); | |
698 | if (IS_ERR(d->clk)) { | |
699 | dev_err(&op->dev, "no dma clk\n"); | |
700 | return PTR_ERR(d->clk); | |
701 | } | |
702 | ||
703 | irq = platform_get_irq(op, 0); | |
704 | ret = devm_request_irq(&op->dev, irq, | |
174b537a | 705 | k3_dma_int_handler, 0, DRIVER_NAME, d); |
8e6152bc ZG |
706 | if (ret) |
707 | return ret; | |
708 | ||
709 | /* init phy channel */ | |
710 | d->phy = devm_kzalloc(&op->dev, | |
711 | d->dma_channels * sizeof(struct k3_dma_phy), GFP_KERNEL); | |
712 | if (d->phy == NULL) | |
713 | return -ENOMEM; | |
714 | ||
715 | for (i = 0; i < d->dma_channels; i++) { | |
716 | struct k3_dma_phy *p = &d->phy[i]; | |
717 | ||
718 | p->idx = i; | |
719 | p->base = d->base + i * 0x40; | |
720 | } | |
721 | ||
722 | INIT_LIST_HEAD(&d->slave.channels); | |
723 | dma_cap_set(DMA_SLAVE, d->slave.cap_mask); | |
724 | dma_cap_set(DMA_MEMCPY, d->slave.cap_mask); | |
725 | d->slave.dev = &op->dev; | |
8e6152bc ZG |
726 | d->slave.device_free_chan_resources = k3_dma_free_chan_resources; |
727 | d->slave.device_tx_status = k3_dma_tx_status; | |
728 | d->slave.device_prep_dma_memcpy = k3_dma_prep_memcpy; | |
729 | d->slave.device_prep_slave_sg = k3_dma_prep_slave_sg; | |
730 | d->slave.device_issue_pending = k3_dma_issue_pending; | |
db08425e | 731 | d->slave.device_config = k3_dma_config; |
a1a9becb KK |
732 | d->slave.device_pause = k3_dma_transfer_pause; |
733 | d->slave.device_resume = k3_dma_transfer_resume; | |
db08425e | 734 | d->slave.device_terminate_all = k3_dma_terminate_all; |
8e6152bc | 735 | d->slave.copy_align = DMA_ALIGN; |
8e6152bc ZG |
736 | |
737 | /* init virtual channel */ | |
738 | d->chans = devm_kzalloc(&op->dev, | |
739 | d->dma_requests * sizeof(struct k3_dma_chan), GFP_KERNEL); | |
740 | if (d->chans == NULL) | |
741 | return -ENOMEM; | |
742 | ||
743 | for (i = 0; i < d->dma_requests; i++) { | |
744 | struct k3_dma_chan *c = &d->chans[i]; | |
745 | ||
746 | c->status = DMA_IN_PROGRESS; | |
747 | INIT_LIST_HEAD(&c->node); | |
748 | c->vc.desc_free = k3_dma_free_desc; | |
749 | vchan_init(&c->vc, &d->slave); | |
750 | } | |
751 | ||
752 | /* Enable clock before accessing registers */ | |
753 | ret = clk_prepare_enable(d->clk); | |
754 | if (ret < 0) { | |
755 | dev_err(&op->dev, "clk_prepare_enable failed: %d\n", ret); | |
756 | return ret; | |
757 | } | |
758 | ||
759 | k3_dma_enable_dma(d, true); | |
760 | ||
761 | ret = dma_async_device_register(&d->slave); | |
762 | if (ret) | |
763 | return ret; | |
764 | ||
765 | ret = of_dma_controller_register((&op->dev)->of_node, | |
766 | k3_of_dma_simple_xlate, d); | |
767 | if (ret) | |
768 | goto of_dma_register_fail; | |
769 | ||
770 | spin_lock_init(&d->lock); | |
771 | INIT_LIST_HEAD(&d->chan_pending); | |
772 | tasklet_init(&d->task, k3_dma_tasklet, (unsigned long)d); | |
773 | platform_set_drvdata(op, d); | |
774 | dev_info(&op->dev, "initialized\n"); | |
775 | ||
776 | return 0; | |
777 | ||
778 | of_dma_register_fail: | |
779 | dma_async_device_unregister(&d->slave); | |
780 | return ret; | |
781 | } | |
782 | ||
783 | static int k3_dma_remove(struct platform_device *op) | |
784 | { | |
785 | struct k3_dma_chan *c, *cn; | |
786 | struct k3_dma_dev *d = platform_get_drvdata(op); | |
787 | ||
788 | dma_async_device_unregister(&d->slave); | |
789 | of_dma_controller_free((&op->dev)->of_node); | |
790 | ||
791 | list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) { | |
792 | list_del(&c->vc.chan.device_node); | |
793 | tasklet_kill(&c->vc.task); | |
794 | } | |
795 | tasklet_kill(&d->task); | |
796 | clk_disable_unprepare(d->clk); | |
797 | return 0; | |
798 | } | |
799 | ||
af2d3139 | 800 | #ifdef CONFIG_PM_SLEEP |
10b3e223 | 801 | static int k3_dma_suspend_dev(struct device *dev) |
8e6152bc ZG |
802 | { |
803 | struct k3_dma_dev *d = dev_get_drvdata(dev); | |
804 | u32 stat = 0; | |
805 | ||
806 | stat = k3_dma_get_chan_stat(d); | |
807 | if (stat) { | |
808 | dev_warn(d->slave.dev, | |
809 | "chan %d is running fail to suspend\n", stat); | |
810 | return -1; | |
811 | } | |
812 | k3_dma_enable_dma(d, false); | |
813 | clk_disable_unprepare(d->clk); | |
814 | return 0; | |
815 | } | |
816 | ||
10b3e223 | 817 | static int k3_dma_resume_dev(struct device *dev) |
8e6152bc ZG |
818 | { |
819 | struct k3_dma_dev *d = dev_get_drvdata(dev); | |
820 | int ret = 0; | |
821 | ||
822 | ret = clk_prepare_enable(d->clk); | |
823 | if (ret < 0) { | |
824 | dev_err(d->slave.dev, "clk_prepare_enable failed: %d\n", ret); | |
825 | return ret; | |
826 | } | |
827 | k3_dma_enable_dma(d, true); | |
828 | return 0; | |
829 | } | |
af2d3139 | 830 | #endif |
8e6152bc | 831 | |
10b3e223 | 832 | static SIMPLE_DEV_PM_OPS(k3_dma_pmops, k3_dma_suspend_dev, k3_dma_resume_dev); |
8e6152bc ZG |
833 | |
834 | static struct platform_driver k3_pdma_driver = { | |
835 | .driver = { | |
836 | .name = DRIVER_NAME, | |
8e6152bc ZG |
837 | .pm = &k3_dma_pmops, |
838 | .of_match_table = k3_pdma_dt_ids, | |
839 | }, | |
840 | .probe = k3_dma_probe, | |
841 | .remove = k3_dma_remove, | |
842 | }; | |
843 | ||
844 | module_platform_driver(k3_pdma_driver); | |
845 | ||
846 | MODULE_DESCRIPTION("Hisilicon k3 DMA Driver"); | |
847 | MODULE_ALIAS("platform:k3dma"); | |
848 | MODULE_LICENSE("GPL v2"); |