Commit | Line | Data |
---|---|---|
c6da0ba8 ZG |
1 | /* |
2 | * Driver For Marvell Two-channel DMA Engine | |
3 | * | |
4 | * Copyright: Marvell International Ltd. | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | */ | |
11 | ||
7331205a | 12 | #include <linux/err.h> |
c6da0ba8 ZG |
13 | #include <linux/module.h> |
14 | #include <linux/init.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/dma-mapping.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/dmaengine.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/device.h> | |
293b2da1 | 22 | #include <linux/platform_data/dma-mmp_tdma.h> |
f1a77570 | 23 | #include <linux/of_device.h> |
7dedc002 | 24 | #include <linux/of_dma.h> |
c6da0ba8 ZG |
25 | |
26 | #include "dmaengine.h" | |
27 | ||
28 | /* | |
29 | * Two-Channel DMA registers | |
30 | */ | |
31 | #define TDBCR 0x00 /* Byte Count */ | |
32 | #define TDSAR 0x10 /* Src Addr */ | |
33 | #define TDDAR 0x20 /* Dst Addr */ | |
34 | #define TDNDPR 0x30 /* Next Desc */ | |
35 | #define TDCR 0x40 /* Control */ | |
36 | #define TDCP 0x60 /* Priority*/ | |
37 | #define TDCDPR 0x70 /* Current Desc */ | |
38 | #define TDIMR 0x80 /* Int Mask */ | |
39 | #define TDISR 0xa0 /* Int Status */ | |
40 | ||
41 | /* Two-Channel DMA Control Register */ | |
42 | #define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */ | |
43 | #define TDCR_SSZ_12_BITS (0x1 << 22) | |
44 | #define TDCR_SSZ_16_BITS (0x2 << 22) | |
45 | #define TDCR_SSZ_20_BITS (0x3 << 22) | |
46 | #define TDCR_SSZ_24_BITS (0x4 << 22) | |
47 | #define TDCR_SSZ_32_BITS (0x5 << 22) | |
48 | #define TDCR_SSZ_SHIFT (0x1 << 22) | |
49 | #define TDCR_SSZ_MASK (0x7 << 22) | |
50 | #define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */ | |
51 | #define TDCR_ABR (0x1 << 20) /* Channel Abort */ | |
52 | #define TDCR_CDE (0x1 << 17) /* Close Desc Enable */ | |
53 | #define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */ | |
54 | #define TDCR_CHANACT (0x1 << 14) /* Channel Active */ | |
55 | #define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */ | |
56 | #define TDCR_CHANEN (0x1 << 12) /* Channel Enable */ | |
57 | #define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */ | |
58 | #define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */ | |
59 | #define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */ | |
60 | #define TDCR_BURSTSZ_4B (0x0 << 6) | |
61 | #define TDCR_BURSTSZ_8B (0x1 << 6) | |
62 | #define TDCR_BURSTSZ_16B (0x3 << 6) | |
63 | #define TDCR_BURSTSZ_32B (0x6 << 6) | |
64 | #define TDCR_BURSTSZ_64B (0x7 << 6) | |
20a90b0e QZ |
65 | #define TDCR_BURSTSZ_SQU_1B (0x5 << 6) |
66 | #define TDCR_BURSTSZ_SQU_2B (0x6 << 6) | |
67 | #define TDCR_BURSTSZ_SQU_4B (0x0 << 6) | |
68 | #define TDCR_BURSTSZ_SQU_8B (0x1 << 6) | |
69 | #define TDCR_BURSTSZ_SQU_16B (0x3 << 6) | |
c6da0ba8 ZG |
70 | #define TDCR_BURSTSZ_SQU_32B (0x7 << 6) |
71 | #define TDCR_BURSTSZ_128B (0x5 << 6) | |
72 | #define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */ | |
73 | #define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */ | |
74 | #define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */ | |
75 | #define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */ | |
76 | #define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */ | |
77 | #define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */ | |
78 | #define TDCR_DSTDESCCONT (0x1 << 1) | |
79 | #define TDCR_SRCDESTCONT (0x1 << 0) | |
80 | ||
81 | /* Two-Channel DMA Int Mask Register */ | |
82 | #define TDIMR_COMP (0x1 << 0) | |
83 | ||
84 | /* Two-Channel DMA Int Status Register */ | |
85 | #define TDISR_COMP (0x1 << 0) | |
86 | ||
87 | /* | |
88 | * Two-Channel DMA Descriptor Struct | |
89 | * NOTE: desc's buf must be aligned to 16 bytes. | |
90 | */ | |
91 | struct mmp_tdma_desc { | |
92 | u32 byte_cnt; | |
93 | u32 src_addr; | |
94 | u32 dst_addr; | |
95 | u32 nxt_desc; | |
96 | }; | |
97 | ||
98 | enum mmp_tdma_type { | |
99 | MMP_AUD_TDMA = 0, | |
100 | PXA910_SQU, | |
101 | }; | |
102 | ||
103 | #define TDMA_ALIGNMENT 3 | |
104 | #define TDMA_MAX_XFER_BYTES SZ_64K | |
105 | ||
106 | struct mmp_tdma_chan { | |
107 | struct device *dev; | |
108 | struct dma_chan chan; | |
109 | struct dma_async_tx_descriptor desc; | |
110 | struct tasklet_struct tasklet; | |
111 | ||
112 | struct mmp_tdma_desc *desc_arr; | |
1eed601a | 113 | dma_addr_t desc_arr_phys; |
c6da0ba8 ZG |
114 | int desc_num; |
115 | enum dma_transfer_direction dir; | |
116 | dma_addr_t dev_addr; | |
117 | u32 burst_sz; | |
118 | enum dma_slave_buswidth buswidth; | |
119 | enum dma_status status; | |
120 | ||
121 | int idx; | |
122 | enum mmp_tdma_type type; | |
123 | int irq; | |
9d0f1fa6 | 124 | void __iomem *reg_base; |
c6da0ba8 ZG |
125 | |
126 | size_t buf_len; | |
127 | size_t period_len; | |
128 | size_t pos; | |
3b0f4a54 NC |
129 | |
130 | struct gen_pool *pool; | |
c6da0ba8 ZG |
131 | }; |
132 | ||
133 | #define TDMA_CHANNEL_NUM 2 | |
134 | struct mmp_tdma_device { | |
135 | struct device *dev; | |
136 | void __iomem *base; | |
137 | struct dma_device device; | |
138 | struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM]; | |
c6da0ba8 ZG |
139 | }; |
140 | ||
141 | #define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan) | |
142 | ||
143 | static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys) | |
144 | { | |
145 | writel(phys, tdmac->reg_base + TDNDPR); | |
146 | writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND, | |
147 | tdmac->reg_base + TDCR); | |
148 | } | |
149 | ||
e6222263 QZ |
150 | static void mmp_tdma_enable_irq(struct mmp_tdma_chan *tdmac, bool enable) |
151 | { | |
152 | if (enable) | |
153 | writel(TDIMR_COMP, tdmac->reg_base + TDIMR); | |
154 | else | |
155 | writel(0, tdmac->reg_base + TDIMR); | |
156 | } | |
157 | ||
c6da0ba8 ZG |
158 | static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac) |
159 | { | |
c6da0ba8 ZG |
160 | /* enable dma chan */ |
161 | writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, | |
162 | tdmac->reg_base + TDCR); | |
163 | tdmac->status = DMA_IN_PROGRESS; | |
164 | } | |
165 | ||
f43a6fd4 | 166 | static int mmp_tdma_disable_chan(struct dma_chan *chan) |
c6da0ba8 | 167 | { |
f43a6fd4 | 168 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); |
1eed601a | 169 | u32 tdcr; |
f43a6fd4 | 170 | |
1eed601a QZ |
171 | tdcr = readl(tdmac->reg_base + TDCR); |
172 | tdcr |= TDCR_ABR; | |
173 | tdcr &= ~TDCR_CHANEN; | |
174 | writel(tdcr, tdmac->reg_base + TDCR); | |
8e3c518f | 175 | |
f64eabd0 | 176 | tdmac->status = DMA_COMPLETE; |
f43a6fd4 MR |
177 | |
178 | return 0; | |
c6da0ba8 ZG |
179 | } |
180 | ||
f43a6fd4 | 181 | static int mmp_tdma_resume_chan(struct dma_chan *chan) |
c6da0ba8 | 182 | { |
f43a6fd4 MR |
183 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); |
184 | ||
c6da0ba8 ZG |
185 | writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, |
186 | tdmac->reg_base + TDCR); | |
187 | tdmac->status = DMA_IN_PROGRESS; | |
f43a6fd4 MR |
188 | |
189 | return 0; | |
c6da0ba8 ZG |
190 | } |
191 | ||
f43a6fd4 | 192 | static int mmp_tdma_pause_chan(struct dma_chan *chan) |
c6da0ba8 | 193 | { |
f43a6fd4 MR |
194 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); |
195 | ||
c6da0ba8 ZG |
196 | writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, |
197 | tdmac->reg_base + TDCR); | |
198 | tdmac->status = DMA_PAUSED; | |
f43a6fd4 MR |
199 | |
200 | return 0; | |
c6da0ba8 ZG |
201 | } |
202 | ||
f43a6fd4 | 203 | static int mmp_tdma_config_chan(struct dma_chan *chan) |
c6da0ba8 | 204 | { |
f43a6fd4 | 205 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); |
a9ebbcd9 | 206 | unsigned int tdcr = 0; |
c6da0ba8 | 207 | |
f43a6fd4 | 208 | mmp_tdma_disable_chan(chan); |
c6da0ba8 ZG |
209 | |
210 | if (tdmac->dir == DMA_MEM_TO_DEV) | |
211 | tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC; | |
212 | else if (tdmac->dir == DMA_DEV_TO_MEM) | |
213 | tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC; | |
214 | ||
215 | if (tdmac->type == MMP_AUD_TDMA) { | |
216 | tdcr |= TDCR_PACKMOD; | |
217 | ||
218 | switch (tdmac->burst_sz) { | |
219 | case 4: | |
220 | tdcr |= TDCR_BURSTSZ_4B; | |
221 | break; | |
222 | case 8: | |
223 | tdcr |= TDCR_BURSTSZ_8B; | |
224 | break; | |
225 | case 16: | |
226 | tdcr |= TDCR_BURSTSZ_16B; | |
227 | break; | |
228 | case 32: | |
229 | tdcr |= TDCR_BURSTSZ_32B; | |
230 | break; | |
231 | case 64: | |
232 | tdcr |= TDCR_BURSTSZ_64B; | |
233 | break; | |
234 | case 128: | |
235 | tdcr |= TDCR_BURSTSZ_128B; | |
236 | break; | |
237 | default: | |
238 | dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n"); | |
239 | return -EINVAL; | |
240 | } | |
241 | ||
242 | switch (tdmac->buswidth) { | |
243 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
244 | tdcr |= TDCR_SSZ_8_BITS; | |
245 | break; | |
246 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
247 | tdcr |= TDCR_SSZ_16_BITS; | |
248 | break; | |
249 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
250 | tdcr |= TDCR_SSZ_32_BITS; | |
251 | break; | |
252 | default: | |
253 | dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n"); | |
254 | return -EINVAL; | |
255 | } | |
256 | } else if (tdmac->type == PXA910_SQU) { | |
c6da0ba8 | 257 | tdcr |= TDCR_SSPMOD; |
20a90b0e QZ |
258 | |
259 | switch (tdmac->burst_sz) { | |
260 | case 1: | |
261 | tdcr |= TDCR_BURSTSZ_SQU_1B; | |
262 | break; | |
263 | case 2: | |
264 | tdcr |= TDCR_BURSTSZ_SQU_2B; | |
265 | break; | |
266 | case 4: | |
267 | tdcr |= TDCR_BURSTSZ_SQU_4B; | |
268 | break; | |
269 | case 8: | |
270 | tdcr |= TDCR_BURSTSZ_SQU_8B; | |
271 | break; | |
272 | case 16: | |
273 | tdcr |= TDCR_BURSTSZ_SQU_16B; | |
274 | break; | |
275 | case 32: | |
276 | tdcr |= TDCR_BURSTSZ_SQU_32B; | |
277 | break; | |
278 | default: | |
279 | dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n"); | |
280 | return -EINVAL; | |
281 | } | |
c6da0ba8 ZG |
282 | } |
283 | ||
284 | writel(tdcr, tdmac->reg_base + TDCR); | |
285 | return 0; | |
286 | } | |
287 | ||
288 | static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac) | |
289 | { | |
290 | u32 reg = readl(tdmac->reg_base + TDISR); | |
291 | ||
292 | if (reg & TDISR_COMP) { | |
293 | /* clear irq */ | |
294 | reg &= ~TDISR_COMP; | |
295 | writel(reg, tdmac->reg_base + TDISR); | |
296 | ||
297 | return 0; | |
298 | } | |
299 | return -EAGAIN; | |
300 | } | |
301 | ||
1eed601a QZ |
302 | static size_t mmp_tdma_get_pos(struct mmp_tdma_chan *tdmac) |
303 | { | |
304 | size_t reg; | |
305 | ||
306 | if (tdmac->idx == 0) { | |
307 | reg = __raw_readl(tdmac->reg_base + TDSAR); | |
308 | reg -= tdmac->desc_arr[0].src_addr; | |
309 | } else if (tdmac->idx == 1) { | |
310 | reg = __raw_readl(tdmac->reg_base + TDDAR); | |
311 | reg -= tdmac->desc_arr[0].dst_addr; | |
312 | } else | |
313 | return -EINVAL; | |
314 | ||
315 | return reg; | |
316 | } | |
317 | ||
c6da0ba8 ZG |
318 | static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id) |
319 | { | |
320 | struct mmp_tdma_chan *tdmac = dev_id; | |
321 | ||
322 | if (mmp_tdma_clear_chan_irq(tdmac) == 0) { | |
c6da0ba8 ZG |
323 | tasklet_schedule(&tdmac->tasklet); |
324 | return IRQ_HANDLED; | |
325 | } else | |
326 | return IRQ_NONE; | |
327 | } | |
328 | ||
329 | static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id) | |
330 | { | |
331 | struct mmp_tdma_device *tdev = dev_id; | |
332 | int i, ret; | |
333 | int irq_num = 0; | |
334 | ||
335 | for (i = 0; i < TDMA_CHANNEL_NUM; i++) { | |
336 | struct mmp_tdma_chan *tdmac = tdev->tdmac[i]; | |
337 | ||
338 | ret = mmp_tdma_chan_handler(irq, tdmac); | |
339 | if (ret == IRQ_HANDLED) | |
340 | irq_num++; | |
341 | } | |
342 | ||
343 | if (irq_num) | |
344 | return IRQ_HANDLED; | |
345 | else | |
346 | return IRQ_NONE; | |
347 | } | |
348 | ||
349 | static void dma_do_tasklet(unsigned long data) | |
350 | { | |
351 | struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data; | |
352 | ||
353 | if (tdmac->desc.callback) | |
354 | tdmac->desc.callback(tdmac->desc.callback_param); | |
355 | ||
356 | } | |
357 | ||
358 | static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac) | |
359 | { | |
360 | struct gen_pool *gpool; | |
361 | int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc); | |
362 | ||
3b0f4a54 | 363 | gpool = tdmac->pool; |
1eed601a | 364 | if (gpool && tdmac->desc_arr) |
c6da0ba8 ZG |
365 | gen_pool_free(gpool, (unsigned long)tdmac->desc_arr, |
366 | size); | |
367 | tdmac->desc_arr = NULL; | |
368 | ||
369 | return; | |
370 | } | |
371 | ||
372 | static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx) | |
373 | { | |
374 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan); | |
375 | ||
376 | mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys); | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan) | |
382 | { | |
383 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
384 | int ret; | |
385 | ||
386 | dma_async_tx_descriptor_init(&tdmac->desc, chan); | |
387 | tdmac->desc.tx_submit = mmp_tdma_tx_submit; | |
388 | ||
389 | if (tdmac->irq) { | |
390 | ret = devm_request_irq(tdmac->dev, tdmac->irq, | |
174b537a | 391 | mmp_tdma_chan_handler, 0, "tdma", tdmac); |
c6da0ba8 ZG |
392 | if (ret) |
393 | return ret; | |
394 | } | |
395 | return 1; | |
396 | } | |
397 | ||
398 | static void mmp_tdma_free_chan_resources(struct dma_chan *chan) | |
399 | { | |
400 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
401 | ||
402 | if (tdmac->irq) | |
403 | devm_free_irq(tdmac->dev, tdmac->irq, tdmac); | |
404 | mmp_tdma_free_descriptor(tdmac); | |
405 | return; | |
406 | } | |
407 | ||
408 | struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac) | |
409 | { | |
410 | struct gen_pool *gpool; | |
411 | int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc); | |
412 | ||
3b0f4a54 | 413 | gpool = tdmac->pool; |
c6da0ba8 ZG |
414 | if (!gpool) |
415 | return NULL; | |
416 | ||
a6dd30e2 | 417 | tdmac->desc_arr = gen_pool_dma_alloc(gpool, size, &tdmac->desc_arr_phys); |
c6da0ba8 ZG |
418 | |
419 | return tdmac->desc_arr; | |
420 | } | |
421 | ||
422 | static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic( | |
423 | struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, | |
424 | size_t period_len, enum dma_transfer_direction direction, | |
31c1e5a1 | 425 | unsigned long flags) |
c6da0ba8 ZG |
426 | { |
427 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
428 | struct mmp_tdma_desc *desc; | |
429 | int num_periods = buf_len / period_len; | |
430 | int i = 0, buf = 0; | |
431 | ||
f64eabd0 | 432 | if (tdmac->status != DMA_COMPLETE) |
c6da0ba8 ZG |
433 | return NULL; |
434 | ||
435 | if (period_len > TDMA_MAX_XFER_BYTES) { | |
436 | dev_err(tdmac->dev, | |
437 | "maximum period size exceeded: %d > %d\n", | |
438 | period_len, TDMA_MAX_XFER_BYTES); | |
439 | goto err_out; | |
440 | } | |
441 | ||
442 | tdmac->status = DMA_IN_PROGRESS; | |
443 | tdmac->desc_num = num_periods; | |
444 | desc = mmp_tdma_alloc_descriptor(tdmac); | |
445 | if (!desc) | |
446 | goto err_out; | |
447 | ||
448 | while (buf < buf_len) { | |
449 | desc = &tdmac->desc_arr[i]; | |
450 | ||
451 | if (i + 1 == num_periods) | |
452 | desc->nxt_desc = tdmac->desc_arr_phys; | |
453 | else | |
454 | desc->nxt_desc = tdmac->desc_arr_phys + | |
455 | sizeof(*desc) * (i + 1); | |
456 | ||
457 | if (direction == DMA_MEM_TO_DEV) { | |
458 | desc->src_addr = dma_addr; | |
459 | desc->dst_addr = tdmac->dev_addr; | |
460 | } else { | |
461 | desc->src_addr = tdmac->dev_addr; | |
462 | desc->dst_addr = dma_addr; | |
463 | } | |
464 | desc->byte_cnt = period_len; | |
465 | dma_addr += period_len; | |
466 | buf += period_len; | |
467 | i++; | |
468 | } | |
469 | ||
e6222263 QZ |
470 | /* enable interrupt */ |
471 | if (flags & DMA_PREP_INTERRUPT) | |
472 | mmp_tdma_enable_irq(tdmac, true); | |
473 | ||
c6da0ba8 ZG |
474 | tdmac->buf_len = buf_len; |
475 | tdmac->period_len = period_len; | |
476 | tdmac->pos = 0; | |
477 | ||
478 | return &tdmac->desc; | |
479 | ||
480 | err_out: | |
481 | tdmac->status = DMA_ERROR; | |
482 | return NULL; | |
483 | } | |
484 | ||
f43a6fd4 | 485 | static int mmp_tdma_terminate_all(struct dma_chan *chan) |
c6da0ba8 ZG |
486 | { |
487 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
f43a6fd4 MR |
488 | |
489 | mmp_tdma_disable_chan(chan); | |
490 | /* disable interrupt */ | |
491 | mmp_tdma_enable_irq(tdmac, false); | |
3c20ba5f AB |
492 | |
493 | return 0; | |
f43a6fd4 MR |
494 | } |
495 | ||
496 | static int mmp_tdma_config(struct dma_chan *chan, | |
497 | struct dma_slave_config *dmaengine_cfg) | |
498 | { | |
499 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
500 | ||
501 | if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { | |
502 | tdmac->dev_addr = dmaengine_cfg->src_addr; | |
503 | tdmac->burst_sz = dmaengine_cfg->src_maxburst; | |
504 | tdmac->buswidth = dmaengine_cfg->src_addr_width; | |
505 | } else { | |
506 | tdmac->dev_addr = dmaengine_cfg->dst_addr; | |
507 | tdmac->burst_sz = dmaengine_cfg->dst_maxburst; | |
508 | tdmac->buswidth = dmaengine_cfg->dst_addr_width; | |
c6da0ba8 | 509 | } |
f43a6fd4 | 510 | tdmac->dir = dmaengine_cfg->direction; |
c6da0ba8 | 511 | |
f43a6fd4 | 512 | return mmp_tdma_config_chan(chan); |
c6da0ba8 ZG |
513 | } |
514 | ||
515 | static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan, | |
516 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
517 | { | |
518 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
519 | ||
1eed601a | 520 | tdmac->pos = mmp_tdma_get_pos(tdmac); |
c14d2bc4 AS |
521 | dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, |
522 | tdmac->buf_len - tdmac->pos); | |
c6da0ba8 ZG |
523 | |
524 | return tdmac->status; | |
525 | } | |
526 | ||
527 | static void mmp_tdma_issue_pending(struct dma_chan *chan) | |
528 | { | |
529 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
530 | ||
531 | mmp_tdma_enable_chan(tdmac); | |
532 | } | |
533 | ||
4bf27b8b | 534 | static int mmp_tdma_remove(struct platform_device *pdev) |
c6da0ba8 ZG |
535 | { |
536 | struct mmp_tdma_device *tdev = platform_get_drvdata(pdev); | |
537 | ||
538 | dma_async_device_unregister(&tdev->device); | |
539 | return 0; | |
540 | } | |
541 | ||
463a1f8b | 542 | static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev, |
3b0f4a54 NC |
543 | int idx, int irq, |
544 | int type, struct gen_pool *pool) | |
c6da0ba8 ZG |
545 | { |
546 | struct mmp_tdma_chan *tdmac; | |
547 | ||
548 | if (idx >= TDMA_CHANNEL_NUM) { | |
549 | dev_err(tdev->dev, "too many channels for device!\n"); | |
550 | return -EINVAL; | |
551 | } | |
552 | ||
553 | /* alloc channel */ | |
554 | tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL); | |
555 | if (!tdmac) { | |
556 | dev_err(tdev->dev, "no free memory for DMA channels!\n"); | |
557 | return -ENOMEM; | |
558 | } | |
559 | if (irq) | |
f1a77570 | 560 | tdmac->irq = irq; |
c6da0ba8 ZG |
561 | tdmac->dev = tdev->dev; |
562 | tdmac->chan.device = &tdev->device; | |
563 | tdmac->idx = idx; | |
564 | tdmac->type = type; | |
9d0f1fa6 | 565 | tdmac->reg_base = tdev->base + idx * 4; |
3b0f4a54 | 566 | tdmac->pool = pool; |
f64eabd0 | 567 | tdmac->status = DMA_COMPLETE; |
c6da0ba8 ZG |
568 | tdev->tdmac[tdmac->idx] = tdmac; |
569 | tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac); | |
570 | ||
571 | /* add the channel to tdma_chan list */ | |
572 | list_add_tail(&tdmac->chan.device_node, | |
573 | &tdev->device.channels); | |
c6da0ba8 ZG |
574 | return 0; |
575 | } | |
576 | ||
7dedc002 NC |
577 | struct mmp_tdma_filter_param { |
578 | struct device_node *of_node; | |
579 | unsigned int chan_id; | |
580 | }; | |
581 | ||
582 | static bool mmp_tdma_filter_fn(struct dma_chan *chan, void *fn_param) | |
583 | { | |
584 | struct mmp_tdma_filter_param *param = fn_param; | |
585 | struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan); | |
586 | struct dma_device *pdma_device = tdmac->chan.device; | |
587 | ||
588 | if (pdma_device->dev->of_node != param->of_node) | |
589 | return false; | |
590 | ||
591 | if (chan->chan_id != param->chan_id) | |
592 | return false; | |
593 | ||
594 | return true; | |
595 | } | |
596 | ||
597 | struct dma_chan *mmp_tdma_xlate(struct of_phandle_args *dma_spec, | |
598 | struct of_dma *ofdma) | |
599 | { | |
600 | struct mmp_tdma_device *tdev = ofdma->of_dma_data; | |
601 | dma_cap_mask_t mask = tdev->device.cap_mask; | |
602 | struct mmp_tdma_filter_param param; | |
603 | ||
604 | if (dma_spec->args_count != 1) | |
605 | return NULL; | |
606 | ||
607 | param.of_node = ofdma->of_node; | |
608 | param.chan_id = dma_spec->args[0]; | |
609 | ||
610 | if (param.chan_id >= TDMA_CHANNEL_NUM) | |
611 | return NULL; | |
612 | ||
613 | return dma_request_channel(mask, mmp_tdma_filter_fn, ¶m); | |
614 | } | |
615 | ||
57c03422 | 616 | static const struct of_device_id mmp_tdma_dt_ids[] = { |
f1a77570 ZG |
617 | { .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA}, |
618 | { .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU}, | |
619 | {} | |
620 | }; | |
621 | MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids); | |
622 | ||
463a1f8b | 623 | static int mmp_tdma_probe(struct platform_device *pdev) |
c6da0ba8 | 624 | { |
f1a77570 ZG |
625 | enum mmp_tdma_type type; |
626 | const struct of_device_id *of_id; | |
c6da0ba8 ZG |
627 | struct mmp_tdma_device *tdev; |
628 | struct resource *iores; | |
629 | int i, ret; | |
f1a77570 | 630 | int irq = 0, irq_num = 0; |
c6da0ba8 | 631 | int chan_num = TDMA_CHANNEL_NUM; |
1eed601a | 632 | struct gen_pool *pool = NULL; |
c6da0ba8 | 633 | |
f1a77570 ZG |
634 | of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev); |
635 | if (of_id) | |
636 | type = (enum mmp_tdma_type) of_id->data; | |
637 | else | |
638 | type = platform_get_device_id(pdev)->driver_data; | |
639 | ||
c6da0ba8 ZG |
640 | /* always have couple channels */ |
641 | tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL); | |
642 | if (!tdev) | |
643 | return -ENOMEM; | |
644 | ||
645 | tdev->dev = &pdev->dev; | |
c6da0ba8 | 646 | |
f1a77570 ZG |
647 | for (i = 0; i < chan_num; i++) { |
648 | if (platform_get_irq(pdev, i) > 0) | |
649 | irq_num++; | |
650 | } | |
c6da0ba8 ZG |
651 | |
652 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
7331205a TR |
653 | tdev->base = devm_ioremap_resource(&pdev->dev, iores); |
654 | if (IS_ERR(tdev->base)) | |
655 | return PTR_ERR(tdev->base); | |
c6da0ba8 | 656 | |
f1a77570 ZG |
657 | INIT_LIST_HEAD(&tdev->device.channels); |
658 | ||
3b0f4a54 | 659 | if (pdev->dev.of_node) |
abdd4a70 | 660 | pool = of_gen_pool_get(pdev->dev.of_node, "asram", 0); |
3b0f4a54 NC |
661 | else |
662 | pool = sram_get_gpool("asram"); | |
663 | if (!pool) { | |
664 | dev_err(&pdev->dev, "asram pool not available\n"); | |
665 | return -ENOMEM; | |
666 | } | |
667 | ||
f1a77570 ZG |
668 | if (irq_num != chan_num) { |
669 | irq = platform_get_irq(pdev, 0); | |
670 | ret = devm_request_irq(&pdev->dev, irq, | |
174b537a | 671 | mmp_tdma_int_handler, 0, "tdma", tdev); |
c6da0ba8 ZG |
672 | if (ret) |
673 | return ret; | |
674 | } | |
675 | ||
c6da0ba8 ZG |
676 | /* initialize channel parameters */ |
677 | for (i = 0; i < chan_num; i++) { | |
f1a77570 | 678 | irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i); |
3b0f4a54 | 679 | ret = mmp_tdma_chan_init(tdev, i, irq, type, pool); |
c6da0ba8 ZG |
680 | if (ret) |
681 | return ret; | |
682 | } | |
683 | ||
f1a77570 ZG |
684 | dma_cap_set(DMA_SLAVE, tdev->device.cap_mask); |
685 | dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask); | |
c6da0ba8 ZG |
686 | tdev->device.dev = &pdev->dev; |
687 | tdev->device.device_alloc_chan_resources = | |
688 | mmp_tdma_alloc_chan_resources; | |
689 | tdev->device.device_free_chan_resources = | |
690 | mmp_tdma_free_chan_resources; | |
691 | tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic; | |
692 | tdev->device.device_tx_status = mmp_tdma_tx_status; | |
693 | tdev->device.device_issue_pending = mmp_tdma_issue_pending; | |
f43a6fd4 MR |
694 | tdev->device.device_config = mmp_tdma_config; |
695 | tdev->device.device_pause = mmp_tdma_pause_chan; | |
696 | tdev->device.device_resume = mmp_tdma_resume_chan; | |
697 | tdev->device.device_terminate_all = mmp_tdma_terminate_all; | |
c6da0ba8 ZG |
698 | tdev->device.copy_align = TDMA_ALIGNMENT; |
699 | ||
700 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
701 | platform_set_drvdata(pdev, tdev); | |
702 | ||
703 | ret = dma_async_device_register(&tdev->device); | |
704 | if (ret) { | |
705 | dev_err(tdev->device.dev, "unable to register\n"); | |
706 | return ret; | |
707 | } | |
708 | ||
7dedc002 NC |
709 | if (pdev->dev.of_node) { |
710 | ret = of_dma_controller_register(pdev->dev.of_node, | |
711 | mmp_tdma_xlate, tdev); | |
712 | if (ret) { | |
713 | dev_err(tdev->device.dev, | |
714 | "failed to register controller\n"); | |
715 | dma_async_device_unregister(&tdev->device); | |
716 | } | |
717 | } | |
718 | ||
c6da0ba8 ZG |
719 | dev_info(tdev->device.dev, "initialized\n"); |
720 | return 0; | |
721 | } | |
722 | ||
723 | static const struct platform_device_id mmp_tdma_id_table[] = { | |
724 | { "mmp-adma", MMP_AUD_TDMA }, | |
725 | { "pxa910-squ", PXA910_SQU }, | |
726 | { }, | |
727 | }; | |
728 | ||
729 | static struct platform_driver mmp_tdma_driver = { | |
730 | .driver = { | |
731 | .name = "mmp-tdma", | |
f1a77570 | 732 | .of_match_table = mmp_tdma_dt_ids, |
c6da0ba8 ZG |
733 | }, |
734 | .id_table = mmp_tdma_id_table, | |
735 | .probe = mmp_tdma_probe, | |
a7d6e3ec | 736 | .remove = mmp_tdma_remove, |
c6da0ba8 ZG |
737 | }; |
738 | ||
739 | module_platform_driver(mmp_tdma_driver); | |
740 | ||
741 | MODULE_LICENSE("GPL"); | |
742 | MODULE_DESCRIPTION("MMP Two-Channel DMA Driver"); | |
743 | MODULE_ALIAS("platform:mmp-tdma"); | |
744 | MODULE_AUTHOR("Leo Yan <leoy@marvell.com>"); | |
745 | MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>"); |