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5f9e685a JJ |
1 | /* |
2 | * MOXA ART SoCs DMA Engine support. | |
3 | * | |
4 | * Copyright (C) 2013 Jonas Jensen | |
5 | * | |
6 | * Jonas Jensen <jonas.jensen@gmail.com> | |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public | |
9 | * License version 2. This program is licensed "as is" without any | |
10 | * warranty of any kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #include <linux/dmaengine.h> | |
14 | #include <linux/dma-mapping.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/list.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/of_address.h> | |
24 | #include <linux/of_irq.h> | |
25 | #include <linux/of_dma.h> | |
26 | #include <linux/bitops.h> | |
27 | ||
28 | #include <asm/cacheflush.h> | |
29 | ||
30 | #include "dmaengine.h" | |
31 | #include "virt-dma.h" | |
32 | ||
33 | #define APB_DMA_MAX_CHANNEL 4 | |
34 | ||
35 | #define REG_OFF_ADDRESS_SOURCE 0 | |
36 | #define REG_OFF_ADDRESS_DEST 4 | |
37 | #define REG_OFF_CYCLES 8 | |
38 | #define REG_OFF_CTRL 12 | |
39 | #define REG_OFF_CHAN_SIZE 16 | |
40 | ||
41 | #define APB_DMA_ENABLE BIT(0) | |
42 | #define APB_DMA_FIN_INT_STS BIT(1) | |
43 | #define APB_DMA_FIN_INT_EN BIT(2) | |
44 | #define APB_DMA_BURST_MODE BIT(3) | |
45 | #define APB_DMA_ERR_INT_STS BIT(4) | |
46 | #define APB_DMA_ERR_INT_EN BIT(5) | |
47 | ||
48 | /* | |
49 | * Unset: APB | |
50 | * Set: AHB | |
51 | */ | |
52 | #define APB_DMA_SOURCE_SELECT 0x40 | |
53 | #define APB_DMA_DEST_SELECT 0x80 | |
54 | ||
55 | #define APB_DMA_SOURCE 0x100 | |
56 | #define APB_DMA_DEST 0x1000 | |
57 | ||
58 | #define APB_DMA_SOURCE_MASK 0x700 | |
59 | #define APB_DMA_DEST_MASK 0x7000 | |
60 | ||
61 | /* | |
62 | * 000: No increment | |
63 | * 001: +1 (Burst=0), +4 (Burst=1) | |
64 | * 010: +2 (Burst=0), +8 (Burst=1) | |
65 | * 011: +4 (Burst=0), +16 (Burst=1) | |
66 | * 101: -1 (Burst=0), -4 (Burst=1) | |
67 | * 110: -2 (Burst=0), -8 (Burst=1) | |
68 | * 111: -4 (Burst=0), -16 (Burst=1) | |
69 | */ | |
70 | #define APB_DMA_SOURCE_INC_0 0 | |
71 | #define APB_DMA_SOURCE_INC_1_4 0x100 | |
72 | #define APB_DMA_SOURCE_INC_2_8 0x200 | |
73 | #define APB_DMA_SOURCE_INC_4_16 0x300 | |
74 | #define APB_DMA_SOURCE_DEC_1_4 0x500 | |
75 | #define APB_DMA_SOURCE_DEC_2_8 0x600 | |
76 | #define APB_DMA_SOURCE_DEC_4_16 0x700 | |
77 | #define APB_DMA_DEST_INC_0 0 | |
78 | #define APB_DMA_DEST_INC_1_4 0x1000 | |
79 | #define APB_DMA_DEST_INC_2_8 0x2000 | |
80 | #define APB_DMA_DEST_INC_4_16 0x3000 | |
81 | #define APB_DMA_DEST_DEC_1_4 0x5000 | |
82 | #define APB_DMA_DEST_DEC_2_8 0x6000 | |
83 | #define APB_DMA_DEST_DEC_4_16 0x7000 | |
84 | ||
85 | /* | |
86 | * Request signal select source/destination address for DMA hardware handshake. | |
87 | * | |
88 | * The request line number is a property of the DMA controller itself, | |
89 | * e.g. MMC must always request channels where dma_slave_config->slave_id is 5. | |
90 | * | |
91 | * 0: No request / Grant signal | |
92 | * 1-15: Request / Grant signal | |
93 | */ | |
94 | #define APB_DMA_SOURCE_REQ_NO 0x1000000 | |
95 | #define APB_DMA_SOURCE_REQ_NO_MASK 0xf000000 | |
96 | #define APB_DMA_DEST_REQ_NO 0x10000 | |
97 | #define APB_DMA_DEST_REQ_NO_MASK 0xf0000 | |
98 | ||
99 | #define APB_DMA_DATA_WIDTH 0x100000 | |
100 | #define APB_DMA_DATA_WIDTH_MASK 0x300000 | |
101 | /* | |
102 | * Data width of transfer: | |
103 | * | |
104 | * 00: Word | |
105 | * 01: Half | |
106 | * 10: Byte | |
107 | */ | |
108 | #define APB_DMA_DATA_WIDTH_4 0 | |
109 | #define APB_DMA_DATA_WIDTH_2 0x100000 | |
110 | #define APB_DMA_DATA_WIDTH_1 0x200000 | |
111 | ||
112 | #define APB_DMA_CYCLES_MASK 0x00ffffff | |
113 | ||
114 | #define MOXART_DMA_DATA_TYPE_S8 0x00 | |
115 | #define MOXART_DMA_DATA_TYPE_S16 0x01 | |
116 | #define MOXART_DMA_DATA_TYPE_S32 0x02 | |
117 | ||
118 | struct moxart_sg { | |
119 | dma_addr_t addr; | |
120 | uint32_t len; | |
121 | }; | |
122 | ||
123 | struct moxart_desc { | |
124 | enum dma_transfer_direction dma_dir; | |
125 | dma_addr_t dev_addr; | |
126 | unsigned int sglen; | |
127 | unsigned int dma_cycles; | |
128 | struct virt_dma_desc vd; | |
129 | uint8_t es; | |
130 | struct moxart_sg sg[0]; | |
131 | }; | |
132 | ||
133 | struct moxart_chan { | |
134 | struct virt_dma_chan vc; | |
135 | ||
136 | void __iomem *base; | |
137 | struct moxart_desc *desc; | |
138 | ||
139 | struct dma_slave_config cfg; | |
140 | ||
141 | bool allocated; | |
142 | bool error; | |
143 | int ch_num; | |
144 | unsigned int line_reqno; | |
145 | unsigned int sgidx; | |
146 | }; | |
147 | ||
148 | struct moxart_dmadev { | |
149 | struct dma_device dma_slave; | |
150 | struct moxart_chan slave_chans[APB_DMA_MAX_CHANNEL]; | |
151 | }; | |
152 | ||
153 | struct moxart_filter_data { | |
154 | struct moxart_dmadev *mdc; | |
155 | struct of_phandle_args *dma_spec; | |
156 | }; | |
157 | ||
158 | static const unsigned int es_bytes[] = { | |
159 | [MOXART_DMA_DATA_TYPE_S8] = 1, | |
160 | [MOXART_DMA_DATA_TYPE_S16] = 2, | |
161 | [MOXART_DMA_DATA_TYPE_S32] = 4, | |
162 | }; | |
163 | ||
164 | static struct device *chan2dev(struct dma_chan *chan) | |
165 | { | |
166 | return &chan->dev->device; | |
167 | } | |
168 | ||
169 | static inline struct moxart_chan *to_moxart_dma_chan(struct dma_chan *c) | |
170 | { | |
171 | return container_of(c, struct moxart_chan, vc.chan); | |
172 | } | |
173 | ||
174 | static inline struct moxart_desc *to_moxart_dma_desc( | |
175 | struct dma_async_tx_descriptor *t) | |
176 | { | |
177 | return container_of(t, struct moxart_desc, vd.tx); | |
178 | } | |
179 | ||
180 | static void moxart_dma_desc_free(struct virt_dma_desc *vd) | |
181 | { | |
182 | kfree(container_of(vd, struct moxart_desc, vd)); | |
183 | } | |
184 | ||
185 | static int moxart_terminate_all(struct dma_chan *chan) | |
186 | { | |
187 | struct moxart_chan *ch = to_moxart_dma_chan(chan); | |
188 | unsigned long flags; | |
189 | LIST_HEAD(head); | |
190 | u32 ctrl; | |
191 | ||
192 | dev_dbg(chan2dev(chan), "%s: ch=%p\n", __func__, ch); | |
193 | ||
194 | spin_lock_irqsave(&ch->vc.lock, flags); | |
195 | ||
fbef403a PU |
196 | if (ch->desc) { |
197 | moxart_dma_desc_free(&ch->desc->vd); | |
5f9e685a | 198 | ch->desc = NULL; |
fbef403a | 199 | } |
5f9e685a JJ |
200 | |
201 | ctrl = readl(ch->base + REG_OFF_CTRL); | |
202 | ctrl &= ~(APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN); | |
203 | writel(ctrl, ch->base + REG_OFF_CTRL); | |
204 | ||
205 | vchan_get_all_descriptors(&ch->vc, &head); | |
206 | spin_unlock_irqrestore(&ch->vc.lock, flags); | |
207 | vchan_dma_desc_free_list(&ch->vc, &head); | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
212 | static int moxart_slave_config(struct dma_chan *chan, | |
213 | struct dma_slave_config *cfg) | |
214 | { | |
215 | struct moxart_chan *ch = to_moxart_dma_chan(chan); | |
216 | u32 ctrl; | |
217 | ||
218 | ch->cfg = *cfg; | |
219 | ||
220 | ctrl = readl(ch->base + REG_OFF_CTRL); | |
221 | ctrl |= APB_DMA_BURST_MODE; | |
222 | ctrl &= ~(APB_DMA_DEST_MASK | APB_DMA_SOURCE_MASK); | |
223 | ctrl &= ~(APB_DMA_DEST_REQ_NO_MASK | APB_DMA_SOURCE_REQ_NO_MASK); | |
224 | ||
225 | switch (ch->cfg.src_addr_width) { | |
226 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
227 | ctrl |= APB_DMA_DATA_WIDTH_1; | |
228 | if (ch->cfg.direction != DMA_MEM_TO_DEV) | |
229 | ctrl |= APB_DMA_DEST_INC_1_4; | |
230 | else | |
231 | ctrl |= APB_DMA_SOURCE_INC_1_4; | |
232 | break; | |
233 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
234 | ctrl |= APB_DMA_DATA_WIDTH_2; | |
235 | if (ch->cfg.direction != DMA_MEM_TO_DEV) | |
236 | ctrl |= APB_DMA_DEST_INC_2_8; | |
237 | else | |
238 | ctrl |= APB_DMA_SOURCE_INC_2_8; | |
239 | break; | |
240 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
241 | ctrl &= ~APB_DMA_DATA_WIDTH; | |
242 | if (ch->cfg.direction != DMA_MEM_TO_DEV) | |
243 | ctrl |= APB_DMA_DEST_INC_4_16; | |
244 | else | |
245 | ctrl |= APB_DMA_SOURCE_INC_4_16; | |
246 | break; | |
247 | default: | |
248 | return -EINVAL; | |
249 | } | |
250 | ||
251 | if (ch->cfg.direction == DMA_MEM_TO_DEV) { | |
252 | ctrl &= ~APB_DMA_DEST_SELECT; | |
253 | ctrl |= APB_DMA_SOURCE_SELECT; | |
254 | ctrl |= (ch->line_reqno << 16 & | |
255 | APB_DMA_DEST_REQ_NO_MASK); | |
256 | } else { | |
257 | ctrl |= APB_DMA_DEST_SELECT; | |
258 | ctrl &= ~APB_DMA_SOURCE_SELECT; | |
259 | ctrl |= (ch->line_reqno << 24 & | |
260 | APB_DMA_SOURCE_REQ_NO_MASK); | |
261 | } | |
262 | ||
263 | writel(ctrl, ch->base + REG_OFF_CTRL); | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
5f9e685a JJ |
268 | static struct dma_async_tx_descriptor *moxart_prep_slave_sg( |
269 | struct dma_chan *chan, struct scatterlist *sgl, | |
270 | unsigned int sg_len, enum dma_transfer_direction dir, | |
271 | unsigned long tx_flags, void *context) | |
272 | { | |
273 | struct moxart_chan *ch = to_moxart_dma_chan(chan); | |
274 | struct moxart_desc *d; | |
275 | enum dma_slave_buswidth dev_width; | |
276 | dma_addr_t dev_addr; | |
277 | struct scatterlist *sgent; | |
278 | unsigned int es; | |
279 | unsigned int i; | |
280 | ||
281 | if (!is_slave_direction(dir)) { | |
282 | dev_err(chan2dev(chan), "%s: invalid DMA direction\n", | |
283 | __func__); | |
284 | return NULL; | |
285 | } | |
286 | ||
287 | if (dir == DMA_DEV_TO_MEM) { | |
288 | dev_addr = ch->cfg.src_addr; | |
289 | dev_width = ch->cfg.src_addr_width; | |
290 | } else { | |
291 | dev_addr = ch->cfg.dst_addr; | |
292 | dev_width = ch->cfg.dst_addr_width; | |
293 | } | |
294 | ||
295 | switch (dev_width) { | |
296 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
297 | es = MOXART_DMA_DATA_TYPE_S8; | |
298 | break; | |
299 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
300 | es = MOXART_DMA_DATA_TYPE_S16; | |
301 | break; | |
302 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
303 | es = MOXART_DMA_DATA_TYPE_S32; | |
304 | break; | |
305 | default: | |
306 | dev_err(chan2dev(chan), "%s: unsupported data width (%u)\n", | |
307 | __func__, dev_width); | |
308 | return NULL; | |
309 | } | |
310 | ||
311 | d = kzalloc(sizeof(*d) + sg_len * sizeof(d->sg[0]), GFP_ATOMIC); | |
312 | if (!d) | |
313 | return NULL; | |
314 | ||
315 | d->dma_dir = dir; | |
316 | d->dev_addr = dev_addr; | |
317 | d->es = es; | |
318 | ||
319 | for_each_sg(sgl, sgent, sg_len, i) { | |
320 | d->sg[i].addr = sg_dma_address(sgent); | |
321 | d->sg[i].len = sg_dma_len(sgent); | |
322 | } | |
323 | ||
324 | d->sglen = sg_len; | |
325 | ||
326 | ch->error = 0; | |
327 | ||
328 | return vchan_tx_prep(&ch->vc, &d->vd, tx_flags); | |
329 | } | |
330 | ||
331 | static struct dma_chan *moxart_of_xlate(struct of_phandle_args *dma_spec, | |
332 | struct of_dma *ofdma) | |
333 | { | |
334 | struct moxart_dmadev *mdc = ofdma->of_dma_data; | |
335 | struct dma_chan *chan; | |
336 | struct moxart_chan *ch; | |
337 | ||
338 | chan = dma_get_any_slave_channel(&mdc->dma_slave); | |
339 | if (!chan) | |
340 | return NULL; | |
341 | ||
342 | ch = to_moxart_dma_chan(chan); | |
343 | ch->line_reqno = dma_spec->args[0]; | |
344 | ||
345 | return chan; | |
346 | } | |
347 | ||
348 | static int moxart_alloc_chan_resources(struct dma_chan *chan) | |
349 | { | |
350 | struct moxart_chan *ch = to_moxart_dma_chan(chan); | |
351 | ||
352 | dev_dbg(chan2dev(chan), "%s: allocating channel #%u\n", | |
353 | __func__, ch->ch_num); | |
354 | ch->allocated = 1; | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | static void moxart_free_chan_resources(struct dma_chan *chan) | |
360 | { | |
361 | struct moxart_chan *ch = to_moxart_dma_chan(chan); | |
362 | ||
363 | vchan_free_chan_resources(&ch->vc); | |
364 | ||
365 | dev_dbg(chan2dev(chan), "%s: freeing channel #%u\n", | |
366 | __func__, ch->ch_num); | |
367 | ch->allocated = 0; | |
368 | } | |
369 | ||
370 | static void moxart_dma_set_params(struct moxart_chan *ch, dma_addr_t src_addr, | |
371 | dma_addr_t dst_addr) | |
372 | { | |
373 | writel(src_addr, ch->base + REG_OFF_ADDRESS_SOURCE); | |
374 | writel(dst_addr, ch->base + REG_OFF_ADDRESS_DEST); | |
375 | } | |
376 | ||
377 | static void moxart_set_transfer_params(struct moxart_chan *ch, unsigned int len) | |
378 | { | |
379 | struct moxart_desc *d = ch->desc; | |
380 | unsigned int sglen_div = es_bytes[d->es]; | |
381 | ||
382 | d->dma_cycles = len >> sglen_div; | |
383 | ||
384 | /* | |
385 | * There are 4 cycles on 64 bytes copied, i.e. one cycle copies 16 | |
386 | * bytes ( when width is APB_DMAB_DATA_WIDTH_4 ). | |
387 | */ | |
388 | writel(d->dma_cycles, ch->base + REG_OFF_CYCLES); | |
389 | ||
390 | dev_dbg(chan2dev(&ch->vc.chan), "%s: set %u DMA cycles (len=%u)\n", | |
391 | __func__, d->dma_cycles, len); | |
392 | } | |
393 | ||
394 | static void moxart_start_dma(struct moxart_chan *ch) | |
395 | { | |
396 | u32 ctrl; | |
397 | ||
398 | ctrl = readl(ch->base + REG_OFF_CTRL); | |
399 | ctrl |= (APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN); | |
400 | writel(ctrl, ch->base + REG_OFF_CTRL); | |
401 | } | |
402 | ||
403 | static void moxart_dma_start_sg(struct moxart_chan *ch, unsigned int idx) | |
404 | { | |
405 | struct moxart_desc *d = ch->desc; | |
406 | struct moxart_sg *sg = ch->desc->sg + idx; | |
407 | ||
408 | if (ch->desc->dma_dir == DMA_MEM_TO_DEV) | |
409 | moxart_dma_set_params(ch, sg->addr, d->dev_addr); | |
410 | else if (ch->desc->dma_dir == DMA_DEV_TO_MEM) | |
411 | moxart_dma_set_params(ch, d->dev_addr, sg->addr); | |
412 | ||
413 | moxart_set_transfer_params(ch, sg->len); | |
414 | ||
415 | moxart_start_dma(ch); | |
416 | } | |
417 | ||
418 | static void moxart_dma_start_desc(struct dma_chan *chan) | |
419 | { | |
420 | struct moxart_chan *ch = to_moxart_dma_chan(chan); | |
421 | struct virt_dma_desc *vd; | |
422 | ||
423 | vd = vchan_next_desc(&ch->vc); | |
424 | ||
425 | if (!vd) { | |
426 | ch->desc = NULL; | |
427 | return; | |
428 | } | |
429 | ||
430 | list_del(&vd->node); | |
431 | ||
432 | ch->desc = to_moxart_dma_desc(&vd->tx); | |
433 | ch->sgidx = 0; | |
434 | ||
435 | moxart_dma_start_sg(ch, 0); | |
436 | } | |
437 | ||
438 | static void moxart_issue_pending(struct dma_chan *chan) | |
439 | { | |
440 | struct moxart_chan *ch = to_moxart_dma_chan(chan); | |
441 | unsigned long flags; | |
442 | ||
443 | spin_lock_irqsave(&ch->vc.lock, flags); | |
444 | if (vchan_issue_pending(&ch->vc) && !ch->desc) | |
445 | moxart_dma_start_desc(chan); | |
446 | spin_unlock_irqrestore(&ch->vc.lock, flags); | |
447 | } | |
448 | ||
449 | static size_t moxart_dma_desc_size(struct moxart_desc *d, | |
450 | unsigned int completed_sgs) | |
451 | { | |
452 | unsigned int i; | |
453 | size_t size; | |
454 | ||
455 | for (size = i = completed_sgs; i < d->sglen; i++) | |
456 | size += d->sg[i].len; | |
457 | ||
458 | return size; | |
459 | } | |
460 | ||
461 | static size_t moxart_dma_desc_size_in_flight(struct moxart_chan *ch) | |
462 | { | |
463 | size_t size; | |
464 | unsigned int completed_cycles, cycles; | |
465 | ||
466 | size = moxart_dma_desc_size(ch->desc, ch->sgidx); | |
467 | cycles = readl(ch->base + REG_OFF_CYCLES); | |
468 | completed_cycles = (ch->desc->dma_cycles - cycles); | |
469 | size -= completed_cycles << es_bytes[ch->desc->es]; | |
470 | ||
471 | dev_dbg(chan2dev(&ch->vc.chan), "%s: size=%zu\n", __func__, size); | |
472 | ||
473 | return size; | |
474 | } | |
475 | ||
476 | static enum dma_status moxart_tx_status(struct dma_chan *chan, | |
477 | dma_cookie_t cookie, | |
478 | struct dma_tx_state *txstate) | |
479 | { | |
480 | struct moxart_chan *ch = to_moxart_dma_chan(chan); | |
481 | struct virt_dma_desc *vd; | |
482 | struct moxart_desc *d; | |
483 | enum dma_status ret; | |
484 | unsigned long flags; | |
485 | ||
486 | /* | |
487 | * dma_cookie_status() assigns initial residue value. | |
488 | */ | |
489 | ret = dma_cookie_status(chan, cookie, txstate); | |
490 | ||
491 | spin_lock_irqsave(&ch->vc.lock, flags); | |
492 | vd = vchan_find_desc(&ch->vc, cookie); | |
493 | if (vd) { | |
494 | d = to_moxart_dma_desc(&vd->tx); | |
495 | txstate->residue = moxart_dma_desc_size(d, 0); | |
496 | } else if (ch->desc && ch->desc->vd.tx.cookie == cookie) { | |
497 | txstate->residue = moxart_dma_desc_size_in_flight(ch); | |
498 | } | |
499 | spin_unlock_irqrestore(&ch->vc.lock, flags); | |
500 | ||
501 | if (ch->error) | |
502 | return DMA_ERROR; | |
503 | ||
504 | return ret; | |
505 | } | |
506 | ||
507 | static void moxart_dma_init(struct dma_device *dma, struct device *dev) | |
508 | { | |
509 | dma->device_prep_slave_sg = moxart_prep_slave_sg; | |
510 | dma->device_alloc_chan_resources = moxart_alloc_chan_resources; | |
511 | dma->device_free_chan_resources = moxart_free_chan_resources; | |
512 | dma->device_issue_pending = moxart_issue_pending; | |
513 | dma->device_tx_status = moxart_tx_status; | |
ac850cc7 MR |
514 | dma->device_config = moxart_slave_config; |
515 | dma->device_terminate_all = moxart_terminate_all; | |
5f9e685a JJ |
516 | dma->dev = dev; |
517 | ||
518 | INIT_LIST_HEAD(&dma->channels); | |
519 | } | |
520 | ||
521 | static irqreturn_t moxart_dma_interrupt(int irq, void *devid) | |
522 | { | |
523 | struct moxart_dmadev *mc = devid; | |
524 | struct moxart_chan *ch = &mc->slave_chans[0]; | |
525 | unsigned int i; | |
526 | unsigned long flags; | |
527 | u32 ctrl; | |
528 | ||
529 | dev_dbg(chan2dev(&ch->vc.chan), "%s\n", __func__); | |
530 | ||
531 | for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) { | |
532 | if (!ch->allocated) | |
533 | continue; | |
534 | ||
535 | ctrl = readl(ch->base + REG_OFF_CTRL); | |
536 | ||
537 | dev_dbg(chan2dev(&ch->vc.chan), "%s: ch=%p ch->base=%p ctrl=%x\n", | |
538 | __func__, ch, ch->base, ctrl); | |
539 | ||
540 | if (ctrl & APB_DMA_FIN_INT_STS) { | |
541 | ctrl &= ~APB_DMA_FIN_INT_STS; | |
542 | if (ch->desc) { | |
543 | spin_lock_irqsave(&ch->vc.lock, flags); | |
544 | if (++ch->sgidx < ch->desc->sglen) { | |
545 | moxart_dma_start_sg(ch, ch->sgidx); | |
546 | } else { | |
547 | vchan_cookie_complete(&ch->desc->vd); | |
548 | moxart_dma_start_desc(&ch->vc.chan); | |
549 | } | |
550 | spin_unlock_irqrestore(&ch->vc.lock, flags); | |
551 | } | |
552 | } | |
553 | ||
554 | if (ctrl & APB_DMA_ERR_INT_STS) { | |
555 | ctrl &= ~APB_DMA_ERR_INT_STS; | |
556 | ch->error = 1; | |
557 | } | |
558 | ||
559 | writel(ctrl, ch->base + REG_OFF_CTRL); | |
560 | } | |
561 | ||
562 | return IRQ_HANDLED; | |
563 | } | |
564 | ||
565 | static int moxart_probe(struct platform_device *pdev) | |
566 | { | |
567 | struct device *dev = &pdev->dev; | |
568 | struct device_node *node = dev->of_node; | |
569 | struct resource *res; | |
570 | static void __iomem *dma_base_addr; | |
571 | int ret, i; | |
572 | unsigned int irq; | |
573 | struct moxart_chan *ch; | |
574 | struct moxart_dmadev *mdc; | |
575 | ||
576 | mdc = devm_kzalloc(dev, sizeof(*mdc), GFP_KERNEL); | |
577 | if (!mdc) { | |
578 | dev_err(dev, "can't allocate DMA container\n"); | |
579 | return -ENOMEM; | |
580 | } | |
581 | ||
582 | irq = irq_of_parse_and_map(node, 0); | |
583 | if (irq == NO_IRQ) { | |
584 | dev_err(dev, "no IRQ resource\n"); | |
585 | return -EINVAL; | |
586 | } | |
587 | ||
588 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
589 | dma_base_addr = devm_ioremap_resource(dev, res); | |
590 | if (IS_ERR(dma_base_addr)) | |
591 | return PTR_ERR(dma_base_addr); | |
592 | ||
593 | dma_cap_zero(mdc->dma_slave.cap_mask); | |
594 | dma_cap_set(DMA_SLAVE, mdc->dma_slave.cap_mask); | |
595 | dma_cap_set(DMA_PRIVATE, mdc->dma_slave.cap_mask); | |
596 | ||
597 | moxart_dma_init(&mdc->dma_slave, dev); | |
598 | ||
599 | ch = &mdc->slave_chans[0]; | |
600 | for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) { | |
601 | ch->ch_num = i; | |
602 | ch->base = dma_base_addr + i * REG_OFF_CHAN_SIZE; | |
603 | ch->allocated = 0; | |
604 | ||
605 | ch->vc.desc_free = moxart_dma_desc_free; | |
606 | vchan_init(&ch->vc, &mdc->dma_slave); | |
607 | ||
608 | dev_dbg(dev, "%s: chs[%d]: ch->ch_num=%u ch->base=%p\n", | |
609 | __func__, i, ch->ch_num, ch->base); | |
610 | } | |
611 | ||
612 | platform_set_drvdata(pdev, mdc); | |
613 | ||
614 | ret = devm_request_irq(dev, irq, moxart_dma_interrupt, 0, | |
615 | "moxart-dma-engine", mdc); | |
616 | if (ret) { | |
617 | dev_err(dev, "devm_request_irq failed\n"); | |
618 | return ret; | |
619 | } | |
620 | ||
621 | ret = dma_async_device_register(&mdc->dma_slave); | |
622 | if (ret) { | |
623 | dev_err(dev, "dma_async_device_register failed\n"); | |
624 | return ret; | |
625 | } | |
626 | ||
627 | ret = of_dma_controller_register(node, moxart_of_xlate, mdc); | |
628 | if (ret) { | |
629 | dev_err(dev, "of_dma_controller_register failed\n"); | |
630 | dma_async_device_unregister(&mdc->dma_slave); | |
631 | return ret; | |
632 | } | |
633 | ||
634 | dev_dbg(dev, "%s: IRQ=%u\n", __func__, irq); | |
635 | ||
636 | return 0; | |
637 | } | |
638 | ||
639 | static int moxart_remove(struct platform_device *pdev) | |
640 | { | |
641 | struct moxart_dmadev *m = platform_get_drvdata(pdev); | |
642 | ||
643 | dma_async_device_unregister(&m->dma_slave); | |
644 | ||
645 | if (pdev->dev.of_node) | |
646 | of_dma_controller_free(pdev->dev.of_node); | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | static const struct of_device_id moxart_dma_match[] = { | |
652 | { .compatible = "moxa,moxart-dma" }, | |
653 | { } | |
654 | }; | |
981ec2b2 | 655 | MODULE_DEVICE_TABLE(of, moxart_dma_match); |
5f9e685a JJ |
656 | |
657 | static struct platform_driver moxart_driver = { | |
658 | .probe = moxart_probe, | |
659 | .remove = moxart_remove, | |
660 | .driver = { | |
661 | .name = "moxart-dma-engine", | |
5f9e685a JJ |
662 | .of_match_table = moxart_dma_match, |
663 | }, | |
664 | }; | |
665 | ||
666 | static int moxart_init(void) | |
667 | { | |
668 | return platform_driver_register(&moxart_driver); | |
669 | } | |
670 | subsys_initcall(moxart_init); | |
671 | ||
672 | static void __exit moxart_exit(void) | |
673 | { | |
674 | platform_driver_unregister(&moxart_driver); | |
675 | } | |
676 | module_exit(moxart_exit); | |
677 | ||
678 | MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>"); | |
679 | MODULE_DESCRIPTION("MOXART DMA engine driver"); | |
680 | MODULE_LICENSE("GPL v2"); |