Commit | Line | Data |
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ff7b0479 SB |
1 | /* |
2 | * offload engine driver for the Marvell XOR engine | |
3 | * Copyright (C) 2007, 2008, Marvell International Ltd. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/module.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
ff7b0479 SB |
22 | #include <linux/delay.h> |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/spinlock.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/memory.h> | |
c510182b | 28 | #include <linux/clk.h> |
f7d12ef5 TP |
29 | #include <linux/of.h> |
30 | #include <linux/of_irq.h> | |
31 | #include <linux/irqdomain.h> | |
c02cecb9 | 32 | #include <linux/platform_data/dma-mv_xor.h> |
d2ebfb33 RKAL |
33 | |
34 | #include "dmaengine.h" | |
ff7b0479 SB |
35 | #include "mv_xor.h" |
36 | ||
37 | static void mv_xor_issue_pending(struct dma_chan *chan); | |
38 | ||
39 | #define to_mv_xor_chan(chan) \ | |
98817b99 | 40 | container_of(chan, struct mv_xor_chan, dmachan) |
ff7b0479 SB |
41 | |
42 | #define to_mv_xor_slot(tx) \ | |
43 | container_of(tx, struct mv_xor_desc_slot, async_tx) | |
44 | ||
c98c1781 | 45 | #define mv_chan_to_devp(chan) \ |
1ef48a26 | 46 | ((chan)->dmadev.dev) |
c98c1781 | 47 | |
ff7b0479 SB |
48 | static void mv_desc_init(struct mv_xor_desc_slot *desc, unsigned long flags) |
49 | { | |
50 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
51 | ||
52 | hw_desc->status = (1 << 31); | |
53 | hw_desc->phy_next_desc = 0; | |
54 | hw_desc->desc_command = (1 << 31); | |
55 | } | |
56 | ||
57 | static u32 mv_desc_get_dest_addr(struct mv_xor_desc_slot *desc) | |
58 | { | |
59 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
60 | return hw_desc->phy_dest_addr; | |
61 | } | |
62 | ||
ff7b0479 SB |
63 | static void mv_desc_set_byte_count(struct mv_xor_desc_slot *desc, |
64 | u32 byte_count) | |
65 | { | |
66 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
67 | hw_desc->byte_count = byte_count; | |
68 | } | |
69 | ||
70 | static void mv_desc_set_next_desc(struct mv_xor_desc_slot *desc, | |
71 | u32 next_desc_addr) | |
72 | { | |
73 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
74 | BUG_ON(hw_desc->phy_next_desc); | |
75 | hw_desc->phy_next_desc = next_desc_addr; | |
76 | } | |
77 | ||
78 | static void mv_desc_clear_next_desc(struct mv_xor_desc_slot *desc) | |
79 | { | |
80 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
81 | hw_desc->phy_next_desc = 0; | |
82 | } | |
83 | ||
ff7b0479 SB |
84 | static void mv_desc_set_dest_addr(struct mv_xor_desc_slot *desc, |
85 | dma_addr_t addr) | |
86 | { | |
87 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
88 | hw_desc->phy_dest_addr = addr; | |
89 | } | |
90 | ||
91 | static int mv_chan_memset_slot_count(size_t len) | |
92 | { | |
93 | return 1; | |
94 | } | |
95 | ||
96 | #define mv_chan_memcpy_slot_count(c) mv_chan_memset_slot_count(c) | |
97 | ||
98 | static void mv_desc_set_src_addr(struct mv_xor_desc_slot *desc, | |
99 | int index, dma_addr_t addr) | |
100 | { | |
101 | struct mv_xor_desc *hw_desc = desc->hw_desc; | |
e03bc654 | 102 | hw_desc->phy_src_addr[mv_phy_src_idx(index)] = addr; |
ff7b0479 SB |
103 | if (desc->type == DMA_XOR) |
104 | hw_desc->desc_command |= (1 << index); | |
105 | } | |
106 | ||
107 | static u32 mv_chan_get_current_desc(struct mv_xor_chan *chan) | |
108 | { | |
5733c38a | 109 | return readl_relaxed(XOR_CURR_DESC(chan)); |
ff7b0479 SB |
110 | } |
111 | ||
112 | static void mv_chan_set_next_descriptor(struct mv_xor_chan *chan, | |
113 | u32 next_desc_addr) | |
114 | { | |
5733c38a | 115 | writel_relaxed(next_desc_addr, XOR_NEXT_DESC(chan)); |
ff7b0479 SB |
116 | } |
117 | ||
ff7b0479 SB |
118 | static void mv_chan_unmask_interrupts(struct mv_xor_chan *chan) |
119 | { | |
5733c38a | 120 | u32 val = readl_relaxed(XOR_INTR_MASK(chan)); |
ff7b0479 | 121 | val |= XOR_INTR_MASK_VALUE << (chan->idx * 16); |
5733c38a | 122 | writel_relaxed(val, XOR_INTR_MASK(chan)); |
ff7b0479 SB |
123 | } |
124 | ||
125 | static u32 mv_chan_get_intr_cause(struct mv_xor_chan *chan) | |
126 | { | |
5733c38a | 127 | u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
128 | intr_cause = (intr_cause >> (chan->idx * 16)) & 0xFFFF; |
129 | return intr_cause; | |
130 | } | |
131 | ||
132 | static int mv_is_err_intr(u32 intr_cause) | |
133 | { | |
134 | if (intr_cause & ((1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9))) | |
135 | return 1; | |
136 | ||
137 | return 0; | |
138 | } | |
139 | ||
140 | static void mv_xor_device_clear_eoc_cause(struct mv_xor_chan *chan) | |
141 | { | |
86363682 | 142 | u32 val = ~(1 << (chan->idx * 16)); |
c98c1781 | 143 | dev_dbg(mv_chan_to_devp(chan), "%s, val 0x%08x\n", __func__, val); |
5733c38a | 144 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
145 | } |
146 | ||
147 | static void mv_xor_device_clear_err_status(struct mv_xor_chan *chan) | |
148 | { | |
149 | u32 val = 0xFFFF0000 >> (chan->idx * 16); | |
5733c38a | 150 | writel_relaxed(val, XOR_INTR_CAUSE(chan)); |
ff7b0479 SB |
151 | } |
152 | ||
153 | static int mv_can_chain(struct mv_xor_desc_slot *desc) | |
154 | { | |
155 | struct mv_xor_desc_slot *chain_old_tail = list_entry( | |
156 | desc->chain_node.prev, struct mv_xor_desc_slot, chain_node); | |
157 | ||
158 | if (chain_old_tail->type != desc->type) | |
159 | return 0; | |
ff7b0479 SB |
160 | |
161 | return 1; | |
162 | } | |
163 | ||
164 | static void mv_set_mode(struct mv_xor_chan *chan, | |
165 | enum dma_transaction_type type) | |
166 | { | |
167 | u32 op_mode; | |
5733c38a | 168 | u32 config = readl_relaxed(XOR_CONFIG(chan)); |
ff7b0479 SB |
169 | |
170 | switch (type) { | |
171 | case DMA_XOR: | |
172 | op_mode = XOR_OPERATION_MODE_XOR; | |
173 | break; | |
174 | case DMA_MEMCPY: | |
175 | op_mode = XOR_OPERATION_MODE_MEMCPY; | |
176 | break; | |
ff7b0479 | 177 | default: |
c98c1781 | 178 | dev_err(mv_chan_to_devp(chan), |
1ba151cd | 179 | "error: unsupported operation %d\n", |
a3fc74bc | 180 | type); |
ff7b0479 SB |
181 | BUG(); |
182 | return; | |
183 | } | |
184 | ||
185 | config &= ~0x7; | |
186 | config |= op_mode; | |
e03bc654 TP |
187 | |
188 | #if defined(__BIG_ENDIAN) | |
189 | config |= XOR_DESCRIPTOR_SWAP; | |
190 | #else | |
191 | config &= ~XOR_DESCRIPTOR_SWAP; | |
192 | #endif | |
193 | ||
5733c38a | 194 | writel_relaxed(config, XOR_CONFIG(chan)); |
ff7b0479 SB |
195 | chan->current_type = type; |
196 | } | |
197 | ||
198 | static void mv_chan_activate(struct mv_xor_chan *chan) | |
199 | { | |
200 | u32 activation; | |
201 | ||
c98c1781 | 202 | dev_dbg(mv_chan_to_devp(chan), " activate chan.\n"); |
5733c38a | 203 | activation = readl_relaxed(XOR_ACTIVATION(chan)); |
ff7b0479 | 204 | activation |= 0x1; |
5733c38a | 205 | writel_relaxed(activation, XOR_ACTIVATION(chan)); |
ff7b0479 SB |
206 | } |
207 | ||
208 | static char mv_chan_is_busy(struct mv_xor_chan *chan) | |
209 | { | |
5733c38a | 210 | u32 state = readl_relaxed(XOR_ACTIVATION(chan)); |
ff7b0479 SB |
211 | |
212 | state = (state >> 4) & 0x3; | |
213 | ||
214 | return (state == 1) ? 1 : 0; | |
215 | } | |
216 | ||
217 | static int mv_chan_xor_slot_count(size_t len, int src_cnt) | |
218 | { | |
219 | return 1; | |
220 | } | |
221 | ||
222 | /** | |
223 | * mv_xor_free_slots - flags descriptor slots for reuse | |
224 | * @slot: Slot to free | |
225 | * Caller must hold &mv_chan->lock while calling this function | |
226 | */ | |
227 | static void mv_xor_free_slots(struct mv_xor_chan *mv_chan, | |
228 | struct mv_xor_desc_slot *slot) | |
229 | { | |
c98c1781 | 230 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d slot %p\n", |
ff7b0479 SB |
231 | __func__, __LINE__, slot); |
232 | ||
233 | slot->slots_per_op = 0; | |
234 | ||
235 | } | |
236 | ||
237 | /* | |
238 | * mv_xor_start_new_chain - program the engine to operate on new chain headed by | |
239 | * sw_desc | |
240 | * Caller must hold &mv_chan->lock while calling this function | |
241 | */ | |
242 | static void mv_xor_start_new_chain(struct mv_xor_chan *mv_chan, | |
243 | struct mv_xor_desc_slot *sw_desc) | |
244 | { | |
c98c1781 | 245 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: sw_desc %p\n", |
ff7b0479 SB |
246 | __func__, __LINE__, sw_desc); |
247 | if (sw_desc->type != mv_chan->current_type) | |
248 | mv_set_mode(mv_chan, sw_desc->type); | |
249 | ||
48a9db46 BZ |
250 | /* set the hardware chain */ |
251 | mv_chan_set_next_descriptor(mv_chan, sw_desc->async_tx.phys); | |
252 | ||
ff7b0479 | 253 | mv_chan->pending += sw_desc->slot_cnt; |
98817b99 | 254 | mv_xor_issue_pending(&mv_chan->dmachan); |
ff7b0479 SB |
255 | } |
256 | ||
257 | static dma_cookie_t | |
258 | mv_xor_run_tx_complete_actions(struct mv_xor_desc_slot *desc, | |
259 | struct mv_xor_chan *mv_chan, dma_cookie_t cookie) | |
260 | { | |
261 | BUG_ON(desc->async_tx.cookie < 0); | |
262 | ||
263 | if (desc->async_tx.cookie > 0) { | |
264 | cookie = desc->async_tx.cookie; | |
265 | ||
266 | /* call the callback (must not sleep or submit new | |
267 | * operations to this channel) | |
268 | */ | |
269 | if (desc->async_tx.callback) | |
270 | desc->async_tx.callback( | |
271 | desc->async_tx.callback_param); | |
272 | ||
d38a8c62 | 273 | dma_descriptor_unmap(&desc->async_tx); |
54f8d501 | 274 | if (desc->group_head) |
ff7b0479 | 275 | desc->group_head = NULL; |
ff7b0479 SB |
276 | } |
277 | ||
278 | /* run dependent operations */ | |
07f2211e | 279 | dma_run_dependencies(&desc->async_tx); |
ff7b0479 SB |
280 | |
281 | return cookie; | |
282 | } | |
283 | ||
284 | static int | |
285 | mv_xor_clean_completed_slots(struct mv_xor_chan *mv_chan) | |
286 | { | |
287 | struct mv_xor_desc_slot *iter, *_iter; | |
288 | ||
c98c1781 | 289 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
ff7b0479 SB |
290 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, |
291 | completed_node) { | |
292 | ||
293 | if (async_tx_test_ack(&iter->async_tx)) { | |
294 | list_del(&iter->completed_node); | |
295 | mv_xor_free_slots(mv_chan, iter); | |
296 | } | |
297 | } | |
298 | return 0; | |
299 | } | |
300 | ||
301 | static int | |
302 | mv_xor_clean_slot(struct mv_xor_desc_slot *desc, | |
303 | struct mv_xor_chan *mv_chan) | |
304 | { | |
c98c1781 | 305 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d: desc %p flags %d\n", |
ff7b0479 SB |
306 | __func__, __LINE__, desc, desc->async_tx.flags); |
307 | list_del(&desc->chain_node); | |
308 | /* the client is allowed to attach dependent operations | |
309 | * until 'ack' is set | |
310 | */ | |
311 | if (!async_tx_test_ack(&desc->async_tx)) { | |
312 | /* move this slot to the completed_slots */ | |
313 | list_add_tail(&desc->completed_node, &mv_chan->completed_slots); | |
314 | return 0; | |
315 | } | |
316 | ||
317 | mv_xor_free_slots(mv_chan, desc); | |
318 | return 0; | |
319 | } | |
320 | ||
321 | static void __mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan) | |
322 | { | |
323 | struct mv_xor_desc_slot *iter, *_iter; | |
324 | dma_cookie_t cookie = 0; | |
325 | int busy = mv_chan_is_busy(mv_chan); | |
326 | u32 current_desc = mv_chan_get_current_desc(mv_chan); | |
327 | int seen_current = 0; | |
328 | ||
c98c1781 TP |
329 | dev_dbg(mv_chan_to_devp(mv_chan), "%s %d\n", __func__, __LINE__); |
330 | dev_dbg(mv_chan_to_devp(mv_chan), "current_desc %x\n", current_desc); | |
ff7b0479 SB |
331 | mv_xor_clean_completed_slots(mv_chan); |
332 | ||
333 | /* free completed slots from the chain starting with | |
334 | * the oldest descriptor | |
335 | */ | |
336 | ||
337 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, | |
338 | chain_node) { | |
339 | prefetch(_iter); | |
340 | prefetch(&_iter->async_tx); | |
341 | ||
342 | /* do not advance past the current descriptor loaded into the | |
343 | * hardware channel, subsequent descriptors are either in | |
344 | * process or have not been submitted | |
345 | */ | |
346 | if (seen_current) | |
347 | break; | |
348 | ||
349 | /* stop the search if we reach the current descriptor and the | |
350 | * channel is busy | |
351 | */ | |
352 | if (iter->async_tx.phys == current_desc) { | |
353 | seen_current = 1; | |
354 | if (busy) | |
355 | break; | |
356 | } | |
357 | ||
358 | cookie = mv_xor_run_tx_complete_actions(iter, mv_chan, cookie); | |
359 | ||
360 | if (mv_xor_clean_slot(iter, mv_chan)) | |
361 | break; | |
362 | } | |
363 | ||
364 | if ((busy == 0) && !list_empty(&mv_chan->chain)) { | |
365 | struct mv_xor_desc_slot *chain_head; | |
366 | chain_head = list_entry(mv_chan->chain.next, | |
367 | struct mv_xor_desc_slot, | |
368 | chain_node); | |
369 | ||
370 | mv_xor_start_new_chain(mv_chan, chain_head); | |
371 | } | |
372 | ||
373 | if (cookie > 0) | |
98817b99 | 374 | mv_chan->dmachan.completed_cookie = cookie; |
ff7b0479 SB |
375 | } |
376 | ||
377 | static void | |
378 | mv_xor_slot_cleanup(struct mv_xor_chan *mv_chan) | |
379 | { | |
380 | spin_lock_bh(&mv_chan->lock); | |
381 | __mv_xor_slot_cleanup(mv_chan); | |
382 | spin_unlock_bh(&mv_chan->lock); | |
383 | } | |
384 | ||
385 | static void mv_xor_tasklet(unsigned long data) | |
386 | { | |
387 | struct mv_xor_chan *chan = (struct mv_xor_chan *) data; | |
8333f65e | 388 | mv_xor_slot_cleanup(chan); |
ff7b0479 SB |
389 | } |
390 | ||
391 | static struct mv_xor_desc_slot * | |
392 | mv_xor_alloc_slots(struct mv_xor_chan *mv_chan, int num_slots, | |
393 | int slots_per_op) | |
394 | { | |
395 | struct mv_xor_desc_slot *iter, *_iter, *alloc_start = NULL; | |
396 | LIST_HEAD(chain); | |
397 | int slots_found, retry = 0; | |
398 | ||
399 | /* start search from the last allocated descrtiptor | |
400 | * if a contiguous allocation can not be found start searching | |
401 | * from the beginning of the list | |
402 | */ | |
403 | retry: | |
404 | slots_found = 0; | |
405 | if (retry == 0) | |
406 | iter = mv_chan->last_used; | |
407 | else | |
408 | iter = list_entry(&mv_chan->all_slots, | |
409 | struct mv_xor_desc_slot, | |
410 | slot_node); | |
411 | ||
412 | list_for_each_entry_safe_continue( | |
413 | iter, _iter, &mv_chan->all_slots, slot_node) { | |
414 | prefetch(_iter); | |
415 | prefetch(&_iter->async_tx); | |
416 | if (iter->slots_per_op) { | |
417 | /* give up after finding the first busy slot | |
418 | * on the second pass through the list | |
419 | */ | |
420 | if (retry) | |
421 | break; | |
422 | ||
423 | slots_found = 0; | |
424 | continue; | |
425 | } | |
426 | ||
427 | /* start the allocation if the slot is correctly aligned */ | |
428 | if (!slots_found++) | |
429 | alloc_start = iter; | |
430 | ||
431 | if (slots_found == num_slots) { | |
432 | struct mv_xor_desc_slot *alloc_tail = NULL; | |
433 | struct mv_xor_desc_slot *last_used = NULL; | |
434 | iter = alloc_start; | |
435 | while (num_slots) { | |
436 | int i; | |
437 | ||
438 | /* pre-ack all but the last descriptor */ | |
439 | async_tx_ack(&iter->async_tx); | |
440 | ||
441 | list_add_tail(&iter->chain_node, &chain); | |
442 | alloc_tail = iter; | |
443 | iter->async_tx.cookie = 0; | |
444 | iter->slot_cnt = num_slots; | |
445 | iter->xor_check_result = NULL; | |
446 | for (i = 0; i < slots_per_op; i++) { | |
447 | iter->slots_per_op = slots_per_op - i; | |
448 | last_used = iter; | |
449 | iter = list_entry(iter->slot_node.next, | |
450 | struct mv_xor_desc_slot, | |
451 | slot_node); | |
452 | } | |
453 | num_slots -= slots_per_op; | |
454 | } | |
455 | alloc_tail->group_head = alloc_start; | |
456 | alloc_tail->async_tx.cookie = -EBUSY; | |
64203b67 | 457 | list_splice(&chain, &alloc_tail->tx_list); |
ff7b0479 SB |
458 | mv_chan->last_used = last_used; |
459 | mv_desc_clear_next_desc(alloc_start); | |
460 | mv_desc_clear_next_desc(alloc_tail); | |
461 | return alloc_tail; | |
462 | } | |
463 | } | |
464 | if (!retry++) | |
465 | goto retry; | |
466 | ||
467 | /* try to free some slots if the allocation fails */ | |
468 | tasklet_schedule(&mv_chan->irq_tasklet); | |
469 | ||
470 | return NULL; | |
471 | } | |
472 | ||
ff7b0479 SB |
473 | /************************ DMA engine API functions ****************************/ |
474 | static dma_cookie_t | |
475 | mv_xor_tx_submit(struct dma_async_tx_descriptor *tx) | |
476 | { | |
477 | struct mv_xor_desc_slot *sw_desc = to_mv_xor_slot(tx); | |
478 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(tx->chan); | |
479 | struct mv_xor_desc_slot *grp_start, *old_chain_tail; | |
480 | dma_cookie_t cookie; | |
481 | int new_hw_chain = 1; | |
482 | ||
c98c1781 | 483 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
484 | "%s sw_desc %p: async_tx %p\n", |
485 | __func__, sw_desc, &sw_desc->async_tx); | |
486 | ||
487 | grp_start = sw_desc->group_head; | |
488 | ||
489 | spin_lock_bh(&mv_chan->lock); | |
884485e1 | 490 | cookie = dma_cookie_assign(tx); |
ff7b0479 SB |
491 | |
492 | if (list_empty(&mv_chan->chain)) | |
64203b67 | 493 | list_splice_init(&sw_desc->tx_list, &mv_chan->chain); |
ff7b0479 SB |
494 | else { |
495 | new_hw_chain = 0; | |
496 | ||
497 | old_chain_tail = list_entry(mv_chan->chain.prev, | |
498 | struct mv_xor_desc_slot, | |
499 | chain_node); | |
64203b67 | 500 | list_splice_init(&grp_start->tx_list, |
ff7b0479 SB |
501 | &old_chain_tail->chain_node); |
502 | ||
503 | if (!mv_can_chain(grp_start)) | |
504 | goto submit_done; | |
505 | ||
c98c1781 | 506 | dev_dbg(mv_chan_to_devp(mv_chan), "Append to last desc %x\n", |
ff7b0479 SB |
507 | old_chain_tail->async_tx.phys); |
508 | ||
509 | /* fix up the hardware chain */ | |
510 | mv_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys); | |
511 | ||
512 | /* if the channel is not busy */ | |
513 | if (!mv_chan_is_busy(mv_chan)) { | |
514 | u32 current_desc = mv_chan_get_current_desc(mv_chan); | |
515 | /* | |
516 | * and the curren desc is the end of the chain before | |
517 | * the append, then we need to start the channel | |
518 | */ | |
519 | if (current_desc == old_chain_tail->async_tx.phys) | |
520 | new_hw_chain = 1; | |
521 | } | |
522 | } | |
523 | ||
524 | if (new_hw_chain) | |
525 | mv_xor_start_new_chain(mv_chan, grp_start); | |
526 | ||
527 | submit_done: | |
528 | spin_unlock_bh(&mv_chan->lock); | |
529 | ||
530 | return cookie; | |
531 | } | |
532 | ||
533 | /* returns the number of allocated descriptors */ | |
aa1e6f1a | 534 | static int mv_xor_alloc_chan_resources(struct dma_chan *chan) |
ff7b0479 SB |
535 | { |
536 | char *hw_desc; | |
537 | int idx; | |
538 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
539 | struct mv_xor_desc_slot *slot = NULL; | |
b503fa01 | 540 | int num_descs_in_pool = MV_XOR_POOL_SIZE/MV_XOR_SLOT_SIZE; |
ff7b0479 SB |
541 | |
542 | /* Allocate descriptor slots */ | |
543 | idx = mv_chan->slots_allocated; | |
544 | while (idx < num_descs_in_pool) { | |
545 | slot = kzalloc(sizeof(*slot), GFP_KERNEL); | |
546 | if (!slot) { | |
547 | printk(KERN_INFO "MV XOR Channel only initialized" | |
548 | " %d descriptor slots", idx); | |
549 | break; | |
550 | } | |
1ef48a26 | 551 | hw_desc = (char *) mv_chan->dma_desc_pool_virt; |
ff7b0479 SB |
552 | slot->hw_desc = (void *) &hw_desc[idx * MV_XOR_SLOT_SIZE]; |
553 | ||
554 | dma_async_tx_descriptor_init(&slot->async_tx, chan); | |
555 | slot->async_tx.tx_submit = mv_xor_tx_submit; | |
556 | INIT_LIST_HEAD(&slot->chain_node); | |
557 | INIT_LIST_HEAD(&slot->slot_node); | |
64203b67 | 558 | INIT_LIST_HEAD(&slot->tx_list); |
1ef48a26 | 559 | hw_desc = (char *) mv_chan->dma_desc_pool; |
ff7b0479 SB |
560 | slot->async_tx.phys = |
561 | (dma_addr_t) &hw_desc[idx * MV_XOR_SLOT_SIZE]; | |
562 | slot->idx = idx++; | |
563 | ||
564 | spin_lock_bh(&mv_chan->lock); | |
565 | mv_chan->slots_allocated = idx; | |
566 | list_add_tail(&slot->slot_node, &mv_chan->all_slots); | |
567 | spin_unlock_bh(&mv_chan->lock); | |
568 | } | |
569 | ||
570 | if (mv_chan->slots_allocated && !mv_chan->last_used) | |
571 | mv_chan->last_used = list_entry(mv_chan->all_slots.next, | |
572 | struct mv_xor_desc_slot, | |
573 | slot_node); | |
574 | ||
c98c1781 | 575 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
576 | "allocated %d descriptor slots last_used: %p\n", |
577 | mv_chan->slots_allocated, mv_chan->last_used); | |
578 | ||
579 | return mv_chan->slots_allocated ? : -ENOMEM; | |
580 | } | |
581 | ||
582 | static struct dma_async_tx_descriptor * | |
583 | mv_xor_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
584 | size_t len, unsigned long flags) | |
585 | { | |
586 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
587 | struct mv_xor_desc_slot *sw_desc, *grp_start; | |
588 | int slot_cnt; | |
589 | ||
c98c1781 | 590 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
591 | "%s dest: %x src %x len: %u flags: %ld\n", |
592 | __func__, dest, src, len, flags); | |
593 | if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) | |
594 | return NULL; | |
595 | ||
7912d300 | 596 | BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); |
ff7b0479 SB |
597 | |
598 | spin_lock_bh(&mv_chan->lock); | |
599 | slot_cnt = mv_chan_memcpy_slot_count(len); | |
600 | sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1); | |
601 | if (sw_desc) { | |
602 | sw_desc->type = DMA_MEMCPY; | |
603 | sw_desc->async_tx.flags = flags; | |
604 | grp_start = sw_desc->group_head; | |
605 | mv_desc_init(grp_start, flags); | |
606 | mv_desc_set_byte_count(grp_start, len); | |
607 | mv_desc_set_dest_addr(sw_desc->group_head, dest); | |
608 | mv_desc_set_src_addr(grp_start, 0, src); | |
609 | sw_desc->unmap_src_cnt = 1; | |
610 | sw_desc->unmap_len = len; | |
611 | } | |
612 | spin_unlock_bh(&mv_chan->lock); | |
613 | ||
c98c1781 | 614 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 | 615 | "%s sw_desc %p async_tx %p\n", |
4c143725 | 616 | __func__, sw_desc, sw_desc ? &sw_desc->async_tx : NULL); |
ff7b0479 SB |
617 | |
618 | return sw_desc ? &sw_desc->async_tx : NULL; | |
619 | } | |
620 | ||
ff7b0479 SB |
621 | static struct dma_async_tx_descriptor * |
622 | mv_xor_prep_dma_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, | |
623 | unsigned int src_cnt, size_t len, unsigned long flags) | |
624 | { | |
625 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
626 | struct mv_xor_desc_slot *sw_desc, *grp_start; | |
627 | int slot_cnt; | |
628 | ||
629 | if (unlikely(len < MV_XOR_MIN_BYTE_COUNT)) | |
630 | return NULL; | |
631 | ||
7912d300 | 632 | BUG_ON(len > MV_XOR_MAX_BYTE_COUNT); |
ff7b0479 | 633 | |
c98c1781 | 634 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
635 | "%s src_cnt: %d len: dest %x %u flags: %ld\n", |
636 | __func__, src_cnt, len, dest, flags); | |
637 | ||
638 | spin_lock_bh(&mv_chan->lock); | |
639 | slot_cnt = mv_chan_xor_slot_count(len, src_cnt); | |
640 | sw_desc = mv_xor_alloc_slots(mv_chan, slot_cnt, 1); | |
641 | if (sw_desc) { | |
642 | sw_desc->type = DMA_XOR; | |
643 | sw_desc->async_tx.flags = flags; | |
644 | grp_start = sw_desc->group_head; | |
645 | mv_desc_init(grp_start, flags); | |
646 | /* the byte count field is the same as in memcpy desc*/ | |
647 | mv_desc_set_byte_count(grp_start, len); | |
648 | mv_desc_set_dest_addr(sw_desc->group_head, dest); | |
649 | sw_desc->unmap_src_cnt = src_cnt; | |
650 | sw_desc->unmap_len = len; | |
651 | while (src_cnt--) | |
652 | mv_desc_set_src_addr(grp_start, src_cnt, src[src_cnt]); | |
653 | } | |
654 | spin_unlock_bh(&mv_chan->lock); | |
c98c1781 | 655 | dev_dbg(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
656 | "%s sw_desc %p async_tx %p \n", |
657 | __func__, sw_desc, &sw_desc->async_tx); | |
658 | return sw_desc ? &sw_desc->async_tx : NULL; | |
659 | } | |
660 | ||
661 | static void mv_xor_free_chan_resources(struct dma_chan *chan) | |
662 | { | |
663 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
664 | struct mv_xor_desc_slot *iter, *_iter; | |
665 | int in_use_descs = 0; | |
666 | ||
667 | mv_xor_slot_cleanup(mv_chan); | |
668 | ||
669 | spin_lock_bh(&mv_chan->lock); | |
670 | list_for_each_entry_safe(iter, _iter, &mv_chan->chain, | |
671 | chain_node) { | |
672 | in_use_descs++; | |
673 | list_del(&iter->chain_node); | |
674 | } | |
675 | list_for_each_entry_safe(iter, _iter, &mv_chan->completed_slots, | |
676 | completed_node) { | |
677 | in_use_descs++; | |
678 | list_del(&iter->completed_node); | |
679 | } | |
680 | list_for_each_entry_safe_reverse( | |
681 | iter, _iter, &mv_chan->all_slots, slot_node) { | |
682 | list_del(&iter->slot_node); | |
683 | kfree(iter); | |
684 | mv_chan->slots_allocated--; | |
685 | } | |
686 | mv_chan->last_used = NULL; | |
687 | ||
c98c1781 | 688 | dev_dbg(mv_chan_to_devp(mv_chan), "%s slots_allocated %d\n", |
ff7b0479 SB |
689 | __func__, mv_chan->slots_allocated); |
690 | spin_unlock_bh(&mv_chan->lock); | |
691 | ||
692 | if (in_use_descs) | |
c98c1781 | 693 | dev_err(mv_chan_to_devp(mv_chan), |
ff7b0479 SB |
694 | "freeing %d in use descriptors!\n", in_use_descs); |
695 | } | |
696 | ||
697 | /** | |
07934481 | 698 | * mv_xor_status - poll the status of an XOR transaction |
ff7b0479 SB |
699 | * @chan: XOR channel handle |
700 | * @cookie: XOR transaction identifier | |
07934481 | 701 | * @txstate: XOR transactions state holder (or NULL) |
ff7b0479 | 702 | */ |
07934481 | 703 | static enum dma_status mv_xor_status(struct dma_chan *chan, |
ff7b0479 | 704 | dma_cookie_t cookie, |
07934481 | 705 | struct dma_tx_state *txstate) |
ff7b0479 SB |
706 | { |
707 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
ff7b0479 SB |
708 | enum dma_status ret; |
709 | ||
96a2af41 | 710 | ret = dma_cookie_status(chan, cookie, txstate); |
ff7b0479 SB |
711 | if (ret == DMA_SUCCESS) { |
712 | mv_xor_clean_completed_slots(mv_chan); | |
713 | return ret; | |
714 | } | |
715 | mv_xor_slot_cleanup(mv_chan); | |
716 | ||
96a2af41 | 717 | return dma_cookie_status(chan, cookie, txstate); |
ff7b0479 SB |
718 | } |
719 | ||
720 | static void mv_dump_xor_regs(struct mv_xor_chan *chan) | |
721 | { | |
722 | u32 val; | |
723 | ||
5733c38a | 724 | val = readl_relaxed(XOR_CONFIG(chan)); |
1ba151cd | 725 | dev_err(mv_chan_to_devp(chan), "config 0x%08x\n", val); |
ff7b0479 | 726 | |
5733c38a | 727 | val = readl_relaxed(XOR_ACTIVATION(chan)); |
1ba151cd | 728 | dev_err(mv_chan_to_devp(chan), "activation 0x%08x\n", val); |
ff7b0479 | 729 | |
5733c38a | 730 | val = readl_relaxed(XOR_INTR_CAUSE(chan)); |
1ba151cd | 731 | dev_err(mv_chan_to_devp(chan), "intr cause 0x%08x\n", val); |
ff7b0479 | 732 | |
5733c38a | 733 | val = readl_relaxed(XOR_INTR_MASK(chan)); |
1ba151cd | 734 | dev_err(mv_chan_to_devp(chan), "intr mask 0x%08x\n", val); |
ff7b0479 | 735 | |
5733c38a | 736 | val = readl_relaxed(XOR_ERROR_CAUSE(chan)); |
1ba151cd | 737 | dev_err(mv_chan_to_devp(chan), "error cause 0x%08x\n", val); |
ff7b0479 | 738 | |
5733c38a | 739 | val = readl_relaxed(XOR_ERROR_ADDR(chan)); |
1ba151cd | 740 | dev_err(mv_chan_to_devp(chan), "error addr 0x%08x\n", val); |
ff7b0479 SB |
741 | } |
742 | ||
743 | static void mv_xor_err_interrupt_handler(struct mv_xor_chan *chan, | |
744 | u32 intr_cause) | |
745 | { | |
746 | if (intr_cause & (1 << 4)) { | |
c98c1781 | 747 | dev_dbg(mv_chan_to_devp(chan), |
ff7b0479 SB |
748 | "ignore this error\n"); |
749 | return; | |
750 | } | |
751 | ||
c98c1781 | 752 | dev_err(mv_chan_to_devp(chan), |
1ba151cd | 753 | "error on chan %d. intr cause 0x%08x\n", |
a3fc74bc | 754 | chan->idx, intr_cause); |
ff7b0479 SB |
755 | |
756 | mv_dump_xor_regs(chan); | |
757 | BUG(); | |
758 | } | |
759 | ||
760 | static irqreturn_t mv_xor_interrupt_handler(int irq, void *data) | |
761 | { | |
762 | struct mv_xor_chan *chan = data; | |
763 | u32 intr_cause = mv_chan_get_intr_cause(chan); | |
764 | ||
c98c1781 | 765 | dev_dbg(mv_chan_to_devp(chan), "intr cause %x\n", intr_cause); |
ff7b0479 SB |
766 | |
767 | if (mv_is_err_intr(intr_cause)) | |
768 | mv_xor_err_interrupt_handler(chan, intr_cause); | |
769 | ||
770 | tasklet_schedule(&chan->irq_tasklet); | |
771 | ||
772 | mv_xor_device_clear_eoc_cause(chan); | |
773 | ||
774 | return IRQ_HANDLED; | |
775 | } | |
776 | ||
777 | static void mv_xor_issue_pending(struct dma_chan *chan) | |
778 | { | |
779 | struct mv_xor_chan *mv_chan = to_mv_xor_chan(chan); | |
780 | ||
781 | if (mv_chan->pending >= MV_XOR_THRESHOLD) { | |
782 | mv_chan->pending = 0; | |
783 | mv_chan_activate(mv_chan); | |
784 | } | |
785 | } | |
786 | ||
787 | /* | |
788 | * Perform a transaction to verify the HW works. | |
789 | */ | |
790 | #define MV_XOR_TEST_SIZE 2000 | |
791 | ||
c2714334 | 792 | static int mv_xor_memcpy_self_test(struct mv_xor_chan *mv_chan) |
ff7b0479 SB |
793 | { |
794 | int i; | |
795 | void *src, *dest; | |
796 | dma_addr_t src_dma, dest_dma; | |
797 | struct dma_chan *dma_chan; | |
798 | dma_cookie_t cookie; | |
799 | struct dma_async_tx_descriptor *tx; | |
800 | int err = 0; | |
ff7b0479 SB |
801 | |
802 | src = kmalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL); | |
803 | if (!src) | |
804 | return -ENOMEM; | |
805 | ||
806 | dest = kzalloc(sizeof(u8) * MV_XOR_TEST_SIZE, GFP_KERNEL); | |
807 | if (!dest) { | |
808 | kfree(src); | |
809 | return -ENOMEM; | |
810 | } | |
811 | ||
812 | /* Fill in src buffer */ | |
813 | for (i = 0; i < MV_XOR_TEST_SIZE; i++) | |
814 | ((u8 *) src)[i] = (u8)i; | |
815 | ||
275cc0c8 | 816 | dma_chan = &mv_chan->dmachan; |
aa1e6f1a | 817 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
ff7b0479 SB |
818 | err = -ENODEV; |
819 | goto out; | |
820 | } | |
821 | ||
822 | dest_dma = dma_map_single(dma_chan->device->dev, dest, | |
823 | MV_XOR_TEST_SIZE, DMA_FROM_DEVICE); | |
824 | ||
825 | src_dma = dma_map_single(dma_chan->device->dev, src, | |
826 | MV_XOR_TEST_SIZE, DMA_TO_DEVICE); | |
827 | ||
828 | tx = mv_xor_prep_dma_memcpy(dma_chan, dest_dma, src_dma, | |
829 | MV_XOR_TEST_SIZE, 0); | |
830 | cookie = mv_xor_tx_submit(tx); | |
831 | mv_xor_issue_pending(dma_chan); | |
832 | async_tx_ack(tx); | |
833 | msleep(1); | |
834 | ||
07934481 | 835 | if (mv_xor_status(dma_chan, cookie, NULL) != |
ff7b0479 | 836 | DMA_SUCCESS) { |
a3fc74bc TP |
837 | dev_err(dma_chan->device->dev, |
838 | "Self-test copy timed out, disabling\n"); | |
ff7b0479 SB |
839 | err = -ENODEV; |
840 | goto free_resources; | |
841 | } | |
842 | ||
c35064c4 | 843 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
ff7b0479 SB |
844 | MV_XOR_TEST_SIZE, DMA_FROM_DEVICE); |
845 | if (memcmp(src, dest, MV_XOR_TEST_SIZE)) { | |
a3fc74bc TP |
846 | dev_err(dma_chan->device->dev, |
847 | "Self-test copy failed compare, disabling\n"); | |
ff7b0479 SB |
848 | err = -ENODEV; |
849 | goto free_resources; | |
850 | } | |
851 | ||
852 | free_resources: | |
853 | mv_xor_free_chan_resources(dma_chan); | |
854 | out: | |
855 | kfree(src); | |
856 | kfree(dest); | |
857 | return err; | |
858 | } | |
859 | ||
860 | #define MV_XOR_NUM_SRC_TEST 4 /* must be <= 15 */ | |
463a1f8b | 861 | static int |
275cc0c8 | 862 | mv_xor_xor_self_test(struct mv_xor_chan *mv_chan) |
ff7b0479 SB |
863 | { |
864 | int i, src_idx; | |
865 | struct page *dest; | |
866 | struct page *xor_srcs[MV_XOR_NUM_SRC_TEST]; | |
867 | dma_addr_t dma_srcs[MV_XOR_NUM_SRC_TEST]; | |
868 | dma_addr_t dest_dma; | |
869 | struct dma_async_tx_descriptor *tx; | |
870 | struct dma_chan *dma_chan; | |
871 | dma_cookie_t cookie; | |
872 | u8 cmp_byte = 0; | |
873 | u32 cmp_word; | |
874 | int err = 0; | |
ff7b0479 SB |
875 | |
876 | for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) { | |
877 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); | |
a09b09ae RK |
878 | if (!xor_srcs[src_idx]) { |
879 | while (src_idx--) | |
ff7b0479 | 880 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
881 | return -ENOMEM; |
882 | } | |
ff7b0479 SB |
883 | } |
884 | ||
885 | dest = alloc_page(GFP_KERNEL); | |
a09b09ae RK |
886 | if (!dest) { |
887 | while (src_idx--) | |
ff7b0479 | 888 | __free_page(xor_srcs[src_idx]); |
a09b09ae RK |
889 | return -ENOMEM; |
890 | } | |
ff7b0479 SB |
891 | |
892 | /* Fill in src buffers */ | |
893 | for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) { | |
894 | u8 *ptr = page_address(xor_srcs[src_idx]); | |
895 | for (i = 0; i < PAGE_SIZE; i++) | |
896 | ptr[i] = (1 << src_idx); | |
897 | } | |
898 | ||
899 | for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) | |
900 | cmp_byte ^= (u8) (1 << src_idx); | |
901 | ||
902 | cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | | |
903 | (cmp_byte << 8) | cmp_byte; | |
904 | ||
905 | memset(page_address(dest), 0, PAGE_SIZE); | |
906 | ||
275cc0c8 | 907 | dma_chan = &mv_chan->dmachan; |
aa1e6f1a | 908 | if (mv_xor_alloc_chan_resources(dma_chan) < 1) { |
ff7b0479 SB |
909 | err = -ENODEV; |
910 | goto out; | |
911 | } | |
912 | ||
913 | /* test xor */ | |
914 | dest_dma = dma_map_page(dma_chan->device->dev, dest, 0, PAGE_SIZE, | |
915 | DMA_FROM_DEVICE); | |
916 | ||
917 | for (i = 0; i < MV_XOR_NUM_SRC_TEST; i++) | |
918 | dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], | |
919 | 0, PAGE_SIZE, DMA_TO_DEVICE); | |
920 | ||
921 | tx = mv_xor_prep_dma_xor(dma_chan, dest_dma, dma_srcs, | |
922 | MV_XOR_NUM_SRC_TEST, PAGE_SIZE, 0); | |
923 | ||
924 | cookie = mv_xor_tx_submit(tx); | |
925 | mv_xor_issue_pending(dma_chan); | |
926 | async_tx_ack(tx); | |
927 | msleep(8); | |
928 | ||
07934481 | 929 | if (mv_xor_status(dma_chan, cookie, NULL) != |
ff7b0479 | 930 | DMA_SUCCESS) { |
a3fc74bc TP |
931 | dev_err(dma_chan->device->dev, |
932 | "Self-test xor timed out, disabling\n"); | |
ff7b0479 SB |
933 | err = -ENODEV; |
934 | goto free_resources; | |
935 | } | |
936 | ||
c35064c4 | 937 | dma_sync_single_for_cpu(dma_chan->device->dev, dest_dma, |
ff7b0479 SB |
938 | PAGE_SIZE, DMA_FROM_DEVICE); |
939 | for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { | |
940 | u32 *ptr = page_address(dest); | |
941 | if (ptr[i] != cmp_word) { | |
a3fc74bc | 942 | dev_err(dma_chan->device->dev, |
1ba151cd JP |
943 | "Self-test xor failed compare, disabling. index %d, data %x, expected %x\n", |
944 | i, ptr[i], cmp_word); | |
ff7b0479 SB |
945 | err = -ENODEV; |
946 | goto free_resources; | |
947 | } | |
948 | } | |
949 | ||
950 | free_resources: | |
951 | mv_xor_free_chan_resources(dma_chan); | |
952 | out: | |
953 | src_idx = MV_XOR_NUM_SRC_TEST; | |
954 | while (src_idx--) | |
955 | __free_page(xor_srcs[src_idx]); | |
956 | __free_page(dest); | |
957 | return err; | |
958 | } | |
959 | ||
34c93c86 AL |
960 | /* This driver does not implement any of the optional DMA operations. */ |
961 | static int | |
962 | mv_xor_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
963 | unsigned long arg) | |
964 | { | |
965 | return -ENOSYS; | |
966 | } | |
967 | ||
1ef48a26 | 968 | static int mv_xor_channel_remove(struct mv_xor_chan *mv_chan) |
ff7b0479 | 969 | { |
ff7b0479 | 970 | struct dma_chan *chan, *_chan; |
1ef48a26 | 971 | struct device *dev = mv_chan->dmadev.dev; |
ff7b0479 | 972 | |
1ef48a26 | 973 | dma_async_device_unregister(&mv_chan->dmadev); |
ff7b0479 | 974 | |
b503fa01 | 975 | dma_free_coherent(dev, MV_XOR_POOL_SIZE, |
1ef48a26 | 976 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
ff7b0479 | 977 | |
1ef48a26 | 978 | list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels, |
a6b4a9d2 | 979 | device_node) { |
ff7b0479 SB |
980 | list_del(&chan->device_node); |
981 | } | |
982 | ||
88eb92cb TP |
983 | free_irq(mv_chan->irq, mv_chan); |
984 | ||
ff7b0479 SB |
985 | return 0; |
986 | } | |
987 | ||
1ef48a26 | 988 | static struct mv_xor_chan * |
297eedba | 989 | mv_xor_channel_add(struct mv_xor_device *xordev, |
a6b4a9d2 | 990 | struct platform_device *pdev, |
b503fa01 | 991 | int idx, dma_cap_mask_t cap_mask, int irq) |
ff7b0479 SB |
992 | { |
993 | int ret = 0; | |
ff7b0479 SB |
994 | struct mv_xor_chan *mv_chan; |
995 | struct dma_device *dma_dev; | |
ff7b0479 | 996 | |
1ef48a26 | 997 | mv_chan = devm_kzalloc(&pdev->dev, sizeof(*mv_chan), GFP_KERNEL); |
a577659f SK |
998 | if (!mv_chan) |
999 | return ERR_PTR(-ENOMEM); | |
ff7b0479 | 1000 | |
9aedbdba | 1001 | mv_chan->idx = idx; |
88eb92cb | 1002 | mv_chan->irq = irq; |
ff7b0479 | 1003 | |
1ef48a26 | 1004 | dma_dev = &mv_chan->dmadev; |
ff7b0479 SB |
1005 | |
1006 | /* allocate coherent memory for hardware descriptors | |
1007 | * note: writecombine gives slightly better performance, but | |
1008 | * requires that we explicitly flush the writes | |
1009 | */ | |
1ef48a26 | 1010 | mv_chan->dma_desc_pool_virt = |
b503fa01 | 1011 | dma_alloc_writecombine(&pdev->dev, MV_XOR_POOL_SIZE, |
1ef48a26 TP |
1012 | &mv_chan->dma_desc_pool, GFP_KERNEL); |
1013 | if (!mv_chan->dma_desc_pool_virt) | |
a6b4a9d2 | 1014 | return ERR_PTR(-ENOMEM); |
ff7b0479 SB |
1015 | |
1016 | /* discover transaction capabilites from the platform data */ | |
a6b4a9d2 | 1017 | dma_dev->cap_mask = cap_mask; |
ff7b0479 SB |
1018 | |
1019 | INIT_LIST_HEAD(&dma_dev->channels); | |
1020 | ||
1021 | /* set base routines */ | |
1022 | dma_dev->device_alloc_chan_resources = mv_xor_alloc_chan_resources; | |
1023 | dma_dev->device_free_chan_resources = mv_xor_free_chan_resources; | |
07934481 | 1024 | dma_dev->device_tx_status = mv_xor_status; |
ff7b0479 | 1025 | dma_dev->device_issue_pending = mv_xor_issue_pending; |
34c93c86 | 1026 | dma_dev->device_control = mv_xor_control; |
ff7b0479 SB |
1027 | dma_dev->dev = &pdev->dev; |
1028 | ||
1029 | /* set prep routines based on capability */ | |
1030 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) | |
1031 | dma_dev->device_prep_dma_memcpy = mv_xor_prep_dma_memcpy; | |
ff7b0479 | 1032 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { |
c019894e | 1033 | dma_dev->max_xor = 8; |
ff7b0479 SB |
1034 | dma_dev->device_prep_dma_xor = mv_xor_prep_dma_xor; |
1035 | } | |
1036 | ||
297eedba | 1037 | mv_chan->mmr_base = xordev->xor_base; |
ff7b0479 SB |
1038 | tasklet_init(&mv_chan->irq_tasklet, mv_xor_tasklet, (unsigned long) |
1039 | mv_chan); | |
1040 | ||
1041 | /* clear errors before enabling interrupts */ | |
1042 | mv_xor_device_clear_err_status(mv_chan); | |
1043 | ||
2d0a0745 TP |
1044 | ret = request_irq(mv_chan->irq, mv_xor_interrupt_handler, |
1045 | 0, dev_name(&pdev->dev), mv_chan); | |
ff7b0479 SB |
1046 | if (ret) |
1047 | goto err_free_dma; | |
1048 | ||
1049 | mv_chan_unmask_interrupts(mv_chan); | |
1050 | ||
1051 | mv_set_mode(mv_chan, DMA_MEMCPY); | |
1052 | ||
1053 | spin_lock_init(&mv_chan->lock); | |
1054 | INIT_LIST_HEAD(&mv_chan->chain); | |
1055 | INIT_LIST_HEAD(&mv_chan->completed_slots); | |
1056 | INIT_LIST_HEAD(&mv_chan->all_slots); | |
98817b99 TP |
1057 | mv_chan->dmachan.device = dma_dev; |
1058 | dma_cookie_init(&mv_chan->dmachan); | |
ff7b0479 | 1059 | |
98817b99 | 1060 | list_add_tail(&mv_chan->dmachan.device_node, &dma_dev->channels); |
ff7b0479 SB |
1061 | |
1062 | if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { | |
275cc0c8 | 1063 | ret = mv_xor_memcpy_self_test(mv_chan); |
ff7b0479 SB |
1064 | dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); |
1065 | if (ret) | |
2d0a0745 | 1066 | goto err_free_irq; |
ff7b0479 SB |
1067 | } |
1068 | ||
1069 | if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { | |
275cc0c8 | 1070 | ret = mv_xor_xor_self_test(mv_chan); |
ff7b0479 SB |
1071 | dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); |
1072 | if (ret) | |
2d0a0745 | 1073 | goto err_free_irq; |
ff7b0479 SB |
1074 | } |
1075 | ||
48a9db46 | 1076 | dev_info(&pdev->dev, "Marvell XOR: ( %s%s%s)\n", |
1ba151cd | 1077 | dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", |
1ba151cd JP |
1078 | dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", |
1079 | dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); | |
ff7b0479 SB |
1080 | |
1081 | dma_async_device_register(dma_dev); | |
1ef48a26 | 1082 | return mv_chan; |
ff7b0479 | 1083 | |
2d0a0745 TP |
1084 | err_free_irq: |
1085 | free_irq(mv_chan->irq, mv_chan); | |
ff7b0479 | 1086 | err_free_dma: |
b503fa01 | 1087 | dma_free_coherent(&pdev->dev, MV_XOR_POOL_SIZE, |
1ef48a26 | 1088 | mv_chan->dma_desc_pool_virt, mv_chan->dma_desc_pool); |
a6b4a9d2 | 1089 | return ERR_PTR(ret); |
ff7b0479 SB |
1090 | } |
1091 | ||
1092 | static void | |
297eedba | 1093 | mv_xor_conf_mbus_windows(struct mv_xor_device *xordev, |
63a9332b | 1094 | const struct mbus_dram_target_info *dram) |
ff7b0479 | 1095 | { |
297eedba | 1096 | void __iomem *base = xordev->xor_base; |
ff7b0479 SB |
1097 | u32 win_enable = 0; |
1098 | int i; | |
1099 | ||
1100 | for (i = 0; i < 8; i++) { | |
1101 | writel(0, base + WINDOW_BASE(i)); | |
1102 | writel(0, base + WINDOW_SIZE(i)); | |
1103 | if (i < 4) | |
1104 | writel(0, base + WINDOW_REMAP_HIGH(i)); | |
1105 | } | |
1106 | ||
1107 | for (i = 0; i < dram->num_cs; i++) { | |
63a9332b | 1108 | const struct mbus_dram_window *cs = dram->cs + i; |
ff7b0479 SB |
1109 | |
1110 | writel((cs->base & 0xffff0000) | | |
1111 | (cs->mbus_attr << 8) | | |
1112 | dram->mbus_dram_target_id, base + WINDOW_BASE(i)); | |
1113 | writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); | |
1114 | ||
1115 | win_enable |= (1 << i); | |
1116 | win_enable |= 3 << (16 + (2 * i)); | |
1117 | } | |
1118 | ||
1119 | writel(win_enable, base + WINDOW_BAR_ENABLE(0)); | |
1120 | writel(win_enable, base + WINDOW_BAR_ENABLE(1)); | |
c4b4b732 TP |
1121 | writel(0, base + WINDOW_OVERRIDE_CTRL(0)); |
1122 | writel(0, base + WINDOW_OVERRIDE_CTRL(1)); | |
ff7b0479 SB |
1123 | } |
1124 | ||
c2714334 | 1125 | static int mv_xor_probe(struct platform_device *pdev) |
ff7b0479 | 1126 | { |
63a9332b | 1127 | const struct mbus_dram_target_info *dram; |
297eedba | 1128 | struct mv_xor_device *xordev; |
d4adcc01 | 1129 | struct mv_xor_platform_data *pdata = dev_get_platdata(&pdev->dev); |
ff7b0479 | 1130 | struct resource *res; |
60d151f3 | 1131 | int i, ret; |
ff7b0479 | 1132 | |
1ba151cd | 1133 | dev_notice(&pdev->dev, "Marvell shared XOR driver\n"); |
ff7b0479 | 1134 | |
297eedba TP |
1135 | xordev = devm_kzalloc(&pdev->dev, sizeof(*xordev), GFP_KERNEL); |
1136 | if (!xordev) | |
ff7b0479 SB |
1137 | return -ENOMEM; |
1138 | ||
1139 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1140 | if (!res) | |
1141 | return -ENODEV; | |
1142 | ||
297eedba TP |
1143 | xordev->xor_base = devm_ioremap(&pdev->dev, res->start, |
1144 | resource_size(res)); | |
1145 | if (!xordev->xor_base) | |
ff7b0479 SB |
1146 | return -EBUSY; |
1147 | ||
1148 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1149 | if (!res) | |
1150 | return -ENODEV; | |
1151 | ||
297eedba TP |
1152 | xordev->xor_high_base = devm_ioremap(&pdev->dev, res->start, |
1153 | resource_size(res)); | |
1154 | if (!xordev->xor_high_base) | |
ff7b0479 SB |
1155 | return -EBUSY; |
1156 | ||
297eedba | 1157 | platform_set_drvdata(pdev, xordev); |
ff7b0479 SB |
1158 | |
1159 | /* | |
1160 | * (Re-)program MBUS remapping windows if we are asked to. | |
1161 | */ | |
63a9332b AL |
1162 | dram = mv_mbus_dram_info(); |
1163 | if (dram) | |
297eedba | 1164 | mv_xor_conf_mbus_windows(xordev, dram); |
ff7b0479 | 1165 | |
c510182b AL |
1166 | /* Not all platforms can gate the clock, so it is not |
1167 | * an error if the clock does not exists. | |
1168 | */ | |
297eedba TP |
1169 | xordev->clk = clk_get(&pdev->dev, NULL); |
1170 | if (!IS_ERR(xordev->clk)) | |
1171 | clk_prepare_enable(xordev->clk); | |
c510182b | 1172 | |
f7d12ef5 TP |
1173 | if (pdev->dev.of_node) { |
1174 | struct device_node *np; | |
1175 | int i = 0; | |
1176 | ||
1177 | for_each_child_of_node(pdev->dev.of_node, np) { | |
1178 | dma_cap_mask_t cap_mask; | |
1179 | int irq; | |
1180 | ||
1181 | dma_cap_zero(cap_mask); | |
1182 | if (of_property_read_bool(np, "dmacap,memcpy")) | |
1183 | dma_cap_set(DMA_MEMCPY, cap_mask); | |
1184 | if (of_property_read_bool(np, "dmacap,xor")) | |
1185 | dma_cap_set(DMA_XOR, cap_mask); | |
f7d12ef5 TP |
1186 | if (of_property_read_bool(np, "dmacap,interrupt")) |
1187 | dma_cap_set(DMA_INTERRUPT, cap_mask); | |
1188 | ||
1189 | irq = irq_of_parse_and_map(np, 0); | |
f8eb9e7d TP |
1190 | if (!irq) { |
1191 | ret = -ENODEV; | |
f7d12ef5 TP |
1192 | goto err_channel_add; |
1193 | } | |
1194 | ||
1195 | xordev->channels[i] = | |
1196 | mv_xor_channel_add(xordev, pdev, i, | |
1197 | cap_mask, irq); | |
1198 | if (IS_ERR(xordev->channels[i])) { | |
1199 | ret = PTR_ERR(xordev->channels[i]); | |
73d9cdca | 1200 | xordev->channels[i] = NULL; |
f7d12ef5 TP |
1201 | irq_dispose_mapping(irq); |
1202 | goto err_channel_add; | |
1203 | } | |
1204 | ||
1205 | i++; | |
1206 | } | |
1207 | } else if (pdata && pdata->channels) { | |
60d151f3 | 1208 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { |
e39f6ec1 | 1209 | struct mv_xor_channel_data *cd; |
60d151f3 TP |
1210 | int irq; |
1211 | ||
1212 | cd = &pdata->channels[i]; | |
1213 | if (!cd) { | |
1214 | ret = -ENODEV; | |
1215 | goto err_channel_add; | |
1216 | } | |
1217 | ||
1218 | irq = platform_get_irq(pdev, i); | |
1219 | if (irq < 0) { | |
1220 | ret = irq; | |
1221 | goto err_channel_add; | |
1222 | } | |
1223 | ||
297eedba | 1224 | xordev->channels[i] = |
9aedbdba | 1225 | mv_xor_channel_add(xordev, pdev, i, |
b503fa01 | 1226 | cd->cap_mask, irq); |
297eedba TP |
1227 | if (IS_ERR(xordev->channels[i])) { |
1228 | ret = PTR_ERR(xordev->channels[i]); | |
60d151f3 TP |
1229 | goto err_channel_add; |
1230 | } | |
1231 | } | |
1232 | } | |
c510182b | 1233 | |
ff7b0479 | 1234 | return 0; |
60d151f3 TP |
1235 | |
1236 | err_channel_add: | |
1237 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) | |
f7d12ef5 | 1238 | if (xordev->channels[i]) { |
ab6e439f | 1239 | mv_xor_channel_remove(xordev->channels[i]); |
f7d12ef5 TP |
1240 | if (pdev->dev.of_node) |
1241 | irq_dispose_mapping(xordev->channels[i]->irq); | |
f7d12ef5 | 1242 | } |
60d151f3 | 1243 | |
dab92064 TP |
1244 | if (!IS_ERR(xordev->clk)) { |
1245 | clk_disable_unprepare(xordev->clk); | |
1246 | clk_put(xordev->clk); | |
1247 | } | |
1248 | ||
60d151f3 | 1249 | return ret; |
ff7b0479 SB |
1250 | } |
1251 | ||
c2714334 | 1252 | static int mv_xor_remove(struct platform_device *pdev) |
ff7b0479 | 1253 | { |
297eedba | 1254 | struct mv_xor_device *xordev = platform_get_drvdata(pdev); |
60d151f3 TP |
1255 | int i; |
1256 | ||
1257 | for (i = 0; i < MV_XOR_MAX_CHANNELS; i++) { | |
297eedba TP |
1258 | if (xordev->channels[i]) |
1259 | mv_xor_channel_remove(xordev->channels[i]); | |
60d151f3 | 1260 | } |
c510182b | 1261 | |
297eedba TP |
1262 | if (!IS_ERR(xordev->clk)) { |
1263 | clk_disable_unprepare(xordev->clk); | |
1264 | clk_put(xordev->clk); | |
c510182b AL |
1265 | } |
1266 | ||
ff7b0479 SB |
1267 | return 0; |
1268 | } | |
1269 | ||
f7d12ef5 | 1270 | #ifdef CONFIG_OF |
c2714334 | 1271 | static struct of_device_id mv_xor_dt_ids[] = { |
f7d12ef5 TP |
1272 | { .compatible = "marvell,orion-xor", }, |
1273 | {}, | |
1274 | }; | |
1275 | MODULE_DEVICE_TABLE(of, mv_xor_dt_ids); | |
1276 | #endif | |
1277 | ||
61971656 TP |
1278 | static struct platform_driver mv_xor_driver = { |
1279 | .probe = mv_xor_probe, | |
c2714334 | 1280 | .remove = mv_xor_remove, |
ff7b0479 | 1281 | .driver = { |
f7d12ef5 TP |
1282 | .owner = THIS_MODULE, |
1283 | .name = MV_XOR_NAME, | |
1284 | .of_match_table = of_match_ptr(mv_xor_dt_ids), | |
ff7b0479 SB |
1285 | }, |
1286 | }; | |
1287 | ||
1288 | ||
1289 | static int __init mv_xor_init(void) | |
1290 | { | |
61971656 | 1291 | return platform_driver_register(&mv_xor_driver); |
ff7b0479 SB |
1292 | } |
1293 | module_init(mv_xor_init); | |
1294 | ||
1295 | /* it's currently unsafe to unload this module */ | |
1296 | #if 0 | |
1297 | static void __exit mv_xor_exit(void) | |
1298 | { | |
1299 | platform_driver_unregister(&mv_xor_driver); | |
ff7b0479 SB |
1300 | return; |
1301 | } | |
1302 | ||
1303 | module_exit(mv_xor_exit); | |
1304 | #endif | |
1305 | ||
1306 | MODULE_AUTHOR("Saeed Bishara <saeed@marvell.com>"); | |
1307 | MODULE_DESCRIPTION("DMA engine driver for Marvell's XOR engine"); | |
1308 | MODULE_LICENSE("GPL"); |