Commit | Line | Data |
---|---|---|
7bedaa55 RK |
1 | /* |
2 | * OMAP DMAengine support | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
fa3ad86a | 8 | #include <linux/delay.h> |
7bedaa55 RK |
9 | #include <linux/dmaengine.h> |
10 | #include <linux/dma-mapping.h> | |
11 | #include <linux/err.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/omap-dma.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/spinlock.h> | |
8d30662a JH |
20 | #include <linux/of_dma.h> |
21 | #include <linux/of_device.h> | |
7bedaa55 RK |
22 | |
23 | #include "virt-dma.h" | |
7d7e1eba | 24 | |
341ce712 PU |
25 | #define OMAP_SDMA_REQUESTS 127 |
26 | #define OMAP_SDMA_CHANNELS 32 | |
27 | ||
7bedaa55 RK |
28 | struct omap_dmadev { |
29 | struct dma_device ddev; | |
30 | spinlock_t lock; | |
31 | struct tasklet_struct task; | |
32 | struct list_head pending; | |
596c471b RK |
33 | void __iomem *base; |
34 | const struct omap_dma_reg *reg_map; | |
1b416c4b | 35 | struct omap_system_dma_plat_info *plat; |
6ddeb6d8 | 36 | bool legacy; |
de506089 | 37 | unsigned dma_requests; |
6ddeb6d8 RK |
38 | spinlock_t irq_lock; |
39 | uint32_t irq_enable_mask; | |
341ce712 | 40 | struct omap_chan *lch_map[OMAP_SDMA_CHANNELS]; |
7bedaa55 RK |
41 | }; |
42 | ||
43 | struct omap_chan { | |
44 | struct virt_dma_chan vc; | |
45 | struct list_head node; | |
596c471b RK |
46 | void __iomem *channel_base; |
47 | const struct omap_dma_reg *reg_map; | |
aa4c5b96 | 48 | uint32_t ccr; |
7bedaa55 RK |
49 | |
50 | struct dma_slave_config cfg; | |
51 | unsigned dma_sig; | |
3a774ea9 | 52 | bool cyclic; |
2dcdf570 | 53 | bool paused; |
7bedaa55 RK |
54 | |
55 | int dma_ch; | |
56 | struct omap_desc *desc; | |
57 | unsigned sgidx; | |
58 | }; | |
59 | ||
60 | struct omap_sg { | |
61 | dma_addr_t addr; | |
62 | uint32_t en; /* number of elements (24-bit) */ | |
63 | uint32_t fn; /* number of frames (16-bit) */ | |
64 | }; | |
65 | ||
66 | struct omap_desc { | |
67 | struct virt_dma_desc vd; | |
68 | enum dma_transfer_direction dir; | |
69 | dma_addr_t dev_addr; | |
70 | ||
7c836bc7 | 71 | int16_t fi; /* for OMAP_DMA_SYNC_PACKET */ |
9043826d | 72 | uint8_t es; /* CSDP_DATA_TYPE_xxx */ |
3ed4d18f | 73 | uint32_t ccr; /* CCR value */ |
965aeb4d | 74 | uint16_t clnk_ctrl; /* CLNK_CTRL value */ |
fa3ad86a | 75 | uint16_t cicr; /* CICR value */ |
2f0d13bd | 76 | uint32_t csdp; /* CSDP value */ |
7bedaa55 RK |
77 | |
78 | unsigned sglen; | |
79 | struct omap_sg sg[0]; | |
80 | }; | |
81 | ||
9043826d RK |
82 | enum { |
83 | CCR_FS = BIT(5), | |
84 | CCR_READ_PRIORITY = BIT(6), | |
85 | CCR_ENABLE = BIT(7), | |
86 | CCR_AUTO_INIT = BIT(8), /* OMAP1 only */ | |
87 | CCR_REPEAT = BIT(9), /* OMAP1 only */ | |
88 | CCR_OMAP31_DISABLE = BIT(10), /* OMAP1 only */ | |
89 | CCR_SUSPEND_SENSITIVE = BIT(8), /* OMAP2+ only */ | |
90 | CCR_RD_ACTIVE = BIT(9), /* OMAP2+ only */ | |
91 | CCR_WR_ACTIVE = BIT(10), /* OMAP2+ only */ | |
92 | CCR_SRC_AMODE_CONSTANT = 0 << 12, | |
93 | CCR_SRC_AMODE_POSTINC = 1 << 12, | |
94 | CCR_SRC_AMODE_SGLIDX = 2 << 12, | |
95 | CCR_SRC_AMODE_DBLIDX = 3 << 12, | |
96 | CCR_DST_AMODE_CONSTANT = 0 << 14, | |
97 | CCR_DST_AMODE_POSTINC = 1 << 14, | |
98 | CCR_DST_AMODE_SGLIDX = 2 << 14, | |
99 | CCR_DST_AMODE_DBLIDX = 3 << 14, | |
100 | CCR_CONSTANT_FILL = BIT(16), | |
101 | CCR_TRANSPARENT_COPY = BIT(17), | |
102 | CCR_BS = BIT(18), | |
103 | CCR_SUPERVISOR = BIT(22), | |
104 | CCR_PREFETCH = BIT(23), | |
105 | CCR_TRIGGER_SRC = BIT(24), | |
106 | CCR_BUFFERING_DISABLE = BIT(25), | |
107 | CCR_WRITE_PRIORITY = BIT(26), | |
108 | CCR_SYNC_ELEMENT = 0, | |
109 | CCR_SYNC_FRAME = CCR_FS, | |
110 | CCR_SYNC_BLOCK = CCR_BS, | |
111 | CCR_SYNC_PACKET = CCR_BS | CCR_FS, | |
112 | ||
113 | CSDP_DATA_TYPE_8 = 0, | |
114 | CSDP_DATA_TYPE_16 = 1, | |
115 | CSDP_DATA_TYPE_32 = 2, | |
116 | CSDP_SRC_PORT_EMIFF = 0 << 2, /* OMAP1 only */ | |
117 | CSDP_SRC_PORT_EMIFS = 1 << 2, /* OMAP1 only */ | |
118 | CSDP_SRC_PORT_OCP_T1 = 2 << 2, /* OMAP1 only */ | |
119 | CSDP_SRC_PORT_TIPB = 3 << 2, /* OMAP1 only */ | |
120 | CSDP_SRC_PORT_OCP_T2 = 4 << 2, /* OMAP1 only */ | |
121 | CSDP_SRC_PORT_MPUI = 5 << 2, /* OMAP1 only */ | |
122 | CSDP_SRC_PACKED = BIT(6), | |
123 | CSDP_SRC_BURST_1 = 0 << 7, | |
124 | CSDP_SRC_BURST_16 = 1 << 7, | |
125 | CSDP_SRC_BURST_32 = 2 << 7, | |
126 | CSDP_SRC_BURST_64 = 3 << 7, | |
127 | CSDP_DST_PORT_EMIFF = 0 << 9, /* OMAP1 only */ | |
128 | CSDP_DST_PORT_EMIFS = 1 << 9, /* OMAP1 only */ | |
129 | CSDP_DST_PORT_OCP_T1 = 2 << 9, /* OMAP1 only */ | |
130 | CSDP_DST_PORT_TIPB = 3 << 9, /* OMAP1 only */ | |
131 | CSDP_DST_PORT_OCP_T2 = 4 << 9, /* OMAP1 only */ | |
132 | CSDP_DST_PORT_MPUI = 5 << 9, /* OMAP1 only */ | |
133 | CSDP_DST_PACKED = BIT(13), | |
134 | CSDP_DST_BURST_1 = 0 << 14, | |
135 | CSDP_DST_BURST_16 = 1 << 14, | |
136 | CSDP_DST_BURST_32 = 2 << 14, | |
137 | CSDP_DST_BURST_64 = 3 << 14, | |
138 | ||
139 | CICR_TOUT_IE = BIT(0), /* OMAP1 only */ | |
140 | CICR_DROP_IE = BIT(1), | |
141 | CICR_HALF_IE = BIT(2), | |
142 | CICR_FRAME_IE = BIT(3), | |
143 | CICR_LAST_IE = BIT(4), | |
144 | CICR_BLOCK_IE = BIT(5), | |
145 | CICR_PKT_IE = BIT(7), /* OMAP2+ only */ | |
146 | CICR_TRANS_ERR_IE = BIT(8), /* OMAP2+ only */ | |
147 | CICR_SUPERVISOR_ERR_IE = BIT(10), /* OMAP2+ only */ | |
148 | CICR_MISALIGNED_ERR_IE = BIT(11), /* OMAP2+ only */ | |
149 | CICR_DRAIN_IE = BIT(12), /* OMAP2+ only */ | |
150 | CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */ | |
151 | ||
152 | CLNK_CTRL_ENABLE_LNK = BIT(15), | |
153 | }; | |
154 | ||
7bedaa55 | 155 | static const unsigned es_bytes[] = { |
9043826d RK |
156 | [CSDP_DATA_TYPE_8] = 1, |
157 | [CSDP_DATA_TYPE_16] = 2, | |
158 | [CSDP_DATA_TYPE_32] = 4, | |
7bedaa55 RK |
159 | }; |
160 | ||
8d30662a JH |
161 | static struct of_dma_filter_info omap_dma_info = { |
162 | .filter_fn = omap_dma_filter_fn, | |
163 | }; | |
164 | ||
7bedaa55 RK |
165 | static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d) |
166 | { | |
167 | return container_of(d, struct omap_dmadev, ddev); | |
168 | } | |
169 | ||
170 | static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c) | |
171 | { | |
172 | return container_of(c, struct omap_chan, vc.chan); | |
173 | } | |
174 | ||
175 | static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t) | |
176 | { | |
177 | return container_of(t, struct omap_desc, vd.tx); | |
178 | } | |
179 | ||
180 | static void omap_dma_desc_free(struct virt_dma_desc *vd) | |
181 | { | |
182 | kfree(container_of(vd, struct omap_desc, vd)); | |
183 | } | |
184 | ||
596c471b RK |
185 | static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr) |
186 | { | |
187 | switch (type) { | |
188 | case OMAP_DMA_REG_16BIT: | |
189 | writew_relaxed(val, addr); | |
190 | break; | |
191 | case OMAP_DMA_REG_2X16BIT: | |
192 | writew_relaxed(val, addr); | |
193 | writew_relaxed(val >> 16, addr + 2); | |
194 | break; | |
195 | case OMAP_DMA_REG_32BIT: | |
196 | writel_relaxed(val, addr); | |
197 | break; | |
198 | default: | |
199 | WARN_ON(1); | |
200 | } | |
201 | } | |
202 | ||
203 | static unsigned omap_dma_read(unsigned type, void __iomem *addr) | |
204 | { | |
205 | unsigned val; | |
206 | ||
207 | switch (type) { | |
208 | case OMAP_DMA_REG_16BIT: | |
209 | val = readw_relaxed(addr); | |
210 | break; | |
211 | case OMAP_DMA_REG_2X16BIT: | |
212 | val = readw_relaxed(addr); | |
213 | val |= readw_relaxed(addr + 2) << 16; | |
214 | break; | |
215 | case OMAP_DMA_REG_32BIT: | |
216 | val = readl_relaxed(addr); | |
217 | break; | |
218 | default: | |
219 | WARN_ON(1); | |
220 | val = 0; | |
221 | } | |
222 | ||
223 | return val; | |
224 | } | |
225 | ||
c5ed98b6 RK |
226 | static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val) |
227 | { | |
596c471b RK |
228 | const struct omap_dma_reg *r = od->reg_map + reg; |
229 | ||
230 | WARN_ON(r->stride); | |
231 | ||
232 | omap_dma_write(val, r->type, od->base + r->offset); | |
c5ed98b6 RK |
233 | } |
234 | ||
235 | static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg) | |
236 | { | |
596c471b RK |
237 | const struct omap_dma_reg *r = od->reg_map + reg; |
238 | ||
239 | WARN_ON(r->stride); | |
240 | ||
241 | return omap_dma_read(r->type, od->base + r->offset); | |
c5ed98b6 RK |
242 | } |
243 | ||
244 | static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val) | |
245 | { | |
596c471b RK |
246 | const struct omap_dma_reg *r = c->reg_map + reg; |
247 | ||
248 | omap_dma_write(val, r->type, c->channel_base + r->offset); | |
c5ed98b6 RK |
249 | } |
250 | ||
251 | static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg) | |
252 | { | |
596c471b RK |
253 | const struct omap_dma_reg *r = c->reg_map + reg; |
254 | ||
255 | return omap_dma_read(r->type, c->channel_base + r->offset); | |
c5ed98b6 RK |
256 | } |
257 | ||
470b23f7 RK |
258 | static void omap_dma_clear_csr(struct omap_chan *c) |
259 | { | |
260 | if (dma_omap1()) | |
c5ed98b6 | 261 | omap_dma_chan_read(c, CSR); |
470b23f7 | 262 | else |
c5ed98b6 | 263 | omap_dma_chan_write(c, CSR, ~0); |
470b23f7 RK |
264 | } |
265 | ||
6ddeb6d8 RK |
266 | static unsigned omap_dma_get_csr(struct omap_chan *c) |
267 | { | |
268 | unsigned val = omap_dma_chan_read(c, CSR); | |
269 | ||
270 | if (!dma_omap1()) | |
271 | omap_dma_chan_write(c, CSR, val); | |
272 | ||
273 | return val; | |
274 | } | |
275 | ||
596c471b RK |
276 | static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c, |
277 | unsigned lch) | |
278 | { | |
279 | c->channel_base = od->base + od->plat->channel_stride * lch; | |
6ddeb6d8 RK |
280 | |
281 | od->lch_map[lch] = c; | |
596c471b RK |
282 | } |
283 | ||
fa3ad86a RK |
284 | static void omap_dma_start(struct omap_chan *c, struct omap_desc *d) |
285 | { | |
286 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
fa3ad86a RK |
287 | |
288 | if (__dma_omap15xx(od->plat->dma_attr)) | |
c5ed98b6 | 289 | omap_dma_chan_write(c, CPC, 0); |
fa3ad86a | 290 | else |
c5ed98b6 | 291 | omap_dma_chan_write(c, CDAC, 0); |
fa3ad86a | 292 | |
470b23f7 | 293 | omap_dma_clear_csr(c); |
fa3ad86a RK |
294 | |
295 | /* Enable interrupts */ | |
c5ed98b6 | 296 | omap_dma_chan_write(c, CICR, d->cicr); |
fa3ad86a | 297 | |
45da7b04 | 298 | /* Enable channel */ |
c5ed98b6 | 299 | omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); |
fa3ad86a RK |
300 | } |
301 | ||
302 | static void omap_dma_stop(struct omap_chan *c) | |
303 | { | |
304 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
305 | uint32_t val; | |
306 | ||
307 | /* disable irq */ | |
c5ed98b6 | 308 | omap_dma_chan_write(c, CICR, 0); |
fa3ad86a | 309 | |
470b23f7 | 310 | omap_dma_clear_csr(c); |
fa3ad86a | 311 | |
c5ed98b6 | 312 | val = omap_dma_chan_read(c, CCR); |
9043826d | 313 | if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) { |
fa3ad86a RK |
314 | uint32_t sysconfig; |
315 | unsigned i; | |
316 | ||
c5ed98b6 | 317 | sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG); |
fa3ad86a RK |
318 | val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK; |
319 | val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); | |
c5ed98b6 | 320 | omap_dma_glbl_write(od, OCP_SYSCONFIG, val); |
fa3ad86a | 321 | |
c5ed98b6 | 322 | val = omap_dma_chan_read(c, CCR); |
9043826d | 323 | val &= ~CCR_ENABLE; |
c5ed98b6 | 324 | omap_dma_chan_write(c, CCR, val); |
fa3ad86a RK |
325 | |
326 | /* Wait for sDMA FIFO to drain */ | |
327 | for (i = 0; ; i++) { | |
c5ed98b6 | 328 | val = omap_dma_chan_read(c, CCR); |
9043826d | 329 | if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))) |
fa3ad86a RK |
330 | break; |
331 | ||
332 | if (i > 100) | |
333 | break; | |
334 | ||
335 | udelay(5); | |
336 | } | |
337 | ||
9043826d | 338 | if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)) |
fa3ad86a RK |
339 | dev_err(c->vc.chan.device->dev, |
340 | "DMA drain did not complete on lch %d\n", | |
341 | c->dma_ch); | |
342 | ||
c5ed98b6 | 343 | omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig); |
fa3ad86a | 344 | } else { |
9043826d | 345 | val &= ~CCR_ENABLE; |
c5ed98b6 | 346 | omap_dma_chan_write(c, CCR, val); |
fa3ad86a RK |
347 | } |
348 | ||
349 | mb(); | |
350 | ||
351 | if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) { | |
c5ed98b6 | 352 | val = omap_dma_chan_read(c, CLNK_CTRL); |
fa3ad86a RK |
353 | |
354 | if (dma_omap1()) | |
355 | val |= 1 << 14; /* set the STOP_LNK bit */ | |
356 | else | |
9043826d | 357 | val &= ~CLNK_CTRL_ENABLE_LNK; |
fa3ad86a | 358 | |
c5ed98b6 | 359 | omap_dma_chan_write(c, CLNK_CTRL, val); |
fa3ad86a RK |
360 | } |
361 | } | |
362 | ||
7bedaa55 RK |
363 | static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d, |
364 | unsigned idx) | |
365 | { | |
366 | struct omap_sg *sg = d->sg + idx; | |
893e63e3 | 367 | unsigned cxsa, cxei, cxfi; |
913a2d0c | 368 | |
4ce98c0a | 369 | if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) { |
893e63e3 RK |
370 | cxsa = CDSA; |
371 | cxei = CDEI; | |
372 | cxfi = CDFI; | |
913a2d0c | 373 | } else { |
893e63e3 RK |
374 | cxsa = CSSA; |
375 | cxei = CSEI; | |
376 | cxfi = CSFI; | |
913a2d0c RK |
377 | } |
378 | ||
c5ed98b6 RK |
379 | omap_dma_chan_write(c, cxsa, sg->addr); |
380 | omap_dma_chan_write(c, cxei, 0); | |
381 | omap_dma_chan_write(c, cxfi, 0); | |
382 | omap_dma_chan_write(c, CEN, sg->en); | |
383 | omap_dma_chan_write(c, CFN, sg->fn); | |
913a2d0c | 384 | |
fa3ad86a | 385 | omap_dma_start(c, d); |
913a2d0c RK |
386 | } |
387 | ||
388 | static void omap_dma_start_desc(struct omap_chan *c) | |
389 | { | |
390 | struct virt_dma_desc *vd = vchan_next_desc(&c->vc); | |
391 | struct omap_desc *d; | |
893e63e3 | 392 | unsigned cxsa, cxei, cxfi; |
b9e97822 | 393 | |
913a2d0c RK |
394 | if (!vd) { |
395 | c->desc = NULL; | |
396 | return; | |
397 | } | |
398 | ||
399 | list_del(&vd->node); | |
400 | ||
401 | c->desc = d = to_omap_dma_desc(&vd->tx); | |
402 | c->sgidx = 0; | |
403 | ||
59871902 RK |
404 | /* |
405 | * This provides the necessary barrier to ensure data held in | |
406 | * DMA coherent memory is visible to the DMA engine prior to | |
407 | * the transfer starting. | |
408 | */ | |
409 | mb(); | |
410 | ||
c5ed98b6 | 411 | omap_dma_chan_write(c, CCR, d->ccr); |
3ed4d18f | 412 | if (dma_omap1()) |
c5ed98b6 | 413 | omap_dma_chan_write(c, CCR2, d->ccr >> 16); |
b9e97822 | 414 | |
4ce98c0a | 415 | if (d->dir == DMA_DEV_TO_MEM || d->dir == DMA_MEM_TO_MEM) { |
893e63e3 RK |
416 | cxsa = CSSA; |
417 | cxei = CSEI; | |
418 | cxfi = CSFI; | |
b9e97822 | 419 | } else { |
893e63e3 RK |
420 | cxsa = CDSA; |
421 | cxei = CDEI; | |
422 | cxfi = CDFI; | |
b9e97822 RK |
423 | } |
424 | ||
c5ed98b6 RK |
425 | omap_dma_chan_write(c, cxsa, d->dev_addr); |
426 | omap_dma_chan_write(c, cxei, 0); | |
427 | omap_dma_chan_write(c, cxfi, d->fi); | |
428 | omap_dma_chan_write(c, CSDP, d->csdp); | |
429 | omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl); | |
b9e97822 | 430 | |
7bedaa55 RK |
431 | omap_dma_start_sg(c, d, 0); |
432 | } | |
433 | ||
434 | static void omap_dma_callback(int ch, u16 status, void *data) | |
435 | { | |
436 | struct omap_chan *c = data; | |
437 | struct omap_desc *d; | |
438 | unsigned long flags; | |
439 | ||
440 | spin_lock_irqsave(&c->vc.lock, flags); | |
441 | d = c->desc; | |
442 | if (d) { | |
3a774ea9 RK |
443 | if (!c->cyclic) { |
444 | if (++c->sgidx < d->sglen) { | |
445 | omap_dma_start_sg(c, d, c->sgidx); | |
446 | } else { | |
447 | omap_dma_start_desc(c); | |
448 | vchan_cookie_complete(&d->vd); | |
449 | } | |
7bedaa55 | 450 | } else { |
3a774ea9 | 451 | vchan_cyclic_callback(&d->vd); |
7bedaa55 RK |
452 | } |
453 | } | |
454 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
455 | } | |
456 | ||
457 | /* | |
458 | * This callback schedules all pending channels. We could be more | |
459 | * clever here by postponing allocation of the real DMA channels to | |
460 | * this point, and freeing them when our virtual channel becomes idle. | |
461 | * | |
462 | * We would then need to deal with 'all channels in-use' | |
463 | */ | |
464 | static void omap_dma_sched(unsigned long data) | |
465 | { | |
466 | struct omap_dmadev *d = (struct omap_dmadev *)data; | |
467 | LIST_HEAD(head); | |
468 | ||
469 | spin_lock_irq(&d->lock); | |
470 | list_splice_tail_init(&d->pending, &head); | |
471 | spin_unlock_irq(&d->lock); | |
472 | ||
473 | while (!list_empty(&head)) { | |
474 | struct omap_chan *c = list_first_entry(&head, | |
475 | struct omap_chan, node); | |
476 | ||
477 | spin_lock_irq(&c->vc.lock); | |
478 | list_del_init(&c->node); | |
479 | omap_dma_start_desc(c); | |
480 | spin_unlock_irq(&c->vc.lock); | |
481 | } | |
482 | } | |
483 | ||
6ddeb6d8 RK |
484 | static irqreturn_t omap_dma_irq(int irq, void *devid) |
485 | { | |
486 | struct omap_dmadev *od = devid; | |
487 | unsigned status, channel; | |
488 | ||
489 | spin_lock(&od->irq_lock); | |
490 | ||
491 | status = omap_dma_glbl_read(od, IRQSTATUS_L1); | |
492 | status &= od->irq_enable_mask; | |
493 | if (status == 0) { | |
494 | spin_unlock(&od->irq_lock); | |
495 | return IRQ_NONE; | |
496 | } | |
497 | ||
498 | while ((channel = ffs(status)) != 0) { | |
499 | unsigned mask, csr; | |
500 | struct omap_chan *c; | |
501 | ||
502 | channel -= 1; | |
503 | mask = BIT(channel); | |
504 | status &= ~mask; | |
505 | ||
506 | c = od->lch_map[channel]; | |
507 | if (c == NULL) { | |
508 | /* This should never happen */ | |
509 | dev_err(od->ddev.dev, "invalid channel %u\n", channel); | |
510 | continue; | |
511 | } | |
512 | ||
513 | csr = omap_dma_get_csr(c); | |
514 | omap_dma_glbl_write(od, IRQSTATUS_L1, mask); | |
515 | ||
516 | omap_dma_callback(channel, csr, c); | |
517 | } | |
518 | ||
519 | spin_unlock(&od->irq_lock); | |
520 | ||
521 | return IRQ_HANDLED; | |
522 | } | |
523 | ||
7bedaa55 RK |
524 | static int omap_dma_alloc_chan_resources(struct dma_chan *chan) |
525 | { | |
596c471b | 526 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
7bedaa55 | 527 | struct omap_chan *c = to_omap_dma_chan(chan); |
596c471b RK |
528 | int ret; |
529 | ||
6ddeb6d8 RK |
530 | if (od->legacy) { |
531 | ret = omap_request_dma(c->dma_sig, "DMA engine", | |
532 | omap_dma_callback, c, &c->dma_ch); | |
533 | } else { | |
534 | ret = omap_request_dma(c->dma_sig, "DMA engine", NULL, NULL, | |
535 | &c->dma_ch); | |
536 | } | |
7bedaa55 | 537 | |
6ddeb6d8 RK |
538 | dev_dbg(od->ddev.dev, "allocating channel %u for %u\n", |
539 | c->dma_ch, c->dma_sig); | |
7bedaa55 | 540 | |
6ddeb6d8 | 541 | if (ret >= 0) { |
596c471b RK |
542 | omap_dma_assign(od, c, c->dma_ch); |
543 | ||
6ddeb6d8 RK |
544 | if (!od->legacy) { |
545 | unsigned val; | |
546 | ||
547 | spin_lock_irq(&od->irq_lock); | |
548 | val = BIT(c->dma_ch); | |
549 | omap_dma_glbl_write(od, IRQSTATUS_L1, val); | |
550 | od->irq_enable_mask |= val; | |
551 | omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask); | |
552 | ||
553 | val = omap_dma_glbl_read(od, IRQENABLE_L0); | |
554 | val &= ~BIT(c->dma_ch); | |
555 | omap_dma_glbl_write(od, IRQENABLE_L0, val); | |
556 | spin_unlock_irq(&od->irq_lock); | |
557 | } | |
558 | } | |
559 | ||
aa4c5b96 RK |
560 | if (dma_omap1()) { |
561 | if (__dma_omap16xx(od->plat->dma_attr)) { | |
562 | c->ccr = CCR_OMAP31_DISABLE; | |
563 | /* Duplicate what plat-omap/dma.c does */ | |
564 | c->ccr |= c->dma_ch + 1; | |
565 | } else { | |
566 | c->ccr = c->dma_sig & 0x1f; | |
567 | } | |
568 | } else { | |
569 | c->ccr = c->dma_sig & 0x1f; | |
570 | c->ccr |= (c->dma_sig & ~0x1f) << 14; | |
571 | } | |
572 | if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING) | |
573 | c->ccr |= CCR_BUFFERING_DISABLE; | |
574 | ||
596c471b | 575 | return ret; |
7bedaa55 RK |
576 | } |
577 | ||
578 | static void omap_dma_free_chan_resources(struct dma_chan *chan) | |
579 | { | |
6ddeb6d8 | 580 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
7bedaa55 RK |
581 | struct omap_chan *c = to_omap_dma_chan(chan); |
582 | ||
6ddeb6d8 RK |
583 | if (!od->legacy) { |
584 | spin_lock_irq(&od->irq_lock); | |
585 | od->irq_enable_mask &= ~BIT(c->dma_ch); | |
586 | omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask); | |
587 | spin_unlock_irq(&od->irq_lock); | |
588 | } | |
589 | ||
596c471b | 590 | c->channel_base = NULL; |
6ddeb6d8 | 591 | od->lch_map[c->dma_ch] = NULL; |
7bedaa55 RK |
592 | vchan_free_chan_resources(&c->vc); |
593 | omap_free_dma(c->dma_ch); | |
594 | ||
6ddeb6d8 | 595 | dev_dbg(od->ddev.dev, "freeing channel for %u\n", c->dma_sig); |
eea531ea | 596 | c->dma_sig = 0; |
7bedaa55 RK |
597 | } |
598 | ||
3850e22f RK |
599 | static size_t omap_dma_sg_size(struct omap_sg *sg) |
600 | { | |
601 | return sg->en * sg->fn; | |
602 | } | |
603 | ||
604 | static size_t omap_dma_desc_size(struct omap_desc *d) | |
605 | { | |
606 | unsigned i; | |
607 | size_t size; | |
608 | ||
609 | for (size = i = 0; i < d->sglen; i++) | |
610 | size += omap_dma_sg_size(&d->sg[i]); | |
611 | ||
612 | return size * es_bytes[d->es]; | |
613 | } | |
614 | ||
615 | static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr) | |
616 | { | |
617 | unsigned i; | |
618 | size_t size, es_size = es_bytes[d->es]; | |
619 | ||
620 | for (size = i = 0; i < d->sglen; i++) { | |
621 | size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size; | |
622 | ||
623 | if (size) | |
624 | size += this_size; | |
625 | else if (addr >= d->sg[i].addr && | |
626 | addr < d->sg[i].addr + this_size) | |
627 | size += d->sg[i].addr + this_size - addr; | |
628 | } | |
629 | return size; | |
630 | } | |
631 | ||
b07fd625 RK |
632 | /* |
633 | * OMAP 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | |
634 | * read before the DMA controller finished disabling the channel. | |
635 | */ | |
636 | static uint32_t omap_dma_chan_read_3_3(struct omap_chan *c, unsigned reg) | |
637 | { | |
638 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
639 | uint32_t val; | |
640 | ||
641 | val = omap_dma_chan_read(c, reg); | |
642 | if (val == 0 && od->plat->errata & DMA_ERRATA_3_3) | |
643 | val = omap_dma_chan_read(c, reg); | |
644 | ||
645 | return val; | |
646 | } | |
647 | ||
3997cab3 RK |
648 | static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c) |
649 | { | |
650 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
b07fd625 | 651 | dma_addr_t addr, cdac; |
3997cab3 | 652 | |
b07fd625 | 653 | if (__dma_omap15xx(od->plat->dma_attr)) { |
c5ed98b6 | 654 | addr = omap_dma_chan_read(c, CPC); |
b07fd625 RK |
655 | } else { |
656 | addr = omap_dma_chan_read_3_3(c, CSAC); | |
657 | cdac = omap_dma_chan_read_3_3(c, CDAC); | |
3997cab3 | 658 | |
3997cab3 RK |
659 | /* |
660 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
661 | * not been started (no data has been transferred so far). | |
662 | * Return the programmed source start address in this case. | |
663 | */ | |
b07fd625 | 664 | if (cdac == 0) |
c5ed98b6 | 665 | addr = omap_dma_chan_read(c, CSSA); |
3997cab3 RK |
666 | } |
667 | ||
668 | if (dma_omap1()) | |
c5ed98b6 | 669 | addr |= omap_dma_chan_read(c, CSSA) & 0xffff0000; |
3997cab3 RK |
670 | |
671 | return addr; | |
672 | } | |
673 | ||
674 | static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c) | |
675 | { | |
676 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
677 | dma_addr_t addr; | |
678 | ||
b07fd625 | 679 | if (__dma_omap15xx(od->plat->dma_attr)) { |
c5ed98b6 | 680 | addr = omap_dma_chan_read(c, CPC); |
b07fd625 RK |
681 | } else { |
682 | addr = omap_dma_chan_read_3_3(c, CDAC); | |
3997cab3 | 683 | |
3997cab3 | 684 | /* |
b07fd625 RK |
685 | * CDAC == 0 indicates that the DMA transfer on the channel |
686 | * has not been started (no data has been transferred so | |
687 | * far). Return the programmed destination start address in | |
688 | * this case. | |
3997cab3 RK |
689 | */ |
690 | if (addr == 0) | |
c5ed98b6 | 691 | addr = omap_dma_chan_read(c, CDSA); |
3997cab3 RK |
692 | } |
693 | ||
694 | if (dma_omap1()) | |
c5ed98b6 | 695 | addr |= omap_dma_chan_read(c, CDSA) & 0xffff0000; |
3997cab3 RK |
696 | |
697 | return addr; | |
698 | } | |
699 | ||
7bedaa55 RK |
700 | static enum dma_status omap_dma_tx_status(struct dma_chan *chan, |
701 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
702 | { | |
3850e22f RK |
703 | struct omap_chan *c = to_omap_dma_chan(chan); |
704 | struct virt_dma_desc *vd; | |
705 | enum dma_status ret; | |
706 | unsigned long flags; | |
707 | ||
708 | ret = dma_cookie_status(chan, cookie, txstate); | |
7cce5083 | 709 | if (ret == DMA_COMPLETE || !txstate) |
3850e22f RK |
710 | return ret; |
711 | ||
712 | spin_lock_irqsave(&c->vc.lock, flags); | |
713 | vd = vchan_find_desc(&c->vc, cookie); | |
714 | if (vd) { | |
715 | txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx)); | |
716 | } else if (c->desc && c->desc->vd.tx.cookie == cookie) { | |
717 | struct omap_desc *d = c->desc; | |
718 | dma_addr_t pos; | |
719 | ||
720 | if (d->dir == DMA_MEM_TO_DEV) | |
3997cab3 | 721 | pos = omap_dma_get_src_pos(c); |
3850e22f | 722 | else if (d->dir == DMA_DEV_TO_MEM) |
3997cab3 | 723 | pos = omap_dma_get_dst_pos(c); |
3850e22f RK |
724 | else |
725 | pos = 0; | |
726 | ||
727 | txstate->residue = omap_dma_desc_size_pos(d, pos); | |
728 | } else { | |
729 | txstate->residue = 0; | |
730 | } | |
731 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
732 | ||
733 | return ret; | |
7bedaa55 RK |
734 | } |
735 | ||
736 | static void omap_dma_issue_pending(struct dma_chan *chan) | |
737 | { | |
738 | struct omap_chan *c = to_omap_dma_chan(chan); | |
739 | unsigned long flags; | |
740 | ||
741 | spin_lock_irqsave(&c->vc.lock, flags); | |
742 | if (vchan_issue_pending(&c->vc) && !c->desc) { | |
76502469 PU |
743 | /* |
744 | * c->cyclic is used only by audio and in this case the DMA need | |
745 | * to be started without delay. | |
746 | */ | |
747 | if (!c->cyclic) { | |
748 | struct omap_dmadev *d = to_omap_dma_dev(chan->device); | |
749 | spin_lock(&d->lock); | |
750 | if (list_empty(&c->node)) | |
751 | list_add_tail(&c->node, &d->pending); | |
752 | spin_unlock(&d->lock); | |
753 | tasklet_schedule(&d->task); | |
754 | } else { | |
755 | omap_dma_start_desc(c); | |
756 | } | |
7bedaa55 RK |
757 | } |
758 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
759 | } | |
760 | ||
761 | static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg( | |
762 | struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen, | |
763 | enum dma_transfer_direction dir, unsigned long tx_flags, void *context) | |
764 | { | |
49ae0b29 | 765 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
7bedaa55 RK |
766 | struct omap_chan *c = to_omap_dma_chan(chan); |
767 | enum dma_slave_buswidth dev_width; | |
768 | struct scatterlist *sgent; | |
769 | struct omap_desc *d; | |
770 | dma_addr_t dev_addr; | |
3ed4d18f | 771 | unsigned i, j = 0, es, en, frame_bytes; |
7bedaa55 RK |
772 | u32 burst; |
773 | ||
774 | if (dir == DMA_DEV_TO_MEM) { | |
775 | dev_addr = c->cfg.src_addr; | |
776 | dev_width = c->cfg.src_addr_width; | |
777 | burst = c->cfg.src_maxburst; | |
7bedaa55 RK |
778 | } else if (dir == DMA_MEM_TO_DEV) { |
779 | dev_addr = c->cfg.dst_addr; | |
780 | dev_width = c->cfg.dst_addr_width; | |
781 | burst = c->cfg.dst_maxburst; | |
7bedaa55 RK |
782 | } else { |
783 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); | |
784 | return NULL; | |
785 | } | |
786 | ||
787 | /* Bus width translates to the element size (ES) */ | |
788 | switch (dev_width) { | |
789 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
9043826d | 790 | es = CSDP_DATA_TYPE_8; |
7bedaa55 RK |
791 | break; |
792 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
9043826d | 793 | es = CSDP_DATA_TYPE_16; |
7bedaa55 RK |
794 | break; |
795 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
9043826d | 796 | es = CSDP_DATA_TYPE_32; |
7bedaa55 RK |
797 | break; |
798 | default: /* not reached */ | |
799 | return NULL; | |
800 | } | |
801 | ||
802 | /* Now allocate and setup the descriptor. */ | |
803 | d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC); | |
804 | if (!d) | |
805 | return NULL; | |
806 | ||
807 | d->dir = dir; | |
808 | d->dev_addr = dev_addr; | |
809 | d->es = es; | |
3ed4d18f | 810 | |
aa4c5b96 | 811 | d->ccr = c->ccr | CCR_SYNC_FRAME; |
3ed4d18f | 812 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 813 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
3ed4d18f | 814 | else |
9043826d | 815 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
3ed4d18f | 816 | |
9043826d | 817 | d->cicr = CICR_DROP_IE | CICR_BLOCK_IE; |
2f0d13bd | 818 | d->csdp = es; |
fa3ad86a | 819 | |
2f0d13bd | 820 | if (dma_omap1()) { |
9043826d | 821 | d->cicr |= CICR_TOUT_IE; |
2f0d13bd RK |
822 | |
823 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 824 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB; |
2f0d13bd | 825 | else |
9043826d | 826 | d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF; |
2f0d13bd | 827 | } else { |
3ed4d18f | 828 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 829 | d->ccr |= CCR_TRIGGER_SRC; |
3ed4d18f | 830 | |
9043826d | 831 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
2f0d13bd | 832 | } |
965aeb4d RK |
833 | if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS) |
834 | d->clnk_ctrl = c->dma_ch; | |
7bedaa55 RK |
835 | |
836 | /* | |
837 | * Build our scatterlist entries: each contains the address, | |
838 | * the number of elements (EN) in each frame, and the number of | |
839 | * frames (FN). Number of bytes for this entry = ES * EN * FN. | |
840 | * | |
841 | * Burst size translates to number of elements with frame sync. | |
842 | * Note: DMA engine defines burst to be the number of dev-width | |
843 | * transfers. | |
844 | */ | |
845 | en = burst; | |
846 | frame_bytes = es_bytes[es] * en; | |
847 | for_each_sg(sgl, sgent, sglen, i) { | |
848 | d->sg[j].addr = sg_dma_address(sgent); | |
849 | d->sg[j].en = en; | |
850 | d->sg[j].fn = sg_dma_len(sgent) / frame_bytes; | |
851 | j++; | |
852 | } | |
853 | ||
854 | d->sglen = j; | |
855 | ||
856 | return vchan_tx_prep(&c->vc, &d->vd, tx_flags); | |
857 | } | |
858 | ||
3a774ea9 RK |
859 | static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic( |
860 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
31c1e5a1 | 861 | size_t period_len, enum dma_transfer_direction dir, unsigned long flags) |
3a774ea9 | 862 | { |
fa3ad86a | 863 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
3a774ea9 RK |
864 | struct omap_chan *c = to_omap_dma_chan(chan); |
865 | enum dma_slave_buswidth dev_width; | |
866 | struct omap_desc *d; | |
867 | dma_addr_t dev_addr; | |
3ed4d18f | 868 | unsigned es; |
3a774ea9 RK |
869 | u32 burst; |
870 | ||
871 | if (dir == DMA_DEV_TO_MEM) { | |
872 | dev_addr = c->cfg.src_addr; | |
873 | dev_width = c->cfg.src_addr_width; | |
874 | burst = c->cfg.src_maxburst; | |
3a774ea9 RK |
875 | } else if (dir == DMA_MEM_TO_DEV) { |
876 | dev_addr = c->cfg.dst_addr; | |
877 | dev_width = c->cfg.dst_addr_width; | |
878 | burst = c->cfg.dst_maxburst; | |
3a774ea9 RK |
879 | } else { |
880 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); | |
881 | return NULL; | |
882 | } | |
883 | ||
884 | /* Bus width translates to the element size (ES) */ | |
885 | switch (dev_width) { | |
886 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
9043826d | 887 | es = CSDP_DATA_TYPE_8; |
3a774ea9 RK |
888 | break; |
889 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
9043826d | 890 | es = CSDP_DATA_TYPE_16; |
3a774ea9 RK |
891 | break; |
892 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
9043826d | 893 | es = CSDP_DATA_TYPE_32; |
3a774ea9 RK |
894 | break; |
895 | default: /* not reached */ | |
896 | return NULL; | |
897 | } | |
898 | ||
899 | /* Now allocate and setup the descriptor. */ | |
900 | d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC); | |
901 | if (!d) | |
902 | return NULL; | |
903 | ||
904 | d->dir = dir; | |
905 | d->dev_addr = dev_addr; | |
906 | d->fi = burst; | |
907 | d->es = es; | |
3a774ea9 RK |
908 | d->sg[0].addr = buf_addr; |
909 | d->sg[0].en = period_len / es_bytes[es]; | |
910 | d->sg[0].fn = buf_len / period_len; | |
911 | d->sglen = 1; | |
3ed4d18f | 912 | |
aa4c5b96 | 913 | d->ccr = c->ccr; |
3ed4d18f | 914 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 915 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
3ed4d18f | 916 | else |
9043826d | 917 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
3ed4d18f | 918 | |
9043826d | 919 | d->cicr = CICR_DROP_IE; |
fa3ad86a | 920 | if (flags & DMA_PREP_INTERRUPT) |
9043826d | 921 | d->cicr |= CICR_FRAME_IE; |
fa3ad86a | 922 | |
2f0d13bd RK |
923 | d->csdp = es; |
924 | ||
925 | if (dma_omap1()) { | |
9043826d | 926 | d->cicr |= CICR_TOUT_IE; |
2f0d13bd RK |
927 | |
928 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 929 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI; |
2f0d13bd | 930 | else |
9043826d | 931 | d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF; |
2f0d13bd | 932 | } else { |
3ed4d18f | 933 | if (burst) |
9043826d RK |
934 | d->ccr |= CCR_SYNC_PACKET; |
935 | else | |
936 | d->ccr |= CCR_SYNC_ELEMENT; | |
3ed4d18f RK |
937 | |
938 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 939 | d->ccr |= CCR_TRIGGER_SRC; |
3ed4d18f | 940 | |
9043826d | 941 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
3a774ea9 | 942 | |
9043826d | 943 | d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64; |
2f0d13bd RK |
944 | } |
945 | ||
965aeb4d RK |
946 | if (__dma_omap15xx(od->plat->dma_attr)) |
947 | d->ccr |= CCR_AUTO_INIT | CCR_REPEAT; | |
948 | else | |
949 | d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK; | |
950 | ||
3ed4d18f | 951 | c->cyclic = true; |
3a774ea9 | 952 | |
2dde5b90 | 953 | return vchan_tx_prep(&c->vc, &d->vd, flags); |
3a774ea9 RK |
954 | } |
955 | ||
4ce98c0a PU |
956 | static struct dma_async_tx_descriptor *omap_dma_prep_dma_memcpy( |
957 | struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, | |
958 | size_t len, unsigned long tx_flags) | |
959 | { | |
960 | struct omap_chan *c = to_omap_dma_chan(chan); | |
961 | struct omap_desc *d; | |
962 | uint8_t data_type; | |
963 | ||
964 | d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC); | |
965 | if (!d) | |
966 | return NULL; | |
967 | ||
968 | data_type = __ffs((src | dest | len)); | |
969 | if (data_type > CSDP_DATA_TYPE_32) | |
970 | data_type = CSDP_DATA_TYPE_32; | |
971 | ||
972 | d->dir = DMA_MEM_TO_MEM; | |
973 | d->dev_addr = src; | |
974 | d->fi = 0; | |
975 | d->es = data_type; | |
976 | d->sg[0].en = len / BIT(data_type); | |
977 | d->sg[0].fn = 1; | |
978 | d->sg[0].addr = dest; | |
979 | d->sglen = 1; | |
980 | d->ccr = c->ccr; | |
981 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_POSTINC; | |
982 | ||
983 | d->cicr = CICR_DROP_IE; | |
984 | if (tx_flags & DMA_PREP_INTERRUPT) | |
985 | d->cicr |= CICR_FRAME_IE; | |
986 | ||
987 | d->csdp = data_type; | |
988 | ||
989 | if (dma_omap1()) { | |
990 | d->cicr |= CICR_TOUT_IE; | |
991 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_EMIFF; | |
992 | } else { | |
993 | d->csdp |= CSDP_DST_PACKED | CSDP_SRC_PACKED; | |
994 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; | |
995 | d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64; | |
996 | } | |
997 | ||
998 | return vchan_tx_prep(&c->vc, &d->vd, tx_flags); | |
999 | } | |
1000 | ||
78ea4fe7 | 1001 | static int omap_dma_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) |
7bedaa55 | 1002 | { |
78ea4fe7 MR |
1003 | struct omap_chan *c = to_omap_dma_chan(chan); |
1004 | ||
7bedaa55 RK |
1005 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
1006 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
1007 | return -EINVAL; | |
1008 | ||
1009 | memcpy(&c->cfg, cfg, sizeof(c->cfg)); | |
1010 | ||
1011 | return 0; | |
1012 | } | |
1013 | ||
78ea4fe7 | 1014 | static int omap_dma_terminate_all(struct dma_chan *chan) |
7bedaa55 | 1015 | { |
78ea4fe7 | 1016 | struct omap_chan *c = to_omap_dma_chan(chan); |
7bedaa55 RK |
1017 | struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device); |
1018 | unsigned long flags; | |
1019 | LIST_HEAD(head); | |
1020 | ||
1021 | spin_lock_irqsave(&c->vc.lock, flags); | |
1022 | ||
1023 | /* Prevent this channel being scheduled */ | |
1024 | spin_lock(&d->lock); | |
1025 | list_del_init(&c->node); | |
1026 | spin_unlock(&d->lock); | |
1027 | ||
1028 | /* | |
1029 | * Stop DMA activity: we assume the callback will not be called | |
fa3ad86a | 1030 | * after omap_dma_stop() returns (even if it does, it will see |
7bedaa55 RK |
1031 | * c->desc is NULL and exit.) |
1032 | */ | |
1033 | if (c->desc) { | |
02d88b73 | 1034 | omap_dma_desc_free(&c->desc->vd); |
7bedaa55 | 1035 | c->desc = NULL; |
2dcdf570 PU |
1036 | /* Avoid stopping the dma twice */ |
1037 | if (!c->paused) | |
fa3ad86a | 1038 | omap_dma_stop(c); |
7bedaa55 RK |
1039 | } |
1040 | ||
3a774ea9 RK |
1041 | if (c->cyclic) { |
1042 | c->cyclic = false; | |
2dcdf570 | 1043 | c->paused = false; |
3a774ea9 RK |
1044 | } |
1045 | ||
7bedaa55 RK |
1046 | vchan_get_all_descriptors(&c->vc, &head); |
1047 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
1048 | vchan_dma_desc_free_list(&c->vc, &head); | |
1049 | ||
1050 | return 0; | |
1051 | } | |
1052 | ||
78ea4fe7 | 1053 | static int omap_dma_pause(struct dma_chan *chan) |
7bedaa55 | 1054 | { |
78ea4fe7 MR |
1055 | struct omap_chan *c = to_omap_dma_chan(chan); |
1056 | ||
2dcdf570 PU |
1057 | /* Pause/Resume only allowed with cyclic mode */ |
1058 | if (!c->cyclic) | |
1059 | return -EINVAL; | |
1060 | ||
1061 | if (!c->paused) { | |
fa3ad86a | 1062 | omap_dma_stop(c); |
2dcdf570 PU |
1063 | c->paused = true; |
1064 | } | |
1065 | ||
1066 | return 0; | |
7bedaa55 RK |
1067 | } |
1068 | ||
78ea4fe7 | 1069 | static int omap_dma_resume(struct dma_chan *chan) |
7bedaa55 | 1070 | { |
78ea4fe7 MR |
1071 | struct omap_chan *c = to_omap_dma_chan(chan); |
1072 | ||
2dcdf570 PU |
1073 | /* Pause/Resume only allowed with cyclic mode */ |
1074 | if (!c->cyclic) | |
1075 | return -EINVAL; | |
1076 | ||
1077 | if (c->paused) { | |
b3d09da7 PU |
1078 | mb(); |
1079 | ||
bfb60745 PU |
1080 | /* Restore channel link register */ |
1081 | omap_dma_chan_write(c, CLNK_CTRL, c->desc->clnk_ctrl); | |
1082 | ||
fa3ad86a | 1083 | omap_dma_start(c, c->desc); |
2dcdf570 PU |
1084 | c->paused = false; |
1085 | } | |
1086 | ||
1087 | return 0; | |
7bedaa55 RK |
1088 | } |
1089 | ||
eea531ea | 1090 | static int omap_dma_chan_init(struct omap_dmadev *od) |
7bedaa55 RK |
1091 | { |
1092 | struct omap_chan *c; | |
1093 | ||
1094 | c = kzalloc(sizeof(*c), GFP_KERNEL); | |
1095 | if (!c) | |
1096 | return -ENOMEM; | |
1097 | ||
596c471b | 1098 | c->reg_map = od->reg_map; |
7bedaa55 RK |
1099 | c->vc.desc_free = omap_dma_desc_free; |
1100 | vchan_init(&c->vc, &od->ddev); | |
1101 | INIT_LIST_HEAD(&c->node); | |
1102 | ||
7bedaa55 RK |
1103 | return 0; |
1104 | } | |
1105 | ||
1106 | static void omap_dma_free(struct omap_dmadev *od) | |
1107 | { | |
1108 | tasklet_kill(&od->task); | |
1109 | while (!list_empty(&od->ddev.channels)) { | |
1110 | struct omap_chan *c = list_first_entry(&od->ddev.channels, | |
1111 | struct omap_chan, vc.chan.device_node); | |
1112 | ||
1113 | list_del(&c->vc.chan.device_node); | |
1114 | tasklet_kill(&c->vc.task); | |
1115 | kfree(c); | |
1116 | } | |
7bedaa55 RK |
1117 | } |
1118 | ||
80b0e0ab PU |
1119 | #define OMAP_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
1120 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
1121 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) | |
1122 | ||
7bedaa55 RK |
1123 | static int omap_dma_probe(struct platform_device *pdev) |
1124 | { | |
1125 | struct omap_dmadev *od; | |
596c471b | 1126 | struct resource *res; |
6ddeb6d8 | 1127 | int rc, i, irq; |
7bedaa55 | 1128 | |
104fce73 | 1129 | od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); |
7bedaa55 RK |
1130 | if (!od) |
1131 | return -ENOMEM; | |
1132 | ||
596c471b RK |
1133 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1134 | od->base = devm_ioremap_resource(&pdev->dev, res); | |
1135 | if (IS_ERR(od->base)) | |
1136 | return PTR_ERR(od->base); | |
1137 | ||
1b416c4b RK |
1138 | od->plat = omap_get_plat_info(); |
1139 | if (!od->plat) | |
1140 | return -EPROBE_DEFER; | |
1141 | ||
596c471b RK |
1142 | od->reg_map = od->plat->reg_map; |
1143 | ||
7bedaa55 | 1144 | dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); |
3a774ea9 | 1145 | dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); |
4ce98c0a | 1146 | dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask); |
7bedaa55 RK |
1147 | od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources; |
1148 | od->ddev.device_free_chan_resources = omap_dma_free_chan_resources; | |
1149 | od->ddev.device_tx_status = omap_dma_tx_status; | |
1150 | od->ddev.device_issue_pending = omap_dma_issue_pending; | |
1151 | od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg; | |
3a774ea9 | 1152 | od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic; |
4ce98c0a | 1153 | od->ddev.device_prep_dma_memcpy = omap_dma_prep_dma_memcpy; |
6c04cd4f | 1154 | od->ddev.device_config = omap_dma_slave_config; |
78ea4fe7 MR |
1155 | od->ddev.device_pause = omap_dma_pause; |
1156 | od->ddev.device_resume = omap_dma_resume; | |
1157 | od->ddev.device_terminate_all = omap_dma_terminate_all; | |
7d15b87d MR |
1158 | od->ddev.src_addr_widths = OMAP_DMA_BUSWIDTHS; |
1159 | od->ddev.dst_addr_widths = OMAP_DMA_BUSWIDTHS; | |
1160 | od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
1161 | od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; | |
7bedaa55 RK |
1162 | od->ddev.dev = &pdev->dev; |
1163 | INIT_LIST_HEAD(&od->ddev.channels); | |
1164 | INIT_LIST_HEAD(&od->pending); | |
1165 | spin_lock_init(&od->lock); | |
6ddeb6d8 | 1166 | spin_lock_init(&od->irq_lock); |
7bedaa55 RK |
1167 | |
1168 | tasklet_init(&od->task, omap_dma_sched, (unsigned long)od); | |
1169 | ||
de506089 PU |
1170 | od->dma_requests = OMAP_SDMA_REQUESTS; |
1171 | if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node, | |
1172 | "dma-requests", | |
1173 | &od->dma_requests)) { | |
1174 | dev_info(&pdev->dev, | |
1175 | "Missing dma-requests property, using %u.\n", | |
1176 | OMAP_SDMA_REQUESTS); | |
1177 | } | |
1178 | ||
8a322226 | 1179 | for (i = 0; i < OMAP_SDMA_CHANNELS; i++) { |
eea531ea | 1180 | rc = omap_dma_chan_init(od); |
7bedaa55 RK |
1181 | if (rc) { |
1182 | omap_dma_free(od); | |
1183 | return rc; | |
1184 | } | |
1185 | } | |
1186 | ||
6ddeb6d8 RK |
1187 | irq = platform_get_irq(pdev, 1); |
1188 | if (irq <= 0) { | |
1189 | dev_info(&pdev->dev, "failed to get L1 IRQ: %d\n", irq); | |
1190 | od->legacy = true; | |
1191 | } else { | |
1192 | /* Disable all interrupts */ | |
1193 | od->irq_enable_mask = 0; | |
1194 | omap_dma_glbl_write(od, IRQENABLE_L1, 0); | |
1195 | ||
1196 | rc = devm_request_irq(&pdev->dev, irq, omap_dma_irq, | |
1197 | IRQF_SHARED, "omap-dma-engine", od); | |
1198 | if (rc) | |
1199 | return rc; | |
1200 | } | |
1201 | ||
7bedaa55 RK |
1202 | rc = dma_async_device_register(&od->ddev); |
1203 | if (rc) { | |
1204 | pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n", | |
1205 | rc); | |
1206 | omap_dma_free(od); | |
8d30662a JH |
1207 | return rc; |
1208 | } | |
1209 | ||
1210 | platform_set_drvdata(pdev, od); | |
1211 | ||
1212 | if (pdev->dev.of_node) { | |
1213 | omap_dma_info.dma_cap = od->ddev.cap_mask; | |
1214 | ||
1215 | /* Device-tree DMA controller registration */ | |
1216 | rc = of_dma_controller_register(pdev->dev.of_node, | |
1217 | of_dma_simple_xlate, &omap_dma_info); | |
1218 | if (rc) { | |
1219 | pr_warn("OMAP-DMA: failed to register DMA controller\n"); | |
1220 | dma_async_device_unregister(&od->ddev); | |
1221 | omap_dma_free(od); | |
1222 | } | |
7bedaa55 RK |
1223 | } |
1224 | ||
1225 | dev_info(&pdev->dev, "OMAP DMA engine driver\n"); | |
1226 | ||
1227 | return rc; | |
1228 | } | |
1229 | ||
1230 | static int omap_dma_remove(struct platform_device *pdev) | |
1231 | { | |
1232 | struct omap_dmadev *od = platform_get_drvdata(pdev); | |
1233 | ||
8d30662a JH |
1234 | if (pdev->dev.of_node) |
1235 | of_dma_controller_free(pdev->dev.of_node); | |
1236 | ||
7bedaa55 | 1237 | dma_async_device_unregister(&od->ddev); |
6ddeb6d8 RK |
1238 | |
1239 | if (!od->legacy) { | |
1240 | /* Disable all interrupts */ | |
1241 | omap_dma_glbl_write(od, IRQENABLE_L0, 0); | |
1242 | } | |
1243 | ||
7bedaa55 RK |
1244 | omap_dma_free(od); |
1245 | ||
1246 | return 0; | |
1247 | } | |
1248 | ||
8d30662a JH |
1249 | static const struct of_device_id omap_dma_match[] = { |
1250 | { .compatible = "ti,omap2420-sdma", }, | |
1251 | { .compatible = "ti,omap2430-sdma", }, | |
1252 | { .compatible = "ti,omap3430-sdma", }, | |
1253 | { .compatible = "ti,omap3630-sdma", }, | |
1254 | { .compatible = "ti,omap4430-sdma", }, | |
1255 | {}, | |
1256 | }; | |
1257 | MODULE_DEVICE_TABLE(of, omap_dma_match); | |
1258 | ||
7bedaa55 RK |
1259 | static struct platform_driver omap_dma_driver = { |
1260 | .probe = omap_dma_probe, | |
1261 | .remove = omap_dma_remove, | |
1262 | .driver = { | |
1263 | .name = "omap-dma-engine", | |
8d30662a | 1264 | .of_match_table = of_match_ptr(omap_dma_match), |
7bedaa55 RK |
1265 | }, |
1266 | }; | |
1267 | ||
1268 | bool omap_dma_filter_fn(struct dma_chan *chan, void *param) | |
1269 | { | |
1270 | if (chan->device->dev->driver == &omap_dma_driver.driver) { | |
eea531ea | 1271 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
7bedaa55 RK |
1272 | struct omap_chan *c = to_omap_dma_chan(chan); |
1273 | unsigned req = *(unsigned *)param; | |
1274 | ||
eea531ea PU |
1275 | if (req <= od->dma_requests) { |
1276 | c->dma_sig = req; | |
1277 | return true; | |
1278 | } | |
7bedaa55 RK |
1279 | } |
1280 | return false; | |
1281 | } | |
1282 | EXPORT_SYMBOL_GPL(omap_dma_filter_fn); | |
1283 | ||
7bedaa55 RK |
1284 | static int omap_dma_init(void) |
1285 | { | |
be1f9481 | 1286 | return platform_driver_register(&omap_dma_driver); |
7bedaa55 RK |
1287 | } |
1288 | subsys_initcall(omap_dma_init); | |
1289 | ||
1290 | static void __exit omap_dma_exit(void) | |
1291 | { | |
7bedaa55 RK |
1292 | platform_driver_unregister(&omap_dma_driver); |
1293 | } | |
1294 | module_exit(omap_dma_exit); | |
1295 | ||
1296 | MODULE_AUTHOR("Russell King"); | |
1297 | MODULE_LICENSE("GPL"); |