[deliverable/linux.git] / drivers / dma / omap-dma.c

/*
 * OMAP DMAengine support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/omap-dma.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include "virt-dma.h"
#include <plat/dma.h>

struct omap_dmadev {
	struct dma_device ddev;
	spinlock_t lock;
	struct tasklet_struct task;
	struct list_head pending;
};

struct omap_chan {
	struct virt_dma_chan vc;
	struct list_head node;

	struct dma_slave_config	cfg;
	unsigned dma_sig;

	int dma_ch;
	struct omap_desc *desc;
	unsigned sgidx;
};

struct omap_sg {
	dma_addr_t addr;
	uint32_t en;		/* number of elements (24-bit) */
	uint32_t fn;		/* number of frames (16-bit) */
};

struct omap_desc {
	struct virt_dma_desc vd;
	enum dma_transfer_direction dir;
	dma_addr_t dev_addr;

	uint8_t es;		/* OMAP_DMA_DATA_TYPE_xxx */
	uint8_t sync_mode;	/* OMAP_DMA_SYNC_xxx */
	uint8_t sync_type;	/* OMAP_DMA_xxx_SYNC* */
	uint8_t periph_port;	/* Peripheral port */

	unsigned sglen;
	struct omap_sg sg[0];
};

static const unsigned es_bytes[] = {
	[OMAP_DMA_DATA_TYPE_S8] = 1,
	[OMAP_DMA_DATA_TYPE_S16] = 2,
	[OMAP_DMA_DATA_TYPE_S32] = 4,
};

static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d)
{
	return container_of(d, struct omap_dmadev, ddev);
}

static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c)
{
	return container_of(c, struct omap_chan, vc.chan);
}

static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t)
{
	return container_of(t, struct omap_desc, vd.tx);
}

static void omap_dma_desc_free(struct virt_dma_desc *vd)
{
	kfree(container_of(vd, struct omap_desc, vd));
}

static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
	unsigned idx)
{
	struct omap_sg *sg = d->sg + idx;

	if (d->dir == DMA_DEV_TO_MEM)
		omap_set_dma_dest_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
			OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
	else
		omap_set_dma_src_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
			OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);

	omap_set_dma_transfer_params(c->dma_ch, d->es, sg->en, sg->fn,
		d->sync_mode, c->dma_sig, d->sync_type);

	omap_start_dma(c->dma_ch);
}

static void omap_dma_start_desc(struct omap_chan *c)
{
	struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
	struct omap_desc *d;

	if (!vd) {
		c->desc = NULL;
		return;
	}

	list_del(&vd->node);

	c->desc = d = to_omap_dma_desc(&vd->tx);
	c->sgidx = 0;

	if (d->dir == DMA_DEV_TO_MEM)
		omap_set_dma_src_params(c->dma_ch, d->periph_port,
			OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, 0);
	else
		omap_set_dma_dest_params(c->dma_ch, d->periph_port,
			OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, 0);

	omap_dma_start_sg(c, d, 0);
}

static void omap_dma_callback(int ch, u16 status, void *data)
{
	struct omap_chan *c = data;
	struct omap_desc *d;
	unsigned long flags;

	spin_lock_irqsave(&c->vc.lock, flags);
	d = c->desc;
	if (d) {
		if (++c->sgidx < d->sglen) {
			omap_dma_start_sg(c, d, c->sgidx);
		} else {
			omap_dma_start_desc(c);
			vchan_cookie_complete(&d->vd);
		}
	}
	spin_unlock_irqrestore(&c->vc.lock, flags);
}

/*
 * This callback schedules all pending channels.  We could be more
 * clever here by postponing allocation of the real DMA channels to
 * this point, and freeing them when our virtual channel becomes idle.
 *
 * We would then need to deal with 'all channels in-use'
 */
static void omap_dma_sched(unsigned long data)
{
	struct omap_dmadev *d = (struct omap_dmadev *)data;
	LIST_HEAD(head);

	spin_lock_irq(&d->lock);
	list_splice_tail_init(&d->pending, &head);
	spin_unlock_irq(&d->lock);

	while (!list_empty(&head)) {
		struct omap_chan *c = list_first_entry(&head,
			struct omap_chan, node);

		spin_lock_irq(&c->vc.lock);
		list_del_init(&c->node);
		omap_dma_start_desc(c);
		spin_unlock_irq(&c->vc.lock);
	}
}

static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
{
	struct omap_chan *c = to_omap_dma_chan(chan);

	dev_info(c->vc.chan.device->dev, "allocating channel for %u\n", c->dma_sig);

	return omap_request_dma(c->dma_sig, "DMA engine",
		omap_dma_callback, c, &c->dma_ch);
}

static void omap_dma_free_chan_resources(struct dma_chan *chan)
{
	struct omap_chan *c = to_omap_dma_chan(chan);

	vchan_free_chan_resources(&c->vc);
	omap_free_dma(c->dma_ch);

	dev_info(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig);
}

static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
	dma_cookie_t cookie, struct dma_tx_state *txstate)
{
	/*
	 * FIXME: do we need to return pending bytes?
	 * We have no users of that info at the moment...
	 */
	return dma_cookie_status(chan, cookie, txstate);
}

static void omap_dma_issue_pending(struct dma_chan *chan)
{
	struct omap_chan *c = to_omap_dma_chan(chan);
	unsigned long flags;

	spin_lock_irqsave(&c->vc.lock, flags);
	if (vchan_issue_pending(&c->vc) && !c->desc) {
		struct omap_dmadev *d = to_omap_dma_dev(chan->device);
		spin_lock(&d->lock);
		if (list_empty(&c->node))
			list_add_tail(&c->node, &d->pending);
		spin_unlock(&d->lock);
		tasklet_schedule(&d->task);
	}
	spin_unlock_irqrestore(&c->vc.lock, flags);
}

static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
	struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen,
	enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
{
	struct omap_chan *c = to_omap_dma_chan(chan);
	enum dma_slave_buswidth dev_width;
	struct scatterlist *sgent;
	struct omap_desc *d;
	dma_addr_t dev_addr;
	unsigned i, j = 0, es, en, frame_bytes, sync_type;
	u32 burst;

	if (dir == DMA_DEV_TO_MEM) {
		dev_addr = c->cfg.src_addr;
		dev_width = c->cfg.src_addr_width;
		burst = c->cfg.src_maxburst;
		sync_type = OMAP_DMA_SRC_SYNC;
	} else if (dir == DMA_MEM_TO_DEV) {
		dev_addr = c->cfg.dst_addr;
		dev_width = c->cfg.dst_addr_width;
		burst = c->cfg.dst_maxburst;
		sync_type = OMAP_DMA_DST_SYNC;
	} else {
		dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
		return NULL;
	}

	/* Bus width translates to the element size (ES) */
	switch (dev_width) {
	case DMA_SLAVE_BUSWIDTH_1_BYTE:
		es = OMAP_DMA_DATA_TYPE_S8;
		break;
	case DMA_SLAVE_BUSWIDTH_2_BYTES:
		es = OMAP_DMA_DATA_TYPE_S16;
		break;
	case DMA_SLAVE_BUSWIDTH_4_BYTES:
		es = OMAP_DMA_DATA_TYPE_S32;
		break;
	default: /* not reached */
		return NULL;
	}

	/* Now allocate and setup the descriptor. */
	d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC);
	if (!d)
		return NULL;

	d->dir = dir;
	d->dev_addr = dev_addr;
	d->es = es;
	d->sync_mode = OMAP_DMA_SYNC_FRAME;
	d->sync_type = sync_type;
	d->periph_port = OMAP_DMA_PORT_TIPB;

	/*
	 * Build our scatterlist entries: each contains the address,
	 * the number of elements (EN) in each frame, and the number of
	 * frames (FN).  Number of bytes for this entry = ES * EN * FN.
	 *
	 * Burst size translates to number of elements with frame sync.
	 * Note: DMA engine defines burst to be the number of dev-width
	 * transfers.
	 */
	en = burst;
	frame_bytes = es_bytes[es] * en;
	for_each_sg(sgl, sgent, sglen, i) {
		d->sg[j].addr = sg_dma_address(sgent);
		d->sg[j].en = en;
		d->sg[j].fn = sg_dma_len(sgent) / frame_bytes;
		j++;
	}

	d->sglen = j;

	return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
}

static int omap_dma_slave_config(struct omap_chan *c, struct dma_slave_config *cfg)
{
	if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
	    cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
		return -EINVAL;

	memcpy(&c->cfg, cfg, sizeof(c->cfg));

	return 0;
}

static int omap_dma_terminate_all(struct omap_chan *c)
{
	struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device);
	unsigned long flags;
	LIST_HEAD(head);

	spin_lock_irqsave(&c->vc.lock, flags);

	/* Prevent this channel being scheduled */
	spin_lock(&d->lock);
	list_del_init(&c->node);
	spin_unlock(&d->lock);

	/*
	 * Stop DMA activity: we assume the callback will not be called
	 * after omap_stop_dma() returns (even if it does, it will see
	 * c->desc is NULL and exit.)
	 */
	if (c->desc) {
		c->desc = NULL;
		omap_stop_dma(c->dma_ch);
	}

	vchan_get_all_descriptors(&c->vc, &head);
	spin_unlock_irqrestore(&c->vc.lock, flags);
	vchan_dma_desc_free_list(&c->vc, &head);

	return 0;
}

static int omap_dma_pause(struct omap_chan *c)
{
	/* FIXME: not supported by platform private API */
	return -EINVAL;
}

static int omap_dma_resume(struct omap_chan *c)
{
	/* FIXME: not supported by platform private API */
	return -EINVAL;
}

static int omap_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
	unsigned long arg)
{
	struct omap_chan *c = to_omap_dma_chan(chan);
	int ret;

	switch (cmd) {
	case DMA_SLAVE_CONFIG:
		ret = omap_dma_slave_config(c, (struct dma_slave_config *)arg);
		break;

	case DMA_TERMINATE_ALL:
		ret = omap_dma_terminate_all(c);
		break;

	case DMA_PAUSE:
		ret = omap_dma_pause(c);
		break;

	case DMA_RESUME:
		ret = omap_dma_resume(c);
		break;

	default:
		ret = -ENXIO;
		break;
	}

	return ret;
}

static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig)
{
	struct omap_chan *c;

	c = kzalloc(sizeof(*c), GFP_KERNEL);
	if (!c)
		return -ENOMEM;

	c->dma_sig = dma_sig;
	c->vc.desc_free = omap_dma_desc_free;
	vchan_init(&c->vc, &od->ddev);
	INIT_LIST_HEAD(&c->node);

	od->ddev.chancnt++;

	return 0;
}

static void omap_dma_free(struct omap_dmadev *od)
{
	tasklet_kill(&od->task);
	while (!list_empty(&od->ddev.channels)) {
		struct omap_chan *c = list_first_entry(&od->ddev.channels,
			struct omap_chan, vc.chan.device_node);

		list_del(&c->vc.chan.device_node);
		tasklet_kill(&c->vc.task);
		kfree(c);
	}
	kfree(od);
}

static int omap_dma_probe(struct platform_device *pdev)
{
	struct omap_dmadev *od;
	int rc, i;

	od = kzalloc(sizeof(*od), GFP_KERNEL);
	if (!od)
		return -ENOMEM;

	dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
	od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
	od->ddev.device_free_chan_resources = omap_dma_free_chan_resources;
	od->ddev.device_tx_status = omap_dma_tx_status;
	od->ddev.device_issue_pending = omap_dma_issue_pending;
	od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg;
	od->ddev.device_control = omap_dma_control;
	od->ddev.dev = &pdev->dev;
	INIT_LIST_HEAD(&od->ddev.channels);
	INIT_LIST_HEAD(&od->pending);
	spin_lock_init(&od->lock);

	tasklet_init(&od->task, omap_dma_sched, (unsigned long)od);

	for (i = 0; i < 127; i++) {
		rc = omap_dma_chan_init(od, i);
		if (rc) {
			omap_dma_free(od);
			return rc;
		}
	}

	rc = dma_async_device_register(&od->ddev);
	if (rc) {
		pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n",
			rc);
		omap_dma_free(od);
	} else {
		platform_set_drvdata(pdev, od);
	}

	dev_info(&pdev->dev, "OMAP DMA engine driver\n");

	return rc;
}

static int omap_dma_remove(struct platform_device *pdev)
{
	struct omap_dmadev *od = platform_get_drvdata(pdev);

	dma_async_device_unregister(&od->ddev);
	omap_dma_free(od);

	return 0;
}

static struct platform_driver omap_dma_driver = {
	.probe	= omap_dma_probe,
	.remove	= omap_dma_remove,
	.driver = {
		.name = "omap-dma-engine",
		.owner = THIS_MODULE,
	},
};

bool omap_dma_filter_fn(struct dma_chan *chan, void *param)
{
	if (chan->device->dev->driver == &omap_dma_driver.driver) {
		struct omap_chan *c = to_omap_dma_chan(chan);
		unsigned req = *(unsigned *)param;

		return req == c->dma_sig;
	}
	return false;
}
EXPORT_SYMBOL_GPL(omap_dma_filter_fn);

static struct platform_device *pdev;

static const struct platform_device_info omap_dma_dev_info = {
	.name = "omap-dma-engine",
	.id = -1,
	.dma_mask = DMA_BIT_MASK(32),
};

static int omap_dma_init(void)
{
	int rc = platform_driver_register(&omap_dma_driver);

	if (rc == 0) {
		pdev = platform_device_register_full(&omap_dma_dev_info);
		if (IS_ERR(pdev)) {
			platform_driver_unregister(&omap_dma_driver);
			rc = PTR_ERR(pdev);
		}
	}
	return rc;
}
subsys_initcall(omap_dma_init);

static void __exit omap_dma_exit(void)
{
	platform_device_unregister(pdev);
	platform_driver_unregister(&omap_dma_driver);
}
module_exit(omap_dma_exit);

MODULE_AUTHOR("Russell King");
MODULE_LICENSE("GPL");
Commit	Line	Data
7bedaa55 RK	1	/*
	2	* OMAP DMAengine support
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8	#include <linux/dmaengine.h>
	9	#include <linux/dma-mapping.h>
	10	#include <linux/err.h>
	11	#include <linux/init.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/list.h>
	14	#include <linux/module.h>
	15	#include <linux/omap-dma.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/slab.h>
	18	#include <linux/spinlock.h>
	19
	20	#include "virt-dma.h"
	21	#include <plat/dma.h>
	22
	23	struct omap_dmadev {
	24	struct dma_device ddev;
	25	spinlock_t lock;
	26	struct tasklet_struct task;
	27	struct list_head pending;
	28	};
	29
	30	struct omap_chan {
	31	struct virt_dma_chan vc;
	32	struct list_head node;
	33
	34	struct dma_slave_config cfg;
	35	unsigned dma_sig;
	36
	37	int dma_ch;
	38	struct omap_desc *desc;
	39	unsigned sgidx;
	40	};
	41
	42	struct omap_sg {
	43	dma_addr_t addr;
	44	uint32_t en; /* number of elements (24-bit) */
	45	uint32_t fn; /* number of frames (16-bit) */
	46	};
	47
	48	struct omap_desc {
	49	struct virt_dma_desc vd;
	50	enum dma_transfer_direction dir;
	51	dma_addr_t dev_addr;
	52
	53	uint8_t es; /* OMAP_DMA_DATA_TYPE_xxx */
	54	uint8_t sync_mode; /* OMAP_DMA_SYNC_xxx */
	55	uint8_t sync_type; /* OMAP_DMA_xxx_SYNC* */
	56	uint8_t periph_port; /* Peripheral port */
	57
	58	unsigned sglen;
	59	struct omap_sg sg[0];
	60	};
	61
	62	static const unsigned es_bytes[] = {
	63	[OMAP_DMA_DATA_TYPE_S8] = 1,
	64	[OMAP_DMA_DATA_TYPE_S16] = 2,
65	[OMAP_DMA_DATA_TYPE_S32] = 4,
66	};
67
68	static inline struct omap_dmadev to_omap_dma_dev(struct dma_device d)
69	{
70	return container_of(d, struct omap_dmadev, ddev);
71	}
72
73	static inline struct omap_chan to_omap_dma_chan(struct dma_chan c)
74	{
75	return container_of(c, struct omap_chan, vc.chan);
76	}
77
78	static inline struct omap_desc to_omap_dma_desc(struct dma_async_tx_descriptor t)
79	{
80	return container_of(t, struct omap_desc, vd.tx);
81	}
82
83	static void omap_dma_desc_free(struct virt_dma_desc *vd)
84	{
85	kfree(container_of(vd, struct omap_desc, vd));
86	}
87
88	static void omap_dma_start_sg(struct omap_chan c, struct omap_desc d,
89	unsigned idx)
90	{
91	struct omap_sg *sg = d->sg + idx;
92
93	if (d->dir == DMA_DEV_TO_MEM)
94	omap_set_dma_dest_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
95	OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
96	else
97	omap_set_dma_src_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
98	OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
99
100	omap_set_dma_transfer_params(c->dma_ch, d->es, sg->en, sg->fn,
101	d->sync_mode, c->dma_sig, d->sync_type);
102
103	omap_start_dma(c->dma_ch);
104	}
105
106	static void omap_dma_start_desc(struct omap_chan *c)
107	{
108	struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
109	struct omap_desc *d;
110
111	if (!vd) {
112	c->desc = NULL;
113	return;
114	}
115
116	list_del(&vd->node);
117
118	c->desc = d = to_omap_dma_desc(&vd->tx);
119	c->sgidx = 0;
120
121	if (d->dir == DMA_DEV_TO_MEM)
122	omap_set_dma_src_params(c->dma_ch, d->periph_port,
123	OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, 0);
124	else
125	omap_set_dma_dest_params(c->dma_ch, d->periph_port,
126	OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, 0);
127
128	omap_dma_start_sg(c, d, 0);
129	}
130
131	static void omap_dma_callback(int ch, u16 status, void *data)
132	{
133	struct omap_chan *c = data;
134	struct omap_desc *d;
135	unsigned long flags;
136
137	spin_lock_irqsave(&c->vc.lock, flags);
138	d = c->desc;
139	if (d) {
140	if (++c->sgidx < d->sglen) {
141	omap_dma_start_sg(c, d, c->sgidx);
142	} else {
143	omap_dma_start_desc(c);
144	vchan_cookie_complete(&d->vd);
145	}
146	}
147	spin_unlock_irqrestore(&c->vc.lock, flags);
148	}
149
150	/*
151	* This callback schedules all pending channels. We could be more
152	* clever here by postponing allocation of the real DMA channels to
153	* this point, and freeing them when our virtual channel becomes idle.
154	*
155	* We would then need to deal with 'all channels in-use'
156	*/
157	static void omap_dma_sched(unsigned long data)
158	{
159	struct omap_dmadev d = (struct omap_dmadev )data;
160	LIST_HEAD(head);
161
162	spin_lock_irq(&d->lock);
163	list_splice_tail_init(&d->pending, &head);
164	spin_unlock_irq(&d->lock);
165
166	while (!list_empty(&head)) {
167	struct omap_chan *c = list_first_entry(&head,
168	struct omap_chan, node);
169
170	spin_lock_irq(&c->vc.lock);
171	list_del_init(&c->node);
172	omap_dma_start_desc(c);
173	spin_unlock_irq(&c->vc.lock);
174	}
175	}
176
177	static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
178	{
179	struct omap_chan *c = to_omap_dma_chan(chan);
180
181	dev_info(c->vc.chan.device->dev, "allocating channel for %u\n", c->dma_sig);
182
183	return omap_request_dma(c->dma_sig, "DMA engine",
184	omap_dma_callback, c, &c->dma_ch);
185	}
186
187	static void omap_dma_free_chan_resources(struct dma_chan *chan)
188	{
189	struct omap_chan *c = to_omap_dma_chan(chan);
190
191	vchan_free_chan_resources(&c->vc);
192	omap_free_dma(c->dma_ch);
193
194	dev_info(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig);
195	}
196
197	static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
198	dma_cookie_t cookie, struct dma_tx_state *txstate)
199	{
200	/*
201	* FIXME: do we need to return pending bytes?
202	* We have no users of that info at the moment...
203	*/
204	return dma_cookie_status(chan, cookie, txstate);
205	}
206
207	static void omap_dma_issue_pending(struct dma_chan *chan)
208	{
209	struct omap_chan *c = to_omap_dma_chan(chan);
210	unsigned long flags;
211
212	spin_lock_irqsave(&c->vc.lock, flags);
213	if (vchan_issue_pending(&c->vc) && !c->desc) {
214	struct omap_dmadev *d = to_omap_dma_dev(chan->device);
215	spin_lock(&d->lock);
216	if (list_empty(&c->node))
217	list_add_tail(&c->node, &d->pending);
218	spin_unlock(&d->lock);
219	tasklet_schedule(&d->task);
220	}
221	spin_unlock_irqrestore(&c->vc.lock, flags);
222	}
223
224	static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
225	struct dma_chan chan, struct scatterlist sgl, unsigned sglen,
226	enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
227	{
228	struct omap_chan *c = to_omap_dma_chan(chan);
229	enum dma_slave_buswidth dev_width;
230	struct scatterlist *sgent;
231	struct omap_desc *d;
232	dma_addr_t dev_addr;
233	unsigned i, j = 0, es, en, frame_bytes, sync_type;
234	u32 burst;
235
236	if (dir == DMA_DEV_TO_MEM) {
237	dev_addr = c->cfg.src_addr;
238	dev_width = c->cfg.src_addr_width;
239	burst = c->cfg.src_maxburst;
240	sync_type = OMAP_DMA_SRC_SYNC;
241	} else if (dir == DMA_MEM_TO_DEV) {
242	dev_addr = c->cfg.dst_addr;
243	dev_width = c->cfg.dst_addr_width;
244	burst = c->cfg.dst_maxburst;
245	sync_type = OMAP_DMA_DST_SYNC;
246	} else {
247	dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
248	return NULL;
249	}
250
251	/* Bus width translates to the element size (ES) */
252	switch (dev_width) {
253	case DMA_SLAVE_BUSWIDTH_1_BYTE:
254	es = OMAP_DMA_DATA_TYPE_S8;
255	break;
256	case DMA_SLAVE_BUSWIDTH_2_BYTES:
257	es = OMAP_DMA_DATA_TYPE_S16;
258	break;
259	case DMA_SLAVE_BUSWIDTH_4_BYTES:
260	es = OMAP_DMA_DATA_TYPE_S32;
261	break;
262	default: /* not reached */
263	return NULL;
264	}
265
266	/* Now allocate and setup the descriptor. */
267	d = kzalloc(sizeof(d) + sglen sizeof(d->sg[0]), GFP_ATOMIC);
268	if (!d)
269	return NULL;
270
271	d->dir = dir;
272	d->dev_addr = dev_addr;
273	d->es = es;
274	d->sync_mode = OMAP_DMA_SYNC_FRAME;
275	d->sync_type = sync_type;
276	d->periph_port = OMAP_DMA_PORT_TIPB;
277
278	/*
279	* Build our scatterlist entries: each contains the address,
280	* the number of elements (EN) in each frame, and the number of
281	* frames (FN). Number of bytes for this entry = ES * EN * FN.
282	*
283	* Burst size translates to number of elements with frame sync.
284	* Note: DMA engine defines burst to be the number of dev-width
285	* transfers.
286	*/
287	en = burst;
288	frame_bytes = es_bytes[es] * en;
289	for_each_sg(sgl, sgent, sglen, i) {
290	d->sg[j].addr = sg_dma_address(sgent);
291	d->sg[j].en = en;
292	d->sg[j].fn = sg_dma_len(sgent) / frame_bytes;
293	j++;
294	}
295
296	d->sglen = j;
297
298	return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
299	}
300
301	static int omap_dma_slave_config(struct omap_chan c, struct dma_slave_config cfg)
302	{
303	if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES \|\|
304	cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
305	return -EINVAL;
306
307	memcpy(&c->cfg, cfg, sizeof(c->cfg));
308
309	return 0;
310	}
311
312	static int omap_dma_terminate_all(struct omap_chan *c)
313	{
314	struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device);
315	unsigned long flags;
316	LIST_HEAD(head);
317
318	spin_lock_irqsave(&c->vc.lock, flags);
319
320	/* Prevent this channel being scheduled */
321	spin_lock(&d->lock);
322	list_del_init(&c->node);
323	spin_unlock(&d->lock);
324
325	/*
326	* Stop DMA activity: we assume the callback will not be called
327	* after omap_stop_dma() returns (even if it does, it will see
328	* c->desc is NULL and exit.)
329	*/
330	if (c->desc) {
331	c->desc = NULL;
332	omap_stop_dma(c->dma_ch);
333	}
334
335	vchan_get_all_descriptors(&c->vc, &head);
336	spin_unlock_irqrestore(&c->vc.lock, flags);
337	vchan_dma_desc_free_list(&c->vc, &head);
338
339	return 0;
340	}
341
342	static int omap_dma_pause(struct omap_chan *c)
343	{
344	/* FIXME: not supported by platform private API */
345	return -EINVAL;
346	}
347
348	static int omap_dma_resume(struct omap_chan *c)
349	{
350	/* FIXME: not supported by platform private API */
351	return -EINVAL;
352	}
353
354	static int omap_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
355	unsigned long arg)
356	{
357	struct omap_chan *c = to_omap_dma_chan(chan);
358	int ret;
359
360	switch (cmd) {
361	case DMA_SLAVE_CONFIG:
362	ret = omap_dma_slave_config(c, (struct dma_slave_config *)arg);
363	break;
364
365	case DMA_TERMINATE_ALL:
366	ret = omap_dma_terminate_all(c);
367	break;
368
369	case DMA_PAUSE:
370	ret = omap_dma_pause(c);
371	break;
372
373	case DMA_RESUME:
374	ret = omap_dma_resume(c);
375	break;
376
377	default:
378	ret = -ENXIO;
379	break;
380	}
381
382	return ret;
383	}
384
385	static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig)
386	{
387	struct omap_chan *c;
388
389	c = kzalloc(sizeof(*c), GFP_KERNEL);
390	if (!c)
391	return -ENOMEM;
392
393	c->dma_sig = dma_sig;
394	c->vc.desc_free = omap_dma_desc_free;
395	vchan_init(&c->vc, &od->ddev);
396	INIT_LIST_HEAD(&c->node);
397
398	od->ddev.chancnt++;
399
400	return 0;
401	}
402
403	static void omap_dma_free(struct omap_dmadev *od)
404	{
405	tasklet_kill(&od->task);
406	while (!list_empty(&od->ddev.channels)) {
407	struct omap_chan *c = list_first_entry(&od->ddev.channels,
408	struct omap_chan, vc.chan.device_node);
409
410	list_del(&c->vc.chan.device_node);
411	tasklet_kill(&c->vc.task);
412	kfree(c);
413	}
414	kfree(od);
415	}
416
417	static int omap_dma_probe(struct platform_device *pdev)
418	{
419	struct omap_dmadev *od;
420	int rc, i;
421
422	od = kzalloc(sizeof(*od), GFP_KERNEL);
423	if (!od)
424	return -ENOMEM;
425
426	dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
427	od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
428	od->ddev.device_free_chan_resources = omap_dma_free_chan_resources;
429	od->ddev.device_tx_status = omap_dma_tx_status;
430	od->ddev.device_issue_pending = omap_dma_issue_pending;
431	od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg;
432	od->ddev.device_control = omap_dma_control;
433	od->ddev.dev = &pdev->dev;
434	INIT_LIST_HEAD(&od->ddev.channels);
435	INIT_LIST_HEAD(&od->pending);
436	spin_lock_init(&od->lock);
437
438	tasklet_init(&od->task, omap_dma_sched, (unsigned long)od);
439
440	for (i = 0; i < 127; i++) {
441	rc = omap_dma_chan_init(od, i);
442	if (rc) {
443	omap_dma_free(od);
444	return rc;
445	}
446	}
447
448	rc = dma_async_device_register(&od->ddev);
449	if (rc) {
450	pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n",
451	rc);
452	omap_dma_free(od);
453	} else {
454	platform_set_drvdata(pdev, od);
455	}
456
457	dev_info(&pdev->dev, "OMAP DMA engine driver\n");
458
459	return rc;
460	}
461
462	static int omap_dma_remove(struct platform_device *pdev)
463	{
464	struct omap_dmadev *od = platform_get_drvdata(pdev);
465
466	dma_async_device_unregister(&od->ddev);
467	omap_dma_free(od);
468
469	return 0;
470	}
471
472	static struct platform_driver omap_dma_driver = {
473	.probe = omap_dma_probe,
474	.remove = omap_dma_remove,
475	.driver = {
476	.name = "omap-dma-engine",
477	.owner = THIS_MODULE,
478	},
479	};
480
481	bool omap_dma_filter_fn(struct dma_chan chan, void param)
482	{
483	if (chan->device->dev->driver == &omap_dma_driver.driver) {
484	struct omap_chan *c = to_omap_dma_chan(chan);
485	unsigned req = (unsigned )param;
486
487	return req == c->dma_sig;
488	}
489	return false;
490	}
491	EXPORT_SYMBOL_GPL(omap_dma_filter_fn);
492
493	static struct platform_device *pdev;
494
495	static const struct platform_device_info omap_dma_dev_info = {
496	.name = "omap-dma-engine",
497	.id = -1,
498	.dma_mask = DMA_BIT_MASK(32),
499	};
500
501	static int omap_dma_init(void)
502	{
503	int rc = platform_driver_register(&omap_dma_driver);
504
505	if (rc == 0) {
506	pdev = platform_device_register_full(&omap_dma_dev_info);
507	if (IS_ERR(pdev)) {
508	platform_driver_unregister(&omap_dma_driver);
509	rc = PTR_ERR(pdev);
510	}
511	}
512	return rc;
513	}
514	subsys_initcall(omap_dma_init);
515
516	static void __exit omap_dma_exit(void)
517	{
518	platform_device_unregister(pdev);
519	platform_driver_unregister(&omap_dma_driver);
520	}
521	module_exit(omap_dma_exit);
522
523	MODULE_AUTHOR("Russell King");
524	MODULE_LICENSE("GPL");