Commit | Line | Data |
---|---|---|
7bedaa55 RK |
1 | /* |
2 | * OMAP DMAengine support | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
fa3ad86a | 8 | #include <linux/delay.h> |
7bedaa55 RK |
9 | #include <linux/dmaengine.h> |
10 | #include <linux/dma-mapping.h> | |
11 | #include <linux/err.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/list.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/omap-dma.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/spinlock.h> | |
8d30662a JH |
20 | #include <linux/of_dma.h> |
21 | #include <linux/of_device.h> | |
7bedaa55 RK |
22 | |
23 | #include "virt-dma.h" | |
7d7e1eba | 24 | |
7bedaa55 RK |
25 | struct omap_dmadev { |
26 | struct dma_device ddev; | |
27 | spinlock_t lock; | |
28 | struct tasklet_struct task; | |
29 | struct list_head pending; | |
1b416c4b | 30 | struct omap_system_dma_plat_info *plat; |
7bedaa55 RK |
31 | }; |
32 | ||
33 | struct omap_chan { | |
34 | struct virt_dma_chan vc; | |
35 | struct list_head node; | |
1b416c4b | 36 | struct omap_system_dma_plat_info *plat; |
7bedaa55 RK |
37 | |
38 | struct dma_slave_config cfg; | |
39 | unsigned dma_sig; | |
3a774ea9 | 40 | bool cyclic; |
2dcdf570 | 41 | bool paused; |
7bedaa55 RK |
42 | |
43 | int dma_ch; | |
44 | struct omap_desc *desc; | |
45 | unsigned sgidx; | |
46 | }; | |
47 | ||
48 | struct omap_sg { | |
49 | dma_addr_t addr; | |
50 | uint32_t en; /* number of elements (24-bit) */ | |
51 | uint32_t fn; /* number of frames (16-bit) */ | |
52 | }; | |
53 | ||
54 | struct omap_desc { | |
55 | struct virt_dma_desc vd; | |
56 | enum dma_transfer_direction dir; | |
57 | dma_addr_t dev_addr; | |
58 | ||
7c836bc7 | 59 | int16_t fi; /* for OMAP_DMA_SYNC_PACKET */ |
9043826d | 60 | uint8_t es; /* CSDP_DATA_TYPE_xxx */ |
3ed4d18f | 61 | uint32_t ccr; /* CCR value */ |
965aeb4d | 62 | uint16_t clnk_ctrl; /* CLNK_CTRL value */ |
fa3ad86a | 63 | uint16_t cicr; /* CICR value */ |
2f0d13bd | 64 | uint32_t csdp; /* CSDP value */ |
7bedaa55 RK |
65 | |
66 | unsigned sglen; | |
67 | struct omap_sg sg[0]; | |
68 | }; | |
69 | ||
9043826d RK |
70 | enum { |
71 | CCR_FS = BIT(5), | |
72 | CCR_READ_PRIORITY = BIT(6), | |
73 | CCR_ENABLE = BIT(7), | |
74 | CCR_AUTO_INIT = BIT(8), /* OMAP1 only */ | |
75 | CCR_REPEAT = BIT(9), /* OMAP1 only */ | |
76 | CCR_OMAP31_DISABLE = BIT(10), /* OMAP1 only */ | |
77 | CCR_SUSPEND_SENSITIVE = BIT(8), /* OMAP2+ only */ | |
78 | CCR_RD_ACTIVE = BIT(9), /* OMAP2+ only */ | |
79 | CCR_WR_ACTIVE = BIT(10), /* OMAP2+ only */ | |
80 | CCR_SRC_AMODE_CONSTANT = 0 << 12, | |
81 | CCR_SRC_AMODE_POSTINC = 1 << 12, | |
82 | CCR_SRC_AMODE_SGLIDX = 2 << 12, | |
83 | CCR_SRC_AMODE_DBLIDX = 3 << 12, | |
84 | CCR_DST_AMODE_CONSTANT = 0 << 14, | |
85 | CCR_DST_AMODE_POSTINC = 1 << 14, | |
86 | CCR_DST_AMODE_SGLIDX = 2 << 14, | |
87 | CCR_DST_AMODE_DBLIDX = 3 << 14, | |
88 | CCR_CONSTANT_FILL = BIT(16), | |
89 | CCR_TRANSPARENT_COPY = BIT(17), | |
90 | CCR_BS = BIT(18), | |
91 | CCR_SUPERVISOR = BIT(22), | |
92 | CCR_PREFETCH = BIT(23), | |
93 | CCR_TRIGGER_SRC = BIT(24), | |
94 | CCR_BUFFERING_DISABLE = BIT(25), | |
95 | CCR_WRITE_PRIORITY = BIT(26), | |
96 | CCR_SYNC_ELEMENT = 0, | |
97 | CCR_SYNC_FRAME = CCR_FS, | |
98 | CCR_SYNC_BLOCK = CCR_BS, | |
99 | CCR_SYNC_PACKET = CCR_BS | CCR_FS, | |
100 | ||
101 | CSDP_DATA_TYPE_8 = 0, | |
102 | CSDP_DATA_TYPE_16 = 1, | |
103 | CSDP_DATA_TYPE_32 = 2, | |
104 | CSDP_SRC_PORT_EMIFF = 0 << 2, /* OMAP1 only */ | |
105 | CSDP_SRC_PORT_EMIFS = 1 << 2, /* OMAP1 only */ | |
106 | CSDP_SRC_PORT_OCP_T1 = 2 << 2, /* OMAP1 only */ | |
107 | CSDP_SRC_PORT_TIPB = 3 << 2, /* OMAP1 only */ | |
108 | CSDP_SRC_PORT_OCP_T2 = 4 << 2, /* OMAP1 only */ | |
109 | CSDP_SRC_PORT_MPUI = 5 << 2, /* OMAP1 only */ | |
110 | CSDP_SRC_PACKED = BIT(6), | |
111 | CSDP_SRC_BURST_1 = 0 << 7, | |
112 | CSDP_SRC_BURST_16 = 1 << 7, | |
113 | CSDP_SRC_BURST_32 = 2 << 7, | |
114 | CSDP_SRC_BURST_64 = 3 << 7, | |
115 | CSDP_DST_PORT_EMIFF = 0 << 9, /* OMAP1 only */ | |
116 | CSDP_DST_PORT_EMIFS = 1 << 9, /* OMAP1 only */ | |
117 | CSDP_DST_PORT_OCP_T1 = 2 << 9, /* OMAP1 only */ | |
118 | CSDP_DST_PORT_TIPB = 3 << 9, /* OMAP1 only */ | |
119 | CSDP_DST_PORT_OCP_T2 = 4 << 9, /* OMAP1 only */ | |
120 | CSDP_DST_PORT_MPUI = 5 << 9, /* OMAP1 only */ | |
121 | CSDP_DST_PACKED = BIT(13), | |
122 | CSDP_DST_BURST_1 = 0 << 14, | |
123 | CSDP_DST_BURST_16 = 1 << 14, | |
124 | CSDP_DST_BURST_32 = 2 << 14, | |
125 | CSDP_DST_BURST_64 = 3 << 14, | |
126 | ||
127 | CICR_TOUT_IE = BIT(0), /* OMAP1 only */ | |
128 | CICR_DROP_IE = BIT(1), | |
129 | CICR_HALF_IE = BIT(2), | |
130 | CICR_FRAME_IE = BIT(3), | |
131 | CICR_LAST_IE = BIT(4), | |
132 | CICR_BLOCK_IE = BIT(5), | |
133 | CICR_PKT_IE = BIT(7), /* OMAP2+ only */ | |
134 | CICR_TRANS_ERR_IE = BIT(8), /* OMAP2+ only */ | |
135 | CICR_SUPERVISOR_ERR_IE = BIT(10), /* OMAP2+ only */ | |
136 | CICR_MISALIGNED_ERR_IE = BIT(11), /* OMAP2+ only */ | |
137 | CICR_DRAIN_IE = BIT(12), /* OMAP2+ only */ | |
138 | CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */ | |
139 | ||
140 | CLNK_CTRL_ENABLE_LNK = BIT(15), | |
141 | }; | |
142 | ||
7bedaa55 | 143 | static const unsigned es_bytes[] = { |
9043826d RK |
144 | [CSDP_DATA_TYPE_8] = 1, |
145 | [CSDP_DATA_TYPE_16] = 2, | |
146 | [CSDP_DATA_TYPE_32] = 4, | |
7bedaa55 RK |
147 | }; |
148 | ||
8d30662a JH |
149 | static struct of_dma_filter_info omap_dma_info = { |
150 | .filter_fn = omap_dma_filter_fn, | |
151 | }; | |
152 | ||
7bedaa55 RK |
153 | static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d) |
154 | { | |
155 | return container_of(d, struct omap_dmadev, ddev); | |
156 | } | |
157 | ||
158 | static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c) | |
159 | { | |
160 | return container_of(c, struct omap_chan, vc.chan); | |
161 | } | |
162 | ||
163 | static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t) | |
164 | { | |
165 | return container_of(t, struct omap_desc, vd.tx); | |
166 | } | |
167 | ||
168 | static void omap_dma_desc_free(struct virt_dma_desc *vd) | |
169 | { | |
170 | kfree(container_of(vd, struct omap_desc, vd)); | |
171 | } | |
172 | ||
c5ed98b6 RK |
173 | static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val) |
174 | { | |
175 | od->plat->dma_write(val, reg, 0); | |
176 | } | |
177 | ||
178 | static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg) | |
179 | { | |
180 | return od->plat->dma_read(reg, 0); | |
181 | } | |
182 | ||
183 | static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val) | |
184 | { | |
185 | c->plat->dma_write(val, reg, c->dma_ch); | |
186 | } | |
187 | ||
188 | static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg) | |
189 | { | |
190 | return c->plat->dma_read(reg, c->dma_ch); | |
191 | } | |
192 | ||
470b23f7 RK |
193 | static void omap_dma_clear_csr(struct omap_chan *c) |
194 | { | |
195 | if (dma_omap1()) | |
c5ed98b6 | 196 | omap_dma_chan_read(c, CSR); |
470b23f7 | 197 | else |
c5ed98b6 | 198 | omap_dma_chan_write(c, CSR, ~0); |
470b23f7 RK |
199 | } |
200 | ||
fa3ad86a RK |
201 | static void omap_dma_start(struct omap_chan *c, struct omap_desc *d) |
202 | { | |
203 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
fa3ad86a RK |
204 | |
205 | if (__dma_omap15xx(od->plat->dma_attr)) | |
c5ed98b6 | 206 | omap_dma_chan_write(c, CPC, 0); |
fa3ad86a | 207 | else |
c5ed98b6 | 208 | omap_dma_chan_write(c, CDAC, 0); |
fa3ad86a | 209 | |
470b23f7 | 210 | omap_dma_clear_csr(c); |
fa3ad86a RK |
211 | |
212 | /* Enable interrupts */ | |
c5ed98b6 | 213 | omap_dma_chan_write(c, CICR, d->cicr); |
fa3ad86a | 214 | |
45da7b04 | 215 | /* Enable channel */ |
c5ed98b6 | 216 | omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); |
fa3ad86a RK |
217 | } |
218 | ||
219 | static void omap_dma_stop(struct omap_chan *c) | |
220 | { | |
221 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
222 | uint32_t val; | |
223 | ||
224 | /* disable irq */ | |
c5ed98b6 | 225 | omap_dma_chan_write(c, CICR, 0); |
fa3ad86a | 226 | |
470b23f7 | 227 | omap_dma_clear_csr(c); |
fa3ad86a | 228 | |
c5ed98b6 | 229 | val = omap_dma_chan_read(c, CCR); |
9043826d | 230 | if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) { |
fa3ad86a RK |
231 | uint32_t sysconfig; |
232 | unsigned i; | |
233 | ||
c5ed98b6 | 234 | sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG); |
fa3ad86a RK |
235 | val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK; |
236 | val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); | |
c5ed98b6 | 237 | omap_dma_glbl_write(od, OCP_SYSCONFIG, val); |
fa3ad86a | 238 | |
c5ed98b6 | 239 | val = omap_dma_chan_read(c, CCR); |
9043826d | 240 | val &= ~CCR_ENABLE; |
c5ed98b6 | 241 | omap_dma_chan_write(c, CCR, val); |
fa3ad86a RK |
242 | |
243 | /* Wait for sDMA FIFO to drain */ | |
244 | for (i = 0; ; i++) { | |
c5ed98b6 | 245 | val = omap_dma_chan_read(c, CCR); |
9043826d | 246 | if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))) |
fa3ad86a RK |
247 | break; |
248 | ||
249 | if (i > 100) | |
250 | break; | |
251 | ||
252 | udelay(5); | |
253 | } | |
254 | ||
9043826d | 255 | if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)) |
fa3ad86a RK |
256 | dev_err(c->vc.chan.device->dev, |
257 | "DMA drain did not complete on lch %d\n", | |
258 | c->dma_ch); | |
259 | ||
c5ed98b6 | 260 | omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig); |
fa3ad86a | 261 | } else { |
9043826d | 262 | val &= ~CCR_ENABLE; |
c5ed98b6 | 263 | omap_dma_chan_write(c, CCR, val); |
fa3ad86a RK |
264 | } |
265 | ||
266 | mb(); | |
267 | ||
268 | if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) { | |
c5ed98b6 | 269 | val = omap_dma_chan_read(c, CLNK_CTRL); |
fa3ad86a RK |
270 | |
271 | if (dma_omap1()) | |
272 | val |= 1 << 14; /* set the STOP_LNK bit */ | |
273 | else | |
9043826d | 274 | val &= ~CLNK_CTRL_ENABLE_LNK; |
fa3ad86a | 275 | |
c5ed98b6 | 276 | omap_dma_chan_write(c, CLNK_CTRL, val); |
fa3ad86a RK |
277 | } |
278 | } | |
279 | ||
7bedaa55 RK |
280 | static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d, |
281 | unsigned idx) | |
282 | { | |
283 | struct omap_sg *sg = d->sg + idx; | |
893e63e3 | 284 | unsigned cxsa, cxei, cxfi; |
913a2d0c RK |
285 | |
286 | if (d->dir == DMA_DEV_TO_MEM) { | |
893e63e3 RK |
287 | cxsa = CDSA; |
288 | cxei = CDEI; | |
289 | cxfi = CDFI; | |
913a2d0c | 290 | } else { |
893e63e3 RK |
291 | cxsa = CSSA; |
292 | cxei = CSEI; | |
293 | cxfi = CSFI; | |
913a2d0c RK |
294 | } |
295 | ||
c5ed98b6 RK |
296 | omap_dma_chan_write(c, cxsa, sg->addr); |
297 | omap_dma_chan_write(c, cxei, 0); | |
298 | omap_dma_chan_write(c, cxfi, 0); | |
299 | omap_dma_chan_write(c, CEN, sg->en); | |
300 | omap_dma_chan_write(c, CFN, sg->fn); | |
913a2d0c | 301 | |
fa3ad86a | 302 | omap_dma_start(c, d); |
913a2d0c RK |
303 | } |
304 | ||
305 | static void omap_dma_start_desc(struct omap_chan *c) | |
306 | { | |
307 | struct virt_dma_desc *vd = vchan_next_desc(&c->vc); | |
308 | struct omap_desc *d; | |
893e63e3 | 309 | unsigned cxsa, cxei, cxfi; |
b9e97822 | 310 | |
913a2d0c RK |
311 | if (!vd) { |
312 | c->desc = NULL; | |
313 | return; | |
314 | } | |
315 | ||
316 | list_del(&vd->node); | |
317 | ||
318 | c->desc = d = to_omap_dma_desc(&vd->tx); | |
319 | c->sgidx = 0; | |
320 | ||
59871902 RK |
321 | /* |
322 | * This provides the necessary barrier to ensure data held in | |
323 | * DMA coherent memory is visible to the DMA engine prior to | |
324 | * the transfer starting. | |
325 | */ | |
326 | mb(); | |
327 | ||
c5ed98b6 | 328 | omap_dma_chan_write(c, CCR, d->ccr); |
3ed4d18f | 329 | if (dma_omap1()) |
c5ed98b6 | 330 | omap_dma_chan_write(c, CCR2, d->ccr >> 16); |
b9e97822 | 331 | |
3ed4d18f | 332 | if (d->dir == DMA_DEV_TO_MEM) { |
893e63e3 RK |
333 | cxsa = CSSA; |
334 | cxei = CSEI; | |
335 | cxfi = CSFI; | |
b9e97822 | 336 | } else { |
893e63e3 RK |
337 | cxsa = CDSA; |
338 | cxei = CDEI; | |
339 | cxfi = CDFI; | |
b9e97822 RK |
340 | } |
341 | ||
c5ed98b6 RK |
342 | omap_dma_chan_write(c, cxsa, d->dev_addr); |
343 | omap_dma_chan_write(c, cxei, 0); | |
344 | omap_dma_chan_write(c, cxfi, d->fi); | |
345 | omap_dma_chan_write(c, CSDP, d->csdp); | |
346 | omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl); | |
b9e97822 | 347 | |
7bedaa55 RK |
348 | omap_dma_start_sg(c, d, 0); |
349 | } | |
350 | ||
351 | static void omap_dma_callback(int ch, u16 status, void *data) | |
352 | { | |
353 | struct omap_chan *c = data; | |
354 | struct omap_desc *d; | |
355 | unsigned long flags; | |
356 | ||
357 | spin_lock_irqsave(&c->vc.lock, flags); | |
358 | d = c->desc; | |
359 | if (d) { | |
3a774ea9 RK |
360 | if (!c->cyclic) { |
361 | if (++c->sgidx < d->sglen) { | |
362 | omap_dma_start_sg(c, d, c->sgidx); | |
363 | } else { | |
364 | omap_dma_start_desc(c); | |
365 | vchan_cookie_complete(&d->vd); | |
366 | } | |
7bedaa55 | 367 | } else { |
3a774ea9 | 368 | vchan_cyclic_callback(&d->vd); |
7bedaa55 RK |
369 | } |
370 | } | |
371 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
372 | } | |
373 | ||
374 | /* | |
375 | * This callback schedules all pending channels. We could be more | |
376 | * clever here by postponing allocation of the real DMA channels to | |
377 | * this point, and freeing them when our virtual channel becomes idle. | |
378 | * | |
379 | * We would then need to deal with 'all channels in-use' | |
380 | */ | |
381 | static void omap_dma_sched(unsigned long data) | |
382 | { | |
383 | struct omap_dmadev *d = (struct omap_dmadev *)data; | |
384 | LIST_HEAD(head); | |
385 | ||
386 | spin_lock_irq(&d->lock); | |
387 | list_splice_tail_init(&d->pending, &head); | |
388 | spin_unlock_irq(&d->lock); | |
389 | ||
390 | while (!list_empty(&head)) { | |
391 | struct omap_chan *c = list_first_entry(&head, | |
392 | struct omap_chan, node); | |
393 | ||
394 | spin_lock_irq(&c->vc.lock); | |
395 | list_del_init(&c->node); | |
396 | omap_dma_start_desc(c); | |
397 | spin_unlock_irq(&c->vc.lock); | |
398 | } | |
399 | } | |
400 | ||
401 | static int omap_dma_alloc_chan_resources(struct dma_chan *chan) | |
402 | { | |
403 | struct omap_chan *c = to_omap_dma_chan(chan); | |
404 | ||
9e2f7d82 | 405 | dev_dbg(c->vc.chan.device->dev, "allocating channel for %u\n", c->dma_sig); |
7bedaa55 RK |
406 | |
407 | return omap_request_dma(c->dma_sig, "DMA engine", | |
408 | omap_dma_callback, c, &c->dma_ch); | |
409 | } | |
410 | ||
411 | static void omap_dma_free_chan_resources(struct dma_chan *chan) | |
412 | { | |
413 | struct omap_chan *c = to_omap_dma_chan(chan); | |
414 | ||
415 | vchan_free_chan_resources(&c->vc); | |
416 | omap_free_dma(c->dma_ch); | |
417 | ||
9e2f7d82 | 418 | dev_dbg(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig); |
7bedaa55 RK |
419 | } |
420 | ||
3850e22f RK |
421 | static size_t omap_dma_sg_size(struct omap_sg *sg) |
422 | { | |
423 | return sg->en * sg->fn; | |
424 | } | |
425 | ||
426 | static size_t omap_dma_desc_size(struct omap_desc *d) | |
427 | { | |
428 | unsigned i; | |
429 | size_t size; | |
430 | ||
431 | for (size = i = 0; i < d->sglen; i++) | |
432 | size += omap_dma_sg_size(&d->sg[i]); | |
433 | ||
434 | return size * es_bytes[d->es]; | |
435 | } | |
436 | ||
437 | static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr) | |
438 | { | |
439 | unsigned i; | |
440 | size_t size, es_size = es_bytes[d->es]; | |
441 | ||
442 | for (size = i = 0; i < d->sglen; i++) { | |
443 | size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size; | |
444 | ||
445 | if (size) | |
446 | size += this_size; | |
447 | else if (addr >= d->sg[i].addr && | |
448 | addr < d->sg[i].addr + this_size) | |
449 | size += d->sg[i].addr + this_size - addr; | |
450 | } | |
451 | return size; | |
452 | } | |
453 | ||
3997cab3 RK |
454 | static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c) |
455 | { | |
456 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
457 | dma_addr_t addr; | |
458 | ||
459 | if (__dma_omap15xx(od->plat->dma_attr)) | |
c5ed98b6 | 460 | addr = omap_dma_chan_read(c, CPC); |
3997cab3 | 461 | else |
c5ed98b6 | 462 | addr = omap_dma_chan_read(c, CSAC); |
3997cab3 RK |
463 | |
464 | if (od->plat->errata & DMA_ERRATA_3_3 && addr == 0) | |
c5ed98b6 | 465 | addr = omap_dma_chan_read(c, CSAC); |
3997cab3 RK |
466 | |
467 | if (!__dma_omap15xx(od->plat->dma_attr)) { | |
468 | /* | |
469 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
470 | * not been started (no data has been transferred so far). | |
471 | * Return the programmed source start address in this case. | |
472 | */ | |
c5ed98b6 RK |
473 | if (omap_dma_chan_read(c, CDAC)) |
474 | addr = omap_dma_chan_read(c, CSAC); | |
3997cab3 | 475 | else |
c5ed98b6 | 476 | addr = omap_dma_chan_read(c, CSSA); |
3997cab3 RK |
477 | } |
478 | ||
479 | if (dma_omap1()) | |
c5ed98b6 | 480 | addr |= omap_dma_chan_read(c, CSSA) & 0xffff0000; |
3997cab3 RK |
481 | |
482 | return addr; | |
483 | } | |
484 | ||
485 | static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c) | |
486 | { | |
487 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); | |
488 | dma_addr_t addr; | |
489 | ||
490 | if (__dma_omap15xx(od->plat->dma_attr)) | |
c5ed98b6 | 491 | addr = omap_dma_chan_read(c, CPC); |
3997cab3 | 492 | else |
c5ed98b6 | 493 | addr = omap_dma_chan_read(c, CDAC); |
3997cab3 RK |
494 | |
495 | /* | |
496 | * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | |
497 | * read before the DMA controller finished disabling the channel. | |
498 | */ | |
499 | if (!__dma_omap15xx(od->plat->dma_attr) && addr == 0) { | |
c5ed98b6 | 500 | addr = omap_dma_chan_read(c, CDAC); |
3997cab3 RK |
501 | /* |
502 | * CDAC == 0 indicates that the DMA transfer on the channel has | |
503 | * not been started (no data has been transferred so far). | |
504 | * Return the programmed destination start address in this case. | |
505 | */ | |
506 | if (addr == 0) | |
c5ed98b6 | 507 | addr = omap_dma_chan_read(c, CDSA); |
3997cab3 RK |
508 | } |
509 | ||
510 | if (dma_omap1()) | |
c5ed98b6 | 511 | addr |= omap_dma_chan_read(c, CDSA) & 0xffff0000; |
3997cab3 RK |
512 | |
513 | return addr; | |
514 | } | |
515 | ||
7bedaa55 RK |
516 | static enum dma_status omap_dma_tx_status(struct dma_chan *chan, |
517 | dma_cookie_t cookie, struct dma_tx_state *txstate) | |
518 | { | |
3850e22f RK |
519 | struct omap_chan *c = to_omap_dma_chan(chan); |
520 | struct virt_dma_desc *vd; | |
521 | enum dma_status ret; | |
522 | unsigned long flags; | |
523 | ||
524 | ret = dma_cookie_status(chan, cookie, txstate); | |
7cce5083 | 525 | if (ret == DMA_COMPLETE || !txstate) |
3850e22f RK |
526 | return ret; |
527 | ||
528 | spin_lock_irqsave(&c->vc.lock, flags); | |
529 | vd = vchan_find_desc(&c->vc, cookie); | |
530 | if (vd) { | |
531 | txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx)); | |
532 | } else if (c->desc && c->desc->vd.tx.cookie == cookie) { | |
533 | struct omap_desc *d = c->desc; | |
534 | dma_addr_t pos; | |
535 | ||
536 | if (d->dir == DMA_MEM_TO_DEV) | |
3997cab3 | 537 | pos = omap_dma_get_src_pos(c); |
3850e22f | 538 | else if (d->dir == DMA_DEV_TO_MEM) |
3997cab3 | 539 | pos = omap_dma_get_dst_pos(c); |
3850e22f RK |
540 | else |
541 | pos = 0; | |
542 | ||
543 | txstate->residue = omap_dma_desc_size_pos(d, pos); | |
544 | } else { | |
545 | txstate->residue = 0; | |
546 | } | |
547 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
548 | ||
549 | return ret; | |
7bedaa55 RK |
550 | } |
551 | ||
552 | static void omap_dma_issue_pending(struct dma_chan *chan) | |
553 | { | |
554 | struct omap_chan *c = to_omap_dma_chan(chan); | |
555 | unsigned long flags; | |
556 | ||
557 | spin_lock_irqsave(&c->vc.lock, flags); | |
558 | if (vchan_issue_pending(&c->vc) && !c->desc) { | |
76502469 PU |
559 | /* |
560 | * c->cyclic is used only by audio and in this case the DMA need | |
561 | * to be started without delay. | |
562 | */ | |
563 | if (!c->cyclic) { | |
564 | struct omap_dmadev *d = to_omap_dma_dev(chan->device); | |
565 | spin_lock(&d->lock); | |
566 | if (list_empty(&c->node)) | |
567 | list_add_tail(&c->node, &d->pending); | |
568 | spin_unlock(&d->lock); | |
569 | tasklet_schedule(&d->task); | |
570 | } else { | |
571 | omap_dma_start_desc(c); | |
572 | } | |
7bedaa55 RK |
573 | } |
574 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
575 | } | |
576 | ||
577 | static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg( | |
578 | struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen, | |
579 | enum dma_transfer_direction dir, unsigned long tx_flags, void *context) | |
580 | { | |
49ae0b29 | 581 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
7bedaa55 RK |
582 | struct omap_chan *c = to_omap_dma_chan(chan); |
583 | enum dma_slave_buswidth dev_width; | |
584 | struct scatterlist *sgent; | |
585 | struct omap_desc *d; | |
586 | dma_addr_t dev_addr; | |
3ed4d18f | 587 | unsigned i, j = 0, es, en, frame_bytes; |
7bedaa55 RK |
588 | u32 burst; |
589 | ||
590 | if (dir == DMA_DEV_TO_MEM) { | |
591 | dev_addr = c->cfg.src_addr; | |
592 | dev_width = c->cfg.src_addr_width; | |
593 | burst = c->cfg.src_maxburst; | |
7bedaa55 RK |
594 | } else if (dir == DMA_MEM_TO_DEV) { |
595 | dev_addr = c->cfg.dst_addr; | |
596 | dev_width = c->cfg.dst_addr_width; | |
597 | burst = c->cfg.dst_maxburst; | |
7bedaa55 RK |
598 | } else { |
599 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); | |
600 | return NULL; | |
601 | } | |
602 | ||
603 | /* Bus width translates to the element size (ES) */ | |
604 | switch (dev_width) { | |
605 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
9043826d | 606 | es = CSDP_DATA_TYPE_8; |
7bedaa55 RK |
607 | break; |
608 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
9043826d | 609 | es = CSDP_DATA_TYPE_16; |
7bedaa55 RK |
610 | break; |
611 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
9043826d | 612 | es = CSDP_DATA_TYPE_32; |
7bedaa55 RK |
613 | break; |
614 | default: /* not reached */ | |
615 | return NULL; | |
616 | } | |
617 | ||
618 | /* Now allocate and setup the descriptor. */ | |
619 | d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC); | |
620 | if (!d) | |
621 | return NULL; | |
622 | ||
623 | d->dir = dir; | |
624 | d->dev_addr = dev_addr; | |
625 | d->es = es; | |
3ed4d18f | 626 | |
9043826d | 627 | d->ccr = CCR_SYNC_FRAME; |
3ed4d18f | 628 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 629 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
3ed4d18f | 630 | else |
9043826d | 631 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
3ed4d18f | 632 | |
9043826d | 633 | d->cicr = CICR_DROP_IE | CICR_BLOCK_IE; |
2f0d13bd | 634 | d->csdp = es; |
fa3ad86a | 635 | |
2f0d13bd | 636 | if (dma_omap1()) { |
3ed4d18f | 637 | if (__dma_omap16xx(od->plat->dma_attr)) { |
9043826d | 638 | d->ccr |= CCR_OMAP31_DISABLE; |
3ed4d18f RK |
639 | /* Duplicate what plat-omap/dma.c does */ |
640 | d->ccr |= c->dma_ch + 1; | |
641 | } else { | |
642 | d->ccr |= c->dma_sig & 0x1f; | |
643 | } | |
644 | ||
9043826d | 645 | d->cicr |= CICR_TOUT_IE; |
2f0d13bd RK |
646 | |
647 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 648 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB; |
2f0d13bd | 649 | else |
9043826d | 650 | d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF; |
2f0d13bd | 651 | } else { |
3ed4d18f RK |
652 | d->ccr |= (c->dma_sig & ~0x1f) << 14; |
653 | d->ccr |= c->dma_sig & 0x1f; | |
3ed4d18f RK |
654 | |
655 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 656 | d->ccr |= CCR_TRIGGER_SRC; |
3ed4d18f | 657 | |
9043826d | 658 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
2f0d13bd | 659 | } |
49ae0b29 RK |
660 | if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING) |
661 | d->ccr |= CCR_BUFFERING_DISABLE; | |
965aeb4d RK |
662 | if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS) |
663 | d->clnk_ctrl = c->dma_ch; | |
7bedaa55 RK |
664 | |
665 | /* | |
666 | * Build our scatterlist entries: each contains the address, | |
667 | * the number of elements (EN) in each frame, and the number of | |
668 | * frames (FN). Number of bytes for this entry = ES * EN * FN. | |
669 | * | |
670 | * Burst size translates to number of elements with frame sync. | |
671 | * Note: DMA engine defines burst to be the number of dev-width | |
672 | * transfers. | |
673 | */ | |
674 | en = burst; | |
675 | frame_bytes = es_bytes[es] * en; | |
676 | for_each_sg(sgl, sgent, sglen, i) { | |
677 | d->sg[j].addr = sg_dma_address(sgent); | |
678 | d->sg[j].en = en; | |
679 | d->sg[j].fn = sg_dma_len(sgent) / frame_bytes; | |
680 | j++; | |
681 | } | |
682 | ||
683 | d->sglen = j; | |
684 | ||
685 | return vchan_tx_prep(&c->vc, &d->vd, tx_flags); | |
686 | } | |
687 | ||
3a774ea9 RK |
688 | static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic( |
689 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, | |
ec8b5e48 PU |
690 | size_t period_len, enum dma_transfer_direction dir, unsigned long flags, |
691 | void *context) | |
3a774ea9 | 692 | { |
fa3ad86a | 693 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
3a774ea9 RK |
694 | struct omap_chan *c = to_omap_dma_chan(chan); |
695 | enum dma_slave_buswidth dev_width; | |
696 | struct omap_desc *d; | |
697 | dma_addr_t dev_addr; | |
3ed4d18f | 698 | unsigned es; |
3a774ea9 RK |
699 | u32 burst; |
700 | ||
701 | if (dir == DMA_DEV_TO_MEM) { | |
702 | dev_addr = c->cfg.src_addr; | |
703 | dev_width = c->cfg.src_addr_width; | |
704 | burst = c->cfg.src_maxburst; | |
3a774ea9 RK |
705 | } else if (dir == DMA_MEM_TO_DEV) { |
706 | dev_addr = c->cfg.dst_addr; | |
707 | dev_width = c->cfg.dst_addr_width; | |
708 | burst = c->cfg.dst_maxburst; | |
3a774ea9 RK |
709 | } else { |
710 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); | |
711 | return NULL; | |
712 | } | |
713 | ||
714 | /* Bus width translates to the element size (ES) */ | |
715 | switch (dev_width) { | |
716 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
9043826d | 717 | es = CSDP_DATA_TYPE_8; |
3a774ea9 RK |
718 | break; |
719 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
9043826d | 720 | es = CSDP_DATA_TYPE_16; |
3a774ea9 RK |
721 | break; |
722 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
9043826d | 723 | es = CSDP_DATA_TYPE_32; |
3a774ea9 RK |
724 | break; |
725 | default: /* not reached */ | |
726 | return NULL; | |
727 | } | |
728 | ||
729 | /* Now allocate and setup the descriptor. */ | |
730 | d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC); | |
731 | if (!d) | |
732 | return NULL; | |
733 | ||
734 | d->dir = dir; | |
735 | d->dev_addr = dev_addr; | |
736 | d->fi = burst; | |
737 | d->es = es; | |
3a774ea9 RK |
738 | d->sg[0].addr = buf_addr; |
739 | d->sg[0].en = period_len / es_bytes[es]; | |
740 | d->sg[0].fn = buf_len / period_len; | |
741 | d->sglen = 1; | |
3ed4d18f RK |
742 | |
743 | d->ccr = 0; | |
3ed4d18f | 744 | if (dir == DMA_DEV_TO_MEM) |
9043826d | 745 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
3ed4d18f | 746 | else |
9043826d | 747 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
3ed4d18f | 748 | |
9043826d | 749 | d->cicr = CICR_DROP_IE; |
fa3ad86a | 750 | if (flags & DMA_PREP_INTERRUPT) |
9043826d | 751 | d->cicr |= CICR_FRAME_IE; |
fa3ad86a | 752 | |
2f0d13bd RK |
753 | d->csdp = es; |
754 | ||
755 | if (dma_omap1()) { | |
3ed4d18f | 756 | if (__dma_omap16xx(od->plat->dma_attr)) { |
9043826d | 757 | d->ccr |= CCR_OMAP31_DISABLE; |
3ed4d18f RK |
758 | /* Duplicate what plat-omap/dma.c does */ |
759 | d->ccr |= c->dma_ch + 1; | |
760 | } else { | |
761 | d->ccr |= c->dma_sig & 0x1f; | |
762 | } | |
763 | ||
9043826d | 764 | d->cicr |= CICR_TOUT_IE; |
2f0d13bd RK |
765 | |
766 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 767 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI; |
2f0d13bd | 768 | else |
9043826d | 769 | d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF; |
2f0d13bd | 770 | } else { |
3ed4d18f RK |
771 | d->ccr |= (c->dma_sig & ~0x1f) << 14; |
772 | d->ccr |= c->dma_sig & 0x1f; | |
773 | ||
774 | if (burst) | |
9043826d RK |
775 | d->ccr |= CCR_SYNC_PACKET; |
776 | else | |
777 | d->ccr |= CCR_SYNC_ELEMENT; | |
3ed4d18f RK |
778 | |
779 | if (dir == DMA_DEV_TO_MEM) | |
9043826d | 780 | d->ccr |= CCR_TRIGGER_SRC; |
3ed4d18f | 781 | |
9043826d | 782 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
3a774ea9 | 783 | |
9043826d | 784 | d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64; |
2f0d13bd | 785 | } |
49ae0b29 RK |
786 | if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING) |
787 | d->ccr |= CCR_BUFFERING_DISABLE; | |
2f0d13bd | 788 | |
965aeb4d RK |
789 | if (__dma_omap15xx(od->plat->dma_attr)) |
790 | d->ccr |= CCR_AUTO_INIT | CCR_REPEAT; | |
791 | else | |
792 | d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK; | |
793 | ||
3ed4d18f | 794 | c->cyclic = true; |
3a774ea9 | 795 | |
2dde5b90 | 796 | return vchan_tx_prep(&c->vc, &d->vd, flags); |
3a774ea9 RK |
797 | } |
798 | ||
7bedaa55 RK |
799 | static int omap_dma_slave_config(struct omap_chan *c, struct dma_slave_config *cfg) |
800 | { | |
801 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || | |
802 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) | |
803 | return -EINVAL; | |
804 | ||
805 | memcpy(&c->cfg, cfg, sizeof(c->cfg)); | |
806 | ||
807 | return 0; | |
808 | } | |
809 | ||
810 | static int omap_dma_terminate_all(struct omap_chan *c) | |
811 | { | |
812 | struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device); | |
813 | unsigned long flags; | |
814 | LIST_HEAD(head); | |
815 | ||
816 | spin_lock_irqsave(&c->vc.lock, flags); | |
817 | ||
818 | /* Prevent this channel being scheduled */ | |
819 | spin_lock(&d->lock); | |
820 | list_del_init(&c->node); | |
821 | spin_unlock(&d->lock); | |
822 | ||
823 | /* | |
824 | * Stop DMA activity: we assume the callback will not be called | |
fa3ad86a | 825 | * after omap_dma_stop() returns (even if it does, it will see |
7bedaa55 RK |
826 | * c->desc is NULL and exit.) |
827 | */ | |
828 | if (c->desc) { | |
829 | c->desc = NULL; | |
2dcdf570 PU |
830 | /* Avoid stopping the dma twice */ |
831 | if (!c->paused) | |
fa3ad86a | 832 | omap_dma_stop(c); |
7bedaa55 RK |
833 | } |
834 | ||
3a774ea9 RK |
835 | if (c->cyclic) { |
836 | c->cyclic = false; | |
2dcdf570 | 837 | c->paused = false; |
3a774ea9 RK |
838 | } |
839 | ||
7bedaa55 RK |
840 | vchan_get_all_descriptors(&c->vc, &head); |
841 | spin_unlock_irqrestore(&c->vc.lock, flags); | |
842 | vchan_dma_desc_free_list(&c->vc, &head); | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
847 | static int omap_dma_pause(struct omap_chan *c) | |
848 | { | |
2dcdf570 PU |
849 | /* Pause/Resume only allowed with cyclic mode */ |
850 | if (!c->cyclic) | |
851 | return -EINVAL; | |
852 | ||
853 | if (!c->paused) { | |
fa3ad86a | 854 | omap_dma_stop(c); |
2dcdf570 PU |
855 | c->paused = true; |
856 | } | |
857 | ||
858 | return 0; | |
7bedaa55 RK |
859 | } |
860 | ||
861 | static int omap_dma_resume(struct omap_chan *c) | |
862 | { | |
2dcdf570 PU |
863 | /* Pause/Resume only allowed with cyclic mode */ |
864 | if (!c->cyclic) | |
865 | return -EINVAL; | |
866 | ||
867 | if (c->paused) { | |
fa3ad86a | 868 | omap_dma_start(c, c->desc); |
2dcdf570 PU |
869 | c->paused = false; |
870 | } | |
871 | ||
872 | return 0; | |
7bedaa55 RK |
873 | } |
874 | ||
875 | static int omap_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, | |
876 | unsigned long arg) | |
877 | { | |
878 | struct omap_chan *c = to_omap_dma_chan(chan); | |
879 | int ret; | |
880 | ||
881 | switch (cmd) { | |
882 | case DMA_SLAVE_CONFIG: | |
883 | ret = omap_dma_slave_config(c, (struct dma_slave_config *)arg); | |
884 | break; | |
885 | ||
886 | case DMA_TERMINATE_ALL: | |
887 | ret = omap_dma_terminate_all(c); | |
888 | break; | |
889 | ||
890 | case DMA_PAUSE: | |
891 | ret = omap_dma_pause(c); | |
892 | break; | |
893 | ||
894 | case DMA_RESUME: | |
895 | ret = omap_dma_resume(c); | |
896 | break; | |
897 | ||
898 | default: | |
899 | ret = -ENXIO; | |
900 | break; | |
901 | } | |
902 | ||
903 | return ret; | |
904 | } | |
905 | ||
906 | static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig) | |
907 | { | |
908 | struct omap_chan *c; | |
909 | ||
910 | c = kzalloc(sizeof(*c), GFP_KERNEL); | |
911 | if (!c) | |
912 | return -ENOMEM; | |
913 | ||
1b416c4b | 914 | c->plat = od->plat; |
7bedaa55 RK |
915 | c->dma_sig = dma_sig; |
916 | c->vc.desc_free = omap_dma_desc_free; | |
917 | vchan_init(&c->vc, &od->ddev); | |
918 | INIT_LIST_HEAD(&c->node); | |
919 | ||
920 | od->ddev.chancnt++; | |
921 | ||
922 | return 0; | |
923 | } | |
924 | ||
925 | static void omap_dma_free(struct omap_dmadev *od) | |
926 | { | |
927 | tasklet_kill(&od->task); | |
928 | while (!list_empty(&od->ddev.channels)) { | |
929 | struct omap_chan *c = list_first_entry(&od->ddev.channels, | |
930 | struct omap_chan, vc.chan.device_node); | |
931 | ||
932 | list_del(&c->vc.chan.device_node); | |
933 | tasklet_kill(&c->vc.task); | |
934 | kfree(c); | |
935 | } | |
7bedaa55 RK |
936 | } |
937 | ||
938 | static int omap_dma_probe(struct platform_device *pdev) | |
939 | { | |
940 | struct omap_dmadev *od; | |
941 | int rc, i; | |
942 | ||
104fce73 | 943 | od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); |
7bedaa55 RK |
944 | if (!od) |
945 | return -ENOMEM; | |
946 | ||
1b416c4b RK |
947 | od->plat = omap_get_plat_info(); |
948 | if (!od->plat) | |
949 | return -EPROBE_DEFER; | |
950 | ||
7bedaa55 | 951 | dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); |
3a774ea9 | 952 | dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); |
7bedaa55 RK |
953 | od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources; |
954 | od->ddev.device_free_chan_resources = omap_dma_free_chan_resources; | |
955 | od->ddev.device_tx_status = omap_dma_tx_status; | |
956 | od->ddev.device_issue_pending = omap_dma_issue_pending; | |
957 | od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg; | |
3a774ea9 | 958 | od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic; |
7bedaa55 RK |
959 | od->ddev.device_control = omap_dma_control; |
960 | od->ddev.dev = &pdev->dev; | |
961 | INIT_LIST_HEAD(&od->ddev.channels); | |
962 | INIT_LIST_HEAD(&od->pending); | |
963 | spin_lock_init(&od->lock); | |
964 | ||
965 | tasklet_init(&od->task, omap_dma_sched, (unsigned long)od); | |
966 | ||
967 | for (i = 0; i < 127; i++) { | |
968 | rc = omap_dma_chan_init(od, i); | |
969 | if (rc) { | |
970 | omap_dma_free(od); | |
971 | return rc; | |
972 | } | |
973 | } | |
974 | ||
975 | rc = dma_async_device_register(&od->ddev); | |
976 | if (rc) { | |
977 | pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n", | |
978 | rc); | |
979 | omap_dma_free(od); | |
8d30662a JH |
980 | return rc; |
981 | } | |
982 | ||
983 | platform_set_drvdata(pdev, od); | |
984 | ||
985 | if (pdev->dev.of_node) { | |
986 | omap_dma_info.dma_cap = od->ddev.cap_mask; | |
987 | ||
988 | /* Device-tree DMA controller registration */ | |
989 | rc = of_dma_controller_register(pdev->dev.of_node, | |
990 | of_dma_simple_xlate, &omap_dma_info); | |
991 | if (rc) { | |
992 | pr_warn("OMAP-DMA: failed to register DMA controller\n"); | |
993 | dma_async_device_unregister(&od->ddev); | |
994 | omap_dma_free(od); | |
995 | } | |
7bedaa55 RK |
996 | } |
997 | ||
998 | dev_info(&pdev->dev, "OMAP DMA engine driver\n"); | |
999 | ||
1000 | return rc; | |
1001 | } | |
1002 | ||
1003 | static int omap_dma_remove(struct platform_device *pdev) | |
1004 | { | |
1005 | struct omap_dmadev *od = platform_get_drvdata(pdev); | |
1006 | ||
8d30662a JH |
1007 | if (pdev->dev.of_node) |
1008 | of_dma_controller_free(pdev->dev.of_node); | |
1009 | ||
7bedaa55 RK |
1010 | dma_async_device_unregister(&od->ddev); |
1011 | omap_dma_free(od); | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
8d30662a JH |
1016 | static const struct of_device_id omap_dma_match[] = { |
1017 | { .compatible = "ti,omap2420-sdma", }, | |
1018 | { .compatible = "ti,omap2430-sdma", }, | |
1019 | { .compatible = "ti,omap3430-sdma", }, | |
1020 | { .compatible = "ti,omap3630-sdma", }, | |
1021 | { .compatible = "ti,omap4430-sdma", }, | |
1022 | {}, | |
1023 | }; | |
1024 | MODULE_DEVICE_TABLE(of, omap_dma_match); | |
1025 | ||
7bedaa55 RK |
1026 | static struct platform_driver omap_dma_driver = { |
1027 | .probe = omap_dma_probe, | |
1028 | .remove = omap_dma_remove, | |
1029 | .driver = { | |
1030 | .name = "omap-dma-engine", | |
1031 | .owner = THIS_MODULE, | |
8d30662a | 1032 | .of_match_table = of_match_ptr(omap_dma_match), |
7bedaa55 RK |
1033 | }, |
1034 | }; | |
1035 | ||
1036 | bool omap_dma_filter_fn(struct dma_chan *chan, void *param) | |
1037 | { | |
1038 | if (chan->device->dev->driver == &omap_dma_driver.driver) { | |
1039 | struct omap_chan *c = to_omap_dma_chan(chan); | |
1040 | unsigned req = *(unsigned *)param; | |
1041 | ||
1042 | return req == c->dma_sig; | |
1043 | } | |
1044 | return false; | |
1045 | } | |
1046 | EXPORT_SYMBOL_GPL(omap_dma_filter_fn); | |
1047 | ||
7bedaa55 RK |
1048 | static int omap_dma_init(void) |
1049 | { | |
be1f9481 | 1050 | return platform_driver_register(&omap_dma_driver); |
7bedaa55 RK |
1051 | } |
1052 | subsys_initcall(omap_dma_init); | |
1053 | ||
1054 | static void __exit omap_dma_exit(void) | |
1055 | { | |
7bedaa55 RK |
1056 | platform_driver_unregister(&omap_dma_driver); |
1057 | } | |
1058 | module_exit(omap_dma_exit); | |
1059 | ||
1060 | MODULE_AUTHOR("Russell King"); | |
1061 | MODULE_LICENSE("GPL"); |