Commit | Line | Data |
---|---|---|
b7d861d9 BK |
1 | /* |
2 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
b3040e40 JB |
4 | * |
5 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | |
6 | * Jaswinder Singh <jassi.brar@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
b7d861d9 | 14 | #include <linux/kernel.h> |
b3040e40 JB |
15 | #include <linux/io.h> |
16 | #include <linux/init.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/module.h> | |
b7d861d9 BK |
19 | #include <linux/string.h> |
20 | #include <linux/delay.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/dma-mapping.h> | |
b3040e40 | 23 | #include <linux/dmaengine.h> |
b3040e40 JB |
24 | #include <linux/amba/bus.h> |
25 | #include <linux/amba/pl330.h> | |
1b9bb715 | 26 | #include <linux/scatterlist.h> |
93ed5544 | 27 | #include <linux/of.h> |
a80258f9 | 28 | #include <linux/of_dma.h> |
bcc7fa95 | 29 | #include <linux/err.h> |
ae43b328 | 30 | #include <linux/pm_runtime.h> |
b3040e40 | 31 | |
d2ebfb33 | 32 | #include "dmaengine.h" |
b7d861d9 BK |
33 | #define PL330_MAX_CHAN 8 |
34 | #define PL330_MAX_IRQS 32 | |
35 | #define PL330_MAX_PERI 32 | |
36 | ||
f0564c7e LPC |
37 | enum pl330_cachectrl { |
38 | CCTRL0, /* Noncacheable and nonbufferable */ | |
39 | CCTRL1, /* Bufferable only */ | |
40 | CCTRL2, /* Cacheable, but do not allocate */ | |
41 | CCTRL3, /* Cacheable and bufferable, but do not allocate */ | |
42 | INVALID1, /* AWCACHE = 0x1000 */ | |
43 | INVALID2, | |
44 | CCTRL6, /* Cacheable write-through, allocate on writes only */ | |
45 | CCTRL7, /* Cacheable write-back, allocate on writes only */ | |
b7d861d9 BK |
46 | }; |
47 | ||
48 | enum pl330_byteswap { | |
49 | SWAP_NO, | |
50 | SWAP_2, | |
51 | SWAP_4, | |
52 | SWAP_8, | |
53 | SWAP_16, | |
54 | }; | |
55 | ||
b7d861d9 BK |
56 | /* Register and Bit field Definitions */ |
57 | #define DS 0x0 | |
58 | #define DS_ST_STOP 0x0 | |
59 | #define DS_ST_EXEC 0x1 | |
60 | #define DS_ST_CMISS 0x2 | |
61 | #define DS_ST_UPDTPC 0x3 | |
62 | #define DS_ST_WFE 0x4 | |
63 | #define DS_ST_ATBRR 0x5 | |
64 | #define DS_ST_QBUSY 0x6 | |
65 | #define DS_ST_WFP 0x7 | |
66 | #define DS_ST_KILL 0x8 | |
67 | #define DS_ST_CMPLT 0x9 | |
68 | #define DS_ST_FLTCMP 0xe | |
69 | #define DS_ST_FAULT 0xf | |
70 | ||
71 | #define DPC 0x4 | |
72 | #define INTEN 0x20 | |
73 | #define ES 0x24 | |
74 | #define INTSTATUS 0x28 | |
75 | #define INTCLR 0x2c | |
76 | #define FSM 0x30 | |
77 | #define FSC 0x34 | |
78 | #define FTM 0x38 | |
79 | ||
80 | #define _FTC 0x40 | |
81 | #define FTC(n) (_FTC + (n)*0x4) | |
82 | ||
83 | #define _CS 0x100 | |
84 | #define CS(n) (_CS + (n)*0x8) | |
85 | #define CS_CNS (1 << 21) | |
86 | ||
87 | #define _CPC 0x104 | |
88 | #define CPC(n) (_CPC + (n)*0x8) | |
89 | ||
90 | #define _SA 0x400 | |
91 | #define SA(n) (_SA + (n)*0x20) | |
92 | ||
93 | #define _DA 0x404 | |
94 | #define DA(n) (_DA + (n)*0x20) | |
95 | ||
96 | #define _CC 0x408 | |
97 | #define CC(n) (_CC + (n)*0x20) | |
98 | ||
99 | #define CC_SRCINC (1 << 0) | |
100 | #define CC_DSTINC (1 << 14) | |
101 | #define CC_SRCPRI (1 << 8) | |
102 | #define CC_DSTPRI (1 << 22) | |
103 | #define CC_SRCNS (1 << 9) | |
104 | #define CC_DSTNS (1 << 23) | |
105 | #define CC_SRCIA (1 << 10) | |
106 | #define CC_DSTIA (1 << 24) | |
107 | #define CC_SRCBRSTLEN_SHFT 4 | |
108 | #define CC_DSTBRSTLEN_SHFT 18 | |
109 | #define CC_SRCBRSTSIZE_SHFT 1 | |
110 | #define CC_DSTBRSTSIZE_SHFT 15 | |
111 | #define CC_SRCCCTRL_SHFT 11 | |
112 | #define CC_SRCCCTRL_MASK 0x7 | |
113 | #define CC_DSTCCTRL_SHFT 25 | |
114 | #define CC_DRCCCTRL_MASK 0x7 | |
115 | #define CC_SWAP_SHFT 28 | |
116 | ||
117 | #define _LC0 0x40c | |
118 | #define LC0(n) (_LC0 + (n)*0x20) | |
119 | ||
120 | #define _LC1 0x410 | |
121 | #define LC1(n) (_LC1 + (n)*0x20) | |
122 | ||
123 | #define DBGSTATUS 0xd00 | |
124 | #define DBG_BUSY (1 << 0) | |
125 | ||
126 | #define DBGCMD 0xd04 | |
127 | #define DBGINST0 0xd08 | |
128 | #define DBGINST1 0xd0c | |
129 | ||
130 | #define CR0 0xe00 | |
131 | #define CR1 0xe04 | |
132 | #define CR2 0xe08 | |
133 | #define CR3 0xe0c | |
134 | #define CR4 0xe10 | |
135 | #define CRD 0xe14 | |
136 | ||
137 | #define PERIPH_ID 0xfe0 | |
3ecf51a4 BK |
138 | #define PERIPH_REV_SHIFT 20 |
139 | #define PERIPH_REV_MASK 0xf | |
140 | #define PERIPH_REV_R0P0 0 | |
141 | #define PERIPH_REV_R1P0 1 | |
142 | #define PERIPH_REV_R1P1 2 | |
b7d861d9 BK |
143 | |
144 | #define CR0_PERIPH_REQ_SET (1 << 0) | |
145 | #define CR0_BOOT_EN_SET (1 << 1) | |
146 | #define CR0_BOOT_MAN_NS (1 << 2) | |
147 | #define CR0_NUM_CHANS_SHIFT 4 | |
148 | #define CR0_NUM_CHANS_MASK 0x7 | |
149 | #define CR0_NUM_PERIPH_SHIFT 12 | |
150 | #define CR0_NUM_PERIPH_MASK 0x1f | |
151 | #define CR0_NUM_EVENTS_SHIFT 17 | |
152 | #define CR0_NUM_EVENTS_MASK 0x1f | |
153 | ||
154 | #define CR1_ICACHE_LEN_SHIFT 0 | |
155 | #define CR1_ICACHE_LEN_MASK 0x7 | |
156 | #define CR1_NUM_ICACHELINES_SHIFT 4 | |
157 | #define CR1_NUM_ICACHELINES_MASK 0xf | |
158 | ||
159 | #define CRD_DATA_WIDTH_SHIFT 0 | |
160 | #define CRD_DATA_WIDTH_MASK 0x7 | |
161 | #define CRD_WR_CAP_SHIFT 4 | |
162 | #define CRD_WR_CAP_MASK 0x7 | |
163 | #define CRD_WR_Q_DEP_SHIFT 8 | |
164 | #define CRD_WR_Q_DEP_MASK 0xf | |
165 | #define CRD_RD_CAP_SHIFT 12 | |
166 | #define CRD_RD_CAP_MASK 0x7 | |
167 | #define CRD_RD_Q_DEP_SHIFT 16 | |
168 | #define CRD_RD_Q_DEP_MASK 0xf | |
169 | #define CRD_DATA_BUFF_SHIFT 20 | |
170 | #define CRD_DATA_BUFF_MASK 0x3ff | |
171 | ||
172 | #define PART 0x330 | |
173 | #define DESIGNER 0x41 | |
174 | #define REVISION 0x0 | |
175 | #define INTEG_CFG 0x0 | |
176 | #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) | |
177 | ||
b7d861d9 BK |
178 | #define PL330_STATE_STOPPED (1 << 0) |
179 | #define PL330_STATE_EXECUTING (1 << 1) | |
180 | #define PL330_STATE_WFE (1 << 2) | |
181 | #define PL330_STATE_FAULTING (1 << 3) | |
182 | #define PL330_STATE_COMPLETING (1 << 4) | |
183 | #define PL330_STATE_WFP (1 << 5) | |
184 | #define PL330_STATE_KILLING (1 << 6) | |
185 | #define PL330_STATE_FAULT_COMPLETING (1 << 7) | |
186 | #define PL330_STATE_CACHEMISS (1 << 8) | |
187 | #define PL330_STATE_UPDTPC (1 << 9) | |
188 | #define PL330_STATE_ATBARRIER (1 << 10) | |
189 | #define PL330_STATE_QUEUEBUSY (1 << 11) | |
190 | #define PL330_STATE_INVALID (1 << 15) | |
191 | ||
192 | #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ | |
193 | | PL330_STATE_WFE | PL330_STATE_FAULTING) | |
194 | ||
195 | #define CMD_DMAADDH 0x54 | |
196 | #define CMD_DMAEND 0x00 | |
197 | #define CMD_DMAFLUSHP 0x35 | |
198 | #define CMD_DMAGO 0xa0 | |
199 | #define CMD_DMALD 0x04 | |
200 | #define CMD_DMALDP 0x25 | |
201 | #define CMD_DMALP 0x20 | |
202 | #define CMD_DMALPEND 0x28 | |
203 | #define CMD_DMAKILL 0x01 | |
204 | #define CMD_DMAMOV 0xbc | |
205 | #define CMD_DMANOP 0x18 | |
206 | #define CMD_DMARMB 0x12 | |
207 | #define CMD_DMASEV 0x34 | |
208 | #define CMD_DMAST 0x08 | |
209 | #define CMD_DMASTP 0x29 | |
210 | #define CMD_DMASTZ 0x0c | |
211 | #define CMD_DMAWFE 0x36 | |
212 | #define CMD_DMAWFP 0x30 | |
213 | #define CMD_DMAWMB 0x13 | |
214 | ||
215 | #define SZ_DMAADDH 3 | |
216 | #define SZ_DMAEND 1 | |
217 | #define SZ_DMAFLUSHP 2 | |
218 | #define SZ_DMALD 1 | |
219 | #define SZ_DMALDP 2 | |
220 | #define SZ_DMALP 2 | |
221 | #define SZ_DMALPEND 2 | |
222 | #define SZ_DMAKILL 1 | |
223 | #define SZ_DMAMOV 6 | |
224 | #define SZ_DMANOP 1 | |
225 | #define SZ_DMARMB 1 | |
226 | #define SZ_DMASEV 2 | |
227 | #define SZ_DMAST 1 | |
228 | #define SZ_DMASTP 2 | |
229 | #define SZ_DMASTZ 1 | |
230 | #define SZ_DMAWFE 2 | |
231 | #define SZ_DMAWFP 2 | |
232 | #define SZ_DMAWMB 1 | |
233 | #define SZ_DMAGO 6 | |
234 | ||
235 | #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) | |
236 | #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) | |
237 | ||
238 | #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) | |
239 | #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) | |
240 | ||
241 | /* | |
242 | * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req | |
243 | * at 1byte/burst for P<->M and M<->M respectively. | |
244 | * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req | |
245 | * should be enough for P<->M and M<->M respectively. | |
246 | */ | |
247 | #define MCODE_BUFF_PER_REQ 256 | |
248 | ||
b7d861d9 BK |
249 | /* Use this _only_ to wait on transient states */ |
250 | #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); | |
251 | ||
252 | #ifdef PL330_DEBUG_MCGEN | |
253 | static unsigned cmd_line; | |
254 | #define PL330_DBGCMD_DUMP(off, x...) do { \ | |
255 | printk("%x:", cmd_line); \ | |
256 | printk(x); \ | |
257 | cmd_line += off; \ | |
258 | } while (0) | |
259 | #define PL330_DBGMC_START(addr) (cmd_line = addr) | |
260 | #else | |
261 | #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) | |
262 | #define PL330_DBGMC_START(addr) do {} while (0) | |
263 | #endif | |
264 | ||
265 | /* The number of default descriptors */ | |
d2ebfb33 | 266 | |
b3040e40 JB |
267 | #define NR_DEFAULT_DESC 16 |
268 | ||
ae43b328 KK |
269 | /* Delay for runtime PM autosuspend, ms */ |
270 | #define PL330_AUTOSUSPEND_DELAY 20 | |
271 | ||
b7d861d9 BK |
272 | /* Populated by the PL330 core driver for DMA API driver's info */ |
273 | struct pl330_config { | |
274 | u32 periph_id; | |
b7d861d9 BK |
275 | #define DMAC_MODE_NS (1 << 0) |
276 | unsigned int mode; | |
277 | unsigned int data_bus_width:10; /* In number of bits */ | |
1f0a5cbf | 278 | unsigned int data_buf_dep:11; |
b7d861d9 BK |
279 | unsigned int num_chan:4; |
280 | unsigned int num_peri:6; | |
281 | u32 peri_ns; | |
282 | unsigned int num_events:6; | |
283 | u32 irq_ns; | |
284 | }; | |
285 | ||
b7d861d9 BK |
286 | /** |
287 | * Request Configuration. | |
288 | * The PL330 core does not modify this and uses the last | |
289 | * working configuration if the request doesn't provide any. | |
290 | * | |
291 | * The Client may want to provide this info only for the | |
292 | * first request and a request with new settings. | |
293 | */ | |
294 | struct pl330_reqcfg { | |
295 | /* Address Incrementing */ | |
296 | unsigned dst_inc:1; | |
297 | unsigned src_inc:1; | |
298 | ||
299 | /* | |
300 | * For now, the SRC & DST protection levels | |
301 | * and burst size/length are assumed same. | |
302 | */ | |
303 | bool nonsecure; | |
304 | bool privileged; | |
305 | bool insnaccess; | |
306 | unsigned brst_len:5; | |
307 | unsigned brst_size:3; /* in power of 2 */ | |
308 | ||
f0564c7e LPC |
309 | enum pl330_cachectrl dcctl; |
310 | enum pl330_cachectrl scctl; | |
b7d861d9 | 311 | enum pl330_byteswap swap; |
3ecf51a4 | 312 | struct pl330_config *pcfg; |
b7d861d9 BK |
313 | }; |
314 | ||
315 | /* | |
316 | * One cycle of DMAC operation. | |
317 | * There may be more than one xfer in a request. | |
318 | */ | |
319 | struct pl330_xfer { | |
320 | u32 src_addr; | |
321 | u32 dst_addr; | |
322 | /* Size to xfer */ | |
323 | u32 bytes; | |
b7d861d9 BK |
324 | }; |
325 | ||
326 | /* The xfer callbacks are made with one of these arguments. */ | |
327 | enum pl330_op_err { | |
328 | /* The all xfers in the request were success. */ | |
329 | PL330_ERR_NONE, | |
330 | /* If req aborted due to global error. */ | |
331 | PL330_ERR_ABORT, | |
332 | /* If req failed due to problem with Channel. */ | |
333 | PL330_ERR_FAIL, | |
334 | }; | |
335 | ||
b7d861d9 BK |
336 | enum dmamov_dst { |
337 | SAR = 0, | |
338 | CCR, | |
339 | DAR, | |
340 | }; | |
341 | ||
342 | enum pl330_dst { | |
343 | SRC = 0, | |
344 | DST, | |
345 | }; | |
346 | ||
347 | enum pl330_cond { | |
348 | SINGLE, | |
349 | BURST, | |
350 | ALWAYS, | |
351 | }; | |
352 | ||
9dc5a315 LPC |
353 | struct dma_pl330_desc; |
354 | ||
b7d861d9 BK |
355 | struct _pl330_req { |
356 | u32 mc_bus; | |
357 | void *mc_cpu; | |
9dc5a315 | 358 | struct dma_pl330_desc *desc; |
b7d861d9 BK |
359 | }; |
360 | ||
361 | /* ToBeDone for tasklet */ | |
362 | struct _pl330_tbd { | |
363 | bool reset_dmac; | |
364 | bool reset_mngr; | |
365 | u8 reset_chan; | |
366 | }; | |
367 | ||
368 | /* A DMAC Thread */ | |
369 | struct pl330_thread { | |
370 | u8 id; | |
371 | int ev; | |
372 | /* If the channel is not yet acquired by any client */ | |
373 | bool free; | |
374 | /* Parent DMAC */ | |
375 | struct pl330_dmac *dmac; | |
376 | /* Only two at a time */ | |
377 | struct _pl330_req req[2]; | |
378 | /* Index of the last enqueued request */ | |
379 | unsigned lstenq; | |
380 | /* Index of the last submitted request or -1 if the DMA is stopped */ | |
381 | int req_running; | |
382 | }; | |
383 | ||
384 | enum pl330_dmac_state { | |
385 | UNINIT, | |
386 | INIT, | |
387 | DYING, | |
388 | }; | |
389 | ||
b3040e40 JB |
390 | enum desc_status { |
391 | /* In the DMAC pool */ | |
392 | FREE, | |
393 | /* | |
d73111c6 | 394 | * Allocated to some channel during prep_xxx |
b3040e40 JB |
395 | * Also may be sitting on the work_list. |
396 | */ | |
397 | PREP, | |
398 | /* | |
399 | * Sitting on the work_list and already submitted | |
400 | * to the PL330 core. Not more than two descriptors | |
401 | * of a channel can be BUSY at any time. | |
402 | */ | |
403 | BUSY, | |
404 | /* | |
405 | * Sitting on the channel work_list but xfer done | |
406 | * by PL330 core | |
407 | */ | |
408 | DONE, | |
409 | }; | |
410 | ||
411 | struct dma_pl330_chan { | |
412 | /* Schedule desc completion */ | |
413 | struct tasklet_struct task; | |
414 | ||
415 | /* DMA-Engine Channel */ | |
416 | struct dma_chan chan; | |
417 | ||
04abf5da LPC |
418 | /* List of submitted descriptors */ |
419 | struct list_head submitted_list; | |
420 | /* List of issued descriptors */ | |
b3040e40 | 421 | struct list_head work_list; |
39ff8613 LPC |
422 | /* List of completed descriptors */ |
423 | struct list_head completed_list; | |
b3040e40 JB |
424 | |
425 | /* Pointer to the DMAC that manages this channel, | |
426 | * NULL if the channel is available to be acquired. | |
427 | * As the parent, this DMAC also provides descriptors | |
428 | * to the channel. | |
429 | */ | |
f6f2421c | 430 | struct pl330_dmac *dmac; |
b3040e40 JB |
431 | |
432 | /* To protect channel manipulation */ | |
433 | spinlock_t lock; | |
434 | ||
65ad6060 LPC |
435 | /* |
436 | * Hardware channel thread of PL330 DMAC. NULL if the channel is | |
437 | * available. | |
b3040e40 | 438 | */ |
65ad6060 | 439 | struct pl330_thread *thread; |
1b9bb715 BK |
440 | |
441 | /* For D-to-M and M-to-D channels */ | |
442 | int burst_sz; /* the peripheral fifo width */ | |
1d0c1d60 | 443 | int burst_len; /* the number of burst */ |
1b9bb715 | 444 | dma_addr_t fifo_addr; |
42bc9cf4 BK |
445 | |
446 | /* for cyclic capability */ | |
447 | bool cyclic; | |
b3040e40 JB |
448 | }; |
449 | ||
f6f2421c | 450 | struct pl330_dmac { |
b3040e40 JB |
451 | /* DMA-Engine Device */ |
452 | struct dma_device ddma; | |
453 | ||
b714b84e LPC |
454 | /* Holds info about sg limitations */ |
455 | struct device_dma_parameters dma_parms; | |
456 | ||
b3040e40 JB |
457 | /* Pool of descriptors available for the DMAC's channels */ |
458 | struct list_head desc_pool; | |
459 | /* To protect desc_pool manipulation */ | |
460 | spinlock_t pool_lock; | |
461 | ||
f6f2421c LPC |
462 | /* Size of MicroCode buffers for each channel. */ |
463 | unsigned mcbufsz; | |
464 | /* ioremap'ed address of PL330 registers. */ | |
465 | void __iomem *base; | |
466 | /* Populated by the PL330 core driver during pl330_add */ | |
467 | struct pl330_config pcfg; | |
468 | ||
469 | spinlock_t lock; | |
470 | /* Maximum possible events/irqs */ | |
471 | int events[32]; | |
472 | /* BUS address of MicroCode buffer */ | |
473 | dma_addr_t mcode_bus; | |
474 | /* CPU address of MicroCode buffer */ | |
475 | void *mcode_cpu; | |
476 | /* List of all Channel threads */ | |
477 | struct pl330_thread *channels; | |
478 | /* Pointer to the MANAGER thread */ | |
479 | struct pl330_thread *manager; | |
480 | /* To handle bad news in interrupt */ | |
481 | struct tasklet_struct tasks; | |
482 | struct _pl330_tbd dmac_tbd; | |
483 | /* State of DMAC operation */ | |
484 | enum pl330_dmac_state state; | |
485 | /* Holds list of reqs with due callbacks */ | |
486 | struct list_head req_done; | |
487 | ||
b3040e40 | 488 | /* Peripheral channels connected to this DMAC */ |
70cbb163 | 489 | unsigned int num_peripherals; |
4e0e6109 | 490 | struct dma_pl330_chan *peripherals; /* keep at end */ |
b3040e40 JB |
491 | }; |
492 | ||
493 | struct dma_pl330_desc { | |
494 | /* To attach to a queue as child */ | |
495 | struct list_head node; | |
496 | ||
497 | /* Descriptor for the DMA Engine API */ | |
498 | struct dma_async_tx_descriptor txd; | |
499 | ||
500 | /* Xfer for PL330 core */ | |
501 | struct pl330_xfer px; | |
502 | ||
503 | struct pl330_reqcfg rqcfg; | |
b3040e40 JB |
504 | |
505 | enum desc_status status; | |
506 | ||
aee4d1fa RB |
507 | int bytes_requested; |
508 | bool last; | |
509 | ||
b3040e40 JB |
510 | /* The channel which currently holds this desc */ |
511 | struct dma_pl330_chan *pchan; | |
9dc5a315 LPC |
512 | |
513 | enum dma_transfer_direction rqtype; | |
514 | /* Index of peripheral for the xfer. */ | |
515 | unsigned peri:5; | |
516 | /* Hook to attach to DMAC's list of reqs with due callback */ | |
517 | struct list_head rqd; | |
518 | }; | |
519 | ||
520 | struct _xfer_spec { | |
521 | u32 ccr; | |
522 | struct dma_pl330_desc *desc; | |
b3040e40 JB |
523 | }; |
524 | ||
b7d861d9 BK |
525 | static inline bool _queue_empty(struct pl330_thread *thrd) |
526 | { | |
8ed30a14 | 527 | return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL; |
b7d861d9 BK |
528 | } |
529 | ||
530 | static inline bool _queue_full(struct pl330_thread *thrd) | |
531 | { | |
8ed30a14 | 532 | return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL; |
b7d861d9 BK |
533 | } |
534 | ||
535 | static inline bool is_manager(struct pl330_thread *thrd) | |
536 | { | |
fbbcd9be | 537 | return thrd->dmac->manager == thrd; |
b7d861d9 BK |
538 | } |
539 | ||
540 | /* If manager of the thread is in Non-Secure mode */ | |
541 | static inline bool _manager_ns(struct pl330_thread *thrd) | |
542 | { | |
f6f2421c | 543 | return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false; |
b7d861d9 BK |
544 | } |
545 | ||
3ecf51a4 BK |
546 | static inline u32 get_revision(u32 periph_id) |
547 | { | |
548 | return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; | |
549 | } | |
550 | ||
b7d861d9 BK |
551 | static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], |
552 | enum pl330_dst da, u16 val) | |
553 | { | |
554 | if (dry_run) | |
555 | return SZ_DMAADDH; | |
556 | ||
557 | buf[0] = CMD_DMAADDH; | |
558 | buf[0] |= (da << 1); | |
3a2307f7 | 559 | *((__le16 *)&buf[1]) = cpu_to_le16(val); |
b7d861d9 BK |
560 | |
561 | PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", | |
562 | da == 1 ? "DA" : "SA", val); | |
563 | ||
564 | return SZ_DMAADDH; | |
565 | } | |
566 | ||
567 | static inline u32 _emit_END(unsigned dry_run, u8 buf[]) | |
568 | { | |
569 | if (dry_run) | |
570 | return SZ_DMAEND; | |
571 | ||
572 | buf[0] = CMD_DMAEND; | |
573 | ||
574 | PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); | |
575 | ||
576 | return SZ_DMAEND; | |
577 | } | |
578 | ||
579 | static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) | |
580 | { | |
581 | if (dry_run) | |
582 | return SZ_DMAFLUSHP; | |
583 | ||
584 | buf[0] = CMD_DMAFLUSHP; | |
585 | ||
586 | peri &= 0x1f; | |
587 | peri <<= 3; | |
588 | buf[1] = peri; | |
589 | ||
590 | PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); | |
591 | ||
592 | return SZ_DMAFLUSHP; | |
593 | } | |
594 | ||
595 | static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
596 | { | |
597 | if (dry_run) | |
598 | return SZ_DMALD; | |
599 | ||
600 | buf[0] = CMD_DMALD; | |
601 | ||
602 | if (cond == SINGLE) | |
603 | buf[0] |= (0 << 1) | (1 << 0); | |
604 | else if (cond == BURST) | |
605 | buf[0] |= (1 << 1) | (1 << 0); | |
606 | ||
607 | PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", | |
608 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
609 | ||
610 | return SZ_DMALD; | |
611 | } | |
612 | ||
613 | static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], | |
614 | enum pl330_cond cond, u8 peri) | |
615 | { | |
616 | if (dry_run) | |
617 | return SZ_DMALDP; | |
618 | ||
619 | buf[0] = CMD_DMALDP; | |
620 | ||
621 | if (cond == BURST) | |
622 | buf[0] |= (1 << 1); | |
623 | ||
624 | peri &= 0x1f; | |
625 | peri <<= 3; | |
626 | buf[1] = peri; | |
627 | ||
628 | PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", | |
629 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
630 | ||
631 | return SZ_DMALDP; | |
632 | } | |
633 | ||
634 | static inline u32 _emit_LP(unsigned dry_run, u8 buf[], | |
635 | unsigned loop, u8 cnt) | |
636 | { | |
637 | if (dry_run) | |
638 | return SZ_DMALP; | |
639 | ||
640 | buf[0] = CMD_DMALP; | |
641 | ||
642 | if (loop) | |
643 | buf[0] |= (1 << 1); | |
644 | ||
645 | cnt--; /* DMAC increments by 1 internally */ | |
646 | buf[1] = cnt; | |
647 | ||
648 | PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); | |
649 | ||
650 | return SZ_DMALP; | |
651 | } | |
652 | ||
653 | struct _arg_LPEND { | |
654 | enum pl330_cond cond; | |
655 | bool forever; | |
656 | unsigned loop; | |
657 | u8 bjump; | |
658 | }; | |
659 | ||
660 | static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], | |
661 | const struct _arg_LPEND *arg) | |
662 | { | |
663 | enum pl330_cond cond = arg->cond; | |
664 | bool forever = arg->forever; | |
665 | unsigned loop = arg->loop; | |
666 | u8 bjump = arg->bjump; | |
667 | ||
668 | if (dry_run) | |
669 | return SZ_DMALPEND; | |
670 | ||
671 | buf[0] = CMD_DMALPEND; | |
672 | ||
673 | if (loop) | |
674 | buf[0] |= (1 << 2); | |
675 | ||
676 | if (!forever) | |
677 | buf[0] |= (1 << 4); | |
678 | ||
679 | if (cond == SINGLE) | |
680 | buf[0] |= (0 << 1) | (1 << 0); | |
681 | else if (cond == BURST) | |
682 | buf[0] |= (1 << 1) | (1 << 0); | |
683 | ||
684 | buf[1] = bjump; | |
685 | ||
686 | PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", | |
687 | forever ? "FE" : "END", | |
688 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), | |
689 | loop ? '1' : '0', | |
690 | bjump); | |
691 | ||
692 | return SZ_DMALPEND; | |
693 | } | |
694 | ||
695 | static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) | |
696 | { | |
697 | if (dry_run) | |
698 | return SZ_DMAKILL; | |
699 | ||
700 | buf[0] = CMD_DMAKILL; | |
701 | ||
702 | return SZ_DMAKILL; | |
703 | } | |
704 | ||
705 | static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], | |
706 | enum dmamov_dst dst, u32 val) | |
707 | { | |
708 | if (dry_run) | |
709 | return SZ_DMAMOV; | |
710 | ||
711 | buf[0] = CMD_DMAMOV; | |
712 | buf[1] = dst; | |
3a2307f7 | 713 | *((__le32 *)&buf[2]) = cpu_to_le32(val); |
b7d861d9 BK |
714 | |
715 | PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", | |
716 | dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); | |
717 | ||
718 | return SZ_DMAMOV; | |
719 | } | |
720 | ||
721 | static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) | |
722 | { | |
723 | if (dry_run) | |
724 | return SZ_DMANOP; | |
725 | ||
726 | buf[0] = CMD_DMANOP; | |
727 | ||
728 | PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); | |
729 | ||
730 | return SZ_DMANOP; | |
731 | } | |
732 | ||
733 | static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) | |
734 | { | |
735 | if (dry_run) | |
736 | return SZ_DMARMB; | |
737 | ||
738 | buf[0] = CMD_DMARMB; | |
739 | ||
740 | PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); | |
741 | ||
742 | return SZ_DMARMB; | |
743 | } | |
744 | ||
745 | static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) | |
746 | { | |
747 | if (dry_run) | |
748 | return SZ_DMASEV; | |
749 | ||
750 | buf[0] = CMD_DMASEV; | |
751 | ||
752 | ev &= 0x1f; | |
753 | ev <<= 3; | |
754 | buf[1] = ev; | |
755 | ||
756 | PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); | |
757 | ||
758 | return SZ_DMASEV; | |
759 | } | |
760 | ||
761 | static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
762 | { | |
763 | if (dry_run) | |
764 | return SZ_DMAST; | |
765 | ||
766 | buf[0] = CMD_DMAST; | |
767 | ||
768 | if (cond == SINGLE) | |
769 | buf[0] |= (0 << 1) | (1 << 0); | |
770 | else if (cond == BURST) | |
771 | buf[0] |= (1 << 1) | (1 << 0); | |
772 | ||
773 | PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", | |
774 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
775 | ||
776 | return SZ_DMAST; | |
777 | } | |
778 | ||
779 | static inline u32 _emit_STP(unsigned dry_run, u8 buf[], | |
780 | enum pl330_cond cond, u8 peri) | |
781 | { | |
782 | if (dry_run) | |
783 | return SZ_DMASTP; | |
784 | ||
785 | buf[0] = CMD_DMASTP; | |
786 | ||
787 | if (cond == BURST) | |
788 | buf[0] |= (1 << 1); | |
789 | ||
790 | peri &= 0x1f; | |
791 | peri <<= 3; | |
792 | buf[1] = peri; | |
793 | ||
794 | PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", | |
795 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
796 | ||
797 | return SZ_DMASTP; | |
798 | } | |
799 | ||
800 | static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) | |
801 | { | |
802 | if (dry_run) | |
803 | return SZ_DMASTZ; | |
804 | ||
805 | buf[0] = CMD_DMASTZ; | |
806 | ||
807 | PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); | |
808 | ||
809 | return SZ_DMASTZ; | |
810 | } | |
811 | ||
812 | static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, | |
813 | unsigned invalidate) | |
814 | { | |
815 | if (dry_run) | |
816 | return SZ_DMAWFE; | |
817 | ||
818 | buf[0] = CMD_DMAWFE; | |
819 | ||
820 | ev &= 0x1f; | |
821 | ev <<= 3; | |
822 | buf[1] = ev; | |
823 | ||
824 | if (invalidate) | |
825 | buf[1] |= (1 << 1); | |
826 | ||
827 | PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", | |
828 | ev >> 3, invalidate ? ", I" : ""); | |
829 | ||
830 | return SZ_DMAWFE; | |
831 | } | |
832 | ||
833 | static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], | |
834 | enum pl330_cond cond, u8 peri) | |
835 | { | |
836 | if (dry_run) | |
837 | return SZ_DMAWFP; | |
838 | ||
839 | buf[0] = CMD_DMAWFP; | |
840 | ||
841 | if (cond == SINGLE) | |
842 | buf[0] |= (0 << 1) | (0 << 0); | |
843 | else if (cond == BURST) | |
844 | buf[0] |= (1 << 1) | (0 << 0); | |
845 | else | |
846 | buf[0] |= (0 << 1) | (1 << 0); | |
847 | ||
848 | peri &= 0x1f; | |
849 | peri <<= 3; | |
850 | buf[1] = peri; | |
851 | ||
852 | PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", | |
853 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); | |
854 | ||
855 | return SZ_DMAWFP; | |
856 | } | |
857 | ||
858 | static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) | |
859 | { | |
860 | if (dry_run) | |
861 | return SZ_DMAWMB; | |
862 | ||
863 | buf[0] = CMD_DMAWMB; | |
864 | ||
865 | PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); | |
866 | ||
867 | return SZ_DMAWMB; | |
868 | } | |
869 | ||
870 | struct _arg_GO { | |
871 | u8 chan; | |
872 | u32 addr; | |
873 | unsigned ns; | |
874 | }; | |
875 | ||
876 | static inline u32 _emit_GO(unsigned dry_run, u8 buf[], | |
877 | const struct _arg_GO *arg) | |
878 | { | |
879 | u8 chan = arg->chan; | |
880 | u32 addr = arg->addr; | |
881 | unsigned ns = arg->ns; | |
882 | ||
883 | if (dry_run) | |
884 | return SZ_DMAGO; | |
885 | ||
886 | buf[0] = CMD_DMAGO; | |
887 | buf[0] |= (ns << 1); | |
888 | ||
889 | buf[1] = chan & 0x7; | |
890 | ||
3a2307f7 | 891 | *((__le32 *)&buf[2]) = cpu_to_le32(addr); |
b7d861d9 BK |
892 | |
893 | return SZ_DMAGO; | |
894 | } | |
895 | ||
896 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
897 | ||
898 | /* Returns Time-Out */ | |
899 | static bool _until_dmac_idle(struct pl330_thread *thrd) | |
900 | { | |
f6f2421c | 901 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
902 | unsigned long loops = msecs_to_loops(5); |
903 | ||
904 | do { | |
905 | /* Until Manager is Idle */ | |
906 | if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) | |
907 | break; | |
908 | ||
909 | cpu_relax(); | |
910 | } while (--loops); | |
911 | ||
912 | if (!loops) | |
913 | return true; | |
914 | ||
915 | return false; | |
916 | } | |
917 | ||
918 | static inline void _execute_DBGINSN(struct pl330_thread *thrd, | |
919 | u8 insn[], bool as_manager) | |
920 | { | |
f6f2421c | 921 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
922 | u32 val; |
923 | ||
924 | val = (insn[0] << 16) | (insn[1] << 24); | |
925 | if (!as_manager) { | |
926 | val |= (1 << 0); | |
927 | val |= (thrd->id << 8); /* Channel Number */ | |
928 | } | |
929 | writel(val, regs + DBGINST0); | |
930 | ||
3a2307f7 | 931 | val = le32_to_cpu(*((__le32 *)&insn[2])); |
b7d861d9 BK |
932 | writel(val, regs + DBGINST1); |
933 | ||
934 | /* If timed out due to halted state-machine */ | |
935 | if (_until_dmac_idle(thrd)) { | |
f6f2421c | 936 | dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n"); |
b7d861d9 BK |
937 | return; |
938 | } | |
939 | ||
940 | /* Get going */ | |
941 | writel(0, regs + DBGCMD); | |
942 | } | |
943 | ||
b7d861d9 BK |
944 | static inline u32 _state(struct pl330_thread *thrd) |
945 | { | |
f6f2421c | 946 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
947 | u32 val; |
948 | ||
949 | if (is_manager(thrd)) | |
950 | val = readl(regs + DS) & 0xf; | |
951 | else | |
952 | val = readl(regs + CS(thrd->id)) & 0xf; | |
953 | ||
954 | switch (val) { | |
955 | case DS_ST_STOP: | |
956 | return PL330_STATE_STOPPED; | |
957 | case DS_ST_EXEC: | |
958 | return PL330_STATE_EXECUTING; | |
959 | case DS_ST_CMISS: | |
960 | return PL330_STATE_CACHEMISS; | |
961 | case DS_ST_UPDTPC: | |
962 | return PL330_STATE_UPDTPC; | |
963 | case DS_ST_WFE: | |
964 | return PL330_STATE_WFE; | |
965 | case DS_ST_FAULT: | |
966 | return PL330_STATE_FAULTING; | |
967 | case DS_ST_ATBRR: | |
968 | if (is_manager(thrd)) | |
969 | return PL330_STATE_INVALID; | |
970 | else | |
971 | return PL330_STATE_ATBARRIER; | |
972 | case DS_ST_QBUSY: | |
973 | if (is_manager(thrd)) | |
974 | return PL330_STATE_INVALID; | |
975 | else | |
976 | return PL330_STATE_QUEUEBUSY; | |
977 | case DS_ST_WFP: | |
978 | if (is_manager(thrd)) | |
979 | return PL330_STATE_INVALID; | |
980 | else | |
981 | return PL330_STATE_WFP; | |
982 | case DS_ST_KILL: | |
983 | if (is_manager(thrd)) | |
984 | return PL330_STATE_INVALID; | |
985 | else | |
986 | return PL330_STATE_KILLING; | |
987 | case DS_ST_CMPLT: | |
988 | if (is_manager(thrd)) | |
989 | return PL330_STATE_INVALID; | |
990 | else | |
991 | return PL330_STATE_COMPLETING; | |
992 | case DS_ST_FLTCMP: | |
993 | if (is_manager(thrd)) | |
994 | return PL330_STATE_INVALID; | |
995 | else | |
996 | return PL330_STATE_FAULT_COMPLETING; | |
997 | default: | |
998 | return PL330_STATE_INVALID; | |
999 | } | |
1000 | } | |
1001 | ||
1002 | static void _stop(struct pl330_thread *thrd) | |
1003 | { | |
f6f2421c | 1004 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
1005 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; |
1006 | ||
1007 | if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) | |
1008 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
1009 | ||
1010 | /* Return if nothing needs to be done */ | |
1011 | if (_state(thrd) == PL330_STATE_COMPLETING | |
1012 | || _state(thrd) == PL330_STATE_KILLING | |
1013 | || _state(thrd) == PL330_STATE_STOPPED) | |
1014 | return; | |
1015 | ||
1016 | _emit_KILL(0, insn); | |
1017 | ||
1018 | /* Stop generating interrupts for SEV */ | |
1019 | writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); | |
1020 | ||
1021 | _execute_DBGINSN(thrd, insn, is_manager(thrd)); | |
1022 | } | |
1023 | ||
1024 | /* Start doing req 'idx' of thread 'thrd' */ | |
1025 | static bool _trigger(struct pl330_thread *thrd) | |
1026 | { | |
f6f2421c | 1027 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 | 1028 | struct _pl330_req *req; |
9dc5a315 | 1029 | struct dma_pl330_desc *desc; |
b7d861d9 BK |
1030 | struct _arg_GO go; |
1031 | unsigned ns; | |
1032 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; | |
1033 | int idx; | |
1034 | ||
1035 | /* Return if already ACTIVE */ | |
1036 | if (_state(thrd) != PL330_STATE_STOPPED) | |
1037 | return true; | |
1038 | ||
1039 | idx = 1 - thrd->lstenq; | |
8ed30a14 | 1040 | if (thrd->req[idx].desc != NULL) { |
b7d861d9 | 1041 | req = &thrd->req[idx]; |
8ed30a14 | 1042 | } else { |
b7d861d9 | 1043 | idx = thrd->lstenq; |
8ed30a14 | 1044 | if (thrd->req[idx].desc != NULL) |
b7d861d9 BK |
1045 | req = &thrd->req[idx]; |
1046 | else | |
1047 | req = NULL; | |
1048 | } | |
1049 | ||
1050 | /* Return if no request */ | |
8ed30a14 | 1051 | if (!req) |
b7d861d9 BK |
1052 | return true; |
1053 | ||
0091b9d6 AK |
1054 | /* Return if req is running */ |
1055 | if (idx == thrd->req_running) | |
1056 | return true; | |
1057 | ||
9dc5a315 | 1058 | desc = req->desc; |
b7d861d9 | 1059 | |
9dc5a315 | 1060 | ns = desc->rqcfg.nonsecure ? 1 : 0; |
b7d861d9 BK |
1061 | |
1062 | /* See 'Abort Sources' point-4 at Page 2-25 */ | |
1063 | if (_manager_ns(thrd) && !ns) | |
f6f2421c | 1064 | dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n", |
b7d861d9 BK |
1065 | __func__, __LINE__); |
1066 | ||
1067 | go.chan = thrd->id; | |
1068 | go.addr = req->mc_bus; | |
1069 | go.ns = ns; | |
1070 | _emit_GO(0, insn, &go); | |
1071 | ||
1072 | /* Set to generate interrupts for SEV */ | |
1073 | writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); | |
1074 | ||
1075 | /* Only manager can execute GO */ | |
1076 | _execute_DBGINSN(thrd, insn, true); | |
1077 | ||
1078 | thrd->req_running = idx; | |
1079 | ||
1080 | return true; | |
1081 | } | |
1082 | ||
1083 | static bool _start(struct pl330_thread *thrd) | |
1084 | { | |
1085 | switch (_state(thrd)) { | |
1086 | case PL330_STATE_FAULT_COMPLETING: | |
1087 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
1088 | ||
1089 | if (_state(thrd) == PL330_STATE_KILLING) | |
1090 | UNTIL(thrd, PL330_STATE_STOPPED) | |
1091 | ||
1092 | case PL330_STATE_FAULTING: | |
1093 | _stop(thrd); | |
1094 | ||
1095 | case PL330_STATE_KILLING: | |
1096 | case PL330_STATE_COMPLETING: | |
1097 | UNTIL(thrd, PL330_STATE_STOPPED) | |
1098 | ||
1099 | case PL330_STATE_STOPPED: | |
1100 | return _trigger(thrd); | |
1101 | ||
1102 | case PL330_STATE_WFP: | |
1103 | case PL330_STATE_QUEUEBUSY: | |
1104 | case PL330_STATE_ATBARRIER: | |
1105 | case PL330_STATE_UPDTPC: | |
1106 | case PL330_STATE_CACHEMISS: | |
1107 | case PL330_STATE_EXECUTING: | |
1108 | return true; | |
1109 | ||
1110 | case PL330_STATE_WFE: /* For RESUME, nothing yet */ | |
1111 | default: | |
1112 | return false; | |
1113 | } | |
1114 | } | |
1115 | ||
1116 | static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], | |
1117 | const struct _xfer_spec *pxs, int cyc) | |
1118 | { | |
1119 | int off = 0; | |
9dc5a315 | 1120 | struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg; |
b7d861d9 | 1121 | |
3ecf51a4 BK |
1122 | /* check lock-up free version */ |
1123 | if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { | |
1124 | while (cyc--) { | |
1125 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1126 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1127 | } | |
1128 | } else { | |
1129 | while (cyc--) { | |
1130 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1131 | off += _emit_RMB(dry_run, &buf[off]); | |
1132 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1133 | off += _emit_WMB(dry_run, &buf[off]); | |
1134 | } | |
b7d861d9 BK |
1135 | } |
1136 | ||
1137 | return off; | |
1138 | } | |
1139 | ||
1140 | static inline int _ldst_devtomem(unsigned dry_run, u8 buf[], | |
1141 | const struct _xfer_spec *pxs, int cyc) | |
1142 | { | |
1143 | int off = 0; | |
1144 | ||
1145 | while (cyc--) { | |
9dc5a315 LPC |
1146 | off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri); |
1147 | off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->desc->peri); | |
b7d861d9 | 1148 | off += _emit_ST(dry_run, &buf[off], ALWAYS); |
9dc5a315 | 1149 | off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri); |
b7d861d9 BK |
1150 | } |
1151 | ||
1152 | return off; | |
1153 | } | |
1154 | ||
1155 | static inline int _ldst_memtodev(unsigned dry_run, u8 buf[], | |
1156 | const struct _xfer_spec *pxs, int cyc) | |
1157 | { | |
1158 | int off = 0; | |
1159 | ||
1160 | while (cyc--) { | |
9dc5a315 | 1161 | off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri); |
b7d861d9 | 1162 | off += _emit_LD(dry_run, &buf[off], ALWAYS); |
9dc5a315 LPC |
1163 | off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->desc->peri); |
1164 | off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri); | |
b7d861d9 BK |
1165 | } |
1166 | ||
1167 | return off; | |
1168 | } | |
1169 | ||
1170 | static int _bursts(unsigned dry_run, u8 buf[], | |
1171 | const struct _xfer_spec *pxs, int cyc) | |
1172 | { | |
1173 | int off = 0; | |
1174 | ||
9dc5a315 | 1175 | switch (pxs->desc->rqtype) { |
585a9d0b | 1176 | case DMA_MEM_TO_DEV: |
b7d861d9 BK |
1177 | off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc); |
1178 | break; | |
585a9d0b | 1179 | case DMA_DEV_TO_MEM: |
b7d861d9 BK |
1180 | off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc); |
1181 | break; | |
585a9d0b | 1182 | case DMA_MEM_TO_MEM: |
b7d861d9 BK |
1183 | off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); |
1184 | break; | |
1185 | default: | |
1186 | off += 0x40000000; /* Scare off the Client */ | |
1187 | break; | |
1188 | } | |
1189 | ||
1190 | return off; | |
1191 | } | |
1192 | ||
1193 | /* Returns bytes consumed and updates bursts */ | |
1194 | static inline int _loop(unsigned dry_run, u8 buf[], | |
1195 | unsigned long *bursts, const struct _xfer_spec *pxs) | |
1196 | { | |
1197 | int cyc, cycmax, szlp, szlpend, szbrst, off; | |
1198 | unsigned lcnt0, lcnt1, ljmp0, ljmp1; | |
1199 | struct _arg_LPEND lpend; | |
1200 | ||
1201 | /* Max iterations possible in DMALP is 256 */ | |
1202 | if (*bursts >= 256*256) { | |
1203 | lcnt1 = 256; | |
1204 | lcnt0 = 256; | |
1205 | cyc = *bursts / lcnt1 / lcnt0; | |
1206 | } else if (*bursts > 256) { | |
1207 | lcnt1 = 256; | |
1208 | lcnt0 = *bursts / lcnt1; | |
1209 | cyc = 1; | |
1210 | } else { | |
1211 | lcnt1 = *bursts; | |
1212 | lcnt0 = 0; | |
1213 | cyc = 1; | |
1214 | } | |
1215 | ||
1216 | szlp = _emit_LP(1, buf, 0, 0); | |
1217 | szbrst = _bursts(1, buf, pxs, 1); | |
1218 | ||
1219 | lpend.cond = ALWAYS; | |
1220 | lpend.forever = false; | |
1221 | lpend.loop = 0; | |
1222 | lpend.bjump = 0; | |
1223 | szlpend = _emit_LPEND(1, buf, &lpend); | |
1224 | ||
1225 | if (lcnt0) { | |
1226 | szlp *= 2; | |
1227 | szlpend *= 2; | |
1228 | } | |
1229 | ||
1230 | /* | |
1231 | * Max bursts that we can unroll due to limit on the | |
1232 | * size of backward jump that can be encoded in DMALPEND | |
1233 | * which is 8-bits and hence 255 | |
1234 | */ | |
1235 | cycmax = (255 - (szlp + szlpend)) / szbrst; | |
1236 | ||
1237 | cyc = (cycmax < cyc) ? cycmax : cyc; | |
1238 | ||
1239 | off = 0; | |
1240 | ||
1241 | if (lcnt0) { | |
1242 | off += _emit_LP(dry_run, &buf[off], 0, lcnt0); | |
1243 | ljmp0 = off; | |
1244 | } | |
1245 | ||
1246 | off += _emit_LP(dry_run, &buf[off], 1, lcnt1); | |
1247 | ljmp1 = off; | |
1248 | ||
1249 | off += _bursts(dry_run, &buf[off], pxs, cyc); | |
1250 | ||
1251 | lpend.cond = ALWAYS; | |
1252 | lpend.forever = false; | |
1253 | lpend.loop = 1; | |
1254 | lpend.bjump = off - ljmp1; | |
1255 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1256 | ||
1257 | if (lcnt0) { | |
1258 | lpend.cond = ALWAYS; | |
1259 | lpend.forever = false; | |
1260 | lpend.loop = 0; | |
1261 | lpend.bjump = off - ljmp0; | |
1262 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1263 | } | |
1264 | ||
1265 | *bursts = lcnt1 * cyc; | |
1266 | if (lcnt0) | |
1267 | *bursts *= lcnt0; | |
1268 | ||
1269 | return off; | |
1270 | } | |
1271 | ||
1272 | static inline int _setup_loops(unsigned dry_run, u8 buf[], | |
1273 | const struct _xfer_spec *pxs) | |
1274 | { | |
9dc5a315 | 1275 | struct pl330_xfer *x = &pxs->desc->px; |
b7d861d9 BK |
1276 | u32 ccr = pxs->ccr; |
1277 | unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); | |
1278 | int off = 0; | |
1279 | ||
1280 | while (bursts) { | |
1281 | c = bursts; | |
1282 | off += _loop(dry_run, &buf[off], &c, pxs); | |
1283 | bursts -= c; | |
1284 | } | |
1285 | ||
1286 | return off; | |
1287 | } | |
1288 | ||
1289 | static inline int _setup_xfer(unsigned dry_run, u8 buf[], | |
1290 | const struct _xfer_spec *pxs) | |
1291 | { | |
9dc5a315 | 1292 | struct pl330_xfer *x = &pxs->desc->px; |
b7d861d9 BK |
1293 | int off = 0; |
1294 | ||
1295 | /* DMAMOV SAR, x->src_addr */ | |
1296 | off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); | |
1297 | /* DMAMOV DAR, x->dst_addr */ | |
1298 | off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); | |
1299 | ||
1300 | /* Setup Loop(s) */ | |
1301 | off += _setup_loops(dry_run, &buf[off], pxs); | |
1302 | ||
1303 | return off; | |
1304 | } | |
1305 | ||
1306 | /* | |
1307 | * A req is a sequence of one or more xfer units. | |
1308 | * Returns the number of bytes taken to setup the MC for the req. | |
1309 | */ | |
1310 | static int _setup_req(unsigned dry_run, struct pl330_thread *thrd, | |
1311 | unsigned index, struct _xfer_spec *pxs) | |
1312 | { | |
1313 | struct _pl330_req *req = &thrd->req[index]; | |
1314 | struct pl330_xfer *x; | |
1315 | u8 *buf = req->mc_cpu; | |
1316 | int off = 0; | |
1317 | ||
1318 | PL330_DBGMC_START(req->mc_bus); | |
1319 | ||
1320 | /* DMAMOV CCR, ccr */ | |
1321 | off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); | |
1322 | ||
9dc5a315 | 1323 | x = &pxs->desc->px; |
d5cef121 LPC |
1324 | /* Error if xfer length is not aligned at burst size */ |
1325 | if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr))) | |
1326 | return -EINVAL; | |
b7d861d9 | 1327 | |
d5cef121 | 1328 | off += _setup_xfer(dry_run, &buf[off], pxs); |
b7d861d9 BK |
1329 | |
1330 | /* DMASEV peripheral/event */ | |
1331 | off += _emit_SEV(dry_run, &buf[off], thrd->ev); | |
1332 | /* DMAEND */ | |
1333 | off += _emit_END(dry_run, &buf[off]); | |
1334 | ||
1335 | return off; | |
1336 | } | |
1337 | ||
1338 | static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) | |
1339 | { | |
1340 | u32 ccr = 0; | |
1341 | ||
1342 | if (rqc->src_inc) | |
1343 | ccr |= CC_SRCINC; | |
1344 | ||
1345 | if (rqc->dst_inc) | |
1346 | ccr |= CC_DSTINC; | |
1347 | ||
1348 | /* We set same protection levels for Src and DST for now */ | |
1349 | if (rqc->privileged) | |
1350 | ccr |= CC_SRCPRI | CC_DSTPRI; | |
1351 | if (rqc->nonsecure) | |
1352 | ccr |= CC_SRCNS | CC_DSTNS; | |
1353 | if (rqc->insnaccess) | |
1354 | ccr |= CC_SRCIA | CC_DSTIA; | |
1355 | ||
1356 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); | |
1357 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); | |
1358 | ||
1359 | ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); | |
1360 | ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); | |
1361 | ||
1362 | ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); | |
1363 | ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); | |
1364 | ||
1365 | ccr |= (rqc->swap << CC_SWAP_SHFT); | |
1366 | ||
1367 | return ccr; | |
1368 | } | |
1369 | ||
b7d861d9 BK |
1370 | /* |
1371 | * Submit a list of xfers after which the client wants notification. | |
1372 | * Client is not notified after each xfer unit, just once after all | |
1373 | * xfer units are done or some error occurs. | |
1374 | */ | |
9dc5a315 LPC |
1375 | static int pl330_submit_req(struct pl330_thread *thrd, |
1376 | struct dma_pl330_desc *desc) | |
b7d861d9 | 1377 | { |
f6f2421c | 1378 | struct pl330_dmac *pl330 = thrd->dmac; |
b7d861d9 BK |
1379 | struct _xfer_spec xs; |
1380 | unsigned long flags; | |
b7d861d9 BK |
1381 | unsigned idx; |
1382 | u32 ccr; | |
1383 | int ret = 0; | |
1384 | ||
b7d861d9 BK |
1385 | if (pl330->state == DYING |
1386 | || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { | |
f6f2421c | 1387 | dev_info(thrd->dmac->ddma.dev, "%s:%d\n", |
b7d861d9 BK |
1388 | __func__, __LINE__); |
1389 | return -EAGAIN; | |
1390 | } | |
1391 | ||
1392 | /* If request for non-existing peripheral */ | |
9dc5a315 LPC |
1393 | if (desc->rqtype != DMA_MEM_TO_MEM && |
1394 | desc->peri >= pl330->pcfg.num_peri) { | |
f6f2421c | 1395 | dev_info(thrd->dmac->ddma.dev, |
b7d861d9 | 1396 | "%s:%d Invalid peripheral(%u)!\n", |
9dc5a315 | 1397 | __func__, __LINE__, desc->peri); |
b7d861d9 BK |
1398 | return -EINVAL; |
1399 | } | |
1400 | ||
1401 | spin_lock_irqsave(&pl330->lock, flags); | |
1402 | ||
1403 | if (_queue_full(thrd)) { | |
1404 | ret = -EAGAIN; | |
1405 | goto xfer_exit; | |
1406 | } | |
1407 | ||
9dc5a315 LPC |
1408 | /* Prefer Secure Channel */ |
1409 | if (!_manager_ns(thrd)) | |
1410 | desc->rqcfg.nonsecure = 0; | |
1411 | else | |
1412 | desc->rqcfg.nonsecure = 1; | |
b7d861d9 | 1413 | |
9dc5a315 | 1414 | ccr = _prepare_ccr(&desc->rqcfg); |
b7d861d9 | 1415 | |
8ed30a14 | 1416 | idx = thrd->req[0].desc == NULL ? 0 : 1; |
b7d861d9 BK |
1417 | |
1418 | xs.ccr = ccr; | |
9dc5a315 | 1419 | xs.desc = desc; |
b7d861d9 BK |
1420 | |
1421 | /* First dry run to check if req is acceptable */ | |
1422 | ret = _setup_req(1, thrd, idx, &xs); | |
1423 | if (ret < 0) | |
1424 | goto xfer_exit; | |
1425 | ||
f6f2421c LPC |
1426 | if (ret > pl330->mcbufsz / 2) { |
1427 | dev_info(pl330->ddma.dev, "%s:%d Trying increasing mcbufsz\n", | |
b7d861d9 BK |
1428 | __func__, __LINE__); |
1429 | ret = -ENOMEM; | |
1430 | goto xfer_exit; | |
1431 | } | |
1432 | ||
1433 | /* Hook the request */ | |
1434 | thrd->lstenq = idx; | |
9dc5a315 | 1435 | thrd->req[idx].desc = desc; |
be025329 | 1436 | _setup_req(0, thrd, idx, &xs); |
b7d861d9 BK |
1437 | |
1438 | ret = 0; | |
1439 | ||
1440 | xfer_exit: | |
1441 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1442 | ||
1443 | return ret; | |
1444 | } | |
1445 | ||
9dc5a315 | 1446 | static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err) |
6079d38c | 1447 | { |
b1e51d77 | 1448 | struct dma_pl330_chan *pch; |
6079d38c LPC |
1449 | unsigned long flags; |
1450 | ||
b1e51d77 JMC |
1451 | if (!desc) |
1452 | return; | |
1453 | ||
1454 | pch = desc->pchan; | |
1455 | ||
6079d38c LPC |
1456 | /* If desc aborted */ |
1457 | if (!pch) | |
1458 | return; | |
1459 | ||
1460 | spin_lock_irqsave(&pch->lock, flags); | |
1461 | ||
1462 | desc->status = DONE; | |
1463 | ||
1464 | spin_unlock_irqrestore(&pch->lock, flags); | |
1465 | ||
1466 | tasklet_schedule(&pch->task); | |
1467 | } | |
1468 | ||
b7d861d9 BK |
1469 | static void pl330_dotask(unsigned long data) |
1470 | { | |
1471 | struct pl330_dmac *pl330 = (struct pl330_dmac *) data; | |
b7d861d9 BK |
1472 | unsigned long flags; |
1473 | int i; | |
1474 | ||
1475 | spin_lock_irqsave(&pl330->lock, flags); | |
1476 | ||
1477 | /* The DMAC itself gone nuts */ | |
1478 | if (pl330->dmac_tbd.reset_dmac) { | |
1479 | pl330->state = DYING; | |
1480 | /* Reset the manager too */ | |
1481 | pl330->dmac_tbd.reset_mngr = true; | |
1482 | /* Clear the reset flag */ | |
1483 | pl330->dmac_tbd.reset_dmac = false; | |
1484 | } | |
1485 | ||
1486 | if (pl330->dmac_tbd.reset_mngr) { | |
1487 | _stop(pl330->manager); | |
1488 | /* Reset all channels */ | |
f6f2421c | 1489 | pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1; |
b7d861d9 BK |
1490 | /* Clear the reset flag */ |
1491 | pl330->dmac_tbd.reset_mngr = false; | |
1492 | } | |
1493 | ||
f6f2421c | 1494 | for (i = 0; i < pl330->pcfg.num_chan; i++) { |
b7d861d9 BK |
1495 | |
1496 | if (pl330->dmac_tbd.reset_chan & (1 << i)) { | |
1497 | struct pl330_thread *thrd = &pl330->channels[i]; | |
f6f2421c | 1498 | void __iomem *regs = pl330->base; |
b7d861d9 BK |
1499 | enum pl330_op_err err; |
1500 | ||
1501 | _stop(thrd); | |
1502 | ||
1503 | if (readl(regs + FSC) & (1 << thrd->id)) | |
1504 | err = PL330_ERR_FAIL; | |
1505 | else | |
1506 | err = PL330_ERR_ABORT; | |
1507 | ||
1508 | spin_unlock_irqrestore(&pl330->lock, flags); | |
9dc5a315 LPC |
1509 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err); |
1510 | dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err); | |
b7d861d9 BK |
1511 | spin_lock_irqsave(&pl330->lock, flags); |
1512 | ||
9dc5a315 LPC |
1513 | thrd->req[0].desc = NULL; |
1514 | thrd->req[1].desc = NULL; | |
8ed30a14 | 1515 | thrd->req_running = -1; |
b7d861d9 BK |
1516 | |
1517 | /* Clear the reset flag */ | |
1518 | pl330->dmac_tbd.reset_chan &= ~(1 << i); | |
1519 | } | |
1520 | } | |
1521 | ||
1522 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1523 | ||
1524 | return; | |
1525 | } | |
1526 | ||
1527 | /* Returns 1 if state was updated, 0 otherwise */ | |
f6f2421c | 1528 | static int pl330_update(struct pl330_dmac *pl330) |
b7d861d9 | 1529 | { |
9dc5a315 | 1530 | struct dma_pl330_desc *descdone, *tmp; |
b7d861d9 BK |
1531 | unsigned long flags; |
1532 | void __iomem *regs; | |
1533 | u32 val; | |
1534 | int id, ev, ret = 0; | |
1535 | ||
f6f2421c | 1536 | regs = pl330->base; |
b7d861d9 BK |
1537 | |
1538 | spin_lock_irqsave(&pl330->lock, flags); | |
1539 | ||
1540 | val = readl(regs + FSM) & 0x1; | |
1541 | if (val) | |
1542 | pl330->dmac_tbd.reset_mngr = true; | |
1543 | else | |
1544 | pl330->dmac_tbd.reset_mngr = false; | |
1545 | ||
f6f2421c | 1546 | val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1); |
b7d861d9 BK |
1547 | pl330->dmac_tbd.reset_chan |= val; |
1548 | if (val) { | |
1549 | int i = 0; | |
f6f2421c | 1550 | while (i < pl330->pcfg.num_chan) { |
b7d861d9 | 1551 | if (val & (1 << i)) { |
f6f2421c | 1552 | dev_info(pl330->ddma.dev, |
b7d861d9 BK |
1553 | "Reset Channel-%d\t CS-%x FTC-%x\n", |
1554 | i, readl(regs + CS(i)), | |
1555 | readl(regs + FTC(i))); | |
1556 | _stop(&pl330->channels[i]); | |
1557 | } | |
1558 | i++; | |
1559 | } | |
1560 | } | |
1561 | ||
1562 | /* Check which event happened i.e, thread notified */ | |
1563 | val = readl(regs + ES); | |
f6f2421c LPC |
1564 | if (pl330->pcfg.num_events < 32 |
1565 | && val & ~((1 << pl330->pcfg.num_events) - 1)) { | |
b7d861d9 | 1566 | pl330->dmac_tbd.reset_dmac = true; |
f6f2421c LPC |
1567 | dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__, |
1568 | __LINE__); | |
b7d861d9 BK |
1569 | ret = 1; |
1570 | goto updt_exit; | |
1571 | } | |
1572 | ||
f6f2421c | 1573 | for (ev = 0; ev < pl330->pcfg.num_events; ev++) { |
b7d861d9 BK |
1574 | if (val & (1 << ev)) { /* Event occurred */ |
1575 | struct pl330_thread *thrd; | |
1576 | u32 inten = readl(regs + INTEN); | |
1577 | int active; | |
1578 | ||
1579 | /* Clear the event */ | |
1580 | if (inten & (1 << ev)) | |
1581 | writel(1 << ev, regs + INTCLR); | |
1582 | ||
1583 | ret = 1; | |
1584 | ||
1585 | id = pl330->events[ev]; | |
1586 | ||
1587 | thrd = &pl330->channels[id]; | |
1588 | ||
1589 | active = thrd->req_running; | |
1590 | if (active == -1) /* Aborted */ | |
1591 | continue; | |
1592 | ||
fdec53d5 | 1593 | /* Detach the req */ |
9dc5a315 LPC |
1594 | descdone = thrd->req[active].desc; |
1595 | thrd->req[active].desc = NULL; | |
fdec53d5 | 1596 | |
0091b9d6 AK |
1597 | thrd->req_running = -1; |
1598 | ||
b7d861d9 BK |
1599 | /* Get going again ASAP */ |
1600 | _start(thrd); | |
1601 | ||
1602 | /* For now, just make a list of callbacks to be done */ | |
9dc5a315 | 1603 | list_add_tail(&descdone->rqd, &pl330->req_done); |
b7d861d9 BK |
1604 | } |
1605 | } | |
1606 | ||
1607 | /* Now that we are in no hurry, do the callbacks */ | |
9dc5a315 LPC |
1608 | list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) { |
1609 | list_del(&descdone->rqd); | |
b7d861d9 | 1610 | spin_unlock_irqrestore(&pl330->lock, flags); |
9dc5a315 | 1611 | dma_pl330_rqcb(descdone, PL330_ERR_NONE); |
b7d861d9 BK |
1612 | spin_lock_irqsave(&pl330->lock, flags); |
1613 | } | |
1614 | ||
1615 | updt_exit: | |
1616 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1617 | ||
1618 | if (pl330->dmac_tbd.reset_dmac | |
1619 | || pl330->dmac_tbd.reset_mngr | |
1620 | || pl330->dmac_tbd.reset_chan) { | |
1621 | ret = 1; | |
1622 | tasklet_schedule(&pl330->tasks); | |
1623 | } | |
1624 | ||
1625 | return ret; | |
1626 | } | |
1627 | ||
b7d861d9 BK |
1628 | /* Reserve an event */ |
1629 | static inline int _alloc_event(struct pl330_thread *thrd) | |
1630 | { | |
1631 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1632 | int ev; |
1633 | ||
f6f2421c | 1634 | for (ev = 0; ev < pl330->pcfg.num_events; ev++) |
b7d861d9 BK |
1635 | if (pl330->events[ev] == -1) { |
1636 | pl330->events[ev] = thrd->id; | |
1637 | return ev; | |
1638 | } | |
1639 | ||
1640 | return -1; | |
1641 | } | |
1642 | ||
f6f2421c | 1643 | static bool _chan_ns(const struct pl330_dmac *pl330, int i) |
b7d861d9 | 1644 | { |
f6f2421c | 1645 | return pl330->pcfg.irq_ns & (1 << i); |
b7d861d9 BK |
1646 | } |
1647 | ||
1648 | /* Upon success, returns IdentityToken for the | |
1649 | * allocated channel, NULL otherwise. | |
1650 | */ | |
f6f2421c | 1651 | static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330) |
b7d861d9 BK |
1652 | { |
1653 | struct pl330_thread *thrd = NULL; | |
b7d861d9 BK |
1654 | unsigned long flags; |
1655 | int chans, i; | |
1656 | ||
b7d861d9 BK |
1657 | if (pl330->state == DYING) |
1658 | return NULL; | |
1659 | ||
f6f2421c | 1660 | chans = pl330->pcfg.num_chan; |
b7d861d9 BK |
1661 | |
1662 | spin_lock_irqsave(&pl330->lock, flags); | |
1663 | ||
1664 | for (i = 0; i < chans; i++) { | |
1665 | thrd = &pl330->channels[i]; | |
1666 | if ((thrd->free) && (!_manager_ns(thrd) || | |
f6f2421c | 1667 | _chan_ns(pl330, i))) { |
b7d861d9 BK |
1668 | thrd->ev = _alloc_event(thrd); |
1669 | if (thrd->ev >= 0) { | |
1670 | thrd->free = false; | |
1671 | thrd->lstenq = 1; | |
9dc5a315 | 1672 | thrd->req[0].desc = NULL; |
9dc5a315 | 1673 | thrd->req[1].desc = NULL; |
8ed30a14 | 1674 | thrd->req_running = -1; |
b7d861d9 BK |
1675 | break; |
1676 | } | |
1677 | } | |
1678 | thrd = NULL; | |
1679 | } | |
1680 | ||
1681 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1682 | ||
1683 | return thrd; | |
1684 | } | |
1685 | ||
1686 | /* Release an event */ | |
1687 | static inline void _free_event(struct pl330_thread *thrd, int ev) | |
1688 | { | |
1689 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1690 | |
1691 | /* If the event is valid and was held by the thread */ | |
f6f2421c | 1692 | if (ev >= 0 && ev < pl330->pcfg.num_events |
b7d861d9 BK |
1693 | && pl330->events[ev] == thrd->id) |
1694 | pl330->events[ev] = -1; | |
1695 | } | |
1696 | ||
65ad6060 | 1697 | static void pl330_release_channel(struct pl330_thread *thrd) |
b7d861d9 | 1698 | { |
b7d861d9 BK |
1699 | struct pl330_dmac *pl330; |
1700 | unsigned long flags; | |
1701 | ||
1702 | if (!thrd || thrd->free) | |
1703 | return; | |
1704 | ||
1705 | _stop(thrd); | |
1706 | ||
9dc5a315 LPC |
1707 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT); |
1708 | dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT); | |
b7d861d9 BK |
1709 | |
1710 | pl330 = thrd->dmac; | |
1711 | ||
1712 | spin_lock_irqsave(&pl330->lock, flags); | |
1713 | _free_event(thrd, thrd->ev); | |
1714 | thrd->free = true; | |
1715 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1716 | } | |
1717 | ||
1718 | /* Initialize the structure for PL330 configuration, that can be used | |
1719 | * by the client driver the make best use of the DMAC | |
1720 | */ | |
f6f2421c | 1721 | static void read_dmac_config(struct pl330_dmac *pl330) |
b7d861d9 | 1722 | { |
f6f2421c | 1723 | void __iomem *regs = pl330->base; |
b7d861d9 BK |
1724 | u32 val; |
1725 | ||
1726 | val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; | |
1727 | val &= CRD_DATA_WIDTH_MASK; | |
f6f2421c | 1728 | pl330->pcfg.data_bus_width = 8 * (1 << val); |
b7d861d9 BK |
1729 | |
1730 | val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; | |
1731 | val &= CRD_DATA_BUFF_MASK; | |
f6f2421c | 1732 | pl330->pcfg.data_buf_dep = val + 1; |
b7d861d9 BK |
1733 | |
1734 | val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; | |
1735 | val &= CR0_NUM_CHANS_MASK; | |
1736 | val += 1; | |
f6f2421c | 1737 | pl330->pcfg.num_chan = val; |
b7d861d9 BK |
1738 | |
1739 | val = readl(regs + CR0); | |
1740 | if (val & CR0_PERIPH_REQ_SET) { | |
1741 | val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; | |
1742 | val += 1; | |
f6f2421c LPC |
1743 | pl330->pcfg.num_peri = val; |
1744 | pl330->pcfg.peri_ns = readl(regs + CR4); | |
b7d861d9 | 1745 | } else { |
f6f2421c | 1746 | pl330->pcfg.num_peri = 0; |
b7d861d9 BK |
1747 | } |
1748 | ||
1749 | val = readl(regs + CR0); | |
1750 | if (val & CR0_BOOT_MAN_NS) | |
f6f2421c | 1751 | pl330->pcfg.mode |= DMAC_MODE_NS; |
b7d861d9 | 1752 | else |
f6f2421c | 1753 | pl330->pcfg.mode &= ~DMAC_MODE_NS; |
b7d861d9 BK |
1754 | |
1755 | val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; | |
1756 | val &= CR0_NUM_EVENTS_MASK; | |
1757 | val += 1; | |
f6f2421c | 1758 | pl330->pcfg.num_events = val; |
b7d861d9 | 1759 | |
f6f2421c | 1760 | pl330->pcfg.irq_ns = readl(regs + CR3); |
b7d861d9 BK |
1761 | } |
1762 | ||
1763 | static inline void _reset_thread(struct pl330_thread *thrd) | |
1764 | { | |
1765 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1766 | |
1767 | thrd->req[0].mc_cpu = pl330->mcode_cpu | |
f6f2421c | 1768 | + (thrd->id * pl330->mcbufsz); |
b7d861d9 | 1769 | thrd->req[0].mc_bus = pl330->mcode_bus |
f6f2421c | 1770 | + (thrd->id * pl330->mcbufsz); |
9dc5a315 | 1771 | thrd->req[0].desc = NULL; |
b7d861d9 BK |
1772 | |
1773 | thrd->req[1].mc_cpu = thrd->req[0].mc_cpu | |
f6f2421c | 1774 | + pl330->mcbufsz / 2; |
b7d861d9 | 1775 | thrd->req[1].mc_bus = thrd->req[0].mc_bus |
f6f2421c | 1776 | + pl330->mcbufsz / 2; |
9dc5a315 | 1777 | thrd->req[1].desc = NULL; |
8ed30a14 LPC |
1778 | |
1779 | thrd->req_running = -1; | |
b7d861d9 BK |
1780 | } |
1781 | ||
1782 | static int dmac_alloc_threads(struct pl330_dmac *pl330) | |
1783 | { | |
f6f2421c | 1784 | int chans = pl330->pcfg.num_chan; |
b7d861d9 BK |
1785 | struct pl330_thread *thrd; |
1786 | int i; | |
1787 | ||
1788 | /* Allocate 1 Manager and 'chans' Channel threads */ | |
1789 | pl330->channels = kzalloc((1 + chans) * sizeof(*thrd), | |
1790 | GFP_KERNEL); | |
1791 | if (!pl330->channels) | |
1792 | return -ENOMEM; | |
1793 | ||
1794 | /* Init Channel threads */ | |
1795 | for (i = 0; i < chans; i++) { | |
1796 | thrd = &pl330->channels[i]; | |
1797 | thrd->id = i; | |
1798 | thrd->dmac = pl330; | |
1799 | _reset_thread(thrd); | |
1800 | thrd->free = true; | |
1801 | } | |
1802 | ||
1803 | /* MANAGER is indexed at the end */ | |
1804 | thrd = &pl330->channels[chans]; | |
1805 | thrd->id = chans; | |
1806 | thrd->dmac = pl330; | |
1807 | thrd->free = false; | |
1808 | pl330->manager = thrd; | |
1809 | ||
1810 | return 0; | |
1811 | } | |
1812 | ||
1813 | static int dmac_alloc_resources(struct pl330_dmac *pl330) | |
1814 | { | |
f6f2421c | 1815 | int chans = pl330->pcfg.num_chan; |
b7d861d9 | 1816 | int ret; |
b3040e40 | 1817 | |
b3040e40 | 1818 | /* |
b7d861d9 BK |
1819 | * Alloc MicroCode buffer for 'chans' Channel threads. |
1820 | * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) | |
b3040e40 | 1821 | */ |
f6f2421c LPC |
1822 | pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev, |
1823 | chans * pl330->mcbufsz, | |
b7d861d9 BK |
1824 | &pl330->mcode_bus, GFP_KERNEL); |
1825 | if (!pl330->mcode_cpu) { | |
f6f2421c | 1826 | dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n", |
b7d861d9 BK |
1827 | __func__, __LINE__); |
1828 | return -ENOMEM; | |
1829 | } | |
1830 | ||
1831 | ret = dmac_alloc_threads(pl330); | |
1832 | if (ret) { | |
f6f2421c | 1833 | dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n", |
b7d861d9 | 1834 | __func__, __LINE__); |
f6f2421c LPC |
1835 | dma_free_coherent(pl330->ddma.dev, |
1836 | chans * pl330->mcbufsz, | |
b7d861d9 BK |
1837 | pl330->mcode_cpu, pl330->mcode_bus); |
1838 | return ret; | |
1839 | } | |
1840 | ||
1841 | return 0; | |
1842 | } | |
1843 | ||
f6f2421c | 1844 | static int pl330_add(struct pl330_dmac *pl330) |
b7d861d9 | 1845 | { |
b7d861d9 BK |
1846 | void __iomem *regs; |
1847 | int i, ret; | |
1848 | ||
f6f2421c | 1849 | regs = pl330->base; |
b3040e40 | 1850 | |
b7d861d9 | 1851 | /* Check if we can handle this DMAC */ |
f6f2421c LPC |
1852 | if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { |
1853 | dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n", | |
1854 | pl330->pcfg.periph_id); | |
b7d861d9 BK |
1855 | return -EINVAL; |
1856 | } | |
b3040e40 | 1857 | |
b7d861d9 | 1858 | /* Read the configuration of the DMAC */ |
f6f2421c | 1859 | read_dmac_config(pl330); |
b3040e40 | 1860 | |
f6f2421c LPC |
1861 | if (pl330->pcfg.num_events == 0) { |
1862 | dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n", | |
b7d861d9 BK |
1863 | __func__, __LINE__); |
1864 | return -EINVAL; | |
1865 | } | |
b3040e40 | 1866 | |
b7d861d9 | 1867 | spin_lock_init(&pl330->lock); |
1b9bb715 | 1868 | |
b7d861d9 | 1869 | INIT_LIST_HEAD(&pl330->req_done); |
42bc9cf4 | 1870 | |
b7d861d9 | 1871 | /* Use default MC buffer size if not provided */ |
f6f2421c LPC |
1872 | if (!pl330->mcbufsz) |
1873 | pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2; | |
b3040e40 | 1874 | |
b7d861d9 | 1875 | /* Mark all events as free */ |
f6f2421c | 1876 | for (i = 0; i < pl330->pcfg.num_events; i++) |
b7d861d9 | 1877 | pl330->events[i] = -1; |
b3040e40 | 1878 | |
b7d861d9 BK |
1879 | /* Allocate resources needed by the DMAC */ |
1880 | ret = dmac_alloc_resources(pl330); | |
1881 | if (ret) { | |
f6f2421c | 1882 | dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n"); |
b7d861d9 BK |
1883 | return ret; |
1884 | } | |
b3040e40 | 1885 | |
b7d861d9 | 1886 | tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); |
b3040e40 | 1887 | |
b7d861d9 | 1888 | pl330->state = INIT; |
a2f5203f | 1889 | |
b7d861d9 BK |
1890 | return 0; |
1891 | } | |
b3040e40 | 1892 | |
b7d861d9 BK |
1893 | static int dmac_free_threads(struct pl330_dmac *pl330) |
1894 | { | |
b7d861d9 BK |
1895 | struct pl330_thread *thrd; |
1896 | int i; | |
b3040e40 | 1897 | |
b7d861d9 | 1898 | /* Release Channel threads */ |
f6f2421c | 1899 | for (i = 0; i < pl330->pcfg.num_chan; i++) { |
b7d861d9 | 1900 | thrd = &pl330->channels[i]; |
65ad6060 | 1901 | pl330_release_channel(thrd); |
b7d861d9 | 1902 | } |
b3040e40 | 1903 | |
b7d861d9 BK |
1904 | /* Free memory */ |
1905 | kfree(pl330->channels); | |
b3040e40 | 1906 | |
b7d861d9 BK |
1907 | return 0; |
1908 | } | |
b3040e40 | 1909 | |
f6f2421c | 1910 | static void pl330_del(struct pl330_dmac *pl330) |
b7d861d9 | 1911 | { |
b7d861d9 BK |
1912 | pl330->state = UNINIT; |
1913 | ||
1914 | tasklet_kill(&pl330->tasks); | |
1915 | ||
1916 | /* Free DMAC resources */ | |
f6f2421c | 1917 | dmac_free_threads(pl330); |
b7d861d9 | 1918 | |
f6f2421c LPC |
1919 | dma_free_coherent(pl330->ddma.dev, |
1920 | pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu, | |
1921 | pl330->mcode_bus); | |
b7d861d9 | 1922 | } |
b3040e40 | 1923 | |
3e2ec13a TA |
1924 | /* forward declaration */ |
1925 | static struct amba_driver pl330_driver; | |
1926 | ||
b3040e40 JB |
1927 | static inline struct dma_pl330_chan * |
1928 | to_pchan(struct dma_chan *ch) | |
1929 | { | |
1930 | if (!ch) | |
1931 | return NULL; | |
1932 | ||
1933 | return container_of(ch, struct dma_pl330_chan, chan); | |
1934 | } | |
1935 | ||
1936 | static inline struct dma_pl330_desc * | |
1937 | to_desc(struct dma_async_tx_descriptor *tx) | |
1938 | { | |
1939 | return container_of(tx, struct dma_pl330_desc, txd); | |
1940 | } | |
1941 | ||
b3040e40 JB |
1942 | static inline void fill_queue(struct dma_pl330_chan *pch) |
1943 | { | |
1944 | struct dma_pl330_desc *desc; | |
1945 | int ret; | |
1946 | ||
1947 | list_for_each_entry(desc, &pch->work_list, node) { | |
1948 | ||
1949 | /* If already submitted */ | |
1950 | if (desc->status == BUSY) | |
30fb980b | 1951 | continue; |
b3040e40 | 1952 | |
9dc5a315 | 1953 | ret = pl330_submit_req(pch->thread, desc); |
b3040e40 JB |
1954 | if (!ret) { |
1955 | desc->status = BUSY; | |
b3040e40 JB |
1956 | } else if (ret == -EAGAIN) { |
1957 | /* QFull or DMAC Dying */ | |
1958 | break; | |
1959 | } else { | |
1960 | /* Unacceptable request */ | |
1961 | desc->status = DONE; | |
f6f2421c | 1962 | dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", |
b3040e40 JB |
1963 | __func__, __LINE__, desc->txd.cookie); |
1964 | tasklet_schedule(&pch->task); | |
1965 | } | |
1966 | } | |
1967 | } | |
1968 | ||
1969 | static void pl330_tasklet(unsigned long data) | |
1970 | { | |
1971 | struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; | |
1972 | struct dma_pl330_desc *desc, *_dt; | |
1973 | unsigned long flags; | |
ae43b328 | 1974 | bool power_down = false; |
b3040e40 JB |
1975 | |
1976 | spin_lock_irqsave(&pch->lock, flags); | |
1977 | ||
1978 | /* Pick up ripe tomatoes */ | |
1979 | list_for_each_entry_safe(desc, _dt, &pch->work_list, node) | |
1980 | if (desc->status == DONE) { | |
30c1dc0f | 1981 | if (!pch->cyclic) |
eab21585 | 1982 | dma_cookie_complete(&desc->txd); |
39ff8613 | 1983 | list_move_tail(&desc->node, &pch->completed_list); |
b3040e40 JB |
1984 | } |
1985 | ||
1986 | /* Try to submit a req imm. next to the last completed cookie */ | |
1987 | fill_queue(pch); | |
1988 | ||
ae43b328 KK |
1989 | if (list_empty(&pch->work_list)) { |
1990 | spin_lock(&pch->thread->dmac->lock); | |
1991 | _stop(pch->thread); | |
1992 | spin_unlock(&pch->thread->dmac->lock); | |
1993 | power_down = true; | |
1994 | } else { | |
1995 | /* Make sure the PL330 Channel thread is active */ | |
1996 | spin_lock(&pch->thread->dmac->lock); | |
1997 | _start(pch->thread); | |
1998 | spin_unlock(&pch->thread->dmac->lock); | |
1999 | } | |
b3040e40 | 2000 | |
39ff8613 LPC |
2001 | while (!list_empty(&pch->completed_list)) { |
2002 | dma_async_tx_callback callback; | |
2003 | void *callback_param; | |
b3040e40 | 2004 | |
39ff8613 LPC |
2005 | desc = list_first_entry(&pch->completed_list, |
2006 | struct dma_pl330_desc, node); | |
2007 | ||
2008 | callback = desc->txd.callback; | |
2009 | callback_param = desc->txd.callback_param; | |
2010 | ||
2011 | if (pch->cyclic) { | |
2012 | desc->status = PREP; | |
2013 | list_move_tail(&desc->node, &pch->work_list); | |
ae43b328 KK |
2014 | if (power_down) { |
2015 | spin_lock(&pch->thread->dmac->lock); | |
2016 | _start(pch->thread); | |
2017 | spin_unlock(&pch->thread->dmac->lock); | |
2018 | power_down = false; | |
2019 | } | |
39ff8613 LPC |
2020 | } else { |
2021 | desc->status = FREE; | |
2022 | list_move_tail(&desc->node, &pch->dmac->desc_pool); | |
2023 | } | |
2024 | ||
d38a8c62 DW |
2025 | dma_descriptor_unmap(&desc->txd); |
2026 | ||
39ff8613 LPC |
2027 | if (callback) { |
2028 | spin_unlock_irqrestore(&pch->lock, flags); | |
2029 | callback(callback_param); | |
2030 | spin_lock_irqsave(&pch->lock, flags); | |
2031 | } | |
2032 | } | |
2033 | spin_unlock_irqrestore(&pch->lock, flags); | |
ae43b328 KK |
2034 | |
2035 | /* If work list empty, power down */ | |
2036 | if (power_down) { | |
2037 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); | |
2038 | pm_runtime_put_autosuspend(pch->dmac->ddma.dev); | |
2039 | } | |
b3040e40 JB |
2040 | } |
2041 | ||
3e2ec13a TA |
2042 | bool pl330_filter(struct dma_chan *chan, void *param) |
2043 | { | |
cd072515 | 2044 | u8 *peri_id; |
3e2ec13a TA |
2045 | |
2046 | if (chan->device->dev->driver != &pl330_driver.drv) | |
2047 | return false; | |
2048 | ||
cd072515 | 2049 | peri_id = chan->private; |
2f986ec6 | 2050 | return *peri_id == (unsigned long)param; |
3e2ec13a TA |
2051 | } |
2052 | EXPORT_SYMBOL(pl330_filter); | |
2053 | ||
a80258f9 PV |
2054 | static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, |
2055 | struct of_dma *ofdma) | |
2056 | { | |
2057 | int count = dma_spec->args_count; | |
f6f2421c | 2058 | struct pl330_dmac *pl330 = ofdma->of_dma_data; |
70cbb163 | 2059 | unsigned int chan_id; |
a80258f9 | 2060 | |
f6f2421c LPC |
2061 | if (!pl330) |
2062 | return NULL; | |
2063 | ||
a80258f9 PV |
2064 | if (count != 1) |
2065 | return NULL; | |
2066 | ||
70cbb163 | 2067 | chan_id = dma_spec->args[0]; |
f6f2421c | 2068 | if (chan_id >= pl330->num_peripherals) |
70cbb163 | 2069 | return NULL; |
a80258f9 | 2070 | |
f6f2421c | 2071 | return dma_get_slave_channel(&pl330->peripherals[chan_id].chan); |
a80258f9 PV |
2072 | } |
2073 | ||
b3040e40 JB |
2074 | static int pl330_alloc_chan_resources(struct dma_chan *chan) |
2075 | { | |
2076 | struct dma_pl330_chan *pch = to_pchan(chan); | |
f6f2421c | 2077 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2078 | unsigned long flags; |
2079 | ||
2080 | spin_lock_irqsave(&pch->lock, flags); | |
2081 | ||
d3ee98cd | 2082 | dma_cookie_init(chan); |
42bc9cf4 | 2083 | pch->cyclic = false; |
b3040e40 | 2084 | |
f6f2421c | 2085 | pch->thread = pl330_request_channel(pl330); |
65ad6060 | 2086 | if (!pch->thread) { |
b3040e40 | 2087 | spin_unlock_irqrestore(&pch->lock, flags); |
02747885 | 2088 | return -ENOMEM; |
b3040e40 JB |
2089 | } |
2090 | ||
2091 | tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); | |
2092 | ||
2093 | spin_unlock_irqrestore(&pch->lock, flags); | |
2094 | ||
2095 | return 1; | |
2096 | } | |
2097 | ||
740aa957 MR |
2098 | static int pl330_config(struct dma_chan *chan, |
2099 | struct dma_slave_config *slave_config) | |
2100 | { | |
2101 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2102 | ||
2103 | if (slave_config->direction == DMA_MEM_TO_DEV) { | |
2104 | if (slave_config->dst_addr) | |
2105 | pch->fifo_addr = slave_config->dst_addr; | |
2106 | if (slave_config->dst_addr_width) | |
2107 | pch->burst_sz = __ffs(slave_config->dst_addr_width); | |
2108 | if (slave_config->dst_maxburst) | |
2109 | pch->burst_len = slave_config->dst_maxburst; | |
2110 | } else if (slave_config->direction == DMA_DEV_TO_MEM) { | |
2111 | if (slave_config->src_addr) | |
2112 | pch->fifo_addr = slave_config->src_addr; | |
2113 | if (slave_config->src_addr_width) | |
2114 | pch->burst_sz = __ffs(slave_config->src_addr_width); | |
2115 | if (slave_config->src_maxburst) | |
2116 | pch->burst_len = slave_config->src_maxburst; | |
2117 | } | |
2118 | ||
2119 | return 0; | |
2120 | } | |
2121 | ||
2122 | static int pl330_terminate_all(struct dma_chan *chan) | |
b3040e40 JB |
2123 | { |
2124 | struct dma_pl330_chan *pch = to_pchan(chan); | |
39ff8613 | 2125 | struct dma_pl330_desc *desc; |
b3040e40 | 2126 | unsigned long flags; |
f6f2421c | 2127 | struct pl330_dmac *pl330 = pch->dmac; |
ae43b886 | 2128 | LIST_HEAD(list); |
b3040e40 | 2129 | |
740aa957 MR |
2130 | spin_lock_irqsave(&pch->lock, flags); |
2131 | spin_lock(&pl330->lock); | |
2132 | _stop(pch->thread); | |
2133 | spin_unlock(&pl330->lock); | |
2134 | ||
2135 | pch->thread->req[0].desc = NULL; | |
2136 | pch->thread->req[1].desc = NULL; | |
2137 | pch->thread->req_running = -1; | |
2138 | ||
2139 | /* Mark all desc done */ | |
2140 | list_for_each_entry(desc, &pch->submitted_list, node) { | |
2141 | desc->status = FREE; | |
2142 | dma_cookie_complete(&desc->txd); | |
2143 | } | |
ae43b328 | 2144 | |
740aa957 MR |
2145 | list_for_each_entry(desc, &pch->work_list , node) { |
2146 | desc->status = FREE; | |
2147 | dma_cookie_complete(&desc->txd); | |
1d0c1d60 | 2148 | } |
b3040e40 | 2149 | |
740aa957 MR |
2150 | list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool); |
2151 | list_splice_tail_init(&pch->work_list, &pl330->desc_pool); | |
2152 | list_splice_tail_init(&pch->completed_list, &pl330->desc_pool); | |
2153 | spin_unlock_irqrestore(&pch->lock, flags); | |
2154 | ||
b3040e40 JB |
2155 | return 0; |
2156 | } | |
2157 | ||
88987d2c RB |
2158 | /* |
2159 | * We don't support DMA_RESUME command because of hardware | |
2160 | * limitations, so after pausing the channel we cannot restore | |
2161 | * it to active state. We have to terminate channel and setup | |
2162 | * DMA transfer again. This pause feature was implemented to | |
2163 | * allow safely read residue before channel termination. | |
2164 | */ | |
5503aed8 | 2165 | static int pl330_pause(struct dma_chan *chan) |
88987d2c RB |
2166 | { |
2167 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2168 | struct pl330_dmac *pl330 = pch->dmac; | |
2169 | unsigned long flags; | |
2170 | ||
2171 | pm_runtime_get_sync(pl330->ddma.dev); | |
2172 | spin_lock_irqsave(&pch->lock, flags); | |
2173 | ||
2174 | spin_lock(&pl330->lock); | |
2175 | _stop(pch->thread); | |
2176 | spin_unlock(&pl330->lock); | |
2177 | ||
2178 | spin_unlock_irqrestore(&pch->lock, flags); | |
2179 | pm_runtime_mark_last_busy(pl330->ddma.dev); | |
2180 | pm_runtime_put_autosuspend(pl330->ddma.dev); | |
2181 | ||
2182 | return 0; | |
2183 | } | |
2184 | ||
b3040e40 JB |
2185 | static void pl330_free_chan_resources(struct dma_chan *chan) |
2186 | { | |
2187 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2188 | unsigned long flags; | |
2189 | ||
b3040e40 JB |
2190 | tasklet_kill(&pch->task); |
2191 | ||
ae43b328 | 2192 | pm_runtime_get_sync(pch->dmac->ddma.dev); |
da331ba8 BZ |
2193 | spin_lock_irqsave(&pch->lock, flags); |
2194 | ||
65ad6060 LPC |
2195 | pl330_release_channel(pch->thread); |
2196 | pch->thread = NULL; | |
b3040e40 | 2197 | |
42bc9cf4 BK |
2198 | if (pch->cyclic) |
2199 | list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); | |
2200 | ||
b3040e40 | 2201 | spin_unlock_irqrestore(&pch->lock, flags); |
ae43b328 KK |
2202 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); |
2203 | pm_runtime_put_autosuspend(pch->dmac->ddma.dev); | |
b3040e40 JB |
2204 | } |
2205 | ||
5503aed8 BD |
2206 | static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch, |
2207 | struct dma_pl330_desc *desc) | |
aee4d1fa RB |
2208 | { |
2209 | struct pl330_thread *thrd = pch->thread; | |
2210 | struct pl330_dmac *pl330 = pch->dmac; | |
2211 | void __iomem *regs = thrd->dmac->base; | |
2212 | u32 val, addr; | |
2213 | ||
2214 | pm_runtime_get_sync(pl330->ddma.dev); | |
2215 | val = addr = 0; | |
2216 | if (desc->rqcfg.src_inc) { | |
2217 | val = readl(regs + SA(thrd->id)); | |
2218 | addr = desc->px.src_addr; | |
2219 | } else { | |
2220 | val = readl(regs + DA(thrd->id)); | |
2221 | addr = desc->px.dst_addr; | |
2222 | } | |
2223 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); | |
2224 | pm_runtime_put_autosuspend(pl330->ddma.dev); | |
2225 | return val - addr; | |
2226 | } | |
2227 | ||
b3040e40 JB |
2228 | static enum dma_status |
2229 | pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, | |
2230 | struct dma_tx_state *txstate) | |
2231 | { | |
aee4d1fa RB |
2232 | enum dma_status ret; |
2233 | unsigned long flags; | |
2234 | struct dma_pl330_desc *desc, *running = NULL; | |
2235 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2236 | unsigned int transferred, residual = 0; | |
2237 | ||
2238 | ret = dma_cookie_status(chan, cookie, txstate); | |
2239 | ||
2240 | if (!txstate) | |
2241 | return ret; | |
2242 | ||
2243 | if (ret == DMA_COMPLETE) | |
2244 | goto out; | |
2245 | ||
2246 | spin_lock_irqsave(&pch->lock, flags); | |
2247 | ||
2248 | if (pch->thread->req_running != -1) | |
2249 | running = pch->thread->req[pch->thread->req_running].desc; | |
2250 | ||
2251 | /* Check in pending list */ | |
2252 | list_for_each_entry(desc, &pch->work_list, node) { | |
2253 | if (desc->status == DONE) | |
2254 | transferred = desc->bytes_requested; | |
2255 | else if (running && desc == running) | |
2256 | transferred = | |
2257 | pl330_get_current_xferred_count(pch, desc); | |
2258 | else | |
2259 | transferred = 0; | |
2260 | residual += desc->bytes_requested - transferred; | |
2261 | if (desc->txd.cookie == cookie) { | |
2262 | ret = desc->status; | |
2263 | break; | |
2264 | } | |
2265 | if (desc->last) | |
2266 | residual = 0; | |
2267 | } | |
2268 | spin_unlock_irqrestore(&pch->lock, flags); | |
2269 | ||
2270 | out: | |
2271 | dma_set_residue(txstate, residual); | |
2272 | ||
2273 | return ret; | |
b3040e40 JB |
2274 | } |
2275 | ||
2276 | static void pl330_issue_pending(struct dma_chan *chan) | |
2277 | { | |
04abf5da LPC |
2278 | struct dma_pl330_chan *pch = to_pchan(chan); |
2279 | unsigned long flags; | |
2280 | ||
2281 | spin_lock_irqsave(&pch->lock, flags); | |
ae43b328 KK |
2282 | if (list_empty(&pch->work_list)) { |
2283 | /* | |
2284 | * Warn on nothing pending. Empty submitted_list may | |
2285 | * break our pm_runtime usage counter as it is | |
2286 | * updated on work_list emptiness status. | |
2287 | */ | |
2288 | WARN_ON(list_empty(&pch->submitted_list)); | |
2289 | pm_runtime_get_sync(pch->dmac->ddma.dev); | |
2290 | } | |
04abf5da LPC |
2291 | list_splice_tail_init(&pch->submitted_list, &pch->work_list); |
2292 | spin_unlock_irqrestore(&pch->lock, flags); | |
2293 | ||
2294 | pl330_tasklet((unsigned long)pch); | |
b3040e40 JB |
2295 | } |
2296 | ||
2297 | /* | |
2298 | * We returned the last one of the circular list of descriptor(s) | |
2299 | * from prep_xxx, so the argument to submit corresponds to the last | |
2300 | * descriptor of the list. | |
2301 | */ | |
2302 | static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) | |
2303 | { | |
2304 | struct dma_pl330_desc *desc, *last = to_desc(tx); | |
2305 | struct dma_pl330_chan *pch = to_pchan(tx->chan); | |
2306 | dma_cookie_t cookie; | |
2307 | unsigned long flags; | |
2308 | ||
2309 | spin_lock_irqsave(&pch->lock, flags); | |
2310 | ||
2311 | /* Assign cookies to all nodes */ | |
b3040e40 JB |
2312 | while (!list_empty(&last->node)) { |
2313 | desc = list_entry(last->node.next, struct dma_pl330_desc, node); | |
fc514460 LPC |
2314 | if (pch->cyclic) { |
2315 | desc->txd.callback = last->txd.callback; | |
2316 | desc->txd.callback_param = last->txd.callback_param; | |
2317 | } | |
aee4d1fa | 2318 | last->last = false; |
b3040e40 | 2319 | |
884485e1 | 2320 | dma_cookie_assign(&desc->txd); |
b3040e40 | 2321 | |
04abf5da | 2322 | list_move_tail(&desc->node, &pch->submitted_list); |
b3040e40 JB |
2323 | } |
2324 | ||
aee4d1fa | 2325 | last->last = true; |
884485e1 | 2326 | cookie = dma_cookie_assign(&last->txd); |
04abf5da | 2327 | list_add_tail(&last->node, &pch->submitted_list); |
b3040e40 JB |
2328 | spin_unlock_irqrestore(&pch->lock, flags); |
2329 | ||
2330 | return cookie; | |
2331 | } | |
2332 | ||
2333 | static inline void _init_desc(struct dma_pl330_desc *desc) | |
2334 | { | |
b3040e40 | 2335 | desc->rqcfg.swap = SWAP_NO; |
f0564c7e LPC |
2336 | desc->rqcfg.scctl = CCTRL0; |
2337 | desc->rqcfg.dcctl = CCTRL0; | |
b3040e40 JB |
2338 | desc->txd.tx_submit = pl330_tx_submit; |
2339 | ||
2340 | INIT_LIST_HEAD(&desc->node); | |
2341 | } | |
2342 | ||
2343 | /* Returns the number of descriptors added to the DMAC pool */ | |
f6f2421c | 2344 | static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count) |
b3040e40 JB |
2345 | { |
2346 | struct dma_pl330_desc *desc; | |
2347 | unsigned long flags; | |
2348 | int i; | |
2349 | ||
0baf8f6a | 2350 | desc = kcalloc(count, sizeof(*desc), flg); |
b3040e40 JB |
2351 | if (!desc) |
2352 | return 0; | |
2353 | ||
f6f2421c | 2354 | spin_lock_irqsave(&pl330->pool_lock, flags); |
b3040e40 JB |
2355 | |
2356 | for (i = 0; i < count; i++) { | |
2357 | _init_desc(&desc[i]); | |
f6f2421c | 2358 | list_add_tail(&desc[i].node, &pl330->desc_pool); |
b3040e40 JB |
2359 | } |
2360 | ||
f6f2421c | 2361 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
b3040e40 JB |
2362 | |
2363 | return count; | |
2364 | } | |
2365 | ||
f6f2421c | 2366 | static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330) |
b3040e40 JB |
2367 | { |
2368 | struct dma_pl330_desc *desc = NULL; | |
2369 | unsigned long flags; | |
2370 | ||
f6f2421c | 2371 | spin_lock_irqsave(&pl330->pool_lock, flags); |
b3040e40 | 2372 | |
f6f2421c LPC |
2373 | if (!list_empty(&pl330->desc_pool)) { |
2374 | desc = list_entry(pl330->desc_pool.next, | |
b3040e40 JB |
2375 | struct dma_pl330_desc, node); |
2376 | ||
2377 | list_del_init(&desc->node); | |
2378 | ||
2379 | desc->status = PREP; | |
2380 | desc->txd.callback = NULL; | |
2381 | } | |
2382 | ||
f6f2421c | 2383 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
b3040e40 JB |
2384 | |
2385 | return desc; | |
2386 | } | |
2387 | ||
2388 | static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) | |
2389 | { | |
f6f2421c | 2390 | struct pl330_dmac *pl330 = pch->dmac; |
cd072515 | 2391 | u8 *peri_id = pch->chan.private; |
b3040e40 JB |
2392 | struct dma_pl330_desc *desc; |
2393 | ||
2394 | /* Pluck one desc from the pool of DMAC */ | |
f6f2421c | 2395 | desc = pluck_desc(pl330); |
b3040e40 JB |
2396 | |
2397 | /* If the DMAC pool is empty, alloc new */ | |
2398 | if (!desc) { | |
f6f2421c | 2399 | if (!add_desc(pl330, GFP_ATOMIC, 1)) |
b3040e40 JB |
2400 | return NULL; |
2401 | ||
2402 | /* Try again */ | |
f6f2421c | 2403 | desc = pluck_desc(pl330); |
b3040e40 | 2404 | if (!desc) { |
f6f2421c | 2405 | dev_err(pch->dmac->ddma.dev, |
b3040e40 JB |
2406 | "%s:%d ALERT!\n", __func__, __LINE__); |
2407 | return NULL; | |
2408 | } | |
2409 | } | |
2410 | ||
2411 | /* Initialize the descriptor */ | |
2412 | desc->pchan = pch; | |
2413 | desc->txd.cookie = 0; | |
2414 | async_tx_ack(&desc->txd); | |
2415 | ||
9dc5a315 | 2416 | desc->peri = peri_id ? pch->chan.chan_id : 0; |
f6f2421c | 2417 | desc->rqcfg.pcfg = &pch->dmac->pcfg; |
b3040e40 JB |
2418 | |
2419 | dma_async_tx_descriptor_init(&desc->txd, &pch->chan); | |
2420 | ||
2421 | return desc; | |
2422 | } | |
2423 | ||
2424 | static inline void fill_px(struct pl330_xfer *px, | |
2425 | dma_addr_t dst, dma_addr_t src, size_t len) | |
2426 | { | |
b3040e40 JB |
2427 | px->bytes = len; |
2428 | px->dst_addr = dst; | |
2429 | px->src_addr = src; | |
2430 | } | |
2431 | ||
2432 | static struct dma_pl330_desc * | |
2433 | __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, | |
2434 | dma_addr_t src, size_t len) | |
2435 | { | |
2436 | struct dma_pl330_desc *desc = pl330_get_desc(pch); | |
2437 | ||
2438 | if (!desc) { | |
f6f2421c | 2439 | dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", |
b3040e40 JB |
2440 | __func__, __LINE__); |
2441 | return NULL; | |
2442 | } | |
2443 | ||
2444 | /* | |
2445 | * Ideally we should lookout for reqs bigger than | |
2446 | * those that can be programmed with 256 bytes of | |
2447 | * MC buffer, but considering a req size is seldom | |
2448 | * going to be word-unaligned and more than 200MB, | |
2449 | * we take it easy. | |
2450 | * Also, should the limit is reached we'd rather | |
2451 | * have the platform increase MC buffer size than | |
2452 | * complicating this API driver. | |
2453 | */ | |
2454 | fill_px(&desc->px, dst, src, len); | |
2455 | ||
2456 | return desc; | |
2457 | } | |
2458 | ||
2459 | /* Call after fixing burst size */ | |
2460 | static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) | |
2461 | { | |
2462 | struct dma_pl330_chan *pch = desc->pchan; | |
f6f2421c | 2463 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2464 | int burst_len; |
2465 | ||
f6f2421c | 2466 | burst_len = pl330->pcfg.data_bus_width / 8; |
c27f9556 | 2467 | burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan; |
b3040e40 JB |
2468 | burst_len >>= desc->rqcfg.brst_size; |
2469 | ||
2470 | /* src/dst_burst_len can't be more than 16 */ | |
2471 | if (burst_len > 16) | |
2472 | burst_len = 16; | |
2473 | ||
2474 | while (burst_len > 1) { | |
2475 | if (!(len % (burst_len << desc->rqcfg.brst_size))) | |
2476 | break; | |
2477 | burst_len--; | |
2478 | } | |
2479 | ||
2480 | return burst_len; | |
2481 | } | |
2482 | ||
42bc9cf4 BK |
2483 | static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( |
2484 | struct dma_chan *chan, dma_addr_t dma_addr, size_t len, | |
185ecb5f | 2485 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 2486 | unsigned long flags) |
42bc9cf4 | 2487 | { |
fc514460 | 2488 | struct dma_pl330_desc *desc = NULL, *first = NULL; |
42bc9cf4 | 2489 | struct dma_pl330_chan *pch = to_pchan(chan); |
f6f2421c | 2490 | struct pl330_dmac *pl330 = pch->dmac; |
fc514460 | 2491 | unsigned int i; |
42bc9cf4 BK |
2492 | dma_addr_t dst; |
2493 | dma_addr_t src; | |
2494 | ||
fc514460 | 2495 | if (len % period_len != 0) |
42bc9cf4 | 2496 | return NULL; |
42bc9cf4 | 2497 | |
fc514460 | 2498 | if (!is_slave_direction(direction)) { |
f6f2421c | 2499 | dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n", |
42bc9cf4 BK |
2500 | __func__, __LINE__); |
2501 | return NULL; | |
2502 | } | |
2503 | ||
fc514460 LPC |
2504 | for (i = 0; i < len / period_len; i++) { |
2505 | desc = pl330_get_desc(pch); | |
2506 | if (!desc) { | |
f6f2421c | 2507 | dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", |
fc514460 | 2508 | __func__, __LINE__); |
42bc9cf4 | 2509 | |
fc514460 LPC |
2510 | if (!first) |
2511 | return NULL; | |
2512 | ||
f6f2421c | 2513 | spin_lock_irqsave(&pl330->pool_lock, flags); |
fc514460 LPC |
2514 | |
2515 | while (!list_empty(&first->node)) { | |
2516 | desc = list_entry(first->node.next, | |
2517 | struct dma_pl330_desc, node); | |
f6f2421c | 2518 | list_move_tail(&desc->node, &pl330->desc_pool); |
fc514460 LPC |
2519 | } |
2520 | ||
f6f2421c | 2521 | list_move_tail(&first->node, &pl330->desc_pool); |
fc514460 | 2522 | |
f6f2421c | 2523 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
42bc9cf4 | 2524 | |
fc514460 LPC |
2525 | return NULL; |
2526 | } | |
2527 | ||
2528 | switch (direction) { | |
2529 | case DMA_MEM_TO_DEV: | |
2530 | desc->rqcfg.src_inc = 1; | |
2531 | desc->rqcfg.dst_inc = 0; | |
fc514460 LPC |
2532 | src = dma_addr; |
2533 | dst = pch->fifo_addr; | |
2534 | break; | |
2535 | case DMA_DEV_TO_MEM: | |
2536 | desc->rqcfg.src_inc = 0; | |
2537 | desc->rqcfg.dst_inc = 1; | |
fc514460 LPC |
2538 | src = pch->fifo_addr; |
2539 | dst = dma_addr; | |
2540 | break; | |
2541 | default: | |
2542 | break; | |
2543 | } | |
2544 | ||
9dc5a315 | 2545 | desc->rqtype = direction; |
fc514460 LPC |
2546 | desc->rqcfg.brst_size = pch->burst_sz; |
2547 | desc->rqcfg.brst_len = 1; | |
aee4d1fa | 2548 | desc->bytes_requested = period_len; |
fc514460 LPC |
2549 | fill_px(&desc->px, dst, src, period_len); |
2550 | ||
2551 | if (!first) | |
2552 | first = desc; | |
2553 | else | |
2554 | list_add_tail(&desc->node, &first->node); | |
2555 | ||
2556 | dma_addr += period_len; | |
2557 | } | |
2558 | ||
2559 | if (!desc) | |
2560 | return NULL; | |
2561 | ||
2562 | pch->cyclic = true; | |
2563 | desc->txd.flags = flags; | |
42bc9cf4 BK |
2564 | |
2565 | return &desc->txd; | |
2566 | } | |
2567 | ||
b3040e40 JB |
2568 | static struct dma_async_tx_descriptor * |
2569 | pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, | |
2570 | dma_addr_t src, size_t len, unsigned long flags) | |
2571 | { | |
2572 | struct dma_pl330_desc *desc; | |
2573 | struct dma_pl330_chan *pch = to_pchan(chan); | |
f6f2421c | 2574 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2575 | int burst; |
2576 | ||
4e0e6109 | 2577 | if (unlikely(!pch || !len)) |
b3040e40 JB |
2578 | return NULL; |
2579 | ||
b3040e40 JB |
2580 | desc = __pl330_prep_dma_memcpy(pch, dst, src, len); |
2581 | if (!desc) | |
2582 | return NULL; | |
2583 | ||
2584 | desc->rqcfg.src_inc = 1; | |
2585 | desc->rqcfg.dst_inc = 1; | |
9dc5a315 | 2586 | desc->rqtype = DMA_MEM_TO_MEM; |
b3040e40 JB |
2587 | |
2588 | /* Select max possible burst size */ | |
f6f2421c | 2589 | burst = pl330->pcfg.data_bus_width / 8; |
b3040e40 | 2590 | |
137bd110 JM |
2591 | /* |
2592 | * Make sure we use a burst size that aligns with all the memcpy | |
2593 | * parameters because our DMA programming algorithm doesn't cope with | |
2594 | * transfers which straddle an entry in the DMA device's MFIFO. | |
2595 | */ | |
2596 | while ((src | dst | len) & (burst - 1)) | |
b3040e40 | 2597 | burst /= 2; |
b3040e40 JB |
2598 | |
2599 | desc->rqcfg.brst_size = 0; | |
2600 | while (burst != (1 << desc->rqcfg.brst_size)) | |
2601 | desc->rqcfg.brst_size++; | |
2602 | ||
137bd110 JM |
2603 | /* |
2604 | * If burst size is smaller than bus width then make sure we only | |
2605 | * transfer one at a time to avoid a burst stradling an MFIFO entry. | |
2606 | */ | |
2607 | if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width) | |
2608 | desc->rqcfg.brst_len = 1; | |
2609 | ||
b3040e40 JB |
2610 | desc->rqcfg.brst_len = get_burst_len(desc, len); |
2611 | ||
2612 | desc->txd.flags = flags; | |
2613 | ||
2614 | return &desc->txd; | |
2615 | } | |
2616 | ||
f6f2421c | 2617 | static void __pl330_giveback_desc(struct pl330_dmac *pl330, |
52a9d179 CP |
2618 | struct dma_pl330_desc *first) |
2619 | { | |
2620 | unsigned long flags; | |
2621 | struct dma_pl330_desc *desc; | |
2622 | ||
2623 | if (!first) | |
2624 | return; | |
2625 | ||
f6f2421c | 2626 | spin_lock_irqsave(&pl330->pool_lock, flags); |
52a9d179 CP |
2627 | |
2628 | while (!list_empty(&first->node)) { | |
2629 | desc = list_entry(first->node.next, | |
2630 | struct dma_pl330_desc, node); | |
f6f2421c | 2631 | list_move_tail(&desc->node, &pl330->desc_pool); |
52a9d179 CP |
2632 | } |
2633 | ||
f6f2421c | 2634 | list_move_tail(&first->node, &pl330->desc_pool); |
52a9d179 | 2635 | |
f6f2421c | 2636 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
52a9d179 CP |
2637 | } |
2638 | ||
b3040e40 JB |
2639 | static struct dma_async_tx_descriptor * |
2640 | pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 2641 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 2642 | unsigned long flg, void *context) |
b3040e40 JB |
2643 | { |
2644 | struct dma_pl330_desc *first, *desc = NULL; | |
2645 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 | 2646 | struct scatterlist *sg; |
1b9bb715 | 2647 | int i; |
b3040e40 JB |
2648 | dma_addr_t addr; |
2649 | ||
cd072515 | 2650 | if (unlikely(!pch || !sgl || !sg_len)) |
b3040e40 JB |
2651 | return NULL; |
2652 | ||
1b9bb715 | 2653 | addr = pch->fifo_addr; |
b3040e40 JB |
2654 | |
2655 | first = NULL; | |
2656 | ||
2657 | for_each_sg(sgl, sg, sg_len, i) { | |
2658 | ||
2659 | desc = pl330_get_desc(pch); | |
2660 | if (!desc) { | |
f6f2421c | 2661 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 | 2662 | |
f6f2421c | 2663 | dev_err(pch->dmac->ddma.dev, |
b3040e40 JB |
2664 | "%s:%d Unable to fetch desc\n", |
2665 | __func__, __LINE__); | |
f6f2421c | 2666 | __pl330_giveback_desc(pl330, first); |
b3040e40 JB |
2667 | |
2668 | return NULL; | |
2669 | } | |
2670 | ||
2671 | if (!first) | |
2672 | first = desc; | |
2673 | else | |
2674 | list_add_tail(&desc->node, &first->node); | |
2675 | ||
db8196df | 2676 | if (direction == DMA_MEM_TO_DEV) { |
b3040e40 JB |
2677 | desc->rqcfg.src_inc = 1; |
2678 | desc->rqcfg.dst_inc = 0; | |
2679 | fill_px(&desc->px, | |
2680 | addr, sg_dma_address(sg), sg_dma_len(sg)); | |
2681 | } else { | |
2682 | desc->rqcfg.src_inc = 0; | |
2683 | desc->rqcfg.dst_inc = 1; | |
2684 | fill_px(&desc->px, | |
2685 | sg_dma_address(sg), addr, sg_dma_len(sg)); | |
2686 | } | |
2687 | ||
1b9bb715 | 2688 | desc->rqcfg.brst_size = pch->burst_sz; |
b3040e40 | 2689 | desc->rqcfg.brst_len = 1; |
9dc5a315 | 2690 | desc->rqtype = direction; |
aee4d1fa | 2691 | desc->bytes_requested = sg_dma_len(sg); |
b3040e40 JB |
2692 | } |
2693 | ||
2694 | /* Return the last desc in the chain */ | |
2695 | desc->txd.flags = flg; | |
2696 | return &desc->txd; | |
2697 | } | |
2698 | ||
2699 | static irqreturn_t pl330_irq_handler(int irq, void *data) | |
2700 | { | |
2701 | if (pl330_update(data)) | |
2702 | return IRQ_HANDLED; | |
2703 | else | |
2704 | return IRQ_NONE; | |
2705 | } | |
2706 | ||
ca38ff13 LPC |
2707 | #define PL330_DMA_BUSWIDTHS \ |
2708 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ | |
2709 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
2710 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
2711 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ | |
2712 | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | |
2713 | ||
b816ccc5 KK |
2714 | /* |
2715 | * Runtime PM callbacks are provided by amba/bus.c driver. | |
2716 | * | |
2717 | * It is assumed here that IRQ safe runtime PM is chosen in probe and amba | |
2718 | * bus driver will only disable/enable the clock in runtime PM callbacks. | |
2719 | */ | |
2720 | static int __maybe_unused pl330_suspend(struct device *dev) | |
2721 | { | |
2722 | struct amba_device *pcdev = to_amba_device(dev); | |
2723 | ||
2724 | pm_runtime_disable(dev); | |
2725 | ||
2726 | if (!pm_runtime_status_suspended(dev)) { | |
2727 | /* amba did not disable the clock */ | |
2728 | amba_pclk_disable(pcdev); | |
2729 | } | |
2730 | amba_pclk_unprepare(pcdev); | |
2731 | ||
2732 | return 0; | |
2733 | } | |
2734 | ||
2735 | static int __maybe_unused pl330_resume(struct device *dev) | |
2736 | { | |
2737 | struct amba_device *pcdev = to_amba_device(dev); | |
2738 | int ret; | |
2739 | ||
2740 | ret = amba_pclk_prepare(pcdev); | |
2741 | if (ret) | |
2742 | return ret; | |
2743 | ||
2744 | if (!pm_runtime_status_suspended(dev)) | |
2745 | ret = amba_pclk_enable(pcdev); | |
2746 | ||
2747 | pm_runtime_enable(dev); | |
2748 | ||
2749 | return ret; | |
2750 | } | |
2751 | ||
2752 | static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume); | |
2753 | ||
463a1f8b | 2754 | static int |
aa25afad | 2755 | pl330_probe(struct amba_device *adev, const struct amba_id *id) |
b3040e40 JB |
2756 | { |
2757 | struct dma_pl330_platdata *pdat; | |
f6f2421c LPC |
2758 | struct pl330_config *pcfg; |
2759 | struct pl330_dmac *pl330; | |
0b94c577 | 2760 | struct dma_pl330_chan *pch, *_p; |
b3040e40 JB |
2761 | struct dma_device *pd; |
2762 | struct resource *res; | |
2763 | int i, ret, irq; | |
4e0e6109 | 2764 | int num_chan; |
b3040e40 | 2765 | |
d4adcc01 | 2766 | pdat = dev_get_platdata(&adev->dev); |
b3040e40 | 2767 | |
64113016 RK |
2768 | ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); |
2769 | if (ret) | |
2770 | return ret; | |
2771 | ||
b3040e40 | 2772 | /* Allocate a new DMAC and its Channels */ |
f6f2421c LPC |
2773 | pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL); |
2774 | if (!pl330) { | |
b3040e40 JB |
2775 | dev_err(&adev->dev, "unable to allocate mem\n"); |
2776 | return -ENOMEM; | |
2777 | } | |
2778 | ||
cee42392 AJ |
2779 | pd = &pl330->ddma; |
2780 | pd->dev = &adev->dev; | |
2781 | ||
f6f2421c | 2782 | pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0; |
b3040e40 JB |
2783 | |
2784 | res = &adev->res; | |
f6f2421c LPC |
2785 | pl330->base = devm_ioremap_resource(&adev->dev, res); |
2786 | if (IS_ERR(pl330->base)) | |
2787 | return PTR_ERR(pl330->base); | |
b3040e40 | 2788 | |
f6f2421c | 2789 | amba_set_drvdata(adev, pl330); |
a2f5203f | 2790 | |
02808b42 | 2791 | for (i = 0; i < AMBA_NR_IRQS; i++) { |
e98b3caf MS |
2792 | irq = adev->irq[i]; |
2793 | if (irq) { | |
2794 | ret = devm_request_irq(&adev->dev, irq, | |
2795 | pl330_irq_handler, 0, | |
f6f2421c | 2796 | dev_name(&adev->dev), pl330); |
e98b3caf MS |
2797 | if (ret) |
2798 | return ret; | |
2799 | } else { | |
2800 | break; | |
2801 | } | |
2802 | } | |
b3040e40 | 2803 | |
f6f2421c LPC |
2804 | pcfg = &pl330->pcfg; |
2805 | ||
2806 | pcfg->periph_id = adev->periphid; | |
2807 | ret = pl330_add(pl330); | |
b3040e40 | 2808 | if (ret) |
173e838c | 2809 | return ret; |
b3040e40 | 2810 | |
f6f2421c LPC |
2811 | INIT_LIST_HEAD(&pl330->desc_pool); |
2812 | spin_lock_init(&pl330->pool_lock); | |
b3040e40 JB |
2813 | |
2814 | /* Create a descriptor pool of default size */ | |
f6f2421c | 2815 | if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC)) |
b3040e40 JB |
2816 | dev_warn(&adev->dev, "unable to allocate desc\n"); |
2817 | ||
b3040e40 JB |
2818 | INIT_LIST_HEAD(&pd->channels); |
2819 | ||
2820 | /* Initialize channel parameters */ | |
c8473828 | 2821 | if (pdat) |
f6f2421c | 2822 | num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan); |
c8473828 | 2823 | else |
f6f2421c | 2824 | num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan); |
c8473828 | 2825 | |
f6f2421c | 2826 | pl330->num_peripherals = num_chan; |
70cbb163 | 2827 | |
f6f2421c LPC |
2828 | pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); |
2829 | if (!pl330->peripherals) { | |
61c6e753 | 2830 | ret = -ENOMEM; |
f6f2421c | 2831 | dev_err(&adev->dev, "unable to allocate pl330->peripherals\n"); |
e4d43c17 | 2832 | goto probe_err2; |
61c6e753 | 2833 | } |
b3040e40 | 2834 | |
4e0e6109 | 2835 | for (i = 0; i < num_chan; i++) { |
f6f2421c | 2836 | pch = &pl330->peripherals[i]; |
93ed5544 TA |
2837 | if (!adev->dev.of_node) |
2838 | pch->chan.private = pdat ? &pdat->peri_id[i] : NULL; | |
2839 | else | |
2840 | pch->chan.private = adev->dev.of_node; | |
b3040e40 | 2841 | |
04abf5da | 2842 | INIT_LIST_HEAD(&pch->submitted_list); |
b3040e40 | 2843 | INIT_LIST_HEAD(&pch->work_list); |
39ff8613 | 2844 | INIT_LIST_HEAD(&pch->completed_list); |
b3040e40 | 2845 | spin_lock_init(&pch->lock); |
65ad6060 | 2846 | pch->thread = NULL; |
b3040e40 | 2847 | pch->chan.device = pd; |
f6f2421c | 2848 | pch->dmac = pl330; |
b3040e40 JB |
2849 | |
2850 | /* Add the channel to the DMAC list */ | |
b3040e40 JB |
2851 | list_add_tail(&pch->chan.device_node, &pd->channels); |
2852 | } | |
2853 | ||
93ed5544 | 2854 | if (pdat) { |
cd072515 | 2855 | pd->cap_mask = pdat->cap_mask; |
93ed5544 | 2856 | } else { |
cd072515 | 2857 | dma_cap_set(DMA_MEMCPY, pd->cap_mask); |
f6f2421c | 2858 | if (pcfg->num_peri) { |
93ed5544 TA |
2859 | dma_cap_set(DMA_SLAVE, pd->cap_mask); |
2860 | dma_cap_set(DMA_CYCLIC, pd->cap_mask); | |
5557a419 | 2861 | dma_cap_set(DMA_PRIVATE, pd->cap_mask); |
93ed5544 TA |
2862 | } |
2863 | } | |
b3040e40 JB |
2864 | |
2865 | pd->device_alloc_chan_resources = pl330_alloc_chan_resources; | |
2866 | pd->device_free_chan_resources = pl330_free_chan_resources; | |
2867 | pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; | |
42bc9cf4 | 2868 | pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; |
b3040e40 JB |
2869 | pd->device_tx_status = pl330_tx_status; |
2870 | pd->device_prep_slave_sg = pl330_prep_slave_sg; | |
740aa957 | 2871 | pd->device_config = pl330_config; |
88987d2c | 2872 | pd->device_pause = pl330_pause; |
740aa957 | 2873 | pd->device_terminate_all = pl330_terminate_all; |
b3040e40 | 2874 | pd->device_issue_pending = pl330_issue_pending; |
dcabe456 MR |
2875 | pd->src_addr_widths = PL330_DMA_BUSWIDTHS; |
2876 | pd->dst_addr_widths = PL330_DMA_BUSWIDTHS; | |
2877 | pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
aee4d1fa | 2878 | pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; |
b3040e40 JB |
2879 | |
2880 | ret = dma_async_device_register(pd); | |
2881 | if (ret) { | |
2882 | dev_err(&adev->dev, "unable to register DMAC\n"); | |
0b94c577 PV |
2883 | goto probe_err3; |
2884 | } | |
2885 | ||
2886 | if (adev->dev.of_node) { | |
2887 | ret = of_dma_controller_register(adev->dev.of_node, | |
f6f2421c | 2888 | of_dma_pl330_xlate, pl330); |
0b94c577 PV |
2889 | if (ret) { |
2890 | dev_err(&adev->dev, | |
2891 | "unable to register DMA to the generic DT DMA helpers\n"); | |
2892 | } | |
b3040e40 | 2893 | } |
b714b84e | 2894 | |
f6f2421c | 2895 | adev->dev.dma_parms = &pl330->dma_parms; |
b714b84e | 2896 | |
dbaf6d85 VK |
2897 | /* |
2898 | * This is the limit for transfers with a buswidth of 1, larger | |
2899 | * buswidths will have larger limits. | |
2900 | */ | |
2901 | ret = dma_set_max_seg_size(&adev->dev, 1900800); | |
2902 | if (ret) | |
2903 | dev_err(&adev->dev, "unable to set the seg size\n"); | |
2904 | ||
b3040e40 | 2905 | |
b3040e40 | 2906 | dev_info(&adev->dev, |
1f0a5cbf | 2907 | "Loaded driver for PL330 DMAC-%x\n", adev->periphid); |
b3040e40 JB |
2908 | dev_info(&adev->dev, |
2909 | "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", | |
f6f2421c LPC |
2910 | pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan, |
2911 | pcfg->num_peri, pcfg->num_events); | |
b3040e40 | 2912 | |
ae43b328 KK |
2913 | pm_runtime_irq_safe(&adev->dev); |
2914 | pm_runtime_use_autosuspend(&adev->dev); | |
2915 | pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY); | |
2916 | pm_runtime_mark_last_busy(&adev->dev); | |
2917 | pm_runtime_put_autosuspend(&adev->dev); | |
2918 | ||
b3040e40 | 2919 | return 0; |
0b94c577 | 2920 | probe_err3: |
0b94c577 | 2921 | /* Idle the DMAC */ |
f6f2421c | 2922 | list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, |
0b94c577 PV |
2923 | chan.device_node) { |
2924 | ||
2925 | /* Remove the channel */ | |
2926 | list_del(&pch->chan.device_node); | |
2927 | ||
2928 | /* Flush the channel */ | |
0f5ebabd | 2929 | if (pch->thread) { |
740aa957 | 2930 | pl330_terminate_all(&pch->chan); |
0f5ebabd KK |
2931 | pl330_free_chan_resources(&pch->chan); |
2932 | } | |
0b94c577 | 2933 | } |
b3040e40 | 2934 | probe_err2: |
f6f2421c | 2935 | pl330_del(pl330); |
b3040e40 JB |
2936 | |
2937 | return ret; | |
2938 | } | |
2939 | ||
4bf27b8b | 2940 | static int pl330_remove(struct amba_device *adev) |
b3040e40 | 2941 | { |
f6f2421c | 2942 | struct pl330_dmac *pl330 = amba_get_drvdata(adev); |
b3040e40 | 2943 | struct dma_pl330_chan *pch, *_p; |
b3040e40 | 2944 | |
ae43b328 KK |
2945 | pm_runtime_get_noresume(pl330->ddma.dev); |
2946 | ||
0b94c577 PV |
2947 | if (adev->dev.of_node) |
2948 | of_dma_controller_free(adev->dev.of_node); | |
421da89a | 2949 | |
f6f2421c | 2950 | dma_async_device_unregister(&pl330->ddma); |
b3040e40 JB |
2951 | |
2952 | /* Idle the DMAC */ | |
f6f2421c | 2953 | list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, |
b3040e40 JB |
2954 | chan.device_node) { |
2955 | ||
2956 | /* Remove the channel */ | |
2957 | list_del(&pch->chan.device_node); | |
2958 | ||
2959 | /* Flush the channel */ | |
6e4a2a83 | 2960 | if (pch->thread) { |
740aa957 | 2961 | pl330_terminate_all(&pch->chan); |
6e4a2a83 KK |
2962 | pl330_free_chan_resources(&pch->chan); |
2963 | } | |
b3040e40 JB |
2964 | } |
2965 | ||
f6f2421c | 2966 | pl330_del(pl330); |
b3040e40 | 2967 | |
b3040e40 JB |
2968 | return 0; |
2969 | } | |
2970 | ||
2971 | static struct amba_id pl330_ids[] = { | |
2972 | { | |
2973 | .id = 0x00041330, | |
2974 | .mask = 0x000fffff, | |
2975 | }, | |
2976 | { 0, 0 }, | |
2977 | }; | |
2978 | ||
e8fa516a DM |
2979 | MODULE_DEVICE_TABLE(amba, pl330_ids); |
2980 | ||
b3040e40 JB |
2981 | static struct amba_driver pl330_driver = { |
2982 | .drv = { | |
2983 | .owner = THIS_MODULE, | |
2984 | .name = "dma-pl330", | |
b816ccc5 | 2985 | .pm = &pl330_pm, |
b3040e40 JB |
2986 | }, |
2987 | .id_table = pl330_ids, | |
2988 | .probe = pl330_probe, | |
2989 | .remove = pl330_remove, | |
2990 | }; | |
2991 | ||
9e5ed094 | 2992 | module_amba_driver(pl330_driver); |
b3040e40 | 2993 | |
046209f6 | 2994 | MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>"); |
b3040e40 JB |
2995 | MODULE_DESCRIPTION("API Driver for PL330 DMAC"); |
2996 | MODULE_LICENSE("GPL"); |