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b7d861d9 BK |
1 | /* |
2 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
b3040e40 JB |
4 | * |
5 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | |
6 | * Jaswinder Singh <jassi.brar@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
b7d861d9 | 14 | #include <linux/kernel.h> |
b3040e40 JB |
15 | #include <linux/io.h> |
16 | #include <linux/init.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/module.h> | |
b7d861d9 BK |
19 | #include <linux/string.h> |
20 | #include <linux/delay.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/dma-mapping.h> | |
b3040e40 | 23 | #include <linux/dmaengine.h> |
b3040e40 JB |
24 | #include <linux/amba/bus.h> |
25 | #include <linux/amba/pl330.h> | |
1b9bb715 | 26 | #include <linux/scatterlist.h> |
93ed5544 | 27 | #include <linux/of.h> |
a80258f9 | 28 | #include <linux/of_dma.h> |
bcc7fa95 | 29 | #include <linux/err.h> |
b3040e40 | 30 | |
d2ebfb33 | 31 | #include "dmaengine.h" |
b7d861d9 BK |
32 | #define PL330_MAX_CHAN 8 |
33 | #define PL330_MAX_IRQS 32 | |
34 | #define PL330_MAX_PERI 32 | |
35 | ||
f0564c7e LPC |
36 | enum pl330_cachectrl { |
37 | CCTRL0, /* Noncacheable and nonbufferable */ | |
38 | CCTRL1, /* Bufferable only */ | |
39 | CCTRL2, /* Cacheable, but do not allocate */ | |
40 | CCTRL3, /* Cacheable and bufferable, but do not allocate */ | |
41 | INVALID1, /* AWCACHE = 0x1000 */ | |
42 | INVALID2, | |
43 | CCTRL6, /* Cacheable write-through, allocate on writes only */ | |
44 | CCTRL7, /* Cacheable write-back, allocate on writes only */ | |
b7d861d9 BK |
45 | }; |
46 | ||
47 | enum pl330_byteswap { | |
48 | SWAP_NO, | |
49 | SWAP_2, | |
50 | SWAP_4, | |
51 | SWAP_8, | |
52 | SWAP_16, | |
53 | }; | |
54 | ||
b7d861d9 BK |
55 | /* Register and Bit field Definitions */ |
56 | #define DS 0x0 | |
57 | #define DS_ST_STOP 0x0 | |
58 | #define DS_ST_EXEC 0x1 | |
59 | #define DS_ST_CMISS 0x2 | |
60 | #define DS_ST_UPDTPC 0x3 | |
61 | #define DS_ST_WFE 0x4 | |
62 | #define DS_ST_ATBRR 0x5 | |
63 | #define DS_ST_QBUSY 0x6 | |
64 | #define DS_ST_WFP 0x7 | |
65 | #define DS_ST_KILL 0x8 | |
66 | #define DS_ST_CMPLT 0x9 | |
67 | #define DS_ST_FLTCMP 0xe | |
68 | #define DS_ST_FAULT 0xf | |
69 | ||
70 | #define DPC 0x4 | |
71 | #define INTEN 0x20 | |
72 | #define ES 0x24 | |
73 | #define INTSTATUS 0x28 | |
74 | #define INTCLR 0x2c | |
75 | #define FSM 0x30 | |
76 | #define FSC 0x34 | |
77 | #define FTM 0x38 | |
78 | ||
79 | #define _FTC 0x40 | |
80 | #define FTC(n) (_FTC + (n)*0x4) | |
81 | ||
82 | #define _CS 0x100 | |
83 | #define CS(n) (_CS + (n)*0x8) | |
84 | #define CS_CNS (1 << 21) | |
85 | ||
86 | #define _CPC 0x104 | |
87 | #define CPC(n) (_CPC + (n)*0x8) | |
88 | ||
89 | #define _SA 0x400 | |
90 | #define SA(n) (_SA + (n)*0x20) | |
91 | ||
92 | #define _DA 0x404 | |
93 | #define DA(n) (_DA + (n)*0x20) | |
94 | ||
95 | #define _CC 0x408 | |
96 | #define CC(n) (_CC + (n)*0x20) | |
97 | ||
98 | #define CC_SRCINC (1 << 0) | |
99 | #define CC_DSTINC (1 << 14) | |
100 | #define CC_SRCPRI (1 << 8) | |
101 | #define CC_DSTPRI (1 << 22) | |
102 | #define CC_SRCNS (1 << 9) | |
103 | #define CC_DSTNS (1 << 23) | |
104 | #define CC_SRCIA (1 << 10) | |
105 | #define CC_DSTIA (1 << 24) | |
106 | #define CC_SRCBRSTLEN_SHFT 4 | |
107 | #define CC_DSTBRSTLEN_SHFT 18 | |
108 | #define CC_SRCBRSTSIZE_SHFT 1 | |
109 | #define CC_DSTBRSTSIZE_SHFT 15 | |
110 | #define CC_SRCCCTRL_SHFT 11 | |
111 | #define CC_SRCCCTRL_MASK 0x7 | |
112 | #define CC_DSTCCTRL_SHFT 25 | |
113 | #define CC_DRCCCTRL_MASK 0x7 | |
114 | #define CC_SWAP_SHFT 28 | |
115 | ||
116 | #define _LC0 0x40c | |
117 | #define LC0(n) (_LC0 + (n)*0x20) | |
118 | ||
119 | #define _LC1 0x410 | |
120 | #define LC1(n) (_LC1 + (n)*0x20) | |
121 | ||
122 | #define DBGSTATUS 0xd00 | |
123 | #define DBG_BUSY (1 << 0) | |
124 | ||
125 | #define DBGCMD 0xd04 | |
126 | #define DBGINST0 0xd08 | |
127 | #define DBGINST1 0xd0c | |
128 | ||
129 | #define CR0 0xe00 | |
130 | #define CR1 0xe04 | |
131 | #define CR2 0xe08 | |
132 | #define CR3 0xe0c | |
133 | #define CR4 0xe10 | |
134 | #define CRD 0xe14 | |
135 | ||
136 | #define PERIPH_ID 0xfe0 | |
3ecf51a4 BK |
137 | #define PERIPH_REV_SHIFT 20 |
138 | #define PERIPH_REV_MASK 0xf | |
139 | #define PERIPH_REV_R0P0 0 | |
140 | #define PERIPH_REV_R1P0 1 | |
141 | #define PERIPH_REV_R1P1 2 | |
b7d861d9 BK |
142 | |
143 | #define CR0_PERIPH_REQ_SET (1 << 0) | |
144 | #define CR0_BOOT_EN_SET (1 << 1) | |
145 | #define CR0_BOOT_MAN_NS (1 << 2) | |
146 | #define CR0_NUM_CHANS_SHIFT 4 | |
147 | #define CR0_NUM_CHANS_MASK 0x7 | |
148 | #define CR0_NUM_PERIPH_SHIFT 12 | |
149 | #define CR0_NUM_PERIPH_MASK 0x1f | |
150 | #define CR0_NUM_EVENTS_SHIFT 17 | |
151 | #define CR0_NUM_EVENTS_MASK 0x1f | |
152 | ||
153 | #define CR1_ICACHE_LEN_SHIFT 0 | |
154 | #define CR1_ICACHE_LEN_MASK 0x7 | |
155 | #define CR1_NUM_ICACHELINES_SHIFT 4 | |
156 | #define CR1_NUM_ICACHELINES_MASK 0xf | |
157 | ||
158 | #define CRD_DATA_WIDTH_SHIFT 0 | |
159 | #define CRD_DATA_WIDTH_MASK 0x7 | |
160 | #define CRD_WR_CAP_SHIFT 4 | |
161 | #define CRD_WR_CAP_MASK 0x7 | |
162 | #define CRD_WR_Q_DEP_SHIFT 8 | |
163 | #define CRD_WR_Q_DEP_MASK 0xf | |
164 | #define CRD_RD_CAP_SHIFT 12 | |
165 | #define CRD_RD_CAP_MASK 0x7 | |
166 | #define CRD_RD_Q_DEP_SHIFT 16 | |
167 | #define CRD_RD_Q_DEP_MASK 0xf | |
168 | #define CRD_DATA_BUFF_SHIFT 20 | |
169 | #define CRD_DATA_BUFF_MASK 0x3ff | |
170 | ||
171 | #define PART 0x330 | |
172 | #define DESIGNER 0x41 | |
173 | #define REVISION 0x0 | |
174 | #define INTEG_CFG 0x0 | |
175 | #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) | |
176 | ||
b7d861d9 BK |
177 | #define PL330_STATE_STOPPED (1 << 0) |
178 | #define PL330_STATE_EXECUTING (1 << 1) | |
179 | #define PL330_STATE_WFE (1 << 2) | |
180 | #define PL330_STATE_FAULTING (1 << 3) | |
181 | #define PL330_STATE_COMPLETING (1 << 4) | |
182 | #define PL330_STATE_WFP (1 << 5) | |
183 | #define PL330_STATE_KILLING (1 << 6) | |
184 | #define PL330_STATE_FAULT_COMPLETING (1 << 7) | |
185 | #define PL330_STATE_CACHEMISS (1 << 8) | |
186 | #define PL330_STATE_UPDTPC (1 << 9) | |
187 | #define PL330_STATE_ATBARRIER (1 << 10) | |
188 | #define PL330_STATE_QUEUEBUSY (1 << 11) | |
189 | #define PL330_STATE_INVALID (1 << 15) | |
190 | ||
191 | #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ | |
192 | | PL330_STATE_WFE | PL330_STATE_FAULTING) | |
193 | ||
194 | #define CMD_DMAADDH 0x54 | |
195 | #define CMD_DMAEND 0x00 | |
196 | #define CMD_DMAFLUSHP 0x35 | |
197 | #define CMD_DMAGO 0xa0 | |
198 | #define CMD_DMALD 0x04 | |
199 | #define CMD_DMALDP 0x25 | |
200 | #define CMD_DMALP 0x20 | |
201 | #define CMD_DMALPEND 0x28 | |
202 | #define CMD_DMAKILL 0x01 | |
203 | #define CMD_DMAMOV 0xbc | |
204 | #define CMD_DMANOP 0x18 | |
205 | #define CMD_DMARMB 0x12 | |
206 | #define CMD_DMASEV 0x34 | |
207 | #define CMD_DMAST 0x08 | |
208 | #define CMD_DMASTP 0x29 | |
209 | #define CMD_DMASTZ 0x0c | |
210 | #define CMD_DMAWFE 0x36 | |
211 | #define CMD_DMAWFP 0x30 | |
212 | #define CMD_DMAWMB 0x13 | |
213 | ||
214 | #define SZ_DMAADDH 3 | |
215 | #define SZ_DMAEND 1 | |
216 | #define SZ_DMAFLUSHP 2 | |
217 | #define SZ_DMALD 1 | |
218 | #define SZ_DMALDP 2 | |
219 | #define SZ_DMALP 2 | |
220 | #define SZ_DMALPEND 2 | |
221 | #define SZ_DMAKILL 1 | |
222 | #define SZ_DMAMOV 6 | |
223 | #define SZ_DMANOP 1 | |
224 | #define SZ_DMARMB 1 | |
225 | #define SZ_DMASEV 2 | |
226 | #define SZ_DMAST 1 | |
227 | #define SZ_DMASTP 2 | |
228 | #define SZ_DMASTZ 1 | |
229 | #define SZ_DMAWFE 2 | |
230 | #define SZ_DMAWFP 2 | |
231 | #define SZ_DMAWMB 1 | |
232 | #define SZ_DMAGO 6 | |
233 | ||
234 | #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) | |
235 | #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) | |
236 | ||
237 | #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) | |
238 | #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) | |
239 | ||
240 | /* | |
241 | * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req | |
242 | * at 1byte/burst for P<->M and M<->M respectively. | |
243 | * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req | |
244 | * should be enough for P<->M and M<->M respectively. | |
245 | */ | |
246 | #define MCODE_BUFF_PER_REQ 256 | |
247 | ||
248 | /* If the _pl330_req is available to the client */ | |
249 | #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND) | |
250 | ||
251 | /* Use this _only_ to wait on transient states */ | |
252 | #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); | |
253 | ||
254 | #ifdef PL330_DEBUG_MCGEN | |
255 | static unsigned cmd_line; | |
256 | #define PL330_DBGCMD_DUMP(off, x...) do { \ | |
257 | printk("%x:", cmd_line); \ | |
258 | printk(x); \ | |
259 | cmd_line += off; \ | |
260 | } while (0) | |
261 | #define PL330_DBGMC_START(addr) (cmd_line = addr) | |
262 | #else | |
263 | #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) | |
264 | #define PL330_DBGMC_START(addr) do {} while (0) | |
265 | #endif | |
266 | ||
267 | /* The number of default descriptors */ | |
d2ebfb33 | 268 | |
b3040e40 JB |
269 | #define NR_DEFAULT_DESC 16 |
270 | ||
b7d861d9 BK |
271 | /* Populated by the PL330 core driver for DMA API driver's info */ |
272 | struct pl330_config { | |
273 | u32 periph_id; | |
b7d861d9 BK |
274 | #define DMAC_MODE_NS (1 << 0) |
275 | unsigned int mode; | |
276 | unsigned int data_bus_width:10; /* In number of bits */ | |
277 | unsigned int data_buf_dep:10; | |
278 | unsigned int num_chan:4; | |
279 | unsigned int num_peri:6; | |
280 | u32 peri_ns; | |
281 | unsigned int num_events:6; | |
282 | u32 irq_ns; | |
283 | }; | |
284 | ||
b7d861d9 BK |
285 | /** |
286 | * Request Configuration. | |
287 | * The PL330 core does not modify this and uses the last | |
288 | * working configuration if the request doesn't provide any. | |
289 | * | |
290 | * The Client may want to provide this info only for the | |
291 | * first request and a request with new settings. | |
292 | */ | |
293 | struct pl330_reqcfg { | |
294 | /* Address Incrementing */ | |
295 | unsigned dst_inc:1; | |
296 | unsigned src_inc:1; | |
297 | ||
298 | /* | |
299 | * For now, the SRC & DST protection levels | |
300 | * and burst size/length are assumed same. | |
301 | */ | |
302 | bool nonsecure; | |
303 | bool privileged; | |
304 | bool insnaccess; | |
305 | unsigned brst_len:5; | |
306 | unsigned brst_size:3; /* in power of 2 */ | |
307 | ||
f0564c7e LPC |
308 | enum pl330_cachectrl dcctl; |
309 | enum pl330_cachectrl scctl; | |
b7d861d9 | 310 | enum pl330_byteswap swap; |
3ecf51a4 | 311 | struct pl330_config *pcfg; |
b7d861d9 BK |
312 | }; |
313 | ||
314 | /* | |
315 | * One cycle of DMAC operation. | |
316 | * There may be more than one xfer in a request. | |
317 | */ | |
318 | struct pl330_xfer { | |
319 | u32 src_addr; | |
320 | u32 dst_addr; | |
321 | /* Size to xfer */ | |
322 | u32 bytes; | |
b7d861d9 BK |
323 | }; |
324 | ||
325 | /* The xfer callbacks are made with one of these arguments. */ | |
326 | enum pl330_op_err { | |
327 | /* The all xfers in the request were success. */ | |
328 | PL330_ERR_NONE, | |
329 | /* If req aborted due to global error. */ | |
330 | PL330_ERR_ABORT, | |
331 | /* If req failed due to problem with Channel. */ | |
332 | PL330_ERR_FAIL, | |
333 | }; | |
334 | ||
b7d861d9 BK |
335 | enum pl330_chan_op { |
336 | /* Start the channel */ | |
337 | PL330_OP_START, | |
338 | /* Abort the active xfer */ | |
339 | PL330_OP_ABORT, | |
340 | /* Stop xfer and flush queue */ | |
341 | PL330_OP_FLUSH, | |
342 | }; | |
343 | ||
b7d861d9 BK |
344 | enum dmamov_dst { |
345 | SAR = 0, | |
346 | CCR, | |
347 | DAR, | |
348 | }; | |
349 | ||
350 | enum pl330_dst { | |
351 | SRC = 0, | |
352 | DST, | |
353 | }; | |
354 | ||
355 | enum pl330_cond { | |
356 | SINGLE, | |
357 | BURST, | |
358 | ALWAYS, | |
359 | }; | |
360 | ||
9dc5a315 LPC |
361 | struct dma_pl330_desc; |
362 | ||
b7d861d9 BK |
363 | struct _pl330_req { |
364 | u32 mc_bus; | |
365 | void *mc_cpu; | |
9dc5a315 | 366 | struct dma_pl330_desc *desc; |
b7d861d9 BK |
367 | }; |
368 | ||
369 | /* ToBeDone for tasklet */ | |
370 | struct _pl330_tbd { | |
371 | bool reset_dmac; | |
372 | bool reset_mngr; | |
373 | u8 reset_chan; | |
374 | }; | |
375 | ||
376 | /* A DMAC Thread */ | |
377 | struct pl330_thread { | |
378 | u8 id; | |
379 | int ev; | |
380 | /* If the channel is not yet acquired by any client */ | |
381 | bool free; | |
382 | /* Parent DMAC */ | |
383 | struct pl330_dmac *dmac; | |
384 | /* Only two at a time */ | |
385 | struct _pl330_req req[2]; | |
386 | /* Index of the last enqueued request */ | |
387 | unsigned lstenq; | |
388 | /* Index of the last submitted request or -1 if the DMA is stopped */ | |
389 | int req_running; | |
390 | }; | |
391 | ||
392 | enum pl330_dmac_state { | |
393 | UNINIT, | |
394 | INIT, | |
395 | DYING, | |
396 | }; | |
397 | ||
b3040e40 JB |
398 | enum desc_status { |
399 | /* In the DMAC pool */ | |
400 | FREE, | |
401 | /* | |
d73111c6 | 402 | * Allocated to some channel during prep_xxx |
b3040e40 JB |
403 | * Also may be sitting on the work_list. |
404 | */ | |
405 | PREP, | |
406 | /* | |
407 | * Sitting on the work_list and already submitted | |
408 | * to the PL330 core. Not more than two descriptors | |
409 | * of a channel can be BUSY at any time. | |
410 | */ | |
411 | BUSY, | |
412 | /* | |
413 | * Sitting on the channel work_list but xfer done | |
414 | * by PL330 core | |
415 | */ | |
416 | DONE, | |
417 | }; | |
418 | ||
419 | struct dma_pl330_chan { | |
420 | /* Schedule desc completion */ | |
421 | struct tasklet_struct task; | |
422 | ||
423 | /* DMA-Engine Channel */ | |
424 | struct dma_chan chan; | |
425 | ||
04abf5da LPC |
426 | /* List of submitted descriptors */ |
427 | struct list_head submitted_list; | |
428 | /* List of issued descriptors */ | |
b3040e40 | 429 | struct list_head work_list; |
39ff8613 LPC |
430 | /* List of completed descriptors */ |
431 | struct list_head completed_list; | |
b3040e40 JB |
432 | |
433 | /* Pointer to the DMAC that manages this channel, | |
434 | * NULL if the channel is available to be acquired. | |
435 | * As the parent, this DMAC also provides descriptors | |
436 | * to the channel. | |
437 | */ | |
f6f2421c | 438 | struct pl330_dmac *dmac; |
b3040e40 JB |
439 | |
440 | /* To protect channel manipulation */ | |
441 | spinlock_t lock; | |
442 | ||
65ad6060 LPC |
443 | /* |
444 | * Hardware channel thread of PL330 DMAC. NULL if the channel is | |
445 | * available. | |
b3040e40 | 446 | */ |
65ad6060 | 447 | struct pl330_thread *thread; |
1b9bb715 BK |
448 | |
449 | /* For D-to-M and M-to-D channels */ | |
450 | int burst_sz; /* the peripheral fifo width */ | |
1d0c1d60 | 451 | int burst_len; /* the number of burst */ |
1b9bb715 | 452 | dma_addr_t fifo_addr; |
42bc9cf4 BK |
453 | |
454 | /* for cyclic capability */ | |
455 | bool cyclic; | |
b3040e40 JB |
456 | }; |
457 | ||
f6f2421c | 458 | struct pl330_dmac { |
b3040e40 JB |
459 | /* DMA-Engine Device */ |
460 | struct dma_device ddma; | |
461 | ||
b714b84e LPC |
462 | /* Holds info about sg limitations */ |
463 | struct device_dma_parameters dma_parms; | |
464 | ||
b3040e40 JB |
465 | /* Pool of descriptors available for the DMAC's channels */ |
466 | struct list_head desc_pool; | |
467 | /* To protect desc_pool manipulation */ | |
468 | spinlock_t pool_lock; | |
469 | ||
f6f2421c LPC |
470 | /* Size of MicroCode buffers for each channel. */ |
471 | unsigned mcbufsz; | |
472 | /* ioremap'ed address of PL330 registers. */ | |
473 | void __iomem *base; | |
474 | /* Populated by the PL330 core driver during pl330_add */ | |
475 | struct pl330_config pcfg; | |
476 | ||
477 | spinlock_t lock; | |
478 | /* Maximum possible events/irqs */ | |
479 | int events[32]; | |
480 | /* BUS address of MicroCode buffer */ | |
481 | dma_addr_t mcode_bus; | |
482 | /* CPU address of MicroCode buffer */ | |
483 | void *mcode_cpu; | |
484 | /* List of all Channel threads */ | |
485 | struct pl330_thread *channels; | |
486 | /* Pointer to the MANAGER thread */ | |
487 | struct pl330_thread *manager; | |
488 | /* To handle bad news in interrupt */ | |
489 | struct tasklet_struct tasks; | |
490 | struct _pl330_tbd dmac_tbd; | |
491 | /* State of DMAC operation */ | |
492 | enum pl330_dmac_state state; | |
493 | /* Holds list of reqs with due callbacks */ | |
494 | struct list_head req_done; | |
495 | ||
b3040e40 | 496 | /* Peripheral channels connected to this DMAC */ |
70cbb163 | 497 | unsigned int num_peripherals; |
4e0e6109 | 498 | struct dma_pl330_chan *peripherals; /* keep at end */ |
b3040e40 JB |
499 | }; |
500 | ||
501 | struct dma_pl330_desc { | |
502 | /* To attach to a queue as child */ | |
503 | struct list_head node; | |
504 | ||
505 | /* Descriptor for the DMA Engine API */ | |
506 | struct dma_async_tx_descriptor txd; | |
507 | ||
508 | /* Xfer for PL330 core */ | |
509 | struct pl330_xfer px; | |
510 | ||
511 | struct pl330_reqcfg rqcfg; | |
b3040e40 JB |
512 | |
513 | enum desc_status status; | |
514 | ||
515 | /* The channel which currently holds this desc */ | |
516 | struct dma_pl330_chan *pchan; | |
9dc5a315 LPC |
517 | |
518 | enum dma_transfer_direction rqtype; | |
519 | /* Index of peripheral for the xfer. */ | |
520 | unsigned peri:5; | |
521 | /* Hook to attach to DMAC's list of reqs with due callback */ | |
522 | struct list_head rqd; | |
523 | }; | |
524 | ||
525 | struct _xfer_spec { | |
526 | u32 ccr; | |
527 | struct dma_pl330_desc *desc; | |
b3040e40 JB |
528 | }; |
529 | ||
b7d861d9 BK |
530 | static inline bool _queue_empty(struct pl330_thread *thrd) |
531 | { | |
532 | return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1])) | |
533 | ? true : false; | |
534 | } | |
535 | ||
536 | static inline bool _queue_full(struct pl330_thread *thrd) | |
537 | { | |
538 | return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1])) | |
539 | ? false : true; | |
540 | } | |
541 | ||
542 | static inline bool is_manager(struct pl330_thread *thrd) | |
543 | { | |
fbbcd9be | 544 | return thrd->dmac->manager == thrd; |
b7d861d9 BK |
545 | } |
546 | ||
547 | /* If manager of the thread is in Non-Secure mode */ | |
548 | static inline bool _manager_ns(struct pl330_thread *thrd) | |
549 | { | |
f6f2421c | 550 | return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false; |
b7d861d9 BK |
551 | } |
552 | ||
3ecf51a4 BK |
553 | static inline u32 get_revision(u32 periph_id) |
554 | { | |
555 | return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; | |
556 | } | |
557 | ||
b7d861d9 BK |
558 | static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], |
559 | enum pl330_dst da, u16 val) | |
560 | { | |
561 | if (dry_run) | |
562 | return SZ_DMAADDH; | |
563 | ||
564 | buf[0] = CMD_DMAADDH; | |
565 | buf[0] |= (da << 1); | |
566 | *((u16 *)&buf[1]) = val; | |
567 | ||
568 | PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", | |
569 | da == 1 ? "DA" : "SA", val); | |
570 | ||
571 | return SZ_DMAADDH; | |
572 | } | |
573 | ||
574 | static inline u32 _emit_END(unsigned dry_run, u8 buf[]) | |
575 | { | |
576 | if (dry_run) | |
577 | return SZ_DMAEND; | |
578 | ||
579 | buf[0] = CMD_DMAEND; | |
580 | ||
581 | PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); | |
582 | ||
583 | return SZ_DMAEND; | |
584 | } | |
585 | ||
586 | static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) | |
587 | { | |
588 | if (dry_run) | |
589 | return SZ_DMAFLUSHP; | |
590 | ||
591 | buf[0] = CMD_DMAFLUSHP; | |
592 | ||
593 | peri &= 0x1f; | |
594 | peri <<= 3; | |
595 | buf[1] = peri; | |
596 | ||
597 | PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); | |
598 | ||
599 | return SZ_DMAFLUSHP; | |
600 | } | |
601 | ||
602 | static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
603 | { | |
604 | if (dry_run) | |
605 | return SZ_DMALD; | |
606 | ||
607 | buf[0] = CMD_DMALD; | |
608 | ||
609 | if (cond == SINGLE) | |
610 | buf[0] |= (0 << 1) | (1 << 0); | |
611 | else if (cond == BURST) | |
612 | buf[0] |= (1 << 1) | (1 << 0); | |
613 | ||
614 | PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", | |
615 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
616 | ||
617 | return SZ_DMALD; | |
618 | } | |
619 | ||
620 | static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], | |
621 | enum pl330_cond cond, u8 peri) | |
622 | { | |
623 | if (dry_run) | |
624 | return SZ_DMALDP; | |
625 | ||
626 | buf[0] = CMD_DMALDP; | |
627 | ||
628 | if (cond == BURST) | |
629 | buf[0] |= (1 << 1); | |
630 | ||
631 | peri &= 0x1f; | |
632 | peri <<= 3; | |
633 | buf[1] = peri; | |
634 | ||
635 | PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", | |
636 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
637 | ||
638 | return SZ_DMALDP; | |
639 | } | |
640 | ||
641 | static inline u32 _emit_LP(unsigned dry_run, u8 buf[], | |
642 | unsigned loop, u8 cnt) | |
643 | { | |
644 | if (dry_run) | |
645 | return SZ_DMALP; | |
646 | ||
647 | buf[0] = CMD_DMALP; | |
648 | ||
649 | if (loop) | |
650 | buf[0] |= (1 << 1); | |
651 | ||
652 | cnt--; /* DMAC increments by 1 internally */ | |
653 | buf[1] = cnt; | |
654 | ||
655 | PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); | |
656 | ||
657 | return SZ_DMALP; | |
658 | } | |
659 | ||
660 | struct _arg_LPEND { | |
661 | enum pl330_cond cond; | |
662 | bool forever; | |
663 | unsigned loop; | |
664 | u8 bjump; | |
665 | }; | |
666 | ||
667 | static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], | |
668 | const struct _arg_LPEND *arg) | |
669 | { | |
670 | enum pl330_cond cond = arg->cond; | |
671 | bool forever = arg->forever; | |
672 | unsigned loop = arg->loop; | |
673 | u8 bjump = arg->bjump; | |
674 | ||
675 | if (dry_run) | |
676 | return SZ_DMALPEND; | |
677 | ||
678 | buf[0] = CMD_DMALPEND; | |
679 | ||
680 | if (loop) | |
681 | buf[0] |= (1 << 2); | |
682 | ||
683 | if (!forever) | |
684 | buf[0] |= (1 << 4); | |
685 | ||
686 | if (cond == SINGLE) | |
687 | buf[0] |= (0 << 1) | (1 << 0); | |
688 | else if (cond == BURST) | |
689 | buf[0] |= (1 << 1) | (1 << 0); | |
690 | ||
691 | buf[1] = bjump; | |
692 | ||
693 | PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", | |
694 | forever ? "FE" : "END", | |
695 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), | |
696 | loop ? '1' : '0', | |
697 | bjump); | |
698 | ||
699 | return SZ_DMALPEND; | |
700 | } | |
701 | ||
702 | static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) | |
703 | { | |
704 | if (dry_run) | |
705 | return SZ_DMAKILL; | |
706 | ||
707 | buf[0] = CMD_DMAKILL; | |
708 | ||
709 | return SZ_DMAKILL; | |
710 | } | |
711 | ||
712 | static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], | |
713 | enum dmamov_dst dst, u32 val) | |
714 | { | |
715 | if (dry_run) | |
716 | return SZ_DMAMOV; | |
717 | ||
718 | buf[0] = CMD_DMAMOV; | |
719 | buf[1] = dst; | |
720 | *((u32 *)&buf[2]) = val; | |
721 | ||
722 | PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", | |
723 | dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); | |
724 | ||
725 | return SZ_DMAMOV; | |
726 | } | |
727 | ||
728 | static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) | |
729 | { | |
730 | if (dry_run) | |
731 | return SZ_DMANOP; | |
732 | ||
733 | buf[0] = CMD_DMANOP; | |
734 | ||
735 | PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); | |
736 | ||
737 | return SZ_DMANOP; | |
738 | } | |
739 | ||
740 | static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) | |
741 | { | |
742 | if (dry_run) | |
743 | return SZ_DMARMB; | |
744 | ||
745 | buf[0] = CMD_DMARMB; | |
746 | ||
747 | PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); | |
748 | ||
749 | return SZ_DMARMB; | |
750 | } | |
751 | ||
752 | static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) | |
753 | { | |
754 | if (dry_run) | |
755 | return SZ_DMASEV; | |
756 | ||
757 | buf[0] = CMD_DMASEV; | |
758 | ||
759 | ev &= 0x1f; | |
760 | ev <<= 3; | |
761 | buf[1] = ev; | |
762 | ||
763 | PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); | |
764 | ||
765 | return SZ_DMASEV; | |
766 | } | |
767 | ||
768 | static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
769 | { | |
770 | if (dry_run) | |
771 | return SZ_DMAST; | |
772 | ||
773 | buf[0] = CMD_DMAST; | |
774 | ||
775 | if (cond == SINGLE) | |
776 | buf[0] |= (0 << 1) | (1 << 0); | |
777 | else if (cond == BURST) | |
778 | buf[0] |= (1 << 1) | (1 << 0); | |
779 | ||
780 | PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", | |
781 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
782 | ||
783 | return SZ_DMAST; | |
784 | } | |
785 | ||
786 | static inline u32 _emit_STP(unsigned dry_run, u8 buf[], | |
787 | enum pl330_cond cond, u8 peri) | |
788 | { | |
789 | if (dry_run) | |
790 | return SZ_DMASTP; | |
791 | ||
792 | buf[0] = CMD_DMASTP; | |
793 | ||
794 | if (cond == BURST) | |
795 | buf[0] |= (1 << 1); | |
796 | ||
797 | peri &= 0x1f; | |
798 | peri <<= 3; | |
799 | buf[1] = peri; | |
800 | ||
801 | PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", | |
802 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
803 | ||
804 | return SZ_DMASTP; | |
805 | } | |
806 | ||
807 | static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) | |
808 | { | |
809 | if (dry_run) | |
810 | return SZ_DMASTZ; | |
811 | ||
812 | buf[0] = CMD_DMASTZ; | |
813 | ||
814 | PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); | |
815 | ||
816 | return SZ_DMASTZ; | |
817 | } | |
818 | ||
819 | static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, | |
820 | unsigned invalidate) | |
821 | { | |
822 | if (dry_run) | |
823 | return SZ_DMAWFE; | |
824 | ||
825 | buf[0] = CMD_DMAWFE; | |
826 | ||
827 | ev &= 0x1f; | |
828 | ev <<= 3; | |
829 | buf[1] = ev; | |
830 | ||
831 | if (invalidate) | |
832 | buf[1] |= (1 << 1); | |
833 | ||
834 | PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", | |
835 | ev >> 3, invalidate ? ", I" : ""); | |
836 | ||
837 | return SZ_DMAWFE; | |
838 | } | |
839 | ||
840 | static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], | |
841 | enum pl330_cond cond, u8 peri) | |
842 | { | |
843 | if (dry_run) | |
844 | return SZ_DMAWFP; | |
845 | ||
846 | buf[0] = CMD_DMAWFP; | |
847 | ||
848 | if (cond == SINGLE) | |
849 | buf[0] |= (0 << 1) | (0 << 0); | |
850 | else if (cond == BURST) | |
851 | buf[0] |= (1 << 1) | (0 << 0); | |
852 | else | |
853 | buf[0] |= (0 << 1) | (1 << 0); | |
854 | ||
855 | peri &= 0x1f; | |
856 | peri <<= 3; | |
857 | buf[1] = peri; | |
858 | ||
859 | PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", | |
860 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); | |
861 | ||
862 | return SZ_DMAWFP; | |
863 | } | |
864 | ||
865 | static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) | |
866 | { | |
867 | if (dry_run) | |
868 | return SZ_DMAWMB; | |
869 | ||
870 | buf[0] = CMD_DMAWMB; | |
871 | ||
872 | PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); | |
873 | ||
874 | return SZ_DMAWMB; | |
875 | } | |
876 | ||
877 | struct _arg_GO { | |
878 | u8 chan; | |
879 | u32 addr; | |
880 | unsigned ns; | |
881 | }; | |
882 | ||
883 | static inline u32 _emit_GO(unsigned dry_run, u8 buf[], | |
884 | const struct _arg_GO *arg) | |
885 | { | |
886 | u8 chan = arg->chan; | |
887 | u32 addr = arg->addr; | |
888 | unsigned ns = arg->ns; | |
889 | ||
890 | if (dry_run) | |
891 | return SZ_DMAGO; | |
892 | ||
893 | buf[0] = CMD_DMAGO; | |
894 | buf[0] |= (ns << 1); | |
895 | ||
896 | buf[1] = chan & 0x7; | |
897 | ||
898 | *((u32 *)&buf[2]) = addr; | |
899 | ||
900 | return SZ_DMAGO; | |
901 | } | |
902 | ||
903 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
904 | ||
905 | /* Returns Time-Out */ | |
906 | static bool _until_dmac_idle(struct pl330_thread *thrd) | |
907 | { | |
f6f2421c | 908 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
909 | unsigned long loops = msecs_to_loops(5); |
910 | ||
911 | do { | |
912 | /* Until Manager is Idle */ | |
913 | if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) | |
914 | break; | |
915 | ||
916 | cpu_relax(); | |
917 | } while (--loops); | |
918 | ||
919 | if (!loops) | |
920 | return true; | |
921 | ||
922 | return false; | |
923 | } | |
924 | ||
925 | static inline void _execute_DBGINSN(struct pl330_thread *thrd, | |
926 | u8 insn[], bool as_manager) | |
927 | { | |
f6f2421c | 928 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
929 | u32 val; |
930 | ||
931 | val = (insn[0] << 16) | (insn[1] << 24); | |
932 | if (!as_manager) { | |
933 | val |= (1 << 0); | |
934 | val |= (thrd->id << 8); /* Channel Number */ | |
935 | } | |
936 | writel(val, regs + DBGINST0); | |
937 | ||
938 | val = *((u32 *)&insn[2]); | |
939 | writel(val, regs + DBGINST1); | |
940 | ||
941 | /* If timed out due to halted state-machine */ | |
942 | if (_until_dmac_idle(thrd)) { | |
f6f2421c | 943 | dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n"); |
b7d861d9 BK |
944 | return; |
945 | } | |
946 | ||
947 | /* Get going */ | |
948 | writel(0, regs + DBGCMD); | |
949 | } | |
950 | ||
951 | /* | |
952 | * Mark a _pl330_req as free. | |
953 | * We do it by writing DMAEND as the first instruction | |
954 | * because no valid request is going to have DMAEND as | |
955 | * its first instruction to execute. | |
956 | */ | |
957 | static void mark_free(struct pl330_thread *thrd, int idx) | |
958 | { | |
959 | struct _pl330_req *req = &thrd->req[idx]; | |
960 | ||
961 | _emit_END(0, req->mc_cpu); | |
b7d861d9 BK |
962 | |
963 | thrd->req_running = -1; | |
964 | } | |
965 | ||
966 | static inline u32 _state(struct pl330_thread *thrd) | |
967 | { | |
f6f2421c | 968 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
969 | u32 val; |
970 | ||
971 | if (is_manager(thrd)) | |
972 | val = readl(regs + DS) & 0xf; | |
973 | else | |
974 | val = readl(regs + CS(thrd->id)) & 0xf; | |
975 | ||
976 | switch (val) { | |
977 | case DS_ST_STOP: | |
978 | return PL330_STATE_STOPPED; | |
979 | case DS_ST_EXEC: | |
980 | return PL330_STATE_EXECUTING; | |
981 | case DS_ST_CMISS: | |
982 | return PL330_STATE_CACHEMISS; | |
983 | case DS_ST_UPDTPC: | |
984 | return PL330_STATE_UPDTPC; | |
985 | case DS_ST_WFE: | |
986 | return PL330_STATE_WFE; | |
987 | case DS_ST_FAULT: | |
988 | return PL330_STATE_FAULTING; | |
989 | case DS_ST_ATBRR: | |
990 | if (is_manager(thrd)) | |
991 | return PL330_STATE_INVALID; | |
992 | else | |
993 | return PL330_STATE_ATBARRIER; | |
994 | case DS_ST_QBUSY: | |
995 | if (is_manager(thrd)) | |
996 | return PL330_STATE_INVALID; | |
997 | else | |
998 | return PL330_STATE_QUEUEBUSY; | |
999 | case DS_ST_WFP: | |
1000 | if (is_manager(thrd)) | |
1001 | return PL330_STATE_INVALID; | |
1002 | else | |
1003 | return PL330_STATE_WFP; | |
1004 | case DS_ST_KILL: | |
1005 | if (is_manager(thrd)) | |
1006 | return PL330_STATE_INVALID; | |
1007 | else | |
1008 | return PL330_STATE_KILLING; | |
1009 | case DS_ST_CMPLT: | |
1010 | if (is_manager(thrd)) | |
1011 | return PL330_STATE_INVALID; | |
1012 | else | |
1013 | return PL330_STATE_COMPLETING; | |
1014 | case DS_ST_FLTCMP: | |
1015 | if (is_manager(thrd)) | |
1016 | return PL330_STATE_INVALID; | |
1017 | else | |
1018 | return PL330_STATE_FAULT_COMPLETING; | |
1019 | default: | |
1020 | return PL330_STATE_INVALID; | |
1021 | } | |
1022 | } | |
1023 | ||
1024 | static void _stop(struct pl330_thread *thrd) | |
1025 | { | |
f6f2421c | 1026 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
1027 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; |
1028 | ||
1029 | if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) | |
1030 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
1031 | ||
1032 | /* Return if nothing needs to be done */ | |
1033 | if (_state(thrd) == PL330_STATE_COMPLETING | |
1034 | || _state(thrd) == PL330_STATE_KILLING | |
1035 | || _state(thrd) == PL330_STATE_STOPPED) | |
1036 | return; | |
1037 | ||
1038 | _emit_KILL(0, insn); | |
1039 | ||
1040 | /* Stop generating interrupts for SEV */ | |
1041 | writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); | |
1042 | ||
1043 | _execute_DBGINSN(thrd, insn, is_manager(thrd)); | |
1044 | } | |
1045 | ||
1046 | /* Start doing req 'idx' of thread 'thrd' */ | |
1047 | static bool _trigger(struct pl330_thread *thrd) | |
1048 | { | |
f6f2421c | 1049 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 | 1050 | struct _pl330_req *req; |
9dc5a315 | 1051 | struct dma_pl330_desc *desc; |
b7d861d9 BK |
1052 | struct _arg_GO go; |
1053 | unsigned ns; | |
1054 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; | |
1055 | int idx; | |
1056 | ||
1057 | /* Return if already ACTIVE */ | |
1058 | if (_state(thrd) != PL330_STATE_STOPPED) | |
1059 | return true; | |
1060 | ||
1061 | idx = 1 - thrd->lstenq; | |
1062 | if (!IS_FREE(&thrd->req[idx])) | |
1063 | req = &thrd->req[idx]; | |
1064 | else { | |
1065 | idx = thrd->lstenq; | |
1066 | if (!IS_FREE(&thrd->req[idx])) | |
1067 | req = &thrd->req[idx]; | |
1068 | else | |
1069 | req = NULL; | |
1070 | } | |
1071 | ||
1072 | /* Return if no request */ | |
9dc5a315 | 1073 | if (!req || !req->desc) |
b7d861d9 BK |
1074 | return true; |
1075 | ||
9dc5a315 | 1076 | desc = req->desc; |
b7d861d9 | 1077 | |
9dc5a315 | 1078 | ns = desc->rqcfg.nonsecure ? 1 : 0; |
b7d861d9 BK |
1079 | |
1080 | /* See 'Abort Sources' point-4 at Page 2-25 */ | |
1081 | if (_manager_ns(thrd) && !ns) | |
f6f2421c | 1082 | dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n", |
b7d861d9 BK |
1083 | __func__, __LINE__); |
1084 | ||
1085 | go.chan = thrd->id; | |
1086 | go.addr = req->mc_bus; | |
1087 | go.ns = ns; | |
1088 | _emit_GO(0, insn, &go); | |
1089 | ||
1090 | /* Set to generate interrupts for SEV */ | |
1091 | writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); | |
1092 | ||
1093 | /* Only manager can execute GO */ | |
1094 | _execute_DBGINSN(thrd, insn, true); | |
1095 | ||
1096 | thrd->req_running = idx; | |
1097 | ||
1098 | return true; | |
1099 | } | |
1100 | ||
1101 | static bool _start(struct pl330_thread *thrd) | |
1102 | { | |
1103 | switch (_state(thrd)) { | |
1104 | case PL330_STATE_FAULT_COMPLETING: | |
1105 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
1106 | ||
1107 | if (_state(thrd) == PL330_STATE_KILLING) | |
1108 | UNTIL(thrd, PL330_STATE_STOPPED) | |
1109 | ||
1110 | case PL330_STATE_FAULTING: | |
1111 | _stop(thrd); | |
1112 | ||
1113 | case PL330_STATE_KILLING: | |
1114 | case PL330_STATE_COMPLETING: | |
1115 | UNTIL(thrd, PL330_STATE_STOPPED) | |
1116 | ||
1117 | case PL330_STATE_STOPPED: | |
1118 | return _trigger(thrd); | |
1119 | ||
1120 | case PL330_STATE_WFP: | |
1121 | case PL330_STATE_QUEUEBUSY: | |
1122 | case PL330_STATE_ATBARRIER: | |
1123 | case PL330_STATE_UPDTPC: | |
1124 | case PL330_STATE_CACHEMISS: | |
1125 | case PL330_STATE_EXECUTING: | |
1126 | return true; | |
1127 | ||
1128 | case PL330_STATE_WFE: /* For RESUME, nothing yet */ | |
1129 | default: | |
1130 | return false; | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], | |
1135 | const struct _xfer_spec *pxs, int cyc) | |
1136 | { | |
1137 | int off = 0; | |
9dc5a315 | 1138 | struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg; |
b7d861d9 | 1139 | |
3ecf51a4 BK |
1140 | /* check lock-up free version */ |
1141 | if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { | |
1142 | while (cyc--) { | |
1143 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1144 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1145 | } | |
1146 | } else { | |
1147 | while (cyc--) { | |
1148 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1149 | off += _emit_RMB(dry_run, &buf[off]); | |
1150 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1151 | off += _emit_WMB(dry_run, &buf[off]); | |
1152 | } | |
b7d861d9 BK |
1153 | } |
1154 | ||
1155 | return off; | |
1156 | } | |
1157 | ||
1158 | static inline int _ldst_devtomem(unsigned dry_run, u8 buf[], | |
1159 | const struct _xfer_spec *pxs, int cyc) | |
1160 | { | |
1161 | int off = 0; | |
1162 | ||
1163 | while (cyc--) { | |
9dc5a315 LPC |
1164 | off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri); |
1165 | off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->desc->peri); | |
b7d861d9 | 1166 | off += _emit_ST(dry_run, &buf[off], ALWAYS); |
9dc5a315 | 1167 | off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri); |
b7d861d9 BK |
1168 | } |
1169 | ||
1170 | return off; | |
1171 | } | |
1172 | ||
1173 | static inline int _ldst_memtodev(unsigned dry_run, u8 buf[], | |
1174 | const struct _xfer_spec *pxs, int cyc) | |
1175 | { | |
1176 | int off = 0; | |
1177 | ||
1178 | while (cyc--) { | |
9dc5a315 | 1179 | off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri); |
b7d861d9 | 1180 | off += _emit_LD(dry_run, &buf[off], ALWAYS); |
9dc5a315 LPC |
1181 | off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->desc->peri); |
1182 | off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri); | |
b7d861d9 BK |
1183 | } |
1184 | ||
1185 | return off; | |
1186 | } | |
1187 | ||
1188 | static int _bursts(unsigned dry_run, u8 buf[], | |
1189 | const struct _xfer_spec *pxs, int cyc) | |
1190 | { | |
1191 | int off = 0; | |
1192 | ||
9dc5a315 | 1193 | switch (pxs->desc->rqtype) { |
585a9d0b | 1194 | case DMA_MEM_TO_DEV: |
b7d861d9 BK |
1195 | off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc); |
1196 | break; | |
585a9d0b | 1197 | case DMA_DEV_TO_MEM: |
b7d861d9 BK |
1198 | off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc); |
1199 | break; | |
585a9d0b | 1200 | case DMA_MEM_TO_MEM: |
b7d861d9 BK |
1201 | off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); |
1202 | break; | |
1203 | default: | |
1204 | off += 0x40000000; /* Scare off the Client */ | |
1205 | break; | |
1206 | } | |
1207 | ||
1208 | return off; | |
1209 | } | |
1210 | ||
1211 | /* Returns bytes consumed and updates bursts */ | |
1212 | static inline int _loop(unsigned dry_run, u8 buf[], | |
1213 | unsigned long *bursts, const struct _xfer_spec *pxs) | |
1214 | { | |
1215 | int cyc, cycmax, szlp, szlpend, szbrst, off; | |
1216 | unsigned lcnt0, lcnt1, ljmp0, ljmp1; | |
1217 | struct _arg_LPEND lpend; | |
1218 | ||
1219 | /* Max iterations possible in DMALP is 256 */ | |
1220 | if (*bursts >= 256*256) { | |
1221 | lcnt1 = 256; | |
1222 | lcnt0 = 256; | |
1223 | cyc = *bursts / lcnt1 / lcnt0; | |
1224 | } else if (*bursts > 256) { | |
1225 | lcnt1 = 256; | |
1226 | lcnt0 = *bursts / lcnt1; | |
1227 | cyc = 1; | |
1228 | } else { | |
1229 | lcnt1 = *bursts; | |
1230 | lcnt0 = 0; | |
1231 | cyc = 1; | |
1232 | } | |
1233 | ||
1234 | szlp = _emit_LP(1, buf, 0, 0); | |
1235 | szbrst = _bursts(1, buf, pxs, 1); | |
1236 | ||
1237 | lpend.cond = ALWAYS; | |
1238 | lpend.forever = false; | |
1239 | lpend.loop = 0; | |
1240 | lpend.bjump = 0; | |
1241 | szlpend = _emit_LPEND(1, buf, &lpend); | |
1242 | ||
1243 | if (lcnt0) { | |
1244 | szlp *= 2; | |
1245 | szlpend *= 2; | |
1246 | } | |
1247 | ||
1248 | /* | |
1249 | * Max bursts that we can unroll due to limit on the | |
1250 | * size of backward jump that can be encoded in DMALPEND | |
1251 | * which is 8-bits and hence 255 | |
1252 | */ | |
1253 | cycmax = (255 - (szlp + szlpend)) / szbrst; | |
1254 | ||
1255 | cyc = (cycmax < cyc) ? cycmax : cyc; | |
1256 | ||
1257 | off = 0; | |
1258 | ||
1259 | if (lcnt0) { | |
1260 | off += _emit_LP(dry_run, &buf[off], 0, lcnt0); | |
1261 | ljmp0 = off; | |
1262 | } | |
1263 | ||
1264 | off += _emit_LP(dry_run, &buf[off], 1, lcnt1); | |
1265 | ljmp1 = off; | |
1266 | ||
1267 | off += _bursts(dry_run, &buf[off], pxs, cyc); | |
1268 | ||
1269 | lpend.cond = ALWAYS; | |
1270 | lpend.forever = false; | |
1271 | lpend.loop = 1; | |
1272 | lpend.bjump = off - ljmp1; | |
1273 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1274 | ||
1275 | if (lcnt0) { | |
1276 | lpend.cond = ALWAYS; | |
1277 | lpend.forever = false; | |
1278 | lpend.loop = 0; | |
1279 | lpend.bjump = off - ljmp0; | |
1280 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1281 | } | |
1282 | ||
1283 | *bursts = lcnt1 * cyc; | |
1284 | if (lcnt0) | |
1285 | *bursts *= lcnt0; | |
1286 | ||
1287 | return off; | |
1288 | } | |
1289 | ||
1290 | static inline int _setup_loops(unsigned dry_run, u8 buf[], | |
1291 | const struct _xfer_spec *pxs) | |
1292 | { | |
9dc5a315 | 1293 | struct pl330_xfer *x = &pxs->desc->px; |
b7d861d9 BK |
1294 | u32 ccr = pxs->ccr; |
1295 | unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); | |
1296 | int off = 0; | |
1297 | ||
1298 | while (bursts) { | |
1299 | c = bursts; | |
1300 | off += _loop(dry_run, &buf[off], &c, pxs); | |
1301 | bursts -= c; | |
1302 | } | |
1303 | ||
1304 | return off; | |
1305 | } | |
1306 | ||
1307 | static inline int _setup_xfer(unsigned dry_run, u8 buf[], | |
1308 | const struct _xfer_spec *pxs) | |
1309 | { | |
9dc5a315 | 1310 | struct pl330_xfer *x = &pxs->desc->px; |
b7d861d9 BK |
1311 | int off = 0; |
1312 | ||
1313 | /* DMAMOV SAR, x->src_addr */ | |
1314 | off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); | |
1315 | /* DMAMOV DAR, x->dst_addr */ | |
1316 | off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); | |
1317 | ||
1318 | /* Setup Loop(s) */ | |
1319 | off += _setup_loops(dry_run, &buf[off], pxs); | |
1320 | ||
1321 | return off; | |
1322 | } | |
1323 | ||
1324 | /* | |
1325 | * A req is a sequence of one or more xfer units. | |
1326 | * Returns the number of bytes taken to setup the MC for the req. | |
1327 | */ | |
1328 | static int _setup_req(unsigned dry_run, struct pl330_thread *thrd, | |
1329 | unsigned index, struct _xfer_spec *pxs) | |
1330 | { | |
1331 | struct _pl330_req *req = &thrd->req[index]; | |
1332 | struct pl330_xfer *x; | |
1333 | u8 *buf = req->mc_cpu; | |
1334 | int off = 0; | |
1335 | ||
1336 | PL330_DBGMC_START(req->mc_bus); | |
1337 | ||
1338 | /* DMAMOV CCR, ccr */ | |
1339 | off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); | |
1340 | ||
9dc5a315 | 1341 | x = &pxs->desc->px; |
d5cef121 LPC |
1342 | /* Error if xfer length is not aligned at burst size */ |
1343 | if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr))) | |
1344 | return -EINVAL; | |
b7d861d9 | 1345 | |
d5cef121 | 1346 | off += _setup_xfer(dry_run, &buf[off], pxs); |
b7d861d9 BK |
1347 | |
1348 | /* DMASEV peripheral/event */ | |
1349 | off += _emit_SEV(dry_run, &buf[off], thrd->ev); | |
1350 | /* DMAEND */ | |
1351 | off += _emit_END(dry_run, &buf[off]); | |
1352 | ||
1353 | return off; | |
1354 | } | |
1355 | ||
1356 | static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) | |
1357 | { | |
1358 | u32 ccr = 0; | |
1359 | ||
1360 | if (rqc->src_inc) | |
1361 | ccr |= CC_SRCINC; | |
1362 | ||
1363 | if (rqc->dst_inc) | |
1364 | ccr |= CC_DSTINC; | |
1365 | ||
1366 | /* We set same protection levels for Src and DST for now */ | |
1367 | if (rqc->privileged) | |
1368 | ccr |= CC_SRCPRI | CC_DSTPRI; | |
1369 | if (rqc->nonsecure) | |
1370 | ccr |= CC_SRCNS | CC_DSTNS; | |
1371 | if (rqc->insnaccess) | |
1372 | ccr |= CC_SRCIA | CC_DSTIA; | |
1373 | ||
1374 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); | |
1375 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); | |
1376 | ||
1377 | ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); | |
1378 | ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); | |
1379 | ||
1380 | ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); | |
1381 | ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); | |
1382 | ||
1383 | ccr |= (rqc->swap << CC_SWAP_SHFT); | |
1384 | ||
1385 | return ccr; | |
1386 | } | |
1387 | ||
b7d861d9 BK |
1388 | /* |
1389 | * Submit a list of xfers after which the client wants notification. | |
1390 | * Client is not notified after each xfer unit, just once after all | |
1391 | * xfer units are done or some error occurs. | |
1392 | */ | |
9dc5a315 LPC |
1393 | static int pl330_submit_req(struct pl330_thread *thrd, |
1394 | struct dma_pl330_desc *desc) | |
b7d861d9 | 1395 | { |
f6f2421c | 1396 | struct pl330_dmac *pl330 = thrd->dmac; |
b7d861d9 BK |
1397 | struct _xfer_spec xs; |
1398 | unsigned long flags; | |
1399 | void __iomem *regs; | |
1400 | unsigned idx; | |
1401 | u32 ccr; | |
1402 | int ret = 0; | |
1403 | ||
1404 | /* No Req or Unacquired Channel or DMAC */ | |
9dc5a315 | 1405 | if (!desc || !thrd || thrd->free) |
b7d861d9 BK |
1406 | return -EINVAL; |
1407 | ||
f6f2421c | 1408 | regs = thrd->dmac->base; |
b7d861d9 BK |
1409 | |
1410 | if (pl330->state == DYING | |
1411 | || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { | |
f6f2421c | 1412 | dev_info(thrd->dmac->ddma.dev, "%s:%d\n", |
b7d861d9 BK |
1413 | __func__, __LINE__); |
1414 | return -EAGAIN; | |
1415 | } | |
1416 | ||
1417 | /* If request for non-existing peripheral */ | |
9dc5a315 LPC |
1418 | if (desc->rqtype != DMA_MEM_TO_MEM && |
1419 | desc->peri >= pl330->pcfg.num_peri) { | |
f6f2421c | 1420 | dev_info(thrd->dmac->ddma.dev, |
b7d861d9 | 1421 | "%s:%d Invalid peripheral(%u)!\n", |
9dc5a315 | 1422 | __func__, __LINE__, desc->peri); |
b7d861d9 BK |
1423 | return -EINVAL; |
1424 | } | |
1425 | ||
1426 | spin_lock_irqsave(&pl330->lock, flags); | |
1427 | ||
1428 | if (_queue_full(thrd)) { | |
1429 | ret = -EAGAIN; | |
1430 | goto xfer_exit; | |
1431 | } | |
1432 | ||
9dc5a315 LPC |
1433 | /* Prefer Secure Channel */ |
1434 | if (!_manager_ns(thrd)) | |
1435 | desc->rqcfg.nonsecure = 0; | |
1436 | else | |
1437 | desc->rqcfg.nonsecure = 1; | |
b7d861d9 | 1438 | |
9dc5a315 | 1439 | ccr = _prepare_ccr(&desc->rqcfg); |
b7d861d9 | 1440 | |
b7d861d9 BK |
1441 | idx = IS_FREE(&thrd->req[0]) ? 0 : 1; |
1442 | ||
1443 | xs.ccr = ccr; | |
9dc5a315 | 1444 | xs.desc = desc; |
b7d861d9 BK |
1445 | |
1446 | /* First dry run to check if req is acceptable */ | |
1447 | ret = _setup_req(1, thrd, idx, &xs); | |
1448 | if (ret < 0) | |
1449 | goto xfer_exit; | |
1450 | ||
f6f2421c LPC |
1451 | if (ret > pl330->mcbufsz / 2) { |
1452 | dev_info(pl330->ddma.dev, "%s:%d Trying increasing mcbufsz\n", | |
b7d861d9 BK |
1453 | __func__, __LINE__); |
1454 | ret = -ENOMEM; | |
1455 | goto xfer_exit; | |
1456 | } | |
1457 | ||
1458 | /* Hook the request */ | |
1459 | thrd->lstenq = idx; | |
9dc5a315 | 1460 | thrd->req[idx].desc = desc; |
be025329 | 1461 | _setup_req(0, thrd, idx, &xs); |
b7d861d9 BK |
1462 | |
1463 | ret = 0; | |
1464 | ||
1465 | xfer_exit: | |
1466 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1467 | ||
1468 | return ret; | |
1469 | } | |
1470 | ||
9dc5a315 | 1471 | static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err) |
6079d38c | 1472 | { |
6079d38c LPC |
1473 | struct dma_pl330_chan *pch = desc->pchan; |
1474 | unsigned long flags; | |
1475 | ||
1476 | /* If desc aborted */ | |
1477 | if (!pch) | |
1478 | return; | |
1479 | ||
1480 | spin_lock_irqsave(&pch->lock, flags); | |
1481 | ||
1482 | desc->status = DONE; | |
1483 | ||
1484 | spin_unlock_irqrestore(&pch->lock, flags); | |
1485 | ||
1486 | tasklet_schedule(&pch->task); | |
1487 | } | |
1488 | ||
b7d861d9 BK |
1489 | static void pl330_dotask(unsigned long data) |
1490 | { | |
1491 | struct pl330_dmac *pl330 = (struct pl330_dmac *) data; | |
b7d861d9 BK |
1492 | unsigned long flags; |
1493 | int i; | |
1494 | ||
1495 | spin_lock_irqsave(&pl330->lock, flags); | |
1496 | ||
1497 | /* The DMAC itself gone nuts */ | |
1498 | if (pl330->dmac_tbd.reset_dmac) { | |
1499 | pl330->state = DYING; | |
1500 | /* Reset the manager too */ | |
1501 | pl330->dmac_tbd.reset_mngr = true; | |
1502 | /* Clear the reset flag */ | |
1503 | pl330->dmac_tbd.reset_dmac = false; | |
1504 | } | |
1505 | ||
1506 | if (pl330->dmac_tbd.reset_mngr) { | |
1507 | _stop(pl330->manager); | |
1508 | /* Reset all channels */ | |
f6f2421c | 1509 | pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1; |
b7d861d9 BK |
1510 | /* Clear the reset flag */ |
1511 | pl330->dmac_tbd.reset_mngr = false; | |
1512 | } | |
1513 | ||
f6f2421c | 1514 | for (i = 0; i < pl330->pcfg.num_chan; i++) { |
b7d861d9 BK |
1515 | |
1516 | if (pl330->dmac_tbd.reset_chan & (1 << i)) { | |
1517 | struct pl330_thread *thrd = &pl330->channels[i]; | |
f6f2421c | 1518 | void __iomem *regs = pl330->base; |
b7d861d9 BK |
1519 | enum pl330_op_err err; |
1520 | ||
1521 | _stop(thrd); | |
1522 | ||
1523 | if (readl(regs + FSC) & (1 << thrd->id)) | |
1524 | err = PL330_ERR_FAIL; | |
1525 | else | |
1526 | err = PL330_ERR_ABORT; | |
1527 | ||
1528 | spin_unlock_irqrestore(&pl330->lock, flags); | |
9dc5a315 LPC |
1529 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err); |
1530 | dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err); | |
b7d861d9 BK |
1531 | spin_lock_irqsave(&pl330->lock, flags); |
1532 | ||
9dc5a315 LPC |
1533 | thrd->req[0].desc = NULL; |
1534 | thrd->req[1].desc = NULL; | |
b7d861d9 BK |
1535 | mark_free(thrd, 0); |
1536 | mark_free(thrd, 1); | |
1537 | ||
1538 | /* Clear the reset flag */ | |
1539 | pl330->dmac_tbd.reset_chan &= ~(1 << i); | |
1540 | } | |
1541 | } | |
1542 | ||
1543 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1544 | ||
1545 | return; | |
1546 | } | |
1547 | ||
1548 | /* Returns 1 if state was updated, 0 otherwise */ | |
f6f2421c | 1549 | static int pl330_update(struct pl330_dmac *pl330) |
b7d861d9 | 1550 | { |
9dc5a315 | 1551 | struct dma_pl330_desc *descdone, *tmp; |
b7d861d9 BK |
1552 | unsigned long flags; |
1553 | void __iomem *regs; | |
1554 | u32 val; | |
1555 | int id, ev, ret = 0; | |
1556 | ||
f6f2421c | 1557 | regs = pl330->base; |
b7d861d9 BK |
1558 | |
1559 | spin_lock_irqsave(&pl330->lock, flags); | |
1560 | ||
1561 | val = readl(regs + FSM) & 0x1; | |
1562 | if (val) | |
1563 | pl330->dmac_tbd.reset_mngr = true; | |
1564 | else | |
1565 | pl330->dmac_tbd.reset_mngr = false; | |
1566 | ||
f6f2421c | 1567 | val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1); |
b7d861d9 BK |
1568 | pl330->dmac_tbd.reset_chan |= val; |
1569 | if (val) { | |
1570 | int i = 0; | |
f6f2421c | 1571 | while (i < pl330->pcfg.num_chan) { |
b7d861d9 | 1572 | if (val & (1 << i)) { |
f6f2421c | 1573 | dev_info(pl330->ddma.dev, |
b7d861d9 BK |
1574 | "Reset Channel-%d\t CS-%x FTC-%x\n", |
1575 | i, readl(regs + CS(i)), | |
1576 | readl(regs + FTC(i))); | |
1577 | _stop(&pl330->channels[i]); | |
1578 | } | |
1579 | i++; | |
1580 | } | |
1581 | } | |
1582 | ||
1583 | /* Check which event happened i.e, thread notified */ | |
1584 | val = readl(regs + ES); | |
f6f2421c LPC |
1585 | if (pl330->pcfg.num_events < 32 |
1586 | && val & ~((1 << pl330->pcfg.num_events) - 1)) { | |
b7d861d9 | 1587 | pl330->dmac_tbd.reset_dmac = true; |
f6f2421c LPC |
1588 | dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__, |
1589 | __LINE__); | |
b7d861d9 BK |
1590 | ret = 1; |
1591 | goto updt_exit; | |
1592 | } | |
1593 | ||
f6f2421c | 1594 | for (ev = 0; ev < pl330->pcfg.num_events; ev++) { |
b7d861d9 BK |
1595 | if (val & (1 << ev)) { /* Event occurred */ |
1596 | struct pl330_thread *thrd; | |
1597 | u32 inten = readl(regs + INTEN); | |
1598 | int active; | |
1599 | ||
1600 | /* Clear the event */ | |
1601 | if (inten & (1 << ev)) | |
1602 | writel(1 << ev, regs + INTCLR); | |
1603 | ||
1604 | ret = 1; | |
1605 | ||
1606 | id = pl330->events[ev]; | |
1607 | ||
1608 | thrd = &pl330->channels[id]; | |
1609 | ||
1610 | active = thrd->req_running; | |
1611 | if (active == -1) /* Aborted */ | |
1612 | continue; | |
1613 | ||
fdec53d5 | 1614 | /* Detach the req */ |
9dc5a315 LPC |
1615 | descdone = thrd->req[active].desc; |
1616 | thrd->req[active].desc = NULL; | |
fdec53d5 | 1617 | |
b7d861d9 BK |
1618 | mark_free(thrd, active); |
1619 | ||
1620 | /* Get going again ASAP */ | |
1621 | _start(thrd); | |
1622 | ||
1623 | /* For now, just make a list of callbacks to be done */ | |
9dc5a315 | 1624 | list_add_tail(&descdone->rqd, &pl330->req_done); |
b7d861d9 BK |
1625 | } |
1626 | } | |
1627 | ||
1628 | /* Now that we are in no hurry, do the callbacks */ | |
9dc5a315 LPC |
1629 | list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) { |
1630 | list_del(&descdone->rqd); | |
b7d861d9 | 1631 | spin_unlock_irqrestore(&pl330->lock, flags); |
9dc5a315 | 1632 | dma_pl330_rqcb(descdone, PL330_ERR_NONE); |
b7d861d9 BK |
1633 | spin_lock_irqsave(&pl330->lock, flags); |
1634 | } | |
1635 | ||
1636 | updt_exit: | |
1637 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1638 | ||
1639 | if (pl330->dmac_tbd.reset_dmac | |
1640 | || pl330->dmac_tbd.reset_mngr | |
1641 | || pl330->dmac_tbd.reset_chan) { | |
1642 | ret = 1; | |
1643 | tasklet_schedule(&pl330->tasks); | |
1644 | } | |
1645 | ||
1646 | return ret; | |
1647 | } | |
1648 | ||
65ad6060 | 1649 | static int pl330_chan_ctrl(struct pl330_thread *thrd, enum pl330_chan_op op) |
b7d861d9 | 1650 | { |
b7d861d9 BK |
1651 | struct pl330_dmac *pl330; |
1652 | unsigned long flags; | |
ef08e782 | 1653 | int ret = 0, active; |
b7d861d9 BK |
1654 | |
1655 | if (!thrd || thrd->free || thrd->dmac->state == DYING) | |
1656 | return -EINVAL; | |
1657 | ||
1658 | pl330 = thrd->dmac; | |
ef08e782 | 1659 | active = thrd->req_running; |
b7d861d9 BK |
1660 | |
1661 | spin_lock_irqsave(&pl330->lock, flags); | |
1662 | ||
1663 | switch (op) { | |
1664 | case PL330_OP_FLUSH: | |
1665 | /* Make sure the channel is stopped */ | |
1666 | _stop(thrd); | |
1667 | ||
9dc5a315 LPC |
1668 | thrd->req[0].desc = NULL; |
1669 | thrd->req[1].desc = NULL; | |
b7d861d9 BK |
1670 | mark_free(thrd, 0); |
1671 | mark_free(thrd, 1); | |
1672 | break; | |
1673 | ||
1674 | case PL330_OP_ABORT: | |
1675 | /* Make sure the channel is stopped */ | |
1676 | _stop(thrd); | |
1677 | ||
1678 | /* ABORT is only for the active req */ | |
1679 | if (active == -1) | |
1680 | break; | |
1681 | ||
9dc5a315 | 1682 | thrd->req[active].desc = NULL; |
b7d861d9 BK |
1683 | mark_free(thrd, active); |
1684 | ||
1685 | /* Start the next */ | |
1686 | case PL330_OP_START: | |
1687 | if ((active == -1) && !_start(thrd)) | |
1688 | ret = -EIO; | |
1689 | break; | |
1690 | ||
1691 | default: | |
1692 | ret = -EINVAL; | |
1693 | } | |
1694 | ||
1695 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1696 | return ret; | |
1697 | } | |
1698 | ||
b7d861d9 BK |
1699 | /* Reserve an event */ |
1700 | static inline int _alloc_event(struct pl330_thread *thrd) | |
1701 | { | |
1702 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1703 | int ev; |
1704 | ||
f6f2421c | 1705 | for (ev = 0; ev < pl330->pcfg.num_events; ev++) |
b7d861d9 BK |
1706 | if (pl330->events[ev] == -1) { |
1707 | pl330->events[ev] = thrd->id; | |
1708 | return ev; | |
1709 | } | |
1710 | ||
1711 | return -1; | |
1712 | } | |
1713 | ||
f6f2421c | 1714 | static bool _chan_ns(const struct pl330_dmac *pl330, int i) |
b7d861d9 | 1715 | { |
f6f2421c | 1716 | return pl330->pcfg.irq_ns & (1 << i); |
b7d861d9 BK |
1717 | } |
1718 | ||
1719 | /* Upon success, returns IdentityToken for the | |
1720 | * allocated channel, NULL otherwise. | |
1721 | */ | |
f6f2421c | 1722 | static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330) |
b7d861d9 BK |
1723 | { |
1724 | struct pl330_thread *thrd = NULL; | |
b7d861d9 BK |
1725 | unsigned long flags; |
1726 | int chans, i; | |
1727 | ||
b7d861d9 BK |
1728 | if (pl330->state == DYING) |
1729 | return NULL; | |
1730 | ||
f6f2421c | 1731 | chans = pl330->pcfg.num_chan; |
b7d861d9 BK |
1732 | |
1733 | spin_lock_irqsave(&pl330->lock, flags); | |
1734 | ||
1735 | for (i = 0; i < chans; i++) { | |
1736 | thrd = &pl330->channels[i]; | |
1737 | if ((thrd->free) && (!_manager_ns(thrd) || | |
f6f2421c | 1738 | _chan_ns(pl330, i))) { |
b7d861d9 BK |
1739 | thrd->ev = _alloc_event(thrd); |
1740 | if (thrd->ev >= 0) { | |
1741 | thrd->free = false; | |
1742 | thrd->lstenq = 1; | |
9dc5a315 | 1743 | thrd->req[0].desc = NULL; |
b7d861d9 | 1744 | mark_free(thrd, 0); |
9dc5a315 | 1745 | thrd->req[1].desc = NULL; |
b7d861d9 BK |
1746 | mark_free(thrd, 1); |
1747 | break; | |
1748 | } | |
1749 | } | |
1750 | thrd = NULL; | |
1751 | } | |
1752 | ||
1753 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1754 | ||
1755 | return thrd; | |
1756 | } | |
1757 | ||
1758 | /* Release an event */ | |
1759 | static inline void _free_event(struct pl330_thread *thrd, int ev) | |
1760 | { | |
1761 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1762 | |
1763 | /* If the event is valid and was held by the thread */ | |
f6f2421c | 1764 | if (ev >= 0 && ev < pl330->pcfg.num_events |
b7d861d9 BK |
1765 | && pl330->events[ev] == thrd->id) |
1766 | pl330->events[ev] = -1; | |
1767 | } | |
1768 | ||
65ad6060 | 1769 | static void pl330_release_channel(struct pl330_thread *thrd) |
b7d861d9 | 1770 | { |
b7d861d9 BK |
1771 | struct pl330_dmac *pl330; |
1772 | unsigned long flags; | |
1773 | ||
1774 | if (!thrd || thrd->free) | |
1775 | return; | |
1776 | ||
1777 | _stop(thrd); | |
1778 | ||
9dc5a315 LPC |
1779 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT); |
1780 | dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT); | |
b7d861d9 BK |
1781 | |
1782 | pl330 = thrd->dmac; | |
1783 | ||
1784 | spin_lock_irqsave(&pl330->lock, flags); | |
1785 | _free_event(thrd, thrd->ev); | |
1786 | thrd->free = true; | |
1787 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1788 | } | |
1789 | ||
1790 | /* Initialize the structure for PL330 configuration, that can be used | |
1791 | * by the client driver the make best use of the DMAC | |
1792 | */ | |
f6f2421c | 1793 | static void read_dmac_config(struct pl330_dmac *pl330) |
b7d861d9 | 1794 | { |
f6f2421c | 1795 | void __iomem *regs = pl330->base; |
b7d861d9 BK |
1796 | u32 val; |
1797 | ||
1798 | val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; | |
1799 | val &= CRD_DATA_WIDTH_MASK; | |
f6f2421c | 1800 | pl330->pcfg.data_bus_width = 8 * (1 << val); |
b7d861d9 BK |
1801 | |
1802 | val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; | |
1803 | val &= CRD_DATA_BUFF_MASK; | |
f6f2421c | 1804 | pl330->pcfg.data_buf_dep = val + 1; |
b7d861d9 BK |
1805 | |
1806 | val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; | |
1807 | val &= CR0_NUM_CHANS_MASK; | |
1808 | val += 1; | |
f6f2421c | 1809 | pl330->pcfg.num_chan = val; |
b7d861d9 BK |
1810 | |
1811 | val = readl(regs + CR0); | |
1812 | if (val & CR0_PERIPH_REQ_SET) { | |
1813 | val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; | |
1814 | val += 1; | |
f6f2421c LPC |
1815 | pl330->pcfg.num_peri = val; |
1816 | pl330->pcfg.peri_ns = readl(regs + CR4); | |
b7d861d9 | 1817 | } else { |
f6f2421c | 1818 | pl330->pcfg.num_peri = 0; |
b7d861d9 BK |
1819 | } |
1820 | ||
1821 | val = readl(regs + CR0); | |
1822 | if (val & CR0_BOOT_MAN_NS) | |
f6f2421c | 1823 | pl330->pcfg.mode |= DMAC_MODE_NS; |
b7d861d9 | 1824 | else |
f6f2421c | 1825 | pl330->pcfg.mode &= ~DMAC_MODE_NS; |
b7d861d9 BK |
1826 | |
1827 | val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; | |
1828 | val &= CR0_NUM_EVENTS_MASK; | |
1829 | val += 1; | |
f6f2421c | 1830 | pl330->pcfg.num_events = val; |
b7d861d9 | 1831 | |
f6f2421c | 1832 | pl330->pcfg.irq_ns = readl(regs + CR3); |
b7d861d9 BK |
1833 | } |
1834 | ||
1835 | static inline void _reset_thread(struct pl330_thread *thrd) | |
1836 | { | |
1837 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1838 | |
1839 | thrd->req[0].mc_cpu = pl330->mcode_cpu | |
f6f2421c | 1840 | + (thrd->id * pl330->mcbufsz); |
b7d861d9 | 1841 | thrd->req[0].mc_bus = pl330->mcode_bus |
f6f2421c | 1842 | + (thrd->id * pl330->mcbufsz); |
9dc5a315 | 1843 | thrd->req[0].desc = NULL; |
b7d861d9 BK |
1844 | mark_free(thrd, 0); |
1845 | ||
1846 | thrd->req[1].mc_cpu = thrd->req[0].mc_cpu | |
f6f2421c | 1847 | + pl330->mcbufsz / 2; |
b7d861d9 | 1848 | thrd->req[1].mc_bus = thrd->req[0].mc_bus |
f6f2421c | 1849 | + pl330->mcbufsz / 2; |
9dc5a315 | 1850 | thrd->req[1].desc = NULL; |
b7d861d9 BK |
1851 | mark_free(thrd, 1); |
1852 | } | |
1853 | ||
1854 | static int dmac_alloc_threads(struct pl330_dmac *pl330) | |
1855 | { | |
f6f2421c | 1856 | int chans = pl330->pcfg.num_chan; |
b7d861d9 BK |
1857 | struct pl330_thread *thrd; |
1858 | int i; | |
1859 | ||
1860 | /* Allocate 1 Manager and 'chans' Channel threads */ | |
1861 | pl330->channels = kzalloc((1 + chans) * sizeof(*thrd), | |
1862 | GFP_KERNEL); | |
1863 | if (!pl330->channels) | |
1864 | return -ENOMEM; | |
1865 | ||
1866 | /* Init Channel threads */ | |
1867 | for (i = 0; i < chans; i++) { | |
1868 | thrd = &pl330->channels[i]; | |
1869 | thrd->id = i; | |
1870 | thrd->dmac = pl330; | |
1871 | _reset_thread(thrd); | |
1872 | thrd->free = true; | |
1873 | } | |
1874 | ||
1875 | /* MANAGER is indexed at the end */ | |
1876 | thrd = &pl330->channels[chans]; | |
1877 | thrd->id = chans; | |
1878 | thrd->dmac = pl330; | |
1879 | thrd->free = false; | |
1880 | pl330->manager = thrd; | |
1881 | ||
1882 | return 0; | |
1883 | } | |
1884 | ||
1885 | static int dmac_alloc_resources(struct pl330_dmac *pl330) | |
1886 | { | |
f6f2421c | 1887 | int chans = pl330->pcfg.num_chan; |
b7d861d9 | 1888 | int ret; |
b3040e40 | 1889 | |
b3040e40 | 1890 | /* |
b7d861d9 BK |
1891 | * Alloc MicroCode buffer for 'chans' Channel threads. |
1892 | * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) | |
b3040e40 | 1893 | */ |
f6f2421c LPC |
1894 | pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev, |
1895 | chans * pl330->mcbufsz, | |
b7d861d9 BK |
1896 | &pl330->mcode_bus, GFP_KERNEL); |
1897 | if (!pl330->mcode_cpu) { | |
f6f2421c | 1898 | dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n", |
b7d861d9 BK |
1899 | __func__, __LINE__); |
1900 | return -ENOMEM; | |
1901 | } | |
1902 | ||
1903 | ret = dmac_alloc_threads(pl330); | |
1904 | if (ret) { | |
f6f2421c | 1905 | dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n", |
b7d861d9 | 1906 | __func__, __LINE__); |
f6f2421c LPC |
1907 | dma_free_coherent(pl330->ddma.dev, |
1908 | chans * pl330->mcbufsz, | |
b7d861d9 BK |
1909 | pl330->mcode_cpu, pl330->mcode_bus); |
1910 | return ret; | |
1911 | } | |
1912 | ||
1913 | return 0; | |
1914 | } | |
1915 | ||
f6f2421c | 1916 | static int pl330_add(struct pl330_dmac *pl330) |
b7d861d9 | 1917 | { |
b7d861d9 BK |
1918 | void __iomem *regs; |
1919 | int i, ret; | |
1920 | ||
f6f2421c | 1921 | regs = pl330->base; |
b3040e40 | 1922 | |
b7d861d9 | 1923 | /* Check if we can handle this DMAC */ |
f6f2421c LPC |
1924 | if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { |
1925 | dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n", | |
1926 | pl330->pcfg.periph_id); | |
b7d861d9 BK |
1927 | return -EINVAL; |
1928 | } | |
b3040e40 | 1929 | |
b7d861d9 | 1930 | /* Read the configuration of the DMAC */ |
f6f2421c | 1931 | read_dmac_config(pl330); |
b3040e40 | 1932 | |
f6f2421c LPC |
1933 | if (pl330->pcfg.num_events == 0) { |
1934 | dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n", | |
b7d861d9 BK |
1935 | __func__, __LINE__); |
1936 | return -EINVAL; | |
1937 | } | |
b3040e40 | 1938 | |
b7d861d9 | 1939 | spin_lock_init(&pl330->lock); |
1b9bb715 | 1940 | |
b7d861d9 | 1941 | INIT_LIST_HEAD(&pl330->req_done); |
42bc9cf4 | 1942 | |
b7d861d9 | 1943 | /* Use default MC buffer size if not provided */ |
f6f2421c LPC |
1944 | if (!pl330->mcbufsz) |
1945 | pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2; | |
b3040e40 | 1946 | |
b7d861d9 | 1947 | /* Mark all events as free */ |
f6f2421c | 1948 | for (i = 0; i < pl330->pcfg.num_events; i++) |
b7d861d9 | 1949 | pl330->events[i] = -1; |
b3040e40 | 1950 | |
b7d861d9 BK |
1951 | /* Allocate resources needed by the DMAC */ |
1952 | ret = dmac_alloc_resources(pl330); | |
1953 | if (ret) { | |
f6f2421c | 1954 | dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n"); |
b7d861d9 BK |
1955 | return ret; |
1956 | } | |
b3040e40 | 1957 | |
b7d861d9 | 1958 | tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); |
b3040e40 | 1959 | |
b7d861d9 | 1960 | pl330->state = INIT; |
a2f5203f | 1961 | |
b7d861d9 BK |
1962 | return 0; |
1963 | } | |
b3040e40 | 1964 | |
b7d861d9 BK |
1965 | static int dmac_free_threads(struct pl330_dmac *pl330) |
1966 | { | |
b7d861d9 BK |
1967 | struct pl330_thread *thrd; |
1968 | int i; | |
b3040e40 | 1969 | |
b7d861d9 | 1970 | /* Release Channel threads */ |
f6f2421c | 1971 | for (i = 0; i < pl330->pcfg.num_chan; i++) { |
b7d861d9 | 1972 | thrd = &pl330->channels[i]; |
65ad6060 | 1973 | pl330_release_channel(thrd); |
b7d861d9 | 1974 | } |
b3040e40 | 1975 | |
b7d861d9 BK |
1976 | /* Free memory */ |
1977 | kfree(pl330->channels); | |
b3040e40 | 1978 | |
b7d861d9 BK |
1979 | return 0; |
1980 | } | |
b3040e40 | 1981 | |
f6f2421c | 1982 | static void pl330_del(struct pl330_dmac *pl330) |
b7d861d9 | 1983 | { |
b7d861d9 BK |
1984 | pl330->state = UNINIT; |
1985 | ||
1986 | tasklet_kill(&pl330->tasks); | |
1987 | ||
1988 | /* Free DMAC resources */ | |
f6f2421c | 1989 | dmac_free_threads(pl330); |
b7d861d9 | 1990 | |
f6f2421c LPC |
1991 | dma_free_coherent(pl330->ddma.dev, |
1992 | pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu, | |
1993 | pl330->mcode_bus); | |
b7d861d9 | 1994 | } |
b3040e40 | 1995 | |
3e2ec13a TA |
1996 | /* forward declaration */ |
1997 | static struct amba_driver pl330_driver; | |
1998 | ||
b3040e40 JB |
1999 | static inline struct dma_pl330_chan * |
2000 | to_pchan(struct dma_chan *ch) | |
2001 | { | |
2002 | if (!ch) | |
2003 | return NULL; | |
2004 | ||
2005 | return container_of(ch, struct dma_pl330_chan, chan); | |
2006 | } | |
2007 | ||
2008 | static inline struct dma_pl330_desc * | |
2009 | to_desc(struct dma_async_tx_descriptor *tx) | |
2010 | { | |
2011 | return container_of(tx, struct dma_pl330_desc, txd); | |
2012 | } | |
2013 | ||
b3040e40 JB |
2014 | static inline void fill_queue(struct dma_pl330_chan *pch) |
2015 | { | |
2016 | struct dma_pl330_desc *desc; | |
2017 | int ret; | |
2018 | ||
2019 | list_for_each_entry(desc, &pch->work_list, node) { | |
2020 | ||
2021 | /* If already submitted */ | |
2022 | if (desc->status == BUSY) | |
30fb980b | 2023 | continue; |
b3040e40 | 2024 | |
9dc5a315 | 2025 | ret = pl330_submit_req(pch->thread, desc); |
b3040e40 JB |
2026 | if (!ret) { |
2027 | desc->status = BUSY; | |
b3040e40 JB |
2028 | } else if (ret == -EAGAIN) { |
2029 | /* QFull or DMAC Dying */ | |
2030 | break; | |
2031 | } else { | |
2032 | /* Unacceptable request */ | |
2033 | desc->status = DONE; | |
f6f2421c | 2034 | dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", |
b3040e40 JB |
2035 | __func__, __LINE__, desc->txd.cookie); |
2036 | tasklet_schedule(&pch->task); | |
2037 | } | |
2038 | } | |
2039 | } | |
2040 | ||
2041 | static void pl330_tasklet(unsigned long data) | |
2042 | { | |
2043 | struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; | |
2044 | struct dma_pl330_desc *desc, *_dt; | |
2045 | unsigned long flags; | |
b3040e40 JB |
2046 | |
2047 | spin_lock_irqsave(&pch->lock, flags); | |
2048 | ||
2049 | /* Pick up ripe tomatoes */ | |
2050 | list_for_each_entry_safe(desc, _dt, &pch->work_list, node) | |
2051 | if (desc->status == DONE) { | |
30c1dc0f | 2052 | if (!pch->cyclic) |
eab21585 | 2053 | dma_cookie_complete(&desc->txd); |
39ff8613 | 2054 | list_move_tail(&desc->node, &pch->completed_list); |
b3040e40 JB |
2055 | } |
2056 | ||
2057 | /* Try to submit a req imm. next to the last completed cookie */ | |
2058 | fill_queue(pch); | |
2059 | ||
2060 | /* Make sure the PL330 Channel thread is active */ | |
65ad6060 | 2061 | pl330_chan_ctrl(pch->thread, PL330_OP_START); |
b3040e40 | 2062 | |
39ff8613 LPC |
2063 | while (!list_empty(&pch->completed_list)) { |
2064 | dma_async_tx_callback callback; | |
2065 | void *callback_param; | |
b3040e40 | 2066 | |
39ff8613 LPC |
2067 | desc = list_first_entry(&pch->completed_list, |
2068 | struct dma_pl330_desc, node); | |
2069 | ||
2070 | callback = desc->txd.callback; | |
2071 | callback_param = desc->txd.callback_param; | |
2072 | ||
2073 | if (pch->cyclic) { | |
2074 | desc->status = PREP; | |
2075 | list_move_tail(&desc->node, &pch->work_list); | |
2076 | } else { | |
2077 | desc->status = FREE; | |
2078 | list_move_tail(&desc->node, &pch->dmac->desc_pool); | |
2079 | } | |
2080 | ||
d38a8c62 DW |
2081 | dma_descriptor_unmap(&desc->txd); |
2082 | ||
39ff8613 LPC |
2083 | if (callback) { |
2084 | spin_unlock_irqrestore(&pch->lock, flags); | |
2085 | callback(callback_param); | |
2086 | spin_lock_irqsave(&pch->lock, flags); | |
2087 | } | |
2088 | } | |
2089 | spin_unlock_irqrestore(&pch->lock, flags); | |
b3040e40 JB |
2090 | } |
2091 | ||
3e2ec13a TA |
2092 | bool pl330_filter(struct dma_chan *chan, void *param) |
2093 | { | |
cd072515 | 2094 | u8 *peri_id; |
3e2ec13a TA |
2095 | |
2096 | if (chan->device->dev->driver != &pl330_driver.drv) | |
2097 | return false; | |
2098 | ||
cd072515 | 2099 | peri_id = chan->private; |
2f986ec6 | 2100 | return *peri_id == (unsigned long)param; |
3e2ec13a TA |
2101 | } |
2102 | EXPORT_SYMBOL(pl330_filter); | |
2103 | ||
a80258f9 PV |
2104 | static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, |
2105 | struct of_dma *ofdma) | |
2106 | { | |
2107 | int count = dma_spec->args_count; | |
f6f2421c | 2108 | struct pl330_dmac *pl330 = ofdma->of_dma_data; |
70cbb163 | 2109 | unsigned int chan_id; |
a80258f9 | 2110 | |
f6f2421c LPC |
2111 | if (!pl330) |
2112 | return NULL; | |
2113 | ||
a80258f9 PV |
2114 | if (count != 1) |
2115 | return NULL; | |
2116 | ||
70cbb163 | 2117 | chan_id = dma_spec->args[0]; |
f6f2421c | 2118 | if (chan_id >= pl330->num_peripherals) |
70cbb163 | 2119 | return NULL; |
a80258f9 | 2120 | |
f6f2421c | 2121 | return dma_get_slave_channel(&pl330->peripherals[chan_id].chan); |
a80258f9 PV |
2122 | } |
2123 | ||
b3040e40 JB |
2124 | static int pl330_alloc_chan_resources(struct dma_chan *chan) |
2125 | { | |
2126 | struct dma_pl330_chan *pch = to_pchan(chan); | |
f6f2421c | 2127 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2128 | unsigned long flags; |
2129 | ||
2130 | spin_lock_irqsave(&pch->lock, flags); | |
2131 | ||
d3ee98cd | 2132 | dma_cookie_init(chan); |
42bc9cf4 | 2133 | pch->cyclic = false; |
b3040e40 | 2134 | |
f6f2421c | 2135 | pch->thread = pl330_request_channel(pl330); |
65ad6060 | 2136 | if (!pch->thread) { |
b3040e40 | 2137 | spin_unlock_irqrestore(&pch->lock, flags); |
02747885 | 2138 | return -ENOMEM; |
b3040e40 JB |
2139 | } |
2140 | ||
2141 | tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); | |
2142 | ||
2143 | spin_unlock_irqrestore(&pch->lock, flags); | |
2144 | ||
2145 | return 1; | |
2146 | } | |
2147 | ||
2148 | static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg) | |
2149 | { | |
2150 | struct dma_pl330_chan *pch = to_pchan(chan); | |
39ff8613 | 2151 | struct dma_pl330_desc *desc; |
b3040e40 | 2152 | unsigned long flags; |
f6f2421c | 2153 | struct pl330_dmac *pl330 = pch->dmac; |
1d0c1d60 | 2154 | struct dma_slave_config *slave_config; |
ae43b886 | 2155 | LIST_HEAD(list); |
b3040e40 | 2156 | |
1d0c1d60 BK |
2157 | switch (cmd) { |
2158 | case DMA_TERMINATE_ALL: | |
2159 | spin_lock_irqsave(&pch->lock, flags); | |
b3040e40 | 2160 | |
1d0c1d60 | 2161 | /* FLUSH the PL330 Channel thread */ |
65ad6060 | 2162 | pl330_chan_ctrl(pch->thread, PL330_OP_FLUSH); |
b3040e40 | 2163 | |
1d0c1d60 | 2164 | /* Mark all desc done */ |
04abf5da LPC |
2165 | list_for_each_entry(desc, &pch->submitted_list, node) { |
2166 | desc->status = FREE; | |
2167 | dma_cookie_complete(&desc->txd); | |
2168 | } | |
2169 | ||
39ff8613 LPC |
2170 | list_for_each_entry(desc, &pch->work_list , node) { |
2171 | desc->status = FREE; | |
2172 | dma_cookie_complete(&desc->txd); | |
2173 | } | |
2174 | ||
2175 | list_for_each_entry(desc, &pch->completed_list , node) { | |
2176 | desc->status = FREE; | |
2177 | dma_cookie_complete(&desc->txd); | |
ae43b886 | 2178 | } |
b3040e40 | 2179 | |
f6f2421c LPC |
2180 | list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool); |
2181 | list_splice_tail_init(&pch->work_list, &pl330->desc_pool); | |
2182 | list_splice_tail_init(&pch->completed_list, &pl330->desc_pool); | |
1d0c1d60 | 2183 | spin_unlock_irqrestore(&pch->lock, flags); |
1d0c1d60 BK |
2184 | break; |
2185 | case DMA_SLAVE_CONFIG: | |
2186 | slave_config = (struct dma_slave_config *)arg; | |
2187 | ||
db8196df | 2188 | if (slave_config->direction == DMA_MEM_TO_DEV) { |
1d0c1d60 BK |
2189 | if (slave_config->dst_addr) |
2190 | pch->fifo_addr = slave_config->dst_addr; | |
2191 | if (slave_config->dst_addr_width) | |
2192 | pch->burst_sz = __ffs(slave_config->dst_addr_width); | |
2193 | if (slave_config->dst_maxburst) | |
2194 | pch->burst_len = slave_config->dst_maxburst; | |
db8196df | 2195 | } else if (slave_config->direction == DMA_DEV_TO_MEM) { |
1d0c1d60 BK |
2196 | if (slave_config->src_addr) |
2197 | pch->fifo_addr = slave_config->src_addr; | |
2198 | if (slave_config->src_addr_width) | |
2199 | pch->burst_sz = __ffs(slave_config->src_addr_width); | |
2200 | if (slave_config->src_maxburst) | |
2201 | pch->burst_len = slave_config->src_maxburst; | |
2202 | } | |
2203 | break; | |
2204 | default: | |
f6f2421c | 2205 | dev_err(pch->dmac->ddma.dev, "Not supported command.\n"); |
1d0c1d60 BK |
2206 | return -ENXIO; |
2207 | } | |
b3040e40 JB |
2208 | |
2209 | return 0; | |
2210 | } | |
2211 | ||
2212 | static void pl330_free_chan_resources(struct dma_chan *chan) | |
2213 | { | |
2214 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2215 | unsigned long flags; | |
2216 | ||
b3040e40 JB |
2217 | tasklet_kill(&pch->task); |
2218 | ||
da331ba8 BZ |
2219 | spin_lock_irqsave(&pch->lock, flags); |
2220 | ||
65ad6060 LPC |
2221 | pl330_release_channel(pch->thread); |
2222 | pch->thread = NULL; | |
b3040e40 | 2223 | |
42bc9cf4 BK |
2224 | if (pch->cyclic) |
2225 | list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); | |
2226 | ||
b3040e40 JB |
2227 | spin_unlock_irqrestore(&pch->lock, flags); |
2228 | } | |
2229 | ||
2230 | static enum dma_status | |
2231 | pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, | |
2232 | struct dma_tx_state *txstate) | |
2233 | { | |
96a2af41 | 2234 | return dma_cookie_status(chan, cookie, txstate); |
b3040e40 JB |
2235 | } |
2236 | ||
2237 | static void pl330_issue_pending(struct dma_chan *chan) | |
2238 | { | |
04abf5da LPC |
2239 | struct dma_pl330_chan *pch = to_pchan(chan); |
2240 | unsigned long flags; | |
2241 | ||
2242 | spin_lock_irqsave(&pch->lock, flags); | |
2243 | list_splice_tail_init(&pch->submitted_list, &pch->work_list); | |
2244 | spin_unlock_irqrestore(&pch->lock, flags); | |
2245 | ||
2246 | pl330_tasklet((unsigned long)pch); | |
b3040e40 JB |
2247 | } |
2248 | ||
2249 | /* | |
2250 | * We returned the last one of the circular list of descriptor(s) | |
2251 | * from prep_xxx, so the argument to submit corresponds to the last | |
2252 | * descriptor of the list. | |
2253 | */ | |
2254 | static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) | |
2255 | { | |
2256 | struct dma_pl330_desc *desc, *last = to_desc(tx); | |
2257 | struct dma_pl330_chan *pch = to_pchan(tx->chan); | |
2258 | dma_cookie_t cookie; | |
2259 | unsigned long flags; | |
2260 | ||
2261 | spin_lock_irqsave(&pch->lock, flags); | |
2262 | ||
2263 | /* Assign cookies to all nodes */ | |
b3040e40 JB |
2264 | while (!list_empty(&last->node)) { |
2265 | desc = list_entry(last->node.next, struct dma_pl330_desc, node); | |
fc514460 LPC |
2266 | if (pch->cyclic) { |
2267 | desc->txd.callback = last->txd.callback; | |
2268 | desc->txd.callback_param = last->txd.callback_param; | |
2269 | } | |
b3040e40 | 2270 | |
884485e1 | 2271 | dma_cookie_assign(&desc->txd); |
b3040e40 | 2272 | |
04abf5da | 2273 | list_move_tail(&desc->node, &pch->submitted_list); |
b3040e40 JB |
2274 | } |
2275 | ||
884485e1 | 2276 | cookie = dma_cookie_assign(&last->txd); |
04abf5da | 2277 | list_add_tail(&last->node, &pch->submitted_list); |
b3040e40 JB |
2278 | spin_unlock_irqrestore(&pch->lock, flags); |
2279 | ||
2280 | return cookie; | |
2281 | } | |
2282 | ||
2283 | static inline void _init_desc(struct dma_pl330_desc *desc) | |
2284 | { | |
b3040e40 | 2285 | desc->rqcfg.swap = SWAP_NO; |
f0564c7e LPC |
2286 | desc->rqcfg.scctl = CCTRL0; |
2287 | desc->rqcfg.dcctl = CCTRL0; | |
b3040e40 JB |
2288 | desc->txd.tx_submit = pl330_tx_submit; |
2289 | ||
2290 | INIT_LIST_HEAD(&desc->node); | |
2291 | } | |
2292 | ||
2293 | /* Returns the number of descriptors added to the DMAC pool */ | |
f6f2421c | 2294 | static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count) |
b3040e40 JB |
2295 | { |
2296 | struct dma_pl330_desc *desc; | |
2297 | unsigned long flags; | |
2298 | int i; | |
2299 | ||
0baf8f6a | 2300 | desc = kcalloc(count, sizeof(*desc), flg); |
b3040e40 JB |
2301 | if (!desc) |
2302 | return 0; | |
2303 | ||
f6f2421c | 2304 | spin_lock_irqsave(&pl330->pool_lock, flags); |
b3040e40 JB |
2305 | |
2306 | for (i = 0; i < count; i++) { | |
2307 | _init_desc(&desc[i]); | |
f6f2421c | 2308 | list_add_tail(&desc[i].node, &pl330->desc_pool); |
b3040e40 JB |
2309 | } |
2310 | ||
f6f2421c | 2311 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
b3040e40 JB |
2312 | |
2313 | return count; | |
2314 | } | |
2315 | ||
f6f2421c | 2316 | static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330) |
b3040e40 JB |
2317 | { |
2318 | struct dma_pl330_desc *desc = NULL; | |
2319 | unsigned long flags; | |
2320 | ||
f6f2421c | 2321 | spin_lock_irqsave(&pl330->pool_lock, flags); |
b3040e40 | 2322 | |
f6f2421c LPC |
2323 | if (!list_empty(&pl330->desc_pool)) { |
2324 | desc = list_entry(pl330->desc_pool.next, | |
b3040e40 JB |
2325 | struct dma_pl330_desc, node); |
2326 | ||
2327 | list_del_init(&desc->node); | |
2328 | ||
2329 | desc->status = PREP; | |
2330 | desc->txd.callback = NULL; | |
2331 | } | |
2332 | ||
f6f2421c | 2333 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
b3040e40 JB |
2334 | |
2335 | return desc; | |
2336 | } | |
2337 | ||
2338 | static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) | |
2339 | { | |
f6f2421c | 2340 | struct pl330_dmac *pl330 = pch->dmac; |
cd072515 | 2341 | u8 *peri_id = pch->chan.private; |
b3040e40 JB |
2342 | struct dma_pl330_desc *desc; |
2343 | ||
2344 | /* Pluck one desc from the pool of DMAC */ | |
f6f2421c | 2345 | desc = pluck_desc(pl330); |
b3040e40 JB |
2346 | |
2347 | /* If the DMAC pool is empty, alloc new */ | |
2348 | if (!desc) { | |
f6f2421c | 2349 | if (!add_desc(pl330, GFP_ATOMIC, 1)) |
b3040e40 JB |
2350 | return NULL; |
2351 | ||
2352 | /* Try again */ | |
f6f2421c | 2353 | desc = pluck_desc(pl330); |
b3040e40 | 2354 | if (!desc) { |
f6f2421c | 2355 | dev_err(pch->dmac->ddma.dev, |
b3040e40 JB |
2356 | "%s:%d ALERT!\n", __func__, __LINE__); |
2357 | return NULL; | |
2358 | } | |
2359 | } | |
2360 | ||
2361 | /* Initialize the descriptor */ | |
2362 | desc->pchan = pch; | |
2363 | desc->txd.cookie = 0; | |
2364 | async_tx_ack(&desc->txd); | |
2365 | ||
9dc5a315 | 2366 | desc->peri = peri_id ? pch->chan.chan_id : 0; |
f6f2421c | 2367 | desc->rqcfg.pcfg = &pch->dmac->pcfg; |
b3040e40 JB |
2368 | |
2369 | dma_async_tx_descriptor_init(&desc->txd, &pch->chan); | |
2370 | ||
2371 | return desc; | |
2372 | } | |
2373 | ||
2374 | static inline void fill_px(struct pl330_xfer *px, | |
2375 | dma_addr_t dst, dma_addr_t src, size_t len) | |
2376 | { | |
b3040e40 JB |
2377 | px->bytes = len; |
2378 | px->dst_addr = dst; | |
2379 | px->src_addr = src; | |
2380 | } | |
2381 | ||
2382 | static struct dma_pl330_desc * | |
2383 | __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, | |
2384 | dma_addr_t src, size_t len) | |
2385 | { | |
2386 | struct dma_pl330_desc *desc = pl330_get_desc(pch); | |
2387 | ||
2388 | if (!desc) { | |
f6f2421c | 2389 | dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", |
b3040e40 JB |
2390 | __func__, __LINE__); |
2391 | return NULL; | |
2392 | } | |
2393 | ||
2394 | /* | |
2395 | * Ideally we should lookout for reqs bigger than | |
2396 | * those that can be programmed with 256 bytes of | |
2397 | * MC buffer, but considering a req size is seldom | |
2398 | * going to be word-unaligned and more than 200MB, | |
2399 | * we take it easy. | |
2400 | * Also, should the limit is reached we'd rather | |
2401 | * have the platform increase MC buffer size than | |
2402 | * complicating this API driver. | |
2403 | */ | |
2404 | fill_px(&desc->px, dst, src, len); | |
2405 | ||
2406 | return desc; | |
2407 | } | |
2408 | ||
2409 | /* Call after fixing burst size */ | |
2410 | static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) | |
2411 | { | |
2412 | struct dma_pl330_chan *pch = desc->pchan; | |
f6f2421c | 2413 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2414 | int burst_len; |
2415 | ||
f6f2421c LPC |
2416 | burst_len = pl330->pcfg.data_bus_width / 8; |
2417 | burst_len *= pl330->pcfg.data_buf_dep; | |
b3040e40 JB |
2418 | burst_len >>= desc->rqcfg.brst_size; |
2419 | ||
2420 | /* src/dst_burst_len can't be more than 16 */ | |
2421 | if (burst_len > 16) | |
2422 | burst_len = 16; | |
2423 | ||
2424 | while (burst_len > 1) { | |
2425 | if (!(len % (burst_len << desc->rqcfg.brst_size))) | |
2426 | break; | |
2427 | burst_len--; | |
2428 | } | |
2429 | ||
2430 | return burst_len; | |
2431 | } | |
2432 | ||
42bc9cf4 BK |
2433 | static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( |
2434 | struct dma_chan *chan, dma_addr_t dma_addr, size_t len, | |
185ecb5f | 2435 | size_t period_len, enum dma_transfer_direction direction, |
ec8b5e48 | 2436 | unsigned long flags, void *context) |
42bc9cf4 | 2437 | { |
fc514460 | 2438 | struct dma_pl330_desc *desc = NULL, *first = NULL; |
42bc9cf4 | 2439 | struct dma_pl330_chan *pch = to_pchan(chan); |
f6f2421c | 2440 | struct pl330_dmac *pl330 = pch->dmac; |
fc514460 | 2441 | unsigned int i; |
42bc9cf4 BK |
2442 | dma_addr_t dst; |
2443 | dma_addr_t src; | |
2444 | ||
fc514460 | 2445 | if (len % period_len != 0) |
42bc9cf4 | 2446 | return NULL; |
42bc9cf4 | 2447 | |
fc514460 | 2448 | if (!is_slave_direction(direction)) { |
f6f2421c | 2449 | dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n", |
42bc9cf4 BK |
2450 | __func__, __LINE__); |
2451 | return NULL; | |
2452 | } | |
2453 | ||
fc514460 LPC |
2454 | for (i = 0; i < len / period_len; i++) { |
2455 | desc = pl330_get_desc(pch); | |
2456 | if (!desc) { | |
f6f2421c | 2457 | dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", |
fc514460 | 2458 | __func__, __LINE__); |
42bc9cf4 | 2459 | |
fc514460 LPC |
2460 | if (!first) |
2461 | return NULL; | |
2462 | ||
f6f2421c | 2463 | spin_lock_irqsave(&pl330->pool_lock, flags); |
fc514460 LPC |
2464 | |
2465 | while (!list_empty(&first->node)) { | |
2466 | desc = list_entry(first->node.next, | |
2467 | struct dma_pl330_desc, node); | |
f6f2421c | 2468 | list_move_tail(&desc->node, &pl330->desc_pool); |
fc514460 LPC |
2469 | } |
2470 | ||
f6f2421c | 2471 | list_move_tail(&first->node, &pl330->desc_pool); |
fc514460 | 2472 | |
f6f2421c | 2473 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
42bc9cf4 | 2474 | |
fc514460 LPC |
2475 | return NULL; |
2476 | } | |
2477 | ||
2478 | switch (direction) { | |
2479 | case DMA_MEM_TO_DEV: | |
2480 | desc->rqcfg.src_inc = 1; | |
2481 | desc->rqcfg.dst_inc = 0; | |
fc514460 LPC |
2482 | src = dma_addr; |
2483 | dst = pch->fifo_addr; | |
2484 | break; | |
2485 | case DMA_DEV_TO_MEM: | |
2486 | desc->rqcfg.src_inc = 0; | |
2487 | desc->rqcfg.dst_inc = 1; | |
fc514460 LPC |
2488 | src = pch->fifo_addr; |
2489 | dst = dma_addr; | |
2490 | break; | |
2491 | default: | |
2492 | break; | |
2493 | } | |
2494 | ||
9dc5a315 | 2495 | desc->rqtype = direction; |
fc514460 LPC |
2496 | desc->rqcfg.brst_size = pch->burst_sz; |
2497 | desc->rqcfg.brst_len = 1; | |
2498 | fill_px(&desc->px, dst, src, period_len); | |
2499 | ||
2500 | if (!first) | |
2501 | first = desc; | |
2502 | else | |
2503 | list_add_tail(&desc->node, &first->node); | |
2504 | ||
2505 | dma_addr += period_len; | |
2506 | } | |
2507 | ||
2508 | if (!desc) | |
2509 | return NULL; | |
2510 | ||
2511 | pch->cyclic = true; | |
2512 | desc->txd.flags = flags; | |
42bc9cf4 BK |
2513 | |
2514 | return &desc->txd; | |
2515 | } | |
2516 | ||
b3040e40 JB |
2517 | static struct dma_async_tx_descriptor * |
2518 | pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, | |
2519 | dma_addr_t src, size_t len, unsigned long flags) | |
2520 | { | |
2521 | struct dma_pl330_desc *desc; | |
2522 | struct dma_pl330_chan *pch = to_pchan(chan); | |
f6f2421c | 2523 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2524 | int burst; |
2525 | ||
4e0e6109 | 2526 | if (unlikely(!pch || !len)) |
b3040e40 JB |
2527 | return NULL; |
2528 | ||
b3040e40 JB |
2529 | desc = __pl330_prep_dma_memcpy(pch, dst, src, len); |
2530 | if (!desc) | |
2531 | return NULL; | |
2532 | ||
2533 | desc->rqcfg.src_inc = 1; | |
2534 | desc->rqcfg.dst_inc = 1; | |
9dc5a315 | 2535 | desc->rqtype = DMA_MEM_TO_MEM; |
b3040e40 JB |
2536 | |
2537 | /* Select max possible burst size */ | |
f6f2421c | 2538 | burst = pl330->pcfg.data_bus_width / 8; |
b3040e40 JB |
2539 | |
2540 | while (burst > 1) { | |
2541 | if (!(len % burst)) | |
2542 | break; | |
2543 | burst /= 2; | |
2544 | } | |
2545 | ||
2546 | desc->rqcfg.brst_size = 0; | |
2547 | while (burst != (1 << desc->rqcfg.brst_size)) | |
2548 | desc->rqcfg.brst_size++; | |
2549 | ||
2550 | desc->rqcfg.brst_len = get_burst_len(desc, len); | |
2551 | ||
2552 | desc->txd.flags = flags; | |
2553 | ||
2554 | return &desc->txd; | |
2555 | } | |
2556 | ||
f6f2421c | 2557 | static void __pl330_giveback_desc(struct pl330_dmac *pl330, |
52a9d179 CP |
2558 | struct dma_pl330_desc *first) |
2559 | { | |
2560 | unsigned long flags; | |
2561 | struct dma_pl330_desc *desc; | |
2562 | ||
2563 | if (!first) | |
2564 | return; | |
2565 | ||
f6f2421c | 2566 | spin_lock_irqsave(&pl330->pool_lock, flags); |
52a9d179 CP |
2567 | |
2568 | while (!list_empty(&first->node)) { | |
2569 | desc = list_entry(first->node.next, | |
2570 | struct dma_pl330_desc, node); | |
f6f2421c | 2571 | list_move_tail(&desc->node, &pl330->desc_pool); |
52a9d179 CP |
2572 | } |
2573 | ||
f6f2421c | 2574 | list_move_tail(&first->node, &pl330->desc_pool); |
52a9d179 | 2575 | |
f6f2421c | 2576 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
52a9d179 CP |
2577 | } |
2578 | ||
b3040e40 JB |
2579 | static struct dma_async_tx_descriptor * |
2580 | pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 2581 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 2582 | unsigned long flg, void *context) |
b3040e40 JB |
2583 | { |
2584 | struct dma_pl330_desc *first, *desc = NULL; | |
2585 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 | 2586 | struct scatterlist *sg; |
1b9bb715 | 2587 | int i; |
b3040e40 JB |
2588 | dma_addr_t addr; |
2589 | ||
cd072515 | 2590 | if (unlikely(!pch || !sgl || !sg_len)) |
b3040e40 JB |
2591 | return NULL; |
2592 | ||
1b9bb715 | 2593 | addr = pch->fifo_addr; |
b3040e40 JB |
2594 | |
2595 | first = NULL; | |
2596 | ||
2597 | for_each_sg(sgl, sg, sg_len, i) { | |
2598 | ||
2599 | desc = pl330_get_desc(pch); | |
2600 | if (!desc) { | |
f6f2421c | 2601 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 | 2602 | |
f6f2421c | 2603 | dev_err(pch->dmac->ddma.dev, |
b3040e40 JB |
2604 | "%s:%d Unable to fetch desc\n", |
2605 | __func__, __LINE__); | |
f6f2421c | 2606 | __pl330_giveback_desc(pl330, first); |
b3040e40 JB |
2607 | |
2608 | return NULL; | |
2609 | } | |
2610 | ||
2611 | if (!first) | |
2612 | first = desc; | |
2613 | else | |
2614 | list_add_tail(&desc->node, &first->node); | |
2615 | ||
db8196df | 2616 | if (direction == DMA_MEM_TO_DEV) { |
b3040e40 JB |
2617 | desc->rqcfg.src_inc = 1; |
2618 | desc->rqcfg.dst_inc = 0; | |
2619 | fill_px(&desc->px, | |
2620 | addr, sg_dma_address(sg), sg_dma_len(sg)); | |
2621 | } else { | |
2622 | desc->rqcfg.src_inc = 0; | |
2623 | desc->rqcfg.dst_inc = 1; | |
2624 | fill_px(&desc->px, | |
2625 | sg_dma_address(sg), addr, sg_dma_len(sg)); | |
2626 | } | |
2627 | ||
1b9bb715 | 2628 | desc->rqcfg.brst_size = pch->burst_sz; |
b3040e40 | 2629 | desc->rqcfg.brst_len = 1; |
9dc5a315 | 2630 | desc->rqtype = direction; |
b3040e40 JB |
2631 | } |
2632 | ||
2633 | /* Return the last desc in the chain */ | |
2634 | desc->txd.flags = flg; | |
2635 | return &desc->txd; | |
2636 | } | |
2637 | ||
2638 | static irqreturn_t pl330_irq_handler(int irq, void *data) | |
2639 | { | |
2640 | if (pl330_update(data)) | |
2641 | return IRQ_HANDLED; | |
2642 | else | |
2643 | return IRQ_NONE; | |
2644 | } | |
2645 | ||
ca38ff13 LPC |
2646 | #define PL330_DMA_BUSWIDTHS \ |
2647 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ | |
2648 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
2649 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
2650 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ | |
2651 | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | |
2652 | ||
2653 | static int pl330_dma_device_slave_caps(struct dma_chan *dchan, | |
2654 | struct dma_slave_caps *caps) | |
2655 | { | |
2656 | caps->src_addr_widths = PL330_DMA_BUSWIDTHS; | |
2657 | caps->dstn_addr_widths = PL330_DMA_BUSWIDTHS; | |
2658 | caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
2659 | caps->cmd_pause = false; | |
2660 | caps->cmd_terminate = true; | |
bfb9bb42 | 2661 | caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; |
ca38ff13 | 2662 | |
ca38ff13 LPC |
2663 | return 0; |
2664 | } | |
2665 | ||
463a1f8b | 2666 | static int |
aa25afad | 2667 | pl330_probe(struct amba_device *adev, const struct amba_id *id) |
b3040e40 JB |
2668 | { |
2669 | struct dma_pl330_platdata *pdat; | |
f6f2421c LPC |
2670 | struct pl330_config *pcfg; |
2671 | struct pl330_dmac *pl330; | |
0b94c577 | 2672 | struct dma_pl330_chan *pch, *_p; |
b3040e40 JB |
2673 | struct dma_device *pd; |
2674 | struct resource *res; | |
2675 | int i, ret, irq; | |
4e0e6109 | 2676 | int num_chan; |
b3040e40 | 2677 | |
d4adcc01 | 2678 | pdat = dev_get_platdata(&adev->dev); |
b3040e40 | 2679 | |
64113016 RK |
2680 | ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); |
2681 | if (ret) | |
2682 | return ret; | |
2683 | ||
b3040e40 | 2684 | /* Allocate a new DMAC and its Channels */ |
f6f2421c LPC |
2685 | pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL); |
2686 | if (!pl330) { | |
b3040e40 JB |
2687 | dev_err(&adev->dev, "unable to allocate mem\n"); |
2688 | return -ENOMEM; | |
2689 | } | |
2690 | ||
f6f2421c | 2691 | pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0; |
b3040e40 JB |
2692 | |
2693 | res = &adev->res; | |
f6f2421c LPC |
2694 | pl330->base = devm_ioremap_resource(&adev->dev, res); |
2695 | if (IS_ERR(pl330->base)) | |
2696 | return PTR_ERR(pl330->base); | |
b3040e40 | 2697 | |
f6f2421c | 2698 | amba_set_drvdata(adev, pl330); |
a2f5203f | 2699 | |
02808b42 | 2700 | for (i = 0; i < AMBA_NR_IRQS; i++) { |
e98b3caf MS |
2701 | irq = adev->irq[i]; |
2702 | if (irq) { | |
2703 | ret = devm_request_irq(&adev->dev, irq, | |
2704 | pl330_irq_handler, 0, | |
f6f2421c | 2705 | dev_name(&adev->dev), pl330); |
e98b3caf MS |
2706 | if (ret) |
2707 | return ret; | |
2708 | } else { | |
2709 | break; | |
2710 | } | |
2711 | } | |
b3040e40 | 2712 | |
f6f2421c LPC |
2713 | pcfg = &pl330->pcfg; |
2714 | ||
2715 | pcfg->periph_id = adev->periphid; | |
2716 | ret = pl330_add(pl330); | |
b3040e40 | 2717 | if (ret) |
173e838c | 2718 | return ret; |
b3040e40 | 2719 | |
f6f2421c LPC |
2720 | INIT_LIST_HEAD(&pl330->desc_pool); |
2721 | spin_lock_init(&pl330->pool_lock); | |
b3040e40 JB |
2722 | |
2723 | /* Create a descriptor pool of default size */ | |
f6f2421c | 2724 | if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC)) |
b3040e40 JB |
2725 | dev_warn(&adev->dev, "unable to allocate desc\n"); |
2726 | ||
f6f2421c | 2727 | pd = &pl330->ddma; |
b3040e40 JB |
2728 | INIT_LIST_HEAD(&pd->channels); |
2729 | ||
2730 | /* Initialize channel parameters */ | |
c8473828 | 2731 | if (pdat) |
f6f2421c | 2732 | num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan); |
c8473828 | 2733 | else |
f6f2421c | 2734 | num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan); |
c8473828 | 2735 | |
f6f2421c | 2736 | pl330->num_peripherals = num_chan; |
70cbb163 | 2737 | |
f6f2421c LPC |
2738 | pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); |
2739 | if (!pl330->peripherals) { | |
61c6e753 | 2740 | ret = -ENOMEM; |
f6f2421c | 2741 | dev_err(&adev->dev, "unable to allocate pl330->peripherals\n"); |
e4d43c17 | 2742 | goto probe_err2; |
61c6e753 | 2743 | } |
b3040e40 | 2744 | |
4e0e6109 | 2745 | for (i = 0; i < num_chan; i++) { |
f6f2421c | 2746 | pch = &pl330->peripherals[i]; |
93ed5544 TA |
2747 | if (!adev->dev.of_node) |
2748 | pch->chan.private = pdat ? &pdat->peri_id[i] : NULL; | |
2749 | else | |
2750 | pch->chan.private = adev->dev.of_node; | |
b3040e40 | 2751 | |
04abf5da | 2752 | INIT_LIST_HEAD(&pch->submitted_list); |
b3040e40 | 2753 | INIT_LIST_HEAD(&pch->work_list); |
39ff8613 | 2754 | INIT_LIST_HEAD(&pch->completed_list); |
b3040e40 | 2755 | spin_lock_init(&pch->lock); |
65ad6060 | 2756 | pch->thread = NULL; |
b3040e40 | 2757 | pch->chan.device = pd; |
f6f2421c | 2758 | pch->dmac = pl330; |
b3040e40 JB |
2759 | |
2760 | /* Add the channel to the DMAC list */ | |
b3040e40 JB |
2761 | list_add_tail(&pch->chan.device_node, &pd->channels); |
2762 | } | |
2763 | ||
2764 | pd->dev = &adev->dev; | |
93ed5544 | 2765 | if (pdat) { |
cd072515 | 2766 | pd->cap_mask = pdat->cap_mask; |
93ed5544 | 2767 | } else { |
cd072515 | 2768 | dma_cap_set(DMA_MEMCPY, pd->cap_mask); |
f6f2421c | 2769 | if (pcfg->num_peri) { |
93ed5544 TA |
2770 | dma_cap_set(DMA_SLAVE, pd->cap_mask); |
2771 | dma_cap_set(DMA_CYCLIC, pd->cap_mask); | |
5557a419 | 2772 | dma_cap_set(DMA_PRIVATE, pd->cap_mask); |
93ed5544 TA |
2773 | } |
2774 | } | |
b3040e40 JB |
2775 | |
2776 | pd->device_alloc_chan_resources = pl330_alloc_chan_resources; | |
2777 | pd->device_free_chan_resources = pl330_free_chan_resources; | |
2778 | pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; | |
42bc9cf4 | 2779 | pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; |
b3040e40 JB |
2780 | pd->device_tx_status = pl330_tx_status; |
2781 | pd->device_prep_slave_sg = pl330_prep_slave_sg; | |
2782 | pd->device_control = pl330_control; | |
2783 | pd->device_issue_pending = pl330_issue_pending; | |
ca38ff13 | 2784 | pd->device_slave_caps = pl330_dma_device_slave_caps; |
b3040e40 JB |
2785 | |
2786 | ret = dma_async_device_register(pd); | |
2787 | if (ret) { | |
2788 | dev_err(&adev->dev, "unable to register DMAC\n"); | |
0b94c577 PV |
2789 | goto probe_err3; |
2790 | } | |
2791 | ||
2792 | if (adev->dev.of_node) { | |
2793 | ret = of_dma_controller_register(adev->dev.of_node, | |
f6f2421c | 2794 | of_dma_pl330_xlate, pl330); |
0b94c577 PV |
2795 | if (ret) { |
2796 | dev_err(&adev->dev, | |
2797 | "unable to register DMA to the generic DT DMA helpers\n"); | |
2798 | } | |
b3040e40 | 2799 | } |
b714b84e | 2800 | |
f6f2421c | 2801 | adev->dev.dma_parms = &pl330->dma_parms; |
b714b84e | 2802 | |
dbaf6d85 VK |
2803 | /* |
2804 | * This is the limit for transfers with a buswidth of 1, larger | |
2805 | * buswidths will have larger limits. | |
2806 | */ | |
2807 | ret = dma_set_max_seg_size(&adev->dev, 1900800); | |
2808 | if (ret) | |
2809 | dev_err(&adev->dev, "unable to set the seg size\n"); | |
2810 | ||
b3040e40 | 2811 | |
b3040e40 JB |
2812 | dev_info(&adev->dev, |
2813 | "Loaded driver for PL330 DMAC-%d\n", adev->periphid); | |
2814 | dev_info(&adev->dev, | |
2815 | "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", | |
f6f2421c LPC |
2816 | pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan, |
2817 | pcfg->num_peri, pcfg->num_events); | |
b3040e40 JB |
2818 | |
2819 | return 0; | |
0b94c577 | 2820 | probe_err3: |
0b94c577 | 2821 | /* Idle the DMAC */ |
f6f2421c | 2822 | list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, |
0b94c577 PV |
2823 | chan.device_node) { |
2824 | ||
2825 | /* Remove the channel */ | |
2826 | list_del(&pch->chan.device_node); | |
2827 | ||
2828 | /* Flush the channel */ | |
2829 | pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); | |
2830 | pl330_free_chan_resources(&pch->chan); | |
2831 | } | |
b3040e40 | 2832 | probe_err2: |
f6f2421c | 2833 | pl330_del(pl330); |
b3040e40 JB |
2834 | |
2835 | return ret; | |
2836 | } | |
2837 | ||
4bf27b8b | 2838 | static int pl330_remove(struct amba_device *adev) |
b3040e40 | 2839 | { |
f6f2421c | 2840 | struct pl330_dmac *pl330 = amba_get_drvdata(adev); |
b3040e40 | 2841 | struct dma_pl330_chan *pch, *_p; |
b3040e40 | 2842 | |
0b94c577 PV |
2843 | if (adev->dev.of_node) |
2844 | of_dma_controller_free(adev->dev.of_node); | |
421da89a | 2845 | |
f6f2421c | 2846 | dma_async_device_unregister(&pl330->ddma); |
b3040e40 JB |
2847 | |
2848 | /* Idle the DMAC */ | |
f6f2421c | 2849 | list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, |
b3040e40 JB |
2850 | chan.device_node) { |
2851 | ||
2852 | /* Remove the channel */ | |
2853 | list_del(&pch->chan.device_node); | |
2854 | ||
2855 | /* Flush the channel */ | |
2856 | pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); | |
2857 | pl330_free_chan_resources(&pch->chan); | |
2858 | } | |
2859 | ||
f6f2421c | 2860 | pl330_del(pl330); |
b3040e40 | 2861 | |
b3040e40 JB |
2862 | return 0; |
2863 | } | |
2864 | ||
2865 | static struct amba_id pl330_ids[] = { | |
2866 | { | |
2867 | .id = 0x00041330, | |
2868 | .mask = 0x000fffff, | |
2869 | }, | |
2870 | { 0, 0 }, | |
2871 | }; | |
2872 | ||
e8fa516a DM |
2873 | MODULE_DEVICE_TABLE(amba, pl330_ids); |
2874 | ||
b3040e40 JB |
2875 | static struct amba_driver pl330_driver = { |
2876 | .drv = { | |
2877 | .owner = THIS_MODULE, | |
2878 | .name = "dma-pl330", | |
2879 | }, | |
2880 | .id_table = pl330_ids, | |
2881 | .probe = pl330_probe, | |
2882 | .remove = pl330_remove, | |
2883 | }; | |
2884 | ||
9e5ed094 | 2885 | module_amba_driver(pl330_driver); |
b3040e40 JB |
2886 | |
2887 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); | |
2888 | MODULE_DESCRIPTION("API Driver for PL330 DMAC"); | |
2889 | MODULE_LICENSE("GPL"); |