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12458ea0 AG |
1 | /* |
2 | * 440SPe's XOR engines support header file | |
3 | * | |
4 | * 2006-2009 (C) DENX Software Engineering. | |
5 | * | |
6 | * Author: Yuri Tikhonov <yur@emcraft.com> | |
7 | * | |
8 | * This file is licensed under the term of the GNU General Public License | |
9 | * version 2. The program licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
11 | */ | |
12 | ||
13 | #ifndef _PPC440SPE_XOR_H | |
14 | #define _PPC440SPE_XOR_H | |
15 | ||
16 | #include <linux/types.h> | |
17 | ||
18 | /* Number of XOR engines available on the contoller */ | |
19 | #define XOR_ENGINES_NUM 1 | |
20 | ||
21 | /* Number of operands supported in the h/w */ | |
22 | #define XOR_MAX_OPS 16 | |
23 | ||
24 | /* | |
25 | * XOR Command Block Control Register bits | |
26 | */ | |
27 | #define XOR_CBCR_LNK_BIT (1<<31) /* link present */ | |
28 | #define XOR_CBCR_TGT_BIT (1<<30) /* target present */ | |
29 | #define XOR_CBCR_CBCE_BIT (1<<29) /* command block compete enable */ | |
30 | #define XOR_CBCR_RNZE_BIT (1<<28) /* result not zero enable */ | |
31 | #define XOR_CBCR_XNOR_BIT (1<<15) /* XOR/XNOR */ | |
32 | #define XOR_CDCR_OAC_MSK (0x7F) /* operand address count */ | |
33 | ||
34 | /* | |
35 | * XORCore Status Register bits | |
36 | */ | |
37 | #define XOR_SR_XCP_BIT (1<<31) /* core processing */ | |
38 | #define XOR_SR_ICB_BIT (1<<17) /* invalid CB */ | |
39 | #define XOR_SR_IC_BIT (1<<16) /* invalid command */ | |
40 | #define XOR_SR_IPE_BIT (1<<15) /* internal parity error */ | |
41 | #define XOR_SR_RNZ_BIT (1<<2) /* result not Zero */ | |
42 | #define XOR_SR_CBC_BIT (1<<1) /* CB complete */ | |
43 | #define XOR_SR_CBLC_BIT (1<<0) /* CB list complete */ | |
44 | ||
45 | /* | |
46 | * XORCore Control Set and Reset Register bits | |
47 | */ | |
48 | #define XOR_CRSR_XASR_BIT (1<<31) /* soft reset */ | |
49 | #define XOR_CRSR_XAE_BIT (1<<30) /* enable */ | |
50 | #define XOR_CRSR_RCBE_BIT (1<<29) /* refetch CB enable */ | |
51 | #define XOR_CRSR_PAUS_BIT (1<<28) /* pause */ | |
52 | #define XOR_CRSR_64BA_BIT (1<<27) /* 64/32 CB format */ | |
53 | #define XOR_CRSR_CLP_BIT (1<<25) /* continue list processing */ | |
54 | ||
55 | /* | |
56 | * XORCore Interrupt Enable Register | |
57 | */ | |
58 | #define XOR_IE_ICBIE_BIT (1<<17) /* Invalid Command Block IRQ Enable */ | |
59 | #define XOR_IE_ICIE_BIT (1<<16) /* Invalid Command IRQ Enable */ | |
60 | #define XOR_IE_RPTIE_BIT (1<<14) /* Read PLB Timeout Error IRQ Enable */ | |
61 | #define XOR_IE_CBCIE_BIT (1<<1) /* CB complete interrupt enable */ | |
62 | #define XOR_IE_CBLCI_BIT (1<<0) /* CB list complete interrupt enable */ | |
63 | ||
64 | /* | |
65 | * XOR Accelerator engine Command Block Type | |
66 | */ | |
67 | struct xor_cb { | |
68 | /* | |
69 | * Basic 64-bit format XOR CB (Table 19-1, p.463, 440spe_um_1_22.pdf) | |
70 | */ | |
71 | u32 cbc; /* control */ | |
72 | u32 cbbc; /* byte count */ | |
73 | u32 cbs; /* status */ | |
74 | u8 pad0[4]; /* reserved */ | |
75 | u32 cbtah; /* target address high */ | |
76 | u32 cbtal; /* target address low */ | |
77 | u32 cblah; /* link address high */ | |
78 | u32 cblal; /* link address low */ | |
79 | struct { | |
80 | u32 h; | |
81 | u32 l; | |
82 | } __attribute__ ((packed)) ops[16]; | |
83 | } __attribute__ ((packed)); | |
84 | ||
85 | /* | |
86 | * XOR hardware registers Table 19-3, UM 1.22 | |
87 | */ | |
88 | struct xor_regs { | |
89 | u32 op_ar[16][2]; /* operand address[0]-high,[1]-low registers */ | |
90 | u8 pad0[352]; /* reserved */ | |
91 | u32 cbcr; /* CB control register */ | |
92 | u32 cbbcr; /* CB byte count register */ | |
93 | u32 cbsr; /* CB status register */ | |
94 | u8 pad1[4]; /* reserved */ | |
95 | u32 cbtahr; /* operand target address high register */ | |
96 | u32 cbtalr; /* operand target address low register */ | |
97 | u32 cblahr; /* CB link address high register */ | |
98 | u32 cblalr; /* CB link address low register */ | |
99 | u32 crsr; /* control set register */ | |
100 | u32 crrr; /* control reset register */ | |
101 | u32 ccbahr; /* current CB address high register */ | |
102 | u32 ccbalr; /* current CB address low register */ | |
103 | u32 plbr; /* PLB configuration register */ | |
104 | u32 ier; /* interrupt enable register */ | |
105 | u32 pecr; /* parity error count register */ | |
106 | u32 sr; /* status register */ | |
107 | u32 revidr; /* revision ID register */ | |
108 | }; | |
109 | ||
110 | #endif /* _PPC440SPE_XOR_H */ |