Commit | Line | Data |
---|---|---|
d8902adc NI |
1 | /* |
2 | * Renesas SuperH DMA Engine support | |
3 | * | |
4 | * base is drivers/dma/flsdma.c | |
5 | * | |
ce3a1ab7 | 6 | * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
d8902adc NI |
7 | * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> |
8 | * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. | |
9 | * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. | |
10 | * | |
11 | * This is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * - DMA of SuperH does not have Hardware DMA chain mode. | |
17 | * - MAX DMA size is 16MB. | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/module.h> | |
4981c4dc GL |
23 | #include <linux/of.h> |
24 | #include <linux/of_device.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
d8902adc NI |
26 | #include <linux/interrupt.h> |
27 | #include <linux/dmaengine.h> | |
28 | #include <linux/delay.h> | |
d8902adc | 29 | #include <linux/platform_device.h> |
20f2a3b5 | 30 | #include <linux/pm_runtime.h> |
b2623a61 | 31 | #include <linux/sh_dma.h> |
03aa18f5 PM |
32 | #include <linux/notifier.h> |
33 | #include <linux/kdebug.h> | |
34 | #include <linux/spinlock.h> | |
35 | #include <linux/rculist.h> | |
d2ebfb33 | 36 | |
e95be94b | 37 | #include "../dmaengine.h" |
d8902adc NI |
38 | #include "shdma.h" |
39 | ||
4620ad54 GL |
40 | /* DMA register */ |
41 | #define SAR 0x00 | |
42 | #define DAR 0x04 | |
43 | #define TCR 0x08 | |
44 | #define CHCR 0x0C | |
45 | #define DMAOR 0x40 | |
46 | ||
47 | #define TEND 0x18 /* USB-DMAC */ | |
48 | ||
ce3a1ab7 | 49 | #define SH_DMAE_DRV_NAME "sh-dma-engine" |
d8902adc | 50 | |
8b1935e6 GL |
51 | /* Default MEMCPY transfer size = 2^2 = 4 bytes */ |
52 | #define LOG2_DEFAULT_XFER_SIZE 2 | |
ce3a1ab7 GL |
53 | #define SH_DMA_SLAVE_NUMBER 256 |
54 | #define SH_DMA_TCR_MAX (16 * 1024 * 1024 - 1) | |
d8902adc | 55 | |
03aa18f5 PM |
56 | /* |
57 | * Used for write-side mutual exclusion for the global device list, | |
2dc66667 | 58 | * read-side synchronization by way of RCU, and per-controller data. |
03aa18f5 PM |
59 | */ |
60 | static DEFINE_SPINLOCK(sh_dmae_lock); | |
61 | static LIST_HEAD(sh_dmae_devices); | |
62 | ||
ca8b3878 GL |
63 | /* |
64 | * Different DMAC implementations provide different ways to clear DMA channels: | |
65 | * (1) none - no CHCLR registers are available | |
66 | * (2) one CHCLR register per channel - 0 has to be written to it to clear | |
67 | * channel buffers | |
68 | * (3) one CHCLR per several channels - 1 has to be written to the bit, | |
69 | * corresponding to the specific channel to reset it | |
70 | */ | |
a28a94e8 | 71 | static void channel_clear(struct sh_dmae_chan *sh_dc) |
c11b46c3 GL |
72 | { |
73 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | |
ca8b3878 GL |
74 | const struct sh_dmae_channel *chan_pdata = shdev->pdata->channel + |
75 | sh_dc->shdma_chan.id; | |
76 | u32 val = shdev->pdata->chclr_bitwise ? 1 << chan_pdata->chclr_bit : 0; | |
c11b46c3 | 77 | |
ca8b3878 | 78 | __raw_writel(val, shdev->chan_reg + chan_pdata->chclr_offset); |
c11b46c3 | 79 | } |
3542a113 | 80 | |
d8902adc NI |
81 | static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) |
82 | { | |
115357e9 | 83 | __raw_writel(data, sh_dc->base + reg); |
d8902adc NI |
84 | } |
85 | ||
86 | static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) | |
87 | { | |
115357e9 | 88 | return __raw_readl(sh_dc->base + reg); |
027811b9 GL |
89 | } |
90 | ||
91 | static u16 dmaor_read(struct sh_dmae_device *shdev) | |
92 | { | |
115357e9 | 93 | void __iomem *addr = shdev->chan_reg + DMAOR; |
e76c3af8 KM |
94 | |
95 | if (shdev->pdata->dmaor_is_32bit) | |
96 | return __raw_readl(addr); | |
97 | else | |
98 | return __raw_readw(addr); | |
027811b9 GL |
99 | } |
100 | ||
101 | static void dmaor_write(struct sh_dmae_device *shdev, u16 data) | |
102 | { | |
115357e9 | 103 | void __iomem *addr = shdev->chan_reg + DMAOR; |
e76c3af8 KM |
104 | |
105 | if (shdev->pdata->dmaor_is_32bit) | |
106 | __raw_writel(data, addr); | |
107 | else | |
108 | __raw_writew(data, addr); | |
d8902adc NI |
109 | } |
110 | ||
5899a723 KM |
111 | static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data) |
112 | { | |
113 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | |
114 | ||
115357e9 | 115 | __raw_writel(data, sh_dc->base + shdev->chcr_offset); |
5899a723 KM |
116 | } |
117 | ||
118 | static u32 chcr_read(struct sh_dmae_chan *sh_dc) | |
119 | { | |
120 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | |
121 | ||
115357e9 | 122 | return __raw_readl(sh_dc->base + shdev->chcr_offset); |
d8902adc NI |
123 | } |
124 | ||
d8902adc NI |
125 | /* |
126 | * Reset DMA controller | |
127 | * | |
128 | * SH7780 has two DMAOR register | |
129 | */ | |
027811b9 | 130 | static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev) |
d8902adc | 131 | { |
2dc66667 GL |
132 | unsigned short dmaor; |
133 | unsigned long flags; | |
134 | ||
135 | spin_lock_irqsave(&sh_dmae_lock, flags); | |
d8902adc | 136 | |
2dc66667 | 137 | dmaor = dmaor_read(shdev); |
027811b9 | 138 | dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME)); |
2dc66667 GL |
139 | |
140 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | |
d8902adc NI |
141 | } |
142 | ||
027811b9 | 143 | static int sh_dmae_rst(struct sh_dmae_device *shdev) |
d8902adc NI |
144 | { |
145 | unsigned short dmaor; | |
2dc66667 | 146 | unsigned long flags; |
d8902adc | 147 | |
2dc66667 | 148 | spin_lock_irqsave(&sh_dmae_lock, flags); |
d8902adc | 149 | |
2dc66667 GL |
150 | dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME); |
151 | ||
c11b46c3 GL |
152 | if (shdev->pdata->chclr_present) { |
153 | int i; | |
154 | for (i = 0; i < shdev->pdata->channel_num; i++) { | |
155 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; | |
156 | if (sh_chan) | |
a28a94e8 | 157 | channel_clear(sh_chan); |
c11b46c3 GL |
158 | } |
159 | } | |
160 | ||
2dc66667 GL |
161 | dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init); |
162 | ||
163 | dmaor = dmaor_read(shdev); | |
164 | ||
165 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | |
166 | ||
167 | if (dmaor & (DMAOR_AE | DMAOR_NMIF)) { | |
ce3a1ab7 | 168 | dev_warn(shdev->shdma_dev.dma_dev.dev, "Can't initialize DMAOR.\n"); |
2dc66667 | 169 | return -EIO; |
d8902adc | 170 | } |
c11b46c3 | 171 | if (shdev->pdata->dmaor_init & ~dmaor) |
ce3a1ab7 | 172 | dev_warn(shdev->shdma_dev.dma_dev.dev, |
c11b46c3 GL |
173 | "DMAOR=0x%x hasn't latched the initial value 0x%x.\n", |
174 | dmaor, shdev->pdata->dmaor_init); | |
d8902adc NI |
175 | return 0; |
176 | } | |
177 | ||
fc461857 | 178 | static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) |
d8902adc | 179 | { |
5899a723 | 180 | u32 chcr = chcr_read(sh_chan); |
fc461857 GL |
181 | |
182 | if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE) | |
183 | return true; /* working */ | |
184 | ||
185 | return false; /* waiting */ | |
d8902adc NI |
186 | } |
187 | ||
8b1935e6 | 188 | static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr) |
d8902adc | 189 | { |
c4e0dd78 | 190 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
2833c47e | 191 | const struct sh_dmae_pdata *pdata = shdev->pdata; |
8b1935e6 GL |
192 | int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) | |
193 | ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift); | |
194 | ||
195 | if (cnt >= pdata->ts_shift_num) | |
196 | cnt = 0; | |
623b4ac4 | 197 | |
8b1935e6 GL |
198 | return pdata->ts_shift[cnt]; |
199 | } | |
200 | ||
201 | static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size) | |
202 | { | |
c4e0dd78 | 203 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
2833c47e | 204 | const struct sh_dmae_pdata *pdata = shdev->pdata; |
8b1935e6 GL |
205 | int i; |
206 | ||
207 | for (i = 0; i < pdata->ts_shift_num; i++) | |
208 | if (pdata->ts_shift[i] == l2size) | |
209 | break; | |
210 | ||
211 | if (i == pdata->ts_shift_num) | |
212 | i = 0; | |
213 | ||
214 | return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) | | |
215 | ((i << pdata->ts_high_shift) & pdata->ts_high_mask); | |
d8902adc NI |
216 | } |
217 | ||
3542a113 | 218 | static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw) |
d8902adc | 219 | { |
3542a113 GL |
220 | sh_dmae_writel(sh_chan, hw->sar, SAR); |
221 | sh_dmae_writel(sh_chan, hw->dar, DAR); | |
cfefe997 | 222 | sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR); |
d8902adc NI |
223 | } |
224 | ||
225 | static void dmae_start(struct sh_dmae_chan *sh_chan) | |
226 | { | |
67c6269e | 227 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
5899a723 | 228 | u32 chcr = chcr_read(sh_chan); |
d8902adc | 229 | |
260bf2c5 KM |
230 | if (shdev->pdata->needs_tend_set) |
231 | sh_dmae_writel(sh_chan, 0xFFFFFFFF, TEND); | |
232 | ||
67c6269e | 233 | chcr |= CHCR_DE | shdev->chcr_ie_bit; |
5899a723 | 234 | chcr_write(sh_chan, chcr & ~CHCR_TE); |
d8902adc NI |
235 | } |
236 | ||
cfefe997 GL |
237 | static void dmae_init(struct sh_dmae_chan *sh_chan) |
238 | { | |
8b1935e6 GL |
239 | /* |
240 | * Default configuration for dual address memory-memory transfer. | |
241 | * 0x400 represents auto-request. | |
242 | */ | |
243 | u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan, | |
244 | LOG2_DEFAULT_XFER_SIZE); | |
245 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr); | |
5899a723 | 246 | chcr_write(sh_chan, chcr); |
cfefe997 GL |
247 | } |
248 | ||
d8902adc NI |
249 | static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) |
250 | { | |
2dc66667 | 251 | /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */ |
fc461857 GL |
252 | if (dmae_is_busy(sh_chan)) |
253 | return -EBUSY; | |
d8902adc | 254 | |
8b1935e6 | 255 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val); |
5899a723 | 256 | chcr_write(sh_chan, val); |
cfefe997 | 257 | |
d8902adc NI |
258 | return 0; |
259 | } | |
260 | ||
d8902adc NI |
261 | static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) |
262 | { | |
c4e0dd78 | 263 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
2833c47e | 264 | const struct sh_dmae_pdata *pdata = shdev->pdata; |
ce3a1ab7 | 265 | const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->shdma_chan.id]; |
115357e9 | 266 | void __iomem *addr = shdev->dmars; |
090b9180 | 267 | unsigned int shift = chan_pdata->dmars_bit; |
fc461857 GL |
268 | |
269 | if (dmae_is_busy(sh_chan)) | |
270 | return -EBUSY; | |
d8902adc | 271 | |
260bf2c5 KM |
272 | if (pdata->no_dmars) |
273 | return 0; | |
274 | ||
26fc02ab MD |
275 | /* in the case of a missing DMARS resource use first memory window */ |
276 | if (!addr) | |
115357e9 GL |
277 | addr = shdev->chan_reg; |
278 | addr += chan_pdata->dmars; | |
26fc02ab | 279 | |
027811b9 GL |
280 | __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift), |
281 | addr); | |
d8902adc NI |
282 | |
283 | return 0; | |
284 | } | |
285 | ||
ce3a1ab7 GL |
286 | static void sh_dmae_start_xfer(struct shdma_chan *schan, |
287 | struct shdma_desc *sdesc) | |
d8902adc | 288 | { |
ce3a1ab7 GL |
289 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
290 | shdma_chan); | |
291 | struct sh_dmae_desc *sh_desc = container_of(sdesc, | |
292 | struct sh_dmae_desc, shdma_desc); | |
293 | dev_dbg(sh_chan->shdma_chan.dev, "Queue #%d to %d: %u@%x -> %x\n", | |
294 | sdesc->async_tx.cookie, sh_chan->shdma_chan.id, | |
295 | sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar); | |
296 | /* Get the ld start address from ld_queue */ | |
297 | dmae_set_reg(sh_chan, &sh_desc->hw); | |
298 | dmae_start(sh_chan); | |
d8902adc NI |
299 | } |
300 | ||
ce3a1ab7 | 301 | static bool sh_dmae_channel_busy(struct shdma_chan *schan) |
d8902adc | 302 | { |
ce3a1ab7 GL |
303 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
304 | shdma_chan); | |
305 | return dmae_is_busy(sh_chan); | |
d8902adc NI |
306 | } |
307 | ||
ce3a1ab7 | 308 | static void sh_dmae_setup_xfer(struct shdma_chan *schan, |
c2cdb7e4 | 309 | int slave_id) |
cfefe997 | 310 | { |
ce3a1ab7 GL |
311 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
312 | shdma_chan); | |
cfefe997 | 313 | |
c2cdb7e4 | 314 | if (slave_id >= 0) { |
ce3a1ab7 | 315 | const struct sh_dmae_slave_config *cfg = |
ecf90fbb | 316 | sh_chan->config; |
cfefe997 | 317 | |
ce3a1ab7 GL |
318 | dmae_set_dmars(sh_chan, cfg->mid_rid); |
319 | dmae_set_chcr(sh_chan, cfg->chcr); | |
fc461857 | 320 | } else { |
ce3a1ab7 | 321 | dmae_init(sh_chan); |
fc461857 | 322 | } |
fc461857 GL |
323 | } |
324 | ||
67eacc15 GL |
325 | /* |
326 | * Find a slave channel configuration from the contoller list by either a slave | |
327 | * ID in the non-DT case, or by a MID/RID value in the DT case | |
328 | */ | |
ce3a1ab7 | 329 | static const struct sh_dmae_slave_config *dmae_find_slave( |
67eacc15 | 330 | struct sh_dmae_chan *sh_chan, int match) |
fc461857 | 331 | { |
ce3a1ab7 | 332 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
2833c47e | 333 | const struct sh_dmae_pdata *pdata = shdev->pdata; |
ce3a1ab7 | 334 | const struct sh_dmae_slave_config *cfg; |
fc461857 GL |
335 | int i; |
336 | ||
67eacc15 GL |
337 | if (!sh_chan->shdma_chan.dev->of_node) { |
338 | if (match >= SH_DMA_SLAVE_NUMBER) | |
339 | return NULL; | |
fc461857 | 340 | |
67eacc15 GL |
341 | for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++) |
342 | if (cfg->slave_id == match) | |
343 | return cfg; | |
344 | } else { | |
345 | for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++) | |
346 | if (cfg->mid_rid == match) { | |
4981c4dc | 347 | sh_chan->shdma_chan.slave_id = i; |
67eacc15 GL |
348 | return cfg; |
349 | } | |
350 | } | |
fc461857 GL |
351 | |
352 | return NULL; | |
353 | } | |
354 | ||
ce3a1ab7 | 355 | static int sh_dmae_set_slave(struct shdma_chan *schan, |
4981c4dc | 356 | int slave_id, dma_addr_t slave_addr, bool try) |
fc461857 | 357 | { |
ce3a1ab7 GL |
358 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
359 | shdma_chan); | |
c2cdb7e4 | 360 | const struct sh_dmae_slave_config *cfg = dmae_find_slave(sh_chan, slave_id); |
ce3a1ab7 | 361 | if (!cfg) |
7c1119bd | 362 | return -ENXIO; |
c014906a | 363 | |
4981c4dc | 364 | if (!try) { |
1ff8df4f | 365 | sh_chan->config = cfg; |
4981c4dc GL |
366 | sh_chan->slave_addr = slave_addr ? : cfg->addr; |
367 | } | |
c3635c78 LW |
368 | |
369 | return 0; | |
cfefe997 GL |
370 | } |
371 | ||
ce3a1ab7 | 372 | static void dmae_halt(struct sh_dmae_chan *sh_chan) |
d8902adc | 373 | { |
ce3a1ab7 GL |
374 | struct sh_dmae_device *shdev = to_sh_dev(sh_chan); |
375 | u32 chcr = chcr_read(sh_chan); | |
3542a113 | 376 | |
ce3a1ab7 GL |
377 | chcr &= ~(CHCR_DE | CHCR_TE | shdev->chcr_ie_bit); |
378 | chcr_write(sh_chan, chcr); | |
3542a113 GL |
379 | } |
380 | ||
ce3a1ab7 GL |
381 | static int sh_dmae_desc_setup(struct shdma_chan *schan, |
382 | struct shdma_desc *sdesc, | |
383 | dma_addr_t src, dma_addr_t dst, size_t *len) | |
3542a113 | 384 | { |
ce3a1ab7 GL |
385 | struct sh_dmae_desc *sh_desc = container_of(sdesc, |
386 | struct sh_dmae_desc, shdma_desc); | |
d8902adc | 387 | |
ce3a1ab7 GL |
388 | if (*len > schan->max_xfer_len) |
389 | *len = schan->max_xfer_len; | |
d8902adc | 390 | |
ce3a1ab7 GL |
391 | sh_desc->hw.sar = src; |
392 | sh_desc->hw.dar = dst; | |
393 | sh_desc->hw.tcr = *len; | |
d8902adc | 394 | |
ce3a1ab7 | 395 | return 0; |
d8902adc NI |
396 | } |
397 | ||
ce3a1ab7 | 398 | static void sh_dmae_halt(struct shdma_chan *schan) |
d8902adc | 399 | { |
ce3a1ab7 GL |
400 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
401 | shdma_chan); | |
402 | dmae_halt(sh_chan); | |
d8902adc NI |
403 | } |
404 | ||
ce3a1ab7 | 405 | static bool sh_dmae_chan_irq(struct shdma_chan *schan, int irq) |
d8902adc | 406 | { |
ce3a1ab7 GL |
407 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, |
408 | shdma_chan); | |
d8902adc | 409 | |
ce3a1ab7 GL |
410 | if (!(chcr_read(sh_chan) & CHCR_TE)) |
411 | return false; | |
d8902adc | 412 | |
ce3a1ab7 GL |
413 | /* DMA stop */ |
414 | dmae_halt(sh_chan); | |
2dc66667 | 415 | |
ce3a1ab7 | 416 | return true; |
d8902adc NI |
417 | } |
418 | ||
4f46f8ac GL |
419 | static size_t sh_dmae_get_partial(struct shdma_chan *schan, |
420 | struct shdma_desc *sdesc) | |
421 | { | |
422 | struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan, | |
423 | shdma_chan); | |
424 | struct sh_dmae_desc *sh_desc = container_of(sdesc, | |
425 | struct sh_dmae_desc, shdma_desc); | |
3c4d9276 KM |
426 | return sh_desc->hw.tcr - |
427 | (sh_dmae_readl(sh_chan, TCR) << sh_chan->xmit_shift); | |
4f46f8ac GL |
428 | } |
429 | ||
2dc66667 GL |
430 | /* Called from error IRQ or NMI */ |
431 | static bool sh_dmae_reset(struct sh_dmae_device *shdev) | |
d8902adc | 432 | { |
ce3a1ab7 | 433 | bool ret; |
d8902adc | 434 | |
47a4dc26 | 435 | /* halt the dma controller */ |
027811b9 | 436 | sh_dmae_ctl_stop(shdev); |
47a4dc26 GL |
437 | |
438 | /* We cannot detect, which channel caused the error, have to reset all */ | |
ce3a1ab7 | 439 | ret = shdma_reset(&shdev->shdma_dev); |
03aa18f5 | 440 | |
027811b9 | 441 | sh_dmae_rst(shdev); |
47a4dc26 | 442 | |
ce3a1ab7 | 443 | return ret; |
03aa18f5 PM |
444 | } |
445 | ||
52d6a5ee | 446 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARM) |
03aa18f5 PM |
447 | static irqreturn_t sh_dmae_err(int irq, void *data) |
448 | { | |
ff7690b4 YS |
449 | struct sh_dmae_device *shdev = data; |
450 | ||
2dc66667 | 451 | if (!(dmaor_read(shdev) & DMAOR_AE)) |
ff7690b4 | 452 | return IRQ_NONE; |
2dc66667 | 453 | |
ce3a1ab7 | 454 | sh_dmae_reset(shdev); |
2dc66667 | 455 | return IRQ_HANDLED; |
d8902adc | 456 | } |
52d6a5ee | 457 | #endif |
d8902adc | 458 | |
ce3a1ab7 GL |
459 | static bool sh_dmae_desc_completed(struct shdma_chan *schan, |
460 | struct shdma_desc *sdesc) | |
d8902adc | 461 | { |
ce3a1ab7 GL |
462 | struct sh_dmae_chan *sh_chan = container_of(schan, |
463 | struct sh_dmae_chan, shdma_chan); | |
464 | struct sh_dmae_desc *sh_desc = container_of(sdesc, | |
465 | struct sh_dmae_desc, shdma_desc); | |
d8902adc | 466 | u32 sar_buf = sh_dmae_readl(sh_chan, SAR); |
cfefe997 | 467 | u32 dar_buf = sh_dmae_readl(sh_chan, DAR); |
86d61b33 | 468 | |
ce3a1ab7 GL |
469 | return (sdesc->direction == DMA_DEV_TO_MEM && |
470 | (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) || | |
471 | (sdesc->direction != DMA_DEV_TO_MEM && | |
472 | (sh_desc->hw.sar + sh_desc->hw.tcr) == sar_buf); | |
d8902adc NI |
473 | } |
474 | ||
03aa18f5 PM |
475 | static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev) |
476 | { | |
03aa18f5 PM |
477 | /* Fast path out if NMIF is not asserted for this controller */ |
478 | if ((dmaor_read(shdev) & DMAOR_NMIF) == 0) | |
479 | return false; | |
480 | ||
2dc66667 | 481 | return sh_dmae_reset(shdev); |
03aa18f5 PM |
482 | } |
483 | ||
484 | static int sh_dmae_nmi_handler(struct notifier_block *self, | |
485 | unsigned long cmd, void *data) | |
486 | { | |
487 | struct sh_dmae_device *shdev; | |
488 | int ret = NOTIFY_DONE; | |
489 | bool triggered; | |
490 | ||
491 | /* | |
492 | * Only concern ourselves with NMI events. | |
493 | * | |
494 | * Normally we would check the die chain value, but as this needs | |
495 | * to be architecture independent, check for NMI context instead. | |
496 | */ | |
497 | if (!in_nmi()) | |
498 | return NOTIFY_DONE; | |
499 | ||
500 | rcu_read_lock(); | |
501 | list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) { | |
502 | /* | |
503 | * Only stop if one of the controllers has NMIF asserted, | |
504 | * we do not want to interfere with regular address error | |
505 | * handling or NMI events that don't concern the DMACs. | |
506 | */ | |
507 | triggered = sh_dmae_nmi_notify(shdev); | |
508 | if (triggered == true) | |
509 | ret = NOTIFY_OK; | |
510 | } | |
511 | rcu_read_unlock(); | |
512 | ||
513 | return ret; | |
514 | } | |
515 | ||
516 | static struct notifier_block sh_dmae_nmi_notifier __read_mostly = { | |
517 | .notifier_call = sh_dmae_nmi_handler, | |
518 | ||
519 | /* Run before NMI debug handler and KGDB */ | |
520 | .priority = 1, | |
521 | }; | |
522 | ||
463a1f8b | 523 | static int sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, |
027811b9 | 524 | int irq, unsigned long flags) |
d8902adc | 525 | { |
5bac942d | 526 | const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id]; |
ce3a1ab7 GL |
527 | struct shdma_dev *sdev = &shdev->shdma_dev; |
528 | struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev); | |
529 | struct sh_dmae_chan *sh_chan; | |
530 | struct shdma_chan *schan; | |
531 | int err; | |
d8902adc | 532 | |
c1c63a14 GL |
533 | sh_chan = devm_kzalloc(sdev->dma_dev.dev, sizeof(struct sh_dmae_chan), |
534 | GFP_KERNEL); | |
ce3a1ab7 GL |
535 | if (!sh_chan) { |
536 | dev_err(sdev->dma_dev.dev, | |
86d61b33 | 537 | "No free memory for allocating dma channels!\n"); |
d8902adc NI |
538 | return -ENOMEM; |
539 | } | |
540 | ||
ce3a1ab7 GL |
541 | schan = &sh_chan->shdma_chan; |
542 | schan->max_xfer_len = SH_DMA_TCR_MAX + 1; | |
8b1935e6 | 543 | |
ce3a1ab7 | 544 | shdma_chan_probe(sdev, schan, id); |
d8902adc | 545 | |
115357e9 | 546 | sh_chan->base = shdev->chan_reg + chan_pdata->offset; |
d8902adc | 547 | |
ce3a1ab7 | 548 | /* set up channel irq */ |
027811b9 | 549 | if (pdev->id >= 0) |
ce3a1ab7 GL |
550 | snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id), |
551 | "sh-dmae%d.%d", pdev->id, id); | |
027811b9 | 552 | else |
ce3a1ab7 GL |
553 | snprintf(sh_chan->dev_id, sizeof(sh_chan->dev_id), |
554 | "sh-dma%d", id); | |
d8902adc | 555 | |
ce3a1ab7 | 556 | err = shdma_request_irq(schan, irq, flags, sh_chan->dev_id); |
d8902adc | 557 | if (err) { |
ce3a1ab7 GL |
558 | dev_err(sdev->dma_dev.dev, |
559 | "DMA channel %d request_irq error %d\n", | |
560 | id, err); | |
d8902adc NI |
561 | goto err_no_irq; |
562 | } | |
563 | ||
ce3a1ab7 | 564 | shdev->chan[id] = sh_chan; |
d8902adc NI |
565 | return 0; |
566 | ||
567 | err_no_irq: | |
568 | /* remove from dmaengine device node */ | |
ce3a1ab7 | 569 | shdma_chan_remove(schan); |
d8902adc NI |
570 | return err; |
571 | } | |
572 | ||
573 | static void sh_dmae_chan_remove(struct sh_dmae_device *shdev) | |
574 | { | |
ce3a1ab7 GL |
575 | struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev; |
576 | struct shdma_chan *schan; | |
d8902adc NI |
577 | int i; |
578 | ||
ce3a1ab7 | 579 | shdma_for_each_chan(schan, &shdev->shdma_dev, i) { |
ce3a1ab7 | 580 | BUG_ON(!schan); |
027811b9 | 581 | |
ce3a1ab7 | 582 | shdma_chan_remove(schan); |
ce3a1ab7 GL |
583 | } |
584 | dma_dev->chancnt = 0; | |
585 | } | |
586 | ||
587 | static void sh_dmae_shutdown(struct platform_device *pdev) | |
588 | { | |
589 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | |
590 | sh_dmae_ctl_stop(shdev); | |
591 | } | |
592 | ||
593 | static int sh_dmae_runtime_suspend(struct device *dev) | |
594 | { | |
595 | return 0; | |
596 | } | |
597 | ||
598 | static int sh_dmae_runtime_resume(struct device *dev) | |
599 | { | |
600 | struct sh_dmae_device *shdev = dev_get_drvdata(dev); | |
601 | ||
602 | return sh_dmae_rst(shdev); | |
603 | } | |
604 | ||
605 | #ifdef CONFIG_PM | |
606 | static int sh_dmae_suspend(struct device *dev) | |
607 | { | |
608 | return 0; | |
609 | } | |
610 | ||
611 | static int sh_dmae_resume(struct device *dev) | |
612 | { | |
613 | struct sh_dmae_device *shdev = dev_get_drvdata(dev); | |
614 | int i, ret; | |
615 | ||
616 | ret = sh_dmae_rst(shdev); | |
617 | if (ret < 0) | |
618 | dev_err(dev, "Failed to reset!\n"); | |
619 | ||
620 | for (i = 0; i < shdev->pdata->channel_num; i++) { | |
621 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; | |
ce3a1ab7 GL |
622 | |
623 | if (!sh_chan->shdma_chan.desc_num) | |
624 | continue; | |
625 | ||
c2cdb7e4 | 626 | if (sh_chan->shdma_chan.slave_id >= 0) { |
ecf90fbb | 627 | const struct sh_dmae_slave_config *cfg = sh_chan->config; |
ce3a1ab7 GL |
628 | dmae_set_dmars(sh_chan, cfg->mid_rid); |
629 | dmae_set_chcr(sh_chan, cfg->chcr); | |
630 | } else { | |
631 | dmae_init(sh_chan); | |
d8902adc NI |
632 | } |
633 | } | |
ce3a1ab7 GL |
634 | |
635 | return 0; | |
d8902adc | 636 | } |
ce3a1ab7 GL |
637 | #else |
638 | #define sh_dmae_suspend NULL | |
639 | #define sh_dmae_resume NULL | |
640 | #endif | |
d8902adc | 641 | |
ce3a1ab7 GL |
642 | const struct dev_pm_ops sh_dmae_pm = { |
643 | .suspend = sh_dmae_suspend, | |
644 | .resume = sh_dmae_resume, | |
645 | .runtime_suspend = sh_dmae_runtime_suspend, | |
646 | .runtime_resume = sh_dmae_runtime_resume, | |
647 | }; | |
648 | ||
649 | static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan) | |
650 | { | |
ecf90fbb GL |
651 | struct sh_dmae_chan *sh_chan = container_of(schan, |
652 | struct sh_dmae_chan, shdma_chan); | |
ce3a1ab7 GL |
653 | |
654 | /* | |
ecf90fbb GL |
655 | * Implicit BUG_ON(!sh_chan->config) |
656 | * This is an exclusive slave DMA operation, may only be called after a | |
657 | * successful slave configuration. | |
ce3a1ab7 | 658 | */ |
4981c4dc | 659 | return sh_chan->slave_addr; |
ce3a1ab7 GL |
660 | } |
661 | ||
662 | static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i) | |
663 | { | |
664 | return &((struct sh_dmae_desc *)buf)[i].shdma_desc; | |
665 | } | |
666 | ||
667 | static const struct shdma_ops sh_dmae_shdma_ops = { | |
668 | .desc_completed = sh_dmae_desc_completed, | |
669 | .halt_channel = sh_dmae_halt, | |
670 | .channel_busy = sh_dmae_channel_busy, | |
671 | .slave_addr = sh_dmae_slave_addr, | |
672 | .desc_setup = sh_dmae_desc_setup, | |
673 | .set_slave = sh_dmae_set_slave, | |
674 | .setup_xfer = sh_dmae_setup_xfer, | |
675 | .start_xfer = sh_dmae_start_xfer, | |
676 | .embedded_desc = sh_dmae_embedded_desc, | |
677 | .chan_irq = sh_dmae_chan_irq, | |
4f46f8ac | 678 | .get_partial = sh_dmae_get_partial, |
ce3a1ab7 GL |
679 | }; |
680 | ||
4981c4dc | 681 | static const struct of_device_id sh_dmae_of_match[] = { |
1e69653d | 682 | {.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,}, |
4981c4dc GL |
683 | {} |
684 | }; | |
685 | MODULE_DEVICE_TABLE(of, sh_dmae_of_match); | |
686 | ||
463a1f8b | 687 | static int sh_dmae_probe(struct platform_device *pdev) |
d8902adc | 688 | { |
4981c4dc | 689 | const struct sh_dmae_pdata *pdata; |
52d6a5ee LP |
690 | unsigned long chan_flag[SH_DMAE_MAX_CHANNELS] = {}; |
691 | int chan_irq[SH_DMAE_MAX_CHANNELS]; | |
692 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARM) | |
693 | unsigned long irqflags = 0; | |
694 | int errirq; | |
695 | #endif | |
300e5f97 | 696 | int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0; |
d8902adc | 697 | struct sh_dmae_device *shdev; |
ce3a1ab7 | 698 | struct dma_device *dma_dev; |
027811b9 | 699 | struct resource *chan, *dmars, *errirq_res, *chanirq_res; |
d8902adc | 700 | |
4981c4dc GL |
701 | if (pdev->dev.of_node) |
702 | pdata = of_match_device(sh_dmae_of_match, &pdev->dev)->data; | |
703 | else | |
265d9c67 | 704 | pdata = dev_get_platdata(&pdev->dev); |
4981c4dc | 705 | |
56adf7e8 | 706 | /* get platform data */ |
027811b9 | 707 | if (!pdata || !pdata->channel_num) |
56adf7e8 DW |
708 | return -ENODEV; |
709 | ||
027811b9 | 710 | chan = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
26fc02ab | 711 | /* DMARS area is optional */ |
027811b9 GL |
712 | dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
713 | /* | |
714 | * IRQ resources: | |
715 | * 1. there always must be at least one IRQ IO-resource. On SH4 it is | |
716 | * the error IRQ, in which case it is the only IRQ in this resource: | |
717 | * start == end. If it is the only IRQ resource, all channels also | |
718 | * use the same IRQ. | |
719 | * 2. DMA channel IRQ resources can be specified one per resource or in | |
720 | * ranges (start != end) | |
721 | * 3. iff all events (channels and, optionally, error) on this | |
722 | * controller use the same IRQ, only one IRQ resource can be | |
723 | * specified, otherwise there must be one IRQ per channel, even if | |
724 | * some of them are equal | |
725 | * 4. if all IRQs on this controller are equal or if some specific IRQs | |
726 | * specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be | |
727 | * requested with the IRQF_SHARED flag | |
728 | */ | |
729 | errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
730 | if (!chan || !errirq_res) | |
731 | return -ENODEV; | |
732 | ||
c1c63a14 GL |
733 | shdev = devm_kzalloc(&pdev->dev, sizeof(struct sh_dmae_device), |
734 | GFP_KERNEL); | |
d8902adc | 735 | if (!shdev) { |
027811b9 | 736 | dev_err(&pdev->dev, "Not enough memory\n"); |
c1c63a14 | 737 | return -ENOMEM; |
027811b9 GL |
738 | } |
739 | ||
ce3a1ab7 GL |
740 | dma_dev = &shdev->shdma_dev.dma_dev; |
741 | ||
c1c63a14 GL |
742 | shdev->chan_reg = devm_ioremap_resource(&pdev->dev, chan); |
743 | if (IS_ERR(shdev->chan_reg)) | |
744 | return PTR_ERR(shdev->chan_reg); | |
027811b9 | 745 | if (dmars) { |
c1c63a14 GL |
746 | shdev->dmars = devm_ioremap_resource(&pdev->dev, dmars); |
747 | if (IS_ERR(shdev->dmars)) | |
748 | return PTR_ERR(shdev->dmars); | |
d8902adc NI |
749 | } |
750 | ||
ce3a1ab7 GL |
751 | if (!pdata->slave_only) |
752 | dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask); | |
753 | if (pdata->slave && pdata->slave_num) | |
754 | dma_cap_set(DMA_SLAVE, dma_dev->cap_mask); | |
755 | ||
756 | /* Default transfer size of 32 bytes requires 32-byte alignment */ | |
757 | dma_dev->copy_align = LOG2_DEFAULT_XFER_SIZE; | |
758 | ||
759 | shdev->shdma_dev.ops = &sh_dmae_shdma_ops; | |
760 | shdev->shdma_dev.desc_size = sizeof(struct sh_dmae_desc); | |
761 | err = shdma_init(&pdev->dev, &shdev->shdma_dev, | |
762 | pdata->channel_num); | |
763 | if (err < 0) | |
764 | goto eshdma; | |
765 | ||
d8902adc | 766 | /* platform data */ |
fa74326c | 767 | shdev->pdata = pdata; |
d8902adc | 768 | |
5899a723 KM |
769 | if (pdata->chcr_offset) |
770 | shdev->chcr_offset = pdata->chcr_offset; | |
771 | else | |
772 | shdev->chcr_offset = CHCR; | |
773 | ||
67c6269e KM |
774 | if (pdata->chcr_ie_bit) |
775 | shdev->chcr_ie_bit = pdata->chcr_ie_bit; | |
776 | else | |
777 | shdev->chcr_ie_bit = CHCR_IE; | |
778 | ||
5c2de444 PM |
779 | platform_set_drvdata(pdev, shdev); |
780 | ||
20f2a3b5 | 781 | pm_runtime_enable(&pdev->dev); |
ce3a1ab7 GL |
782 | err = pm_runtime_get_sync(&pdev->dev); |
783 | if (err < 0) | |
784 | dev_err(&pdev->dev, "%s(): GET = %d\n", __func__, err); | |
20f2a3b5 | 785 | |
31705e21 | 786 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 787 | list_add_tail_rcu(&shdev->node, &sh_dmae_devices); |
31705e21 | 788 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 789 | |
2dc66667 | 790 | /* reset dma controller - only needed as a test */ |
027811b9 | 791 | err = sh_dmae_rst(shdev); |
d8902adc NI |
792 | if (err) |
793 | goto rst_err; | |
794 | ||
927a7c9c | 795 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) |
027811b9 GL |
796 | chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); |
797 | ||
798 | if (!chanirq_res) | |
799 | chanirq_res = errirq_res; | |
800 | else | |
801 | irqres++; | |
802 | ||
803 | if (chanirq_res == errirq_res || | |
804 | (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE) | |
d8902adc | 805 | irqflags = IRQF_SHARED; |
027811b9 GL |
806 | |
807 | errirq = errirq_res->start; | |
808 | ||
c1c63a14 GL |
809 | err = devm_request_irq(&pdev->dev, errirq, sh_dmae_err, irqflags, |
810 | "DMAC Address Error", shdev); | |
027811b9 GL |
811 | if (err) { |
812 | dev_err(&pdev->dev, | |
813 | "DMA failed requesting irq #%d, error %d\n", | |
814 | errirq, err); | |
815 | goto eirq_err; | |
d8902adc NI |
816 | } |
817 | ||
027811b9 GL |
818 | #else |
819 | chanirq_res = errirq_res; | |
927a7c9c | 820 | #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */ |
027811b9 GL |
821 | |
822 | if (chanirq_res->start == chanirq_res->end && | |
823 | !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) { | |
824 | /* Special case - all multiplexed */ | |
825 | for (; irq_cnt < pdata->channel_num; irq_cnt++) { | |
ce3a1ab7 | 826 | if (irq_cnt < SH_DMAE_MAX_CHANNELS) { |
300e5f97 MD |
827 | chan_irq[irq_cnt] = chanirq_res->start; |
828 | chan_flag[irq_cnt] = IRQF_SHARED; | |
829 | } else { | |
830 | irq_cap = 1; | |
831 | break; | |
832 | } | |
d8902adc | 833 | } |
027811b9 GL |
834 | } else { |
835 | do { | |
836 | for (i = chanirq_res->start; i <= chanirq_res->end; i++) { | |
ce3a1ab7 | 837 | if (irq_cnt >= SH_DMAE_MAX_CHANNELS) { |
dcee0bb7 MD |
838 | irq_cap = 1; |
839 | break; | |
840 | } | |
841 | ||
027811b9 GL |
842 | if ((errirq_res->flags & IORESOURCE_BITS) == |
843 | IORESOURCE_IRQ_SHAREABLE) | |
844 | chan_flag[irq_cnt] = IRQF_SHARED; | |
845 | else | |
174b537a | 846 | chan_flag[irq_cnt] = 0; |
027811b9 GL |
847 | dev_dbg(&pdev->dev, |
848 | "Found IRQ %d for channel %d\n", | |
849 | i, irq_cnt); | |
850 | chan_irq[irq_cnt++] = i; | |
300e5f97 MD |
851 | } |
852 | ||
ce3a1ab7 | 853 | if (irq_cnt >= SH_DMAE_MAX_CHANNELS) |
300e5f97 | 854 | break; |
dcee0bb7 | 855 | |
027811b9 GL |
856 | chanirq_res = platform_get_resource(pdev, |
857 | IORESOURCE_IRQ, ++irqres); | |
858 | } while (irq_cnt < pdata->channel_num && chanirq_res); | |
d8902adc | 859 | } |
027811b9 | 860 | |
d8902adc | 861 | /* Create DMA Channel */ |
300e5f97 | 862 | for (i = 0; i < irq_cnt; i++) { |
027811b9 | 863 | err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]); |
d8902adc NI |
864 | if (err) |
865 | goto chan_probe_err; | |
866 | } | |
867 | ||
300e5f97 MD |
868 | if (irq_cap) |
869 | dev_notice(&pdev->dev, "Attempting to register %d DMA " | |
870 | "channels when a maximum of %d are supported.\n", | |
ce3a1ab7 | 871 | pdata->channel_num, SH_DMAE_MAX_CHANNELS); |
300e5f97 | 872 | |
20f2a3b5 GL |
873 | pm_runtime_put(&pdev->dev); |
874 | ||
ce3a1ab7 GL |
875 | err = dma_async_device_register(&shdev->shdma_dev.dma_dev); |
876 | if (err < 0) | |
877 | goto edmadevreg; | |
d8902adc NI |
878 | |
879 | return err; | |
880 | ||
ce3a1ab7 GL |
881 | edmadevreg: |
882 | pm_runtime_get(&pdev->dev); | |
883 | ||
d8902adc NI |
884 | chan_probe_err: |
885 | sh_dmae_chan_remove(shdev); | |
300e5f97 | 886 | |
927a7c9c | 887 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) |
d8902adc | 888 | eirq_err: |
027811b9 | 889 | #endif |
d8902adc | 890 | rst_err: |
31705e21 | 891 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 892 | list_del_rcu(&shdev->node); |
31705e21 | 893 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 894 | |
20f2a3b5 | 895 | pm_runtime_put(&pdev->dev); |
467017b8 GL |
896 | pm_runtime_disable(&pdev->dev); |
897 | ||
ce3a1ab7 GL |
898 | shdma_cleanup(&shdev->shdma_dev); |
899 | eshdma: | |
31705e21 | 900 | synchronize_rcu(); |
d8902adc | 901 | |
d8902adc NI |
902 | return err; |
903 | } | |
904 | ||
4bf27b8b | 905 | static int sh_dmae_remove(struct platform_device *pdev) |
d8902adc NI |
906 | { |
907 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | |
ce3a1ab7 | 908 | struct dma_device *dma_dev = &shdev->shdma_dev.dma_dev; |
d8902adc | 909 | |
ce3a1ab7 | 910 | dma_async_device_unregister(dma_dev); |
d8902adc | 911 | |
31705e21 | 912 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 913 | list_del_rcu(&shdev->node); |
31705e21 | 914 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 915 | |
20f2a3b5 GL |
916 | pm_runtime_disable(&pdev->dev); |
917 | ||
ce3a1ab7 GL |
918 | sh_dmae_chan_remove(shdev); |
919 | shdma_cleanup(&shdev->shdma_dev); | |
920 | ||
31705e21 | 921 | synchronize_rcu(); |
027811b9 | 922 | |
d8902adc NI |
923 | return 0; |
924 | } | |
925 | ||
d8902adc | 926 | static struct platform_driver sh_dmae_driver = { |
ce3a1ab7 | 927 | .driver = { |
7a5c106a | 928 | .owner = THIS_MODULE, |
467017b8 | 929 | .pm = &sh_dmae_pm, |
ce3a1ab7 | 930 | .name = SH_DMAE_DRV_NAME, |
67eacc15 | 931 | .of_match_table = sh_dmae_of_match, |
d8902adc | 932 | }, |
a7d6e3ec | 933 | .remove = sh_dmae_remove, |
ce3a1ab7 | 934 | .shutdown = sh_dmae_shutdown, |
d8902adc NI |
935 | }; |
936 | ||
937 | static int __init sh_dmae_init(void) | |
938 | { | |
661382fe GL |
939 | /* Wire up NMI handling */ |
940 | int err = register_die_notifier(&sh_dmae_nmi_notifier); | |
941 | if (err) | |
942 | return err; | |
943 | ||
d8902adc NI |
944 | return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe); |
945 | } | |
946 | module_init(sh_dmae_init); | |
947 | ||
948 | static void __exit sh_dmae_exit(void) | |
949 | { | |
950 | platform_driver_unregister(&sh_dmae_driver); | |
661382fe GL |
951 | |
952 | unregister_die_notifier(&sh_dmae_nmi_notifier); | |
d8902adc NI |
953 | } |
954 | module_exit(sh_dmae_exit); | |
955 | ||
956 | MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>"); | |
957 | MODULE_DESCRIPTION("Renesas SH DMA Engine driver"); | |
958 | MODULE_LICENSE("GPL"); | |
ce3a1ab7 | 959 | MODULE_ALIAS("platform:" SH_DMAE_DRV_NAME); |