Commit | Line | Data |
---|---|---|
d8902adc NI |
1 | /* |
2 | * Renesas SuperH DMA Engine support | |
3 | * | |
4 | * base is drivers/dma/flsdma.c | |
5 | * | |
6 | * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
7 | * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. | |
8 | * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. | |
9 | * | |
10 | * This is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * - DMA of SuperH does not have Hardware DMA chain mode. | |
16 | * - MAX DMA size is 16MB. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
d8902adc NI |
23 | #include <linux/interrupt.h> |
24 | #include <linux/dmaengine.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/dma-mapping.h> | |
d8902adc | 27 | #include <linux/platform_device.h> |
20f2a3b5 | 28 | #include <linux/pm_runtime.h> |
b2623a61 | 29 | #include <linux/sh_dma.h> |
03aa18f5 PM |
30 | #include <linux/notifier.h> |
31 | #include <linux/kdebug.h> | |
32 | #include <linux/spinlock.h> | |
33 | #include <linux/rculist.h> | |
d8902adc NI |
34 | #include "shdma.h" |
35 | ||
36 | /* DMA descriptor control */ | |
3542a113 GL |
37 | enum sh_dmae_desc_status { |
38 | DESC_IDLE, | |
39 | DESC_PREPARED, | |
40 | DESC_SUBMITTED, | |
41 | DESC_COMPLETED, /* completed, have to call callback */ | |
42 | DESC_WAITING, /* callback called, waiting for ack / re-submit */ | |
43 | }; | |
d8902adc NI |
44 | |
45 | #define NR_DESCS_PER_CHANNEL 32 | |
8b1935e6 GL |
46 | /* Default MEMCPY transfer size = 2^2 = 4 bytes */ |
47 | #define LOG2_DEFAULT_XFER_SIZE 2 | |
d8902adc | 48 | |
03aa18f5 PM |
49 | /* |
50 | * Used for write-side mutual exclusion for the global device list, | |
2dc66667 | 51 | * read-side synchronization by way of RCU, and per-controller data. |
03aa18f5 PM |
52 | */ |
53 | static DEFINE_SPINLOCK(sh_dmae_lock); | |
54 | static LIST_HEAD(sh_dmae_devices); | |
55 | ||
cfefe997 | 56 | /* A bitmask with bits enough for enum sh_dmae_slave_chan_id */ |
02ca5083 | 57 | static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SH_DMA_SLAVE_NUMBER)]; |
cfefe997 | 58 | |
3542a113 GL |
59 | static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all); |
60 | ||
d8902adc NI |
61 | static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg) |
62 | { | |
027811b9 | 63 | __raw_writel(data, sh_dc->base + reg / sizeof(u32)); |
d8902adc NI |
64 | } |
65 | ||
66 | static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg) | |
67 | { | |
027811b9 GL |
68 | return __raw_readl(sh_dc->base + reg / sizeof(u32)); |
69 | } | |
70 | ||
71 | static u16 dmaor_read(struct sh_dmae_device *shdev) | |
72 | { | |
73 | return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32)); | |
74 | } | |
75 | ||
76 | static void dmaor_write(struct sh_dmae_device *shdev, u16 data) | |
77 | { | |
78 | __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32)); | |
d8902adc NI |
79 | } |
80 | ||
d8902adc NI |
81 | /* |
82 | * Reset DMA controller | |
83 | * | |
84 | * SH7780 has two DMAOR register | |
85 | */ | |
027811b9 | 86 | static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev) |
d8902adc | 87 | { |
2dc66667 GL |
88 | unsigned short dmaor; |
89 | unsigned long flags; | |
90 | ||
91 | spin_lock_irqsave(&sh_dmae_lock, flags); | |
d8902adc | 92 | |
2dc66667 | 93 | dmaor = dmaor_read(shdev); |
027811b9 | 94 | dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME)); |
2dc66667 GL |
95 | |
96 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | |
d8902adc NI |
97 | } |
98 | ||
027811b9 | 99 | static int sh_dmae_rst(struct sh_dmae_device *shdev) |
d8902adc NI |
100 | { |
101 | unsigned short dmaor; | |
2dc66667 | 102 | unsigned long flags; |
d8902adc | 103 | |
2dc66667 | 104 | spin_lock_irqsave(&sh_dmae_lock, flags); |
d8902adc | 105 | |
2dc66667 GL |
106 | dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME); |
107 | ||
108 | dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init); | |
109 | ||
110 | dmaor = dmaor_read(shdev); | |
111 | ||
112 | spin_unlock_irqrestore(&sh_dmae_lock, flags); | |
113 | ||
114 | if (dmaor & (DMAOR_AE | DMAOR_NMIF)) { | |
115 | dev_warn(shdev->common.dev, "Can't initialize DMAOR.\n"); | |
116 | return -EIO; | |
d8902adc NI |
117 | } |
118 | return 0; | |
119 | } | |
120 | ||
fc461857 | 121 | static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) |
d8902adc NI |
122 | { |
123 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | |
fc461857 GL |
124 | |
125 | if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE) | |
126 | return true; /* working */ | |
127 | ||
128 | return false; /* waiting */ | |
d8902adc NI |
129 | } |
130 | ||
8b1935e6 | 131 | static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr) |
d8902adc | 132 | { |
8b1935e6 GL |
133 | struct sh_dmae_device *shdev = container_of(sh_chan->common.device, |
134 | struct sh_dmae_device, common); | |
135 | struct sh_dmae_pdata *pdata = shdev->pdata; | |
136 | int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) | | |
137 | ((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift); | |
138 | ||
139 | if (cnt >= pdata->ts_shift_num) | |
140 | cnt = 0; | |
623b4ac4 | 141 | |
8b1935e6 GL |
142 | return pdata->ts_shift[cnt]; |
143 | } | |
144 | ||
145 | static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size) | |
146 | { | |
147 | struct sh_dmae_device *shdev = container_of(sh_chan->common.device, | |
148 | struct sh_dmae_device, common); | |
149 | struct sh_dmae_pdata *pdata = shdev->pdata; | |
150 | int i; | |
151 | ||
152 | for (i = 0; i < pdata->ts_shift_num; i++) | |
153 | if (pdata->ts_shift[i] == l2size) | |
154 | break; | |
155 | ||
156 | if (i == pdata->ts_shift_num) | |
157 | i = 0; | |
158 | ||
159 | return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) | | |
160 | ((i << pdata->ts_high_shift) & pdata->ts_high_mask); | |
d8902adc NI |
161 | } |
162 | ||
3542a113 | 163 | static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw) |
d8902adc | 164 | { |
3542a113 GL |
165 | sh_dmae_writel(sh_chan, hw->sar, SAR); |
166 | sh_dmae_writel(sh_chan, hw->dar, DAR); | |
cfefe997 | 167 | sh_dmae_writel(sh_chan, hw->tcr >> sh_chan->xmit_shift, TCR); |
d8902adc NI |
168 | } |
169 | ||
170 | static void dmae_start(struct sh_dmae_chan *sh_chan) | |
171 | { | |
172 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | |
173 | ||
86d61b33 | 174 | chcr |= CHCR_DE | CHCR_IE; |
cfefe997 | 175 | sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR); |
d8902adc NI |
176 | } |
177 | ||
178 | static void dmae_halt(struct sh_dmae_chan *sh_chan) | |
179 | { | |
180 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | |
181 | ||
182 | chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); | |
183 | sh_dmae_writel(sh_chan, chcr, CHCR); | |
184 | } | |
185 | ||
cfefe997 GL |
186 | static void dmae_init(struct sh_dmae_chan *sh_chan) |
187 | { | |
8b1935e6 GL |
188 | /* |
189 | * Default configuration for dual address memory-memory transfer. | |
190 | * 0x400 represents auto-request. | |
191 | */ | |
192 | u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan, | |
193 | LOG2_DEFAULT_XFER_SIZE); | |
194 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr); | |
cfefe997 GL |
195 | sh_dmae_writel(sh_chan, chcr, CHCR); |
196 | } | |
197 | ||
d8902adc NI |
198 | static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) |
199 | { | |
2dc66667 | 200 | /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */ |
fc461857 GL |
201 | if (dmae_is_busy(sh_chan)) |
202 | return -EBUSY; | |
d8902adc | 203 | |
8b1935e6 | 204 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val); |
d8902adc | 205 | sh_dmae_writel(sh_chan, val, CHCR); |
cfefe997 | 206 | |
d8902adc NI |
207 | return 0; |
208 | } | |
209 | ||
d8902adc NI |
210 | static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val) |
211 | { | |
027811b9 GL |
212 | struct sh_dmae_device *shdev = container_of(sh_chan->common.device, |
213 | struct sh_dmae_device, common); | |
214 | struct sh_dmae_pdata *pdata = shdev->pdata; | |
5bac942d | 215 | const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id]; |
26fc02ab | 216 | u16 __iomem *addr = shdev->dmars; |
027811b9 | 217 | int shift = chan_pdata->dmars_bit; |
fc461857 GL |
218 | |
219 | if (dmae_is_busy(sh_chan)) | |
220 | return -EBUSY; | |
d8902adc | 221 | |
26fc02ab MD |
222 | /* in the case of a missing DMARS resource use first memory window */ |
223 | if (!addr) | |
224 | addr = (u16 __iomem *)shdev->chan_reg; | |
225 | addr += chan_pdata->dmars / sizeof(u16); | |
226 | ||
027811b9 GL |
227 | __raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift), |
228 | addr); | |
d8902adc NI |
229 | |
230 | return 0; | |
231 | } | |
232 | ||
233 | static dma_cookie_t sh_dmae_tx_submit(struct dma_async_tx_descriptor *tx) | |
234 | { | |
3542a113 | 235 | struct sh_desc *desc = tx_to_sh_desc(tx), *chunk, *last = desc, *c; |
d8902adc | 236 | struct sh_dmae_chan *sh_chan = to_sh_chan(tx->chan); |
3542a113 | 237 | dma_async_tx_callback callback = tx->callback; |
d8902adc NI |
238 | dma_cookie_t cookie; |
239 | ||
240 | spin_lock_bh(&sh_chan->desc_lock); | |
241 | ||
242 | cookie = sh_chan->common.cookie; | |
243 | cookie++; | |
244 | if (cookie < 0) | |
245 | cookie = 1; | |
246 | ||
3542a113 GL |
247 | sh_chan->common.cookie = cookie; |
248 | tx->cookie = cookie; | |
249 | ||
250 | /* Mark all chunks of this descriptor as submitted, move to the queue */ | |
251 | list_for_each_entry_safe(chunk, c, desc->node.prev, node) { | |
252 | /* | |
253 | * All chunks are on the global ld_free, so, we have to find | |
254 | * the end of the chain ourselves | |
255 | */ | |
256 | if (chunk != desc && (chunk->mark == DESC_IDLE || | |
257 | chunk->async_tx.cookie > 0 || | |
258 | chunk->async_tx.cookie == -EBUSY || | |
259 | &chunk->node == &sh_chan->ld_free)) | |
260 | break; | |
261 | chunk->mark = DESC_SUBMITTED; | |
262 | /* Callback goes to the last chunk */ | |
263 | chunk->async_tx.callback = NULL; | |
264 | chunk->cookie = cookie; | |
265 | list_move_tail(&chunk->node, &sh_chan->ld_queue); | |
266 | last = chunk; | |
267 | } | |
d8902adc | 268 | |
3542a113 GL |
269 | last->async_tx.callback = callback; |
270 | last->async_tx.callback_param = tx->callback_param; | |
271 | ||
272 | dev_dbg(sh_chan->dev, "submit #%d@%p on %d: %x[%d] -> %x\n", | |
273 | tx->cookie, &last->async_tx, sh_chan->id, | |
274 | desc->hw.sar, desc->hw.tcr, desc->hw.dar); | |
d8902adc NI |
275 | |
276 | spin_unlock_bh(&sh_chan->desc_lock); | |
277 | ||
278 | return cookie; | |
279 | } | |
280 | ||
3542a113 | 281 | /* Called with desc_lock held */ |
d8902adc NI |
282 | static struct sh_desc *sh_dmae_get_desc(struct sh_dmae_chan *sh_chan) |
283 | { | |
3542a113 | 284 | struct sh_desc *desc; |
d8902adc | 285 | |
3542a113 GL |
286 | list_for_each_entry(desc, &sh_chan->ld_free, node) |
287 | if (desc->mark != DESC_PREPARED) { | |
288 | BUG_ON(desc->mark != DESC_IDLE); | |
d8902adc | 289 | list_del(&desc->node); |
3542a113 | 290 | return desc; |
d8902adc | 291 | } |
d8902adc | 292 | |
3542a113 | 293 | return NULL; |
d8902adc NI |
294 | } |
295 | ||
5bac942d | 296 | static const struct sh_dmae_slave_config *sh_dmae_find_slave( |
4bab9d42 | 297 | struct sh_dmae_chan *sh_chan, struct sh_dmae_slave *param) |
cfefe997 GL |
298 | { |
299 | struct dma_device *dma_dev = sh_chan->common.device; | |
300 | struct sh_dmae_device *shdev = container_of(dma_dev, | |
301 | struct sh_dmae_device, common); | |
027811b9 | 302 | struct sh_dmae_pdata *pdata = shdev->pdata; |
cfefe997 GL |
303 | int i; |
304 | ||
02ca5083 | 305 | if (param->slave_id >= SH_DMA_SLAVE_NUMBER) |
cfefe997 GL |
306 | return NULL; |
307 | ||
027811b9 | 308 | for (i = 0; i < pdata->slave_num; i++) |
4bab9d42 | 309 | if (pdata->slave[i].slave_id == param->slave_id) |
027811b9 | 310 | return pdata->slave + i; |
cfefe997 GL |
311 | |
312 | return NULL; | |
313 | } | |
314 | ||
d8902adc NI |
315 | static int sh_dmae_alloc_chan_resources(struct dma_chan *chan) |
316 | { | |
317 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
318 | struct sh_desc *desc; | |
cfefe997 | 319 | struct sh_dmae_slave *param = chan->private; |
83515bc7 | 320 | int ret; |
cfefe997 | 321 | |
20f2a3b5 GL |
322 | pm_runtime_get_sync(sh_chan->dev); |
323 | ||
cfefe997 GL |
324 | /* |
325 | * This relies on the guarantee from dmaengine that alloc_chan_resources | |
326 | * never runs concurrently with itself or free_chan_resources. | |
327 | */ | |
328 | if (param) { | |
5bac942d | 329 | const struct sh_dmae_slave_config *cfg; |
cfefe997 | 330 | |
4bab9d42 | 331 | cfg = sh_dmae_find_slave(sh_chan, param); |
83515bc7 GL |
332 | if (!cfg) { |
333 | ret = -EINVAL; | |
334 | goto efindslave; | |
335 | } | |
cfefe997 | 336 | |
83515bc7 GL |
337 | if (test_and_set_bit(param->slave_id, sh_dmae_slave_used)) { |
338 | ret = -EBUSY; | |
339 | goto etestused; | |
340 | } | |
cfefe997 GL |
341 | |
342 | param->config = cfg; | |
343 | ||
344 | dmae_set_dmars(sh_chan, cfg->mid_rid); | |
345 | dmae_set_chcr(sh_chan, cfg->chcr); | |
a1b2cc50 | 346 | } else { |
8b1935e6 | 347 | dmae_init(sh_chan); |
cfefe997 | 348 | } |
d8902adc NI |
349 | |
350 | spin_lock_bh(&sh_chan->desc_lock); | |
351 | while (sh_chan->descs_allocated < NR_DESCS_PER_CHANNEL) { | |
352 | spin_unlock_bh(&sh_chan->desc_lock); | |
353 | desc = kzalloc(sizeof(struct sh_desc), GFP_KERNEL); | |
354 | if (!desc) { | |
355 | spin_lock_bh(&sh_chan->desc_lock); | |
356 | break; | |
357 | } | |
358 | dma_async_tx_descriptor_init(&desc->async_tx, | |
359 | &sh_chan->common); | |
360 | desc->async_tx.tx_submit = sh_dmae_tx_submit; | |
3542a113 | 361 | desc->mark = DESC_IDLE; |
d8902adc NI |
362 | |
363 | spin_lock_bh(&sh_chan->desc_lock); | |
3542a113 | 364 | list_add(&desc->node, &sh_chan->ld_free); |
d8902adc NI |
365 | sh_chan->descs_allocated++; |
366 | } | |
367 | spin_unlock_bh(&sh_chan->desc_lock); | |
368 | ||
83515bc7 GL |
369 | if (!sh_chan->descs_allocated) { |
370 | ret = -ENOMEM; | |
371 | goto edescalloc; | |
372 | } | |
20f2a3b5 | 373 | |
d8902adc | 374 | return sh_chan->descs_allocated; |
83515bc7 GL |
375 | |
376 | edescalloc: | |
377 | if (param) | |
378 | clear_bit(param->slave_id, sh_dmae_slave_used); | |
379 | etestused: | |
380 | efindslave: | |
381 | pm_runtime_put(sh_chan->dev); | |
382 | return ret; | |
d8902adc NI |
383 | } |
384 | ||
385 | /* | |
386 | * sh_dma_free_chan_resources - Free all resources of the channel. | |
387 | */ | |
388 | static void sh_dmae_free_chan_resources(struct dma_chan *chan) | |
389 | { | |
390 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
391 | struct sh_desc *desc, *_desc; | |
392 | LIST_HEAD(list); | |
20f2a3b5 | 393 | int descs = sh_chan->descs_allocated; |
d8902adc | 394 | |
2dc66667 GL |
395 | /* Protect against ISR */ |
396 | spin_lock_irq(&sh_chan->desc_lock); | |
cfefe997 | 397 | dmae_halt(sh_chan); |
2dc66667 GL |
398 | spin_unlock_irq(&sh_chan->desc_lock); |
399 | ||
400 | /* Now no new interrupts will occur */ | |
cfefe997 | 401 | |
3542a113 GL |
402 | /* Prepared and not submitted descriptors can still be on the queue */ |
403 | if (!list_empty(&sh_chan->ld_queue)) | |
404 | sh_dmae_chan_ld_cleanup(sh_chan, true); | |
405 | ||
cfefe997 GL |
406 | if (chan->private) { |
407 | /* The caller is holding dma_list_mutex */ | |
408 | struct sh_dmae_slave *param = chan->private; | |
409 | clear_bit(param->slave_id, sh_dmae_slave_used); | |
2dc66667 | 410 | chan->private = NULL; |
cfefe997 GL |
411 | } |
412 | ||
d8902adc NI |
413 | spin_lock_bh(&sh_chan->desc_lock); |
414 | ||
415 | list_splice_init(&sh_chan->ld_free, &list); | |
416 | sh_chan->descs_allocated = 0; | |
417 | ||
418 | spin_unlock_bh(&sh_chan->desc_lock); | |
419 | ||
20f2a3b5 GL |
420 | if (descs > 0) |
421 | pm_runtime_put(sh_chan->dev); | |
422 | ||
d8902adc NI |
423 | list_for_each_entry_safe(desc, _desc, &list, node) |
424 | kfree(desc); | |
425 | } | |
426 | ||
cfefe997 | 427 | /** |
fc461857 GL |
428 | * sh_dmae_add_desc - get, set up and return one transfer descriptor |
429 | * @sh_chan: DMA channel | |
430 | * @flags: DMA transfer flags | |
431 | * @dest: destination DMA address, incremented when direction equals | |
432 | * DMA_FROM_DEVICE or DMA_BIDIRECTIONAL | |
433 | * @src: source DMA address, incremented when direction equals | |
434 | * DMA_TO_DEVICE or DMA_BIDIRECTIONAL | |
435 | * @len: DMA transfer length | |
436 | * @first: if NULL, set to the current descriptor and cookie set to -EBUSY | |
437 | * @direction: needed for slave DMA to decide which address to keep constant, | |
438 | * equals DMA_BIDIRECTIONAL for MEMCPY | |
439 | * Returns 0 or an error | |
440 | * Locks: called with desc_lock held | |
441 | */ | |
442 | static struct sh_desc *sh_dmae_add_desc(struct sh_dmae_chan *sh_chan, | |
443 | unsigned long flags, dma_addr_t *dest, dma_addr_t *src, size_t *len, | |
444 | struct sh_desc **first, enum dma_data_direction direction) | |
d8902adc | 445 | { |
fc461857 | 446 | struct sh_desc *new; |
d8902adc NI |
447 | size_t copy_size; |
448 | ||
fc461857 | 449 | if (!*len) |
d8902adc NI |
450 | return NULL; |
451 | ||
fc461857 GL |
452 | /* Allocate the link descriptor from the free list */ |
453 | new = sh_dmae_get_desc(sh_chan); | |
454 | if (!new) { | |
455 | dev_err(sh_chan->dev, "No free link descriptor available\n"); | |
d8902adc | 456 | return NULL; |
fc461857 | 457 | } |
d8902adc | 458 | |
fc461857 GL |
459 | copy_size = min(*len, (size_t)SH_DMA_TCR_MAX + 1); |
460 | ||
461 | new->hw.sar = *src; | |
462 | new->hw.dar = *dest; | |
463 | new->hw.tcr = copy_size; | |
464 | ||
465 | if (!*first) { | |
466 | /* First desc */ | |
467 | new->async_tx.cookie = -EBUSY; | |
468 | *first = new; | |
469 | } else { | |
470 | /* Other desc - invisible to the user */ | |
471 | new->async_tx.cookie = -EINVAL; | |
472 | } | |
473 | ||
cfefe997 GL |
474 | dev_dbg(sh_chan->dev, |
475 | "chaining (%u/%u)@%x -> %x with %p, cookie %d, shift %d\n", | |
fc461857 | 476 | copy_size, *len, *src, *dest, &new->async_tx, |
cfefe997 | 477 | new->async_tx.cookie, sh_chan->xmit_shift); |
fc461857 GL |
478 | |
479 | new->mark = DESC_PREPARED; | |
480 | new->async_tx.flags = flags; | |
cfefe997 | 481 | new->direction = direction; |
fc461857 GL |
482 | |
483 | *len -= copy_size; | |
484 | if (direction == DMA_BIDIRECTIONAL || direction == DMA_TO_DEVICE) | |
485 | *src += copy_size; | |
486 | if (direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE) | |
487 | *dest += copy_size; | |
488 | ||
489 | return new; | |
490 | } | |
491 | ||
492 | /* | |
493 | * sh_dmae_prep_sg - prepare transfer descriptors from an SG list | |
494 | * | |
495 | * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also | |
496 | * converted to scatter-gather to guarantee consistent locking and a correct | |
497 | * list manipulation. For slave DMA direction carries the usual meaning, and, | |
498 | * logically, the SG list is RAM and the addr variable contains slave address, | |
499 | * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_BIDIRECTIONAL | |
500 | * and the SG list contains only one element and points at the source buffer. | |
501 | */ | |
502 | static struct dma_async_tx_descriptor *sh_dmae_prep_sg(struct sh_dmae_chan *sh_chan, | |
503 | struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr, | |
504 | enum dma_data_direction direction, unsigned long flags) | |
505 | { | |
506 | struct scatterlist *sg; | |
507 | struct sh_desc *first = NULL, *new = NULL /* compiler... */; | |
508 | LIST_HEAD(tx_list); | |
509 | int chunks = 0; | |
510 | int i; | |
511 | ||
512 | if (!sg_len) | |
513 | return NULL; | |
514 | ||
515 | for_each_sg(sgl, sg, sg_len, i) | |
516 | chunks += (sg_dma_len(sg) + SH_DMA_TCR_MAX) / | |
517 | (SH_DMA_TCR_MAX + 1); | |
d8902adc | 518 | |
3542a113 GL |
519 | /* Have to lock the whole loop to protect against concurrent release */ |
520 | spin_lock_bh(&sh_chan->desc_lock); | |
521 | ||
522 | /* | |
523 | * Chaining: | |
524 | * first descriptor is what user is dealing with in all API calls, its | |
525 | * cookie is at first set to -EBUSY, at tx-submit to a positive | |
526 | * number | |
527 | * if more than one chunk is needed further chunks have cookie = -EINVAL | |
528 | * the last chunk, if not equal to the first, has cookie = -ENOSPC | |
529 | * all chunks are linked onto the tx_list head with their .node heads | |
530 | * only during this function, then they are immediately spliced | |
531 | * back onto the free list in form of a chain | |
532 | */ | |
fc461857 GL |
533 | for_each_sg(sgl, sg, sg_len, i) { |
534 | dma_addr_t sg_addr = sg_dma_address(sg); | |
535 | size_t len = sg_dma_len(sg); | |
536 | ||
537 | if (!len) | |
538 | goto err_get_desc; | |
539 | ||
540 | do { | |
541 | dev_dbg(sh_chan->dev, "Add SG #%d@%p[%d], dma %llx\n", | |
542 | i, sg, len, (unsigned long long)sg_addr); | |
543 | ||
544 | if (direction == DMA_FROM_DEVICE) | |
545 | new = sh_dmae_add_desc(sh_chan, flags, | |
546 | &sg_addr, addr, &len, &first, | |
547 | direction); | |
548 | else | |
549 | new = sh_dmae_add_desc(sh_chan, flags, | |
550 | addr, &sg_addr, &len, &first, | |
551 | direction); | |
552 | if (!new) | |
553 | goto err_get_desc; | |
554 | ||
555 | new->chunks = chunks--; | |
556 | list_add_tail(&new->node, &tx_list); | |
557 | } while (len); | |
558 | } | |
d8902adc | 559 | |
3542a113 GL |
560 | if (new != first) |
561 | new->async_tx.cookie = -ENOSPC; | |
d8902adc | 562 | |
3542a113 GL |
563 | /* Put them back on the free list, so, they don't get lost */ |
564 | list_splice_tail(&tx_list, &sh_chan->ld_free); | |
d8902adc | 565 | |
3542a113 | 566 | spin_unlock_bh(&sh_chan->desc_lock); |
d8902adc | 567 | |
3542a113 | 568 | return &first->async_tx; |
fc461857 GL |
569 | |
570 | err_get_desc: | |
571 | list_for_each_entry(new, &tx_list, node) | |
572 | new->mark = DESC_IDLE; | |
573 | list_splice(&tx_list, &sh_chan->ld_free); | |
574 | ||
575 | spin_unlock_bh(&sh_chan->desc_lock); | |
576 | ||
577 | return NULL; | |
578 | } | |
579 | ||
580 | static struct dma_async_tx_descriptor *sh_dmae_prep_memcpy( | |
581 | struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, | |
582 | size_t len, unsigned long flags) | |
583 | { | |
584 | struct sh_dmae_chan *sh_chan; | |
585 | struct scatterlist sg; | |
586 | ||
587 | if (!chan || !len) | |
588 | return NULL; | |
589 | ||
590 | sh_chan = to_sh_chan(chan); | |
591 | ||
592 | sg_init_table(&sg, 1); | |
593 | sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len, | |
594 | offset_in_page(dma_src)); | |
595 | sg_dma_address(&sg) = dma_src; | |
596 | sg_dma_len(&sg) = len; | |
597 | ||
598 | return sh_dmae_prep_sg(sh_chan, &sg, 1, &dma_dest, DMA_BIDIRECTIONAL, | |
599 | flags); | |
d8902adc NI |
600 | } |
601 | ||
cfefe997 GL |
602 | static struct dma_async_tx_descriptor *sh_dmae_prep_slave_sg( |
603 | struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, | |
604 | enum dma_data_direction direction, unsigned long flags) | |
605 | { | |
606 | struct sh_dmae_slave *param; | |
607 | struct sh_dmae_chan *sh_chan; | |
5bac942d | 608 | dma_addr_t slave_addr; |
cfefe997 GL |
609 | |
610 | if (!chan) | |
611 | return NULL; | |
612 | ||
613 | sh_chan = to_sh_chan(chan); | |
614 | param = chan->private; | |
615 | ||
616 | /* Someone calling slave DMA on a public channel? */ | |
617 | if (!param || !sg_len) { | |
618 | dev_warn(sh_chan->dev, "%s: bad parameter: %p, %d, %d\n", | |
619 | __func__, param, sg_len, param ? param->slave_id : -1); | |
620 | return NULL; | |
621 | } | |
622 | ||
9f9ff20d DC |
623 | slave_addr = param->config->addr; |
624 | ||
cfefe997 GL |
625 | /* |
626 | * if (param != NULL), this is a successfully requested slave channel, | |
627 | * therefore param->config != NULL too. | |
628 | */ | |
5bac942d | 629 | return sh_dmae_prep_sg(sh_chan, sgl, sg_len, &slave_addr, |
cfefe997 GL |
630 | direction, flags); |
631 | } | |
632 | ||
05827630 LW |
633 | static int sh_dmae_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
634 | unsigned long arg) | |
cfefe997 GL |
635 | { |
636 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
637 | ||
c3635c78 LW |
638 | /* Only supports DMA_TERMINATE_ALL */ |
639 | if (cmd != DMA_TERMINATE_ALL) | |
640 | return -ENXIO; | |
641 | ||
cfefe997 | 642 | if (!chan) |
c3635c78 | 643 | return -EINVAL; |
cfefe997 | 644 | |
2dc66667 | 645 | spin_lock_bh(&sh_chan->desc_lock); |
c014906a GL |
646 | dmae_halt(sh_chan); |
647 | ||
c014906a GL |
648 | if (!list_empty(&sh_chan->ld_queue)) { |
649 | /* Record partial transfer */ | |
650 | struct sh_desc *desc = list_entry(sh_chan->ld_queue.next, | |
651 | struct sh_desc, node); | |
652 | desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) << | |
653 | sh_chan->xmit_shift; | |
654 | ||
655 | } | |
656 | spin_unlock_bh(&sh_chan->desc_lock); | |
657 | ||
cfefe997 | 658 | sh_dmae_chan_ld_cleanup(sh_chan, true); |
c3635c78 LW |
659 | |
660 | return 0; | |
cfefe997 GL |
661 | } |
662 | ||
3542a113 | 663 | static dma_async_tx_callback __ld_cleanup(struct sh_dmae_chan *sh_chan, bool all) |
d8902adc NI |
664 | { |
665 | struct sh_desc *desc, *_desc; | |
3542a113 GL |
666 | /* Is the "exposed" head of a chain acked? */ |
667 | bool head_acked = false; | |
668 | dma_cookie_t cookie = 0; | |
669 | dma_async_tx_callback callback = NULL; | |
670 | void *param = NULL; | |
d8902adc NI |
671 | |
672 | spin_lock_bh(&sh_chan->desc_lock); | |
673 | list_for_each_entry_safe(desc, _desc, &sh_chan->ld_queue, node) { | |
3542a113 GL |
674 | struct dma_async_tx_descriptor *tx = &desc->async_tx; |
675 | ||
676 | BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie); | |
677 | BUG_ON(desc->mark != DESC_SUBMITTED && | |
678 | desc->mark != DESC_COMPLETED && | |
679 | desc->mark != DESC_WAITING); | |
680 | ||
681 | /* | |
682 | * queue is ordered, and we use this loop to (1) clean up all | |
683 | * completed descriptors, and to (2) update descriptor flags of | |
684 | * any chunks in a (partially) completed chain | |
685 | */ | |
686 | if (!all && desc->mark == DESC_SUBMITTED && | |
687 | desc->cookie != cookie) | |
d8902adc NI |
688 | break; |
689 | ||
3542a113 GL |
690 | if (tx->cookie > 0) |
691 | cookie = tx->cookie; | |
d8902adc | 692 | |
3542a113 | 693 | if (desc->mark == DESC_COMPLETED && desc->chunks == 1) { |
cfefe997 GL |
694 | if (sh_chan->completed_cookie != desc->cookie - 1) |
695 | dev_dbg(sh_chan->dev, | |
696 | "Completing cookie %d, expected %d\n", | |
697 | desc->cookie, | |
698 | sh_chan->completed_cookie + 1); | |
3542a113 GL |
699 | sh_chan->completed_cookie = desc->cookie; |
700 | } | |
d8902adc | 701 | |
3542a113 GL |
702 | /* Call callback on the last chunk */ |
703 | if (desc->mark == DESC_COMPLETED && tx->callback) { | |
704 | desc->mark = DESC_WAITING; | |
705 | callback = tx->callback; | |
706 | param = tx->callback_param; | |
707 | dev_dbg(sh_chan->dev, "descriptor #%d@%p on %d callback\n", | |
708 | tx->cookie, tx, sh_chan->id); | |
709 | BUG_ON(desc->chunks != 1); | |
710 | break; | |
711 | } | |
d8902adc | 712 | |
3542a113 GL |
713 | if (tx->cookie > 0 || tx->cookie == -EBUSY) { |
714 | if (desc->mark == DESC_COMPLETED) { | |
715 | BUG_ON(tx->cookie < 0); | |
716 | desc->mark = DESC_WAITING; | |
717 | } | |
718 | head_acked = async_tx_test_ack(tx); | |
719 | } else { | |
720 | switch (desc->mark) { | |
721 | case DESC_COMPLETED: | |
722 | desc->mark = DESC_WAITING; | |
723 | /* Fall through */ | |
724 | case DESC_WAITING: | |
725 | if (head_acked) | |
726 | async_tx_ack(&desc->async_tx); | |
727 | } | |
728 | } | |
729 | ||
730 | dev_dbg(sh_chan->dev, "descriptor %p #%d completed.\n", | |
731 | tx, tx->cookie); | |
732 | ||
733 | if (((desc->mark == DESC_COMPLETED || | |
734 | desc->mark == DESC_WAITING) && | |
735 | async_tx_test_ack(&desc->async_tx)) || all) { | |
736 | /* Remove from ld_queue list */ | |
737 | desc->mark = DESC_IDLE; | |
738 | list_move(&desc->node, &sh_chan->ld_free); | |
d8902adc NI |
739 | } |
740 | } | |
2dc66667 GL |
741 | |
742 | if (all && !callback) | |
743 | /* | |
744 | * Terminating and the loop completed normally: forgive | |
745 | * uncompleted cookies | |
746 | */ | |
747 | sh_chan->completed_cookie = sh_chan->common.cookie; | |
748 | ||
d8902adc | 749 | spin_unlock_bh(&sh_chan->desc_lock); |
3542a113 GL |
750 | |
751 | if (callback) | |
752 | callback(param); | |
753 | ||
754 | return callback; | |
755 | } | |
756 | ||
757 | /* | |
758 | * sh_chan_ld_cleanup - Clean up link descriptors | |
759 | * | |
760 | * This function cleans up the ld_queue of DMA channel. | |
761 | */ | |
762 | static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all) | |
763 | { | |
764 | while (__ld_cleanup(sh_chan, all)) | |
765 | ; | |
d8902adc NI |
766 | } |
767 | ||
768 | static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan) | |
769 | { | |
47a4dc26 | 770 | struct sh_desc *desc; |
d8902adc | 771 | |
3542a113 | 772 | spin_lock_bh(&sh_chan->desc_lock); |
d8902adc | 773 | /* DMA work check */ |
3542a113 GL |
774 | if (dmae_is_busy(sh_chan)) { |
775 | spin_unlock_bh(&sh_chan->desc_lock); | |
d8902adc | 776 | return; |
3542a113 | 777 | } |
d8902adc | 778 | |
5a3a7658 | 779 | /* Find the first not transferred descriptor */ |
47a4dc26 GL |
780 | list_for_each_entry(desc, &sh_chan->ld_queue, node) |
781 | if (desc->mark == DESC_SUBMITTED) { | |
c014906a GL |
782 | dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n", |
783 | desc->async_tx.cookie, sh_chan->id, | |
784 | desc->hw.tcr, desc->hw.sar, desc->hw.dar); | |
3542a113 | 785 | /* Get the ld start address from ld_queue */ |
47a4dc26 | 786 | dmae_set_reg(sh_chan, &desc->hw); |
3542a113 GL |
787 | dmae_start(sh_chan); |
788 | break; | |
789 | } | |
790 | ||
791 | spin_unlock_bh(&sh_chan->desc_lock); | |
d8902adc NI |
792 | } |
793 | ||
794 | static void sh_dmae_memcpy_issue_pending(struct dma_chan *chan) | |
795 | { | |
796 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
797 | sh_chan_xfer_ld_queue(sh_chan); | |
798 | } | |
799 | ||
07934481 | 800 | static enum dma_status sh_dmae_tx_status(struct dma_chan *chan, |
d8902adc | 801 | dma_cookie_t cookie, |
07934481 | 802 | struct dma_tx_state *txstate) |
d8902adc NI |
803 | { |
804 | struct sh_dmae_chan *sh_chan = to_sh_chan(chan); | |
805 | dma_cookie_t last_used; | |
806 | dma_cookie_t last_complete; | |
47a4dc26 | 807 | enum dma_status status; |
d8902adc | 808 | |
3542a113 | 809 | sh_dmae_chan_ld_cleanup(sh_chan, false); |
d8902adc | 810 | |
2dc66667 | 811 | /* First read completed cookie to avoid a skew */ |
d8902adc | 812 | last_complete = sh_chan->completed_cookie; |
2dc66667 GL |
813 | rmb(); |
814 | last_used = chan->cookie; | |
3542a113 | 815 | BUG_ON(last_complete < 0); |
bca34692 | 816 | dma_set_tx_state(txstate, last_complete, last_used, 0); |
d8902adc | 817 | |
47a4dc26 GL |
818 | spin_lock_bh(&sh_chan->desc_lock); |
819 | ||
820 | status = dma_async_is_complete(cookie, last_complete, last_used); | |
821 | ||
822 | /* | |
823 | * If we don't find cookie on the queue, it has been aborted and we have | |
824 | * to report error | |
825 | */ | |
826 | if (status != DMA_SUCCESS) { | |
827 | struct sh_desc *desc; | |
828 | status = DMA_ERROR; | |
829 | list_for_each_entry(desc, &sh_chan->ld_queue, node) | |
830 | if (desc->cookie == cookie) { | |
831 | status = DMA_IN_PROGRESS; | |
832 | break; | |
833 | } | |
834 | } | |
835 | ||
836 | spin_unlock_bh(&sh_chan->desc_lock); | |
837 | ||
838 | return status; | |
d8902adc NI |
839 | } |
840 | ||
841 | static irqreturn_t sh_dmae_interrupt(int irq, void *data) | |
842 | { | |
843 | irqreturn_t ret = IRQ_NONE; | |
2dc66667 GL |
844 | struct sh_dmae_chan *sh_chan = data; |
845 | u32 chcr; | |
846 | ||
847 | spin_lock(&sh_chan->desc_lock); | |
848 | ||
849 | chcr = sh_dmae_readl(sh_chan, CHCR); | |
d8902adc NI |
850 | |
851 | if (chcr & CHCR_TE) { | |
852 | /* DMA stop */ | |
853 | dmae_halt(sh_chan); | |
854 | ||
855 | ret = IRQ_HANDLED; | |
856 | tasklet_schedule(&sh_chan->tasklet); | |
857 | } | |
858 | ||
2dc66667 GL |
859 | spin_unlock(&sh_chan->desc_lock); |
860 | ||
d8902adc NI |
861 | return ret; |
862 | } | |
863 | ||
2dc66667 GL |
864 | /* Called from error IRQ or NMI */ |
865 | static bool sh_dmae_reset(struct sh_dmae_device *shdev) | |
d8902adc | 866 | { |
03aa18f5 | 867 | unsigned int handled = 0; |
47a4dc26 | 868 | int i; |
d8902adc | 869 | |
47a4dc26 | 870 | /* halt the dma controller */ |
027811b9 | 871 | sh_dmae_ctl_stop(shdev); |
47a4dc26 GL |
872 | |
873 | /* We cannot detect, which channel caused the error, have to reset all */ | |
8b1935e6 | 874 | for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) { |
47a4dc26 | 875 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; |
03aa18f5 | 876 | struct sh_desc *desc; |
2dc66667 | 877 | LIST_HEAD(dl); |
03aa18f5 PM |
878 | |
879 | if (!sh_chan) | |
880 | continue; | |
881 | ||
2dc66667 GL |
882 | spin_lock(&sh_chan->desc_lock); |
883 | ||
03aa18f5 PM |
884 | /* Stop the channel */ |
885 | dmae_halt(sh_chan); | |
886 | ||
2dc66667 GL |
887 | list_splice_init(&sh_chan->ld_queue, &dl); |
888 | ||
889 | spin_unlock(&sh_chan->desc_lock); | |
890 | ||
03aa18f5 | 891 | /* Complete all */ |
2dc66667 | 892 | list_for_each_entry(desc, &dl, node) { |
03aa18f5 PM |
893 | struct dma_async_tx_descriptor *tx = &desc->async_tx; |
894 | desc->mark = DESC_IDLE; | |
895 | if (tx->callback) | |
896 | tx->callback(tx->callback_param); | |
d8902adc | 897 | } |
03aa18f5 | 898 | |
2dc66667 GL |
899 | spin_lock(&sh_chan->desc_lock); |
900 | list_splice(&dl, &sh_chan->ld_free); | |
901 | spin_unlock(&sh_chan->desc_lock); | |
902 | ||
03aa18f5 | 903 | handled++; |
d8902adc | 904 | } |
03aa18f5 | 905 | |
027811b9 | 906 | sh_dmae_rst(shdev); |
47a4dc26 | 907 | |
03aa18f5 PM |
908 | return !!handled; |
909 | } | |
910 | ||
911 | static irqreturn_t sh_dmae_err(int irq, void *data) | |
912 | { | |
ff7690b4 YS |
913 | struct sh_dmae_device *shdev = data; |
914 | ||
2dc66667 | 915 | if (!(dmaor_read(shdev) & DMAOR_AE)) |
ff7690b4 | 916 | return IRQ_NONE; |
2dc66667 GL |
917 | |
918 | sh_dmae_reset(data); | |
919 | return IRQ_HANDLED; | |
d8902adc | 920 | } |
d8902adc NI |
921 | |
922 | static void dmae_do_tasklet(unsigned long data) | |
923 | { | |
924 | struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data; | |
3542a113 | 925 | struct sh_desc *desc; |
d8902adc | 926 | u32 sar_buf = sh_dmae_readl(sh_chan, SAR); |
cfefe997 | 927 | u32 dar_buf = sh_dmae_readl(sh_chan, DAR); |
86d61b33 | 928 | |
3542a113 GL |
929 | spin_lock(&sh_chan->desc_lock); |
930 | list_for_each_entry(desc, &sh_chan->ld_queue, node) { | |
cfefe997 GL |
931 | if (desc->mark == DESC_SUBMITTED && |
932 | ((desc->direction == DMA_FROM_DEVICE && | |
933 | (desc->hw.dar + desc->hw.tcr) == dar_buf) || | |
934 | (desc->hw.sar + desc->hw.tcr) == sar_buf)) { | |
3542a113 GL |
935 | dev_dbg(sh_chan->dev, "done #%d@%p dst %u\n", |
936 | desc->async_tx.cookie, &desc->async_tx, | |
937 | desc->hw.dar); | |
938 | desc->mark = DESC_COMPLETED; | |
d8902adc NI |
939 | break; |
940 | } | |
941 | } | |
3542a113 | 942 | spin_unlock(&sh_chan->desc_lock); |
d8902adc | 943 | |
d8902adc NI |
944 | /* Next desc */ |
945 | sh_chan_xfer_ld_queue(sh_chan); | |
3542a113 | 946 | sh_dmae_chan_ld_cleanup(sh_chan, false); |
d8902adc NI |
947 | } |
948 | ||
03aa18f5 PM |
949 | static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev) |
950 | { | |
03aa18f5 PM |
951 | /* Fast path out if NMIF is not asserted for this controller */ |
952 | if ((dmaor_read(shdev) & DMAOR_NMIF) == 0) | |
953 | return false; | |
954 | ||
2dc66667 | 955 | return sh_dmae_reset(shdev); |
03aa18f5 PM |
956 | } |
957 | ||
958 | static int sh_dmae_nmi_handler(struct notifier_block *self, | |
959 | unsigned long cmd, void *data) | |
960 | { | |
961 | struct sh_dmae_device *shdev; | |
962 | int ret = NOTIFY_DONE; | |
963 | bool triggered; | |
964 | ||
965 | /* | |
966 | * Only concern ourselves with NMI events. | |
967 | * | |
968 | * Normally we would check the die chain value, but as this needs | |
969 | * to be architecture independent, check for NMI context instead. | |
970 | */ | |
971 | if (!in_nmi()) | |
972 | return NOTIFY_DONE; | |
973 | ||
974 | rcu_read_lock(); | |
975 | list_for_each_entry_rcu(shdev, &sh_dmae_devices, node) { | |
976 | /* | |
977 | * Only stop if one of the controllers has NMIF asserted, | |
978 | * we do not want to interfere with regular address error | |
979 | * handling or NMI events that don't concern the DMACs. | |
980 | */ | |
981 | triggered = sh_dmae_nmi_notify(shdev); | |
982 | if (triggered == true) | |
983 | ret = NOTIFY_OK; | |
984 | } | |
985 | rcu_read_unlock(); | |
986 | ||
987 | return ret; | |
988 | } | |
989 | ||
990 | static struct notifier_block sh_dmae_nmi_notifier __read_mostly = { | |
991 | .notifier_call = sh_dmae_nmi_handler, | |
992 | ||
993 | /* Run before NMI debug handler and KGDB */ | |
994 | .priority = 1, | |
995 | }; | |
996 | ||
027811b9 GL |
997 | static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id, |
998 | int irq, unsigned long flags) | |
d8902adc NI |
999 | { |
1000 | int err; | |
5bac942d | 1001 | const struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id]; |
027811b9 | 1002 | struct platform_device *pdev = to_platform_device(shdev->common.dev); |
d8902adc NI |
1003 | struct sh_dmae_chan *new_sh_chan; |
1004 | ||
1005 | /* alloc channel */ | |
1006 | new_sh_chan = kzalloc(sizeof(struct sh_dmae_chan), GFP_KERNEL); | |
1007 | if (!new_sh_chan) { | |
86d61b33 GL |
1008 | dev_err(shdev->common.dev, |
1009 | "No free memory for allocating dma channels!\n"); | |
d8902adc NI |
1010 | return -ENOMEM; |
1011 | } | |
1012 | ||
8b1935e6 GL |
1013 | /* copy struct dma_device */ |
1014 | new_sh_chan->common.device = &shdev->common; | |
1015 | ||
d8902adc NI |
1016 | new_sh_chan->dev = shdev->common.dev; |
1017 | new_sh_chan->id = id; | |
027811b9 GL |
1018 | new_sh_chan->irq = irq; |
1019 | new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32); | |
d8902adc NI |
1020 | |
1021 | /* Init DMA tasklet */ | |
1022 | tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet, | |
1023 | (unsigned long)new_sh_chan); | |
1024 | ||
d8902adc NI |
1025 | spin_lock_init(&new_sh_chan->desc_lock); |
1026 | ||
1027 | /* Init descripter manage list */ | |
1028 | INIT_LIST_HEAD(&new_sh_chan->ld_queue); | |
1029 | INIT_LIST_HEAD(&new_sh_chan->ld_free); | |
1030 | ||
d8902adc NI |
1031 | /* Add the channel to DMA device channel list */ |
1032 | list_add_tail(&new_sh_chan->common.device_node, | |
1033 | &shdev->common.channels); | |
1034 | shdev->common.chancnt++; | |
1035 | ||
027811b9 GL |
1036 | if (pdev->id >= 0) |
1037 | snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id), | |
1038 | "sh-dmae%d.%d", pdev->id, new_sh_chan->id); | |
1039 | else | |
1040 | snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id), | |
1041 | "sh-dma%d", new_sh_chan->id); | |
d8902adc NI |
1042 | |
1043 | /* set up channel irq */ | |
027811b9 | 1044 | err = request_irq(irq, &sh_dmae_interrupt, flags, |
86d61b33 | 1045 | new_sh_chan->dev_id, new_sh_chan); |
d8902adc NI |
1046 | if (err) { |
1047 | dev_err(shdev->common.dev, "DMA channel %d request_irq error " | |
1048 | "with return %d\n", id, err); | |
1049 | goto err_no_irq; | |
1050 | } | |
1051 | ||
d8902adc NI |
1052 | shdev->chan[id] = new_sh_chan; |
1053 | return 0; | |
1054 | ||
1055 | err_no_irq: | |
1056 | /* remove from dmaengine device node */ | |
1057 | list_del(&new_sh_chan->common.device_node); | |
1058 | kfree(new_sh_chan); | |
1059 | return err; | |
1060 | } | |
1061 | ||
1062 | static void sh_dmae_chan_remove(struct sh_dmae_device *shdev) | |
1063 | { | |
1064 | int i; | |
1065 | ||
1066 | for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) { | |
1067 | if (shdev->chan[i]) { | |
027811b9 GL |
1068 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; |
1069 | ||
1070 | free_irq(sh_chan->irq, sh_chan); | |
d8902adc | 1071 | |
027811b9 GL |
1072 | list_del(&sh_chan->common.device_node); |
1073 | kfree(sh_chan); | |
d8902adc NI |
1074 | shdev->chan[i] = NULL; |
1075 | } | |
1076 | } | |
1077 | shdev->common.chancnt = 0; | |
1078 | } | |
1079 | ||
1080 | static int __init sh_dmae_probe(struct platform_device *pdev) | |
1081 | { | |
027811b9 GL |
1082 | struct sh_dmae_pdata *pdata = pdev->dev.platform_data; |
1083 | unsigned long irqflags = IRQF_DISABLED, | |
8b1935e6 GL |
1084 | chan_flag[SH_DMAC_MAX_CHANNELS] = {}; |
1085 | int errirq, chan_irq[SH_DMAC_MAX_CHANNELS]; | |
300e5f97 | 1086 | int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0; |
d8902adc | 1087 | struct sh_dmae_device *shdev; |
027811b9 | 1088 | struct resource *chan, *dmars, *errirq_res, *chanirq_res; |
d8902adc | 1089 | |
56adf7e8 | 1090 | /* get platform data */ |
027811b9 | 1091 | if (!pdata || !pdata->channel_num) |
56adf7e8 DW |
1092 | return -ENODEV; |
1093 | ||
027811b9 | 1094 | chan = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
26fc02ab | 1095 | /* DMARS area is optional */ |
027811b9 GL |
1096 | dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1097 | /* | |
1098 | * IRQ resources: | |
1099 | * 1. there always must be at least one IRQ IO-resource. On SH4 it is | |
1100 | * the error IRQ, in which case it is the only IRQ in this resource: | |
1101 | * start == end. If it is the only IRQ resource, all channels also | |
1102 | * use the same IRQ. | |
1103 | * 2. DMA channel IRQ resources can be specified one per resource or in | |
1104 | * ranges (start != end) | |
1105 | * 3. iff all events (channels and, optionally, error) on this | |
1106 | * controller use the same IRQ, only one IRQ resource can be | |
1107 | * specified, otherwise there must be one IRQ per channel, even if | |
1108 | * some of them are equal | |
1109 | * 4. if all IRQs on this controller are equal or if some specific IRQs | |
1110 | * specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be | |
1111 | * requested with the IRQF_SHARED flag | |
1112 | */ | |
1113 | errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1114 | if (!chan || !errirq_res) | |
1115 | return -ENODEV; | |
1116 | ||
1117 | if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) { | |
1118 | dev_err(&pdev->dev, "DMAC register region already claimed\n"); | |
1119 | return -EBUSY; | |
1120 | } | |
1121 | ||
1122 | if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) { | |
1123 | dev_err(&pdev->dev, "DMAC DMARS region already claimed\n"); | |
1124 | err = -EBUSY; | |
1125 | goto ermrdmars; | |
1126 | } | |
1127 | ||
1128 | err = -ENOMEM; | |
d8902adc NI |
1129 | shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL); |
1130 | if (!shdev) { | |
027811b9 GL |
1131 | dev_err(&pdev->dev, "Not enough memory\n"); |
1132 | goto ealloc; | |
1133 | } | |
1134 | ||
1135 | shdev->chan_reg = ioremap(chan->start, resource_size(chan)); | |
1136 | if (!shdev->chan_reg) | |
1137 | goto emapchan; | |
1138 | if (dmars) { | |
1139 | shdev->dmars = ioremap(dmars->start, resource_size(dmars)); | |
1140 | if (!shdev->dmars) | |
1141 | goto emapdmars; | |
d8902adc NI |
1142 | } |
1143 | ||
d8902adc | 1144 | /* platform data */ |
027811b9 | 1145 | shdev->pdata = pdata; |
d8902adc | 1146 | |
5c2de444 PM |
1147 | platform_set_drvdata(pdev, shdev); |
1148 | ||
20f2a3b5 GL |
1149 | pm_runtime_enable(&pdev->dev); |
1150 | pm_runtime_get_sync(&pdev->dev); | |
1151 | ||
31705e21 | 1152 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 1153 | list_add_tail_rcu(&shdev->node, &sh_dmae_devices); |
31705e21 | 1154 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 1155 | |
2dc66667 | 1156 | /* reset dma controller - only needed as a test */ |
027811b9 | 1157 | err = sh_dmae_rst(shdev); |
d8902adc NI |
1158 | if (err) |
1159 | goto rst_err; | |
1160 | ||
d8902adc NI |
1161 | INIT_LIST_HEAD(&shdev->common.channels); |
1162 | ||
1163 | dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask); | |
26fc02ab | 1164 | if (pdata->slave && pdata->slave_num) |
027811b9 | 1165 | dma_cap_set(DMA_SLAVE, shdev->common.cap_mask); |
cfefe997 | 1166 | |
d8902adc NI |
1167 | shdev->common.device_alloc_chan_resources |
1168 | = sh_dmae_alloc_chan_resources; | |
1169 | shdev->common.device_free_chan_resources = sh_dmae_free_chan_resources; | |
1170 | shdev->common.device_prep_dma_memcpy = sh_dmae_prep_memcpy; | |
07934481 | 1171 | shdev->common.device_tx_status = sh_dmae_tx_status; |
d8902adc | 1172 | shdev->common.device_issue_pending = sh_dmae_memcpy_issue_pending; |
cfefe997 GL |
1173 | |
1174 | /* Compulsory for DMA_SLAVE fields */ | |
1175 | shdev->common.device_prep_slave_sg = sh_dmae_prep_slave_sg; | |
c3635c78 | 1176 | shdev->common.device_control = sh_dmae_control; |
cfefe997 | 1177 | |
d8902adc | 1178 | shdev->common.dev = &pdev->dev; |
ddb4f0f0 | 1179 | /* Default transfer size of 32 bytes requires 32-byte alignment */ |
8b1935e6 | 1180 | shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE; |
d8902adc | 1181 | |
927a7c9c | 1182 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) |
027811b9 GL |
1183 | chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); |
1184 | ||
1185 | if (!chanirq_res) | |
1186 | chanirq_res = errirq_res; | |
1187 | else | |
1188 | irqres++; | |
1189 | ||
1190 | if (chanirq_res == errirq_res || | |
1191 | (errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE) | |
d8902adc | 1192 | irqflags = IRQF_SHARED; |
027811b9 GL |
1193 | |
1194 | errirq = errirq_res->start; | |
1195 | ||
1196 | err = request_irq(errirq, sh_dmae_err, irqflags, | |
1197 | "DMAC Address Error", shdev); | |
1198 | if (err) { | |
1199 | dev_err(&pdev->dev, | |
1200 | "DMA failed requesting irq #%d, error %d\n", | |
1201 | errirq, err); | |
1202 | goto eirq_err; | |
d8902adc NI |
1203 | } |
1204 | ||
027811b9 GL |
1205 | #else |
1206 | chanirq_res = errirq_res; | |
927a7c9c | 1207 | #endif /* CONFIG_CPU_SH4 || CONFIG_ARCH_SHMOBILE */ |
027811b9 GL |
1208 | |
1209 | if (chanirq_res->start == chanirq_res->end && | |
1210 | !platform_get_resource(pdev, IORESOURCE_IRQ, 1)) { | |
1211 | /* Special case - all multiplexed */ | |
1212 | for (; irq_cnt < pdata->channel_num; irq_cnt++) { | |
300e5f97 MD |
1213 | if (irq_cnt < SH_DMAC_MAX_CHANNELS) { |
1214 | chan_irq[irq_cnt] = chanirq_res->start; | |
1215 | chan_flag[irq_cnt] = IRQF_SHARED; | |
1216 | } else { | |
1217 | irq_cap = 1; | |
1218 | break; | |
1219 | } | |
d8902adc | 1220 | } |
027811b9 GL |
1221 | } else { |
1222 | do { | |
1223 | for (i = chanirq_res->start; i <= chanirq_res->end; i++) { | |
1224 | if ((errirq_res->flags & IORESOURCE_BITS) == | |
1225 | IORESOURCE_IRQ_SHAREABLE) | |
1226 | chan_flag[irq_cnt] = IRQF_SHARED; | |
1227 | else | |
1228 | chan_flag[irq_cnt] = IRQF_DISABLED; | |
1229 | dev_dbg(&pdev->dev, | |
1230 | "Found IRQ %d for channel %d\n", | |
1231 | i, irq_cnt); | |
1232 | chan_irq[irq_cnt++] = i; | |
300e5f97 MD |
1233 | |
1234 | if (irq_cnt >= SH_DMAC_MAX_CHANNELS) | |
1235 | break; | |
1236 | } | |
1237 | ||
1238 | if (irq_cnt >= SH_DMAC_MAX_CHANNELS) { | |
1239 | irq_cap = 1; | |
1240 | break; | |
027811b9 GL |
1241 | } |
1242 | chanirq_res = platform_get_resource(pdev, | |
1243 | IORESOURCE_IRQ, ++irqres); | |
1244 | } while (irq_cnt < pdata->channel_num && chanirq_res); | |
d8902adc | 1245 | } |
027811b9 | 1246 | |
d8902adc | 1247 | /* Create DMA Channel */ |
300e5f97 | 1248 | for (i = 0; i < irq_cnt; i++) { |
027811b9 | 1249 | err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]); |
d8902adc NI |
1250 | if (err) |
1251 | goto chan_probe_err; | |
1252 | } | |
1253 | ||
300e5f97 MD |
1254 | if (irq_cap) |
1255 | dev_notice(&pdev->dev, "Attempting to register %d DMA " | |
1256 | "channels when a maximum of %d are supported.\n", | |
1257 | pdata->channel_num, SH_DMAC_MAX_CHANNELS); | |
1258 | ||
20f2a3b5 GL |
1259 | pm_runtime_put(&pdev->dev); |
1260 | ||
d8902adc NI |
1261 | dma_async_device_register(&shdev->common); |
1262 | ||
1263 | return err; | |
1264 | ||
1265 | chan_probe_err: | |
1266 | sh_dmae_chan_remove(shdev); | |
300e5f97 | 1267 | |
927a7c9c | 1268 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) |
027811b9 | 1269 | free_irq(errirq, shdev); |
d8902adc | 1270 | eirq_err: |
027811b9 | 1271 | #endif |
d8902adc | 1272 | rst_err: |
31705e21 | 1273 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 1274 | list_del_rcu(&shdev->node); |
31705e21 | 1275 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 1276 | |
20f2a3b5 | 1277 | pm_runtime_put(&pdev->dev); |
467017b8 GL |
1278 | pm_runtime_disable(&pdev->dev); |
1279 | ||
027811b9 GL |
1280 | if (dmars) |
1281 | iounmap(shdev->dmars); | |
5c2de444 PM |
1282 | |
1283 | platform_set_drvdata(pdev, NULL); | |
027811b9 GL |
1284 | emapdmars: |
1285 | iounmap(shdev->chan_reg); | |
31705e21 | 1286 | synchronize_rcu(); |
027811b9 | 1287 | emapchan: |
d8902adc | 1288 | kfree(shdev); |
027811b9 GL |
1289 | ealloc: |
1290 | if (dmars) | |
1291 | release_mem_region(dmars->start, resource_size(dmars)); | |
1292 | ermrdmars: | |
1293 | release_mem_region(chan->start, resource_size(chan)); | |
d8902adc | 1294 | |
d8902adc NI |
1295 | return err; |
1296 | } | |
1297 | ||
1298 | static int __exit sh_dmae_remove(struct platform_device *pdev) | |
1299 | { | |
1300 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | |
027811b9 GL |
1301 | struct resource *res; |
1302 | int errirq = platform_get_irq(pdev, 0); | |
d8902adc NI |
1303 | |
1304 | dma_async_device_unregister(&shdev->common); | |
1305 | ||
027811b9 GL |
1306 | if (errirq > 0) |
1307 | free_irq(errirq, shdev); | |
d8902adc | 1308 | |
31705e21 | 1309 | spin_lock_irq(&sh_dmae_lock); |
03aa18f5 | 1310 | list_del_rcu(&shdev->node); |
31705e21 | 1311 | spin_unlock_irq(&sh_dmae_lock); |
03aa18f5 | 1312 | |
d8902adc NI |
1313 | /* channel data remove */ |
1314 | sh_dmae_chan_remove(shdev); | |
1315 | ||
20f2a3b5 GL |
1316 | pm_runtime_disable(&pdev->dev); |
1317 | ||
027811b9 GL |
1318 | if (shdev->dmars) |
1319 | iounmap(shdev->dmars); | |
1320 | iounmap(shdev->chan_reg); | |
1321 | ||
5c2de444 PM |
1322 | platform_set_drvdata(pdev, NULL); |
1323 | ||
31705e21 | 1324 | synchronize_rcu(); |
d8902adc NI |
1325 | kfree(shdev); |
1326 | ||
027811b9 GL |
1327 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1328 | if (res) | |
1329 | release_mem_region(res->start, resource_size(res)); | |
1330 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1331 | if (res) | |
1332 | release_mem_region(res->start, resource_size(res)); | |
1333 | ||
d8902adc NI |
1334 | return 0; |
1335 | } | |
1336 | ||
1337 | static void sh_dmae_shutdown(struct platform_device *pdev) | |
1338 | { | |
1339 | struct sh_dmae_device *shdev = platform_get_drvdata(pdev); | |
027811b9 | 1340 | sh_dmae_ctl_stop(shdev); |
d8902adc NI |
1341 | } |
1342 | ||
467017b8 GL |
1343 | static int sh_dmae_runtime_suspend(struct device *dev) |
1344 | { | |
1345 | return 0; | |
1346 | } | |
1347 | ||
1348 | static int sh_dmae_runtime_resume(struct device *dev) | |
1349 | { | |
1350 | struct sh_dmae_device *shdev = dev_get_drvdata(dev); | |
1351 | ||
1352 | return sh_dmae_rst(shdev); | |
1353 | } | |
1354 | ||
1355 | #ifdef CONFIG_PM | |
1356 | static int sh_dmae_suspend(struct device *dev) | |
1357 | { | |
1358 | struct sh_dmae_device *shdev = dev_get_drvdata(dev); | |
1359 | int i; | |
1360 | ||
1361 | for (i = 0; i < shdev->pdata->channel_num; i++) { | |
1362 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; | |
1363 | if (sh_chan->descs_allocated) | |
1364 | sh_chan->pm_error = pm_runtime_put_sync(dev); | |
1365 | } | |
1366 | ||
1367 | return 0; | |
1368 | } | |
1369 | ||
1370 | static int sh_dmae_resume(struct device *dev) | |
1371 | { | |
1372 | struct sh_dmae_device *shdev = dev_get_drvdata(dev); | |
1373 | int i; | |
1374 | ||
1375 | for (i = 0; i < shdev->pdata->channel_num; i++) { | |
1376 | struct sh_dmae_chan *sh_chan = shdev->chan[i]; | |
1377 | struct sh_dmae_slave *param = sh_chan->common.private; | |
1378 | ||
1379 | if (!sh_chan->descs_allocated) | |
1380 | continue; | |
1381 | ||
1382 | if (!sh_chan->pm_error) | |
1383 | pm_runtime_get_sync(dev); | |
1384 | ||
1385 | if (param) { | |
1386 | const struct sh_dmae_slave_config *cfg = param->config; | |
1387 | dmae_set_dmars(sh_chan, cfg->mid_rid); | |
1388 | dmae_set_chcr(sh_chan, cfg->chcr); | |
1389 | } else { | |
1390 | dmae_init(sh_chan); | |
1391 | } | |
1392 | } | |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | #else | |
1397 | #define sh_dmae_suspend NULL | |
1398 | #define sh_dmae_resume NULL | |
1399 | #endif | |
1400 | ||
1401 | const struct dev_pm_ops sh_dmae_pm = { | |
1402 | .suspend = sh_dmae_suspend, | |
1403 | .resume = sh_dmae_resume, | |
1404 | .runtime_suspend = sh_dmae_runtime_suspend, | |
1405 | .runtime_resume = sh_dmae_runtime_resume, | |
1406 | }; | |
1407 | ||
d8902adc NI |
1408 | static struct platform_driver sh_dmae_driver = { |
1409 | .remove = __exit_p(sh_dmae_remove), | |
1410 | .shutdown = sh_dmae_shutdown, | |
1411 | .driver = { | |
7a5c106a | 1412 | .owner = THIS_MODULE, |
d8902adc | 1413 | .name = "sh-dma-engine", |
467017b8 | 1414 | .pm = &sh_dmae_pm, |
d8902adc NI |
1415 | }, |
1416 | }; | |
1417 | ||
1418 | static int __init sh_dmae_init(void) | |
1419 | { | |
661382fe GL |
1420 | /* Wire up NMI handling */ |
1421 | int err = register_die_notifier(&sh_dmae_nmi_notifier); | |
1422 | if (err) | |
1423 | return err; | |
1424 | ||
d8902adc NI |
1425 | return platform_driver_probe(&sh_dmae_driver, sh_dmae_probe); |
1426 | } | |
1427 | module_init(sh_dmae_init); | |
1428 | ||
1429 | static void __exit sh_dmae_exit(void) | |
1430 | { | |
1431 | platform_driver_unregister(&sh_dmae_driver); | |
661382fe GL |
1432 | |
1433 | unregister_die_notifier(&sh_dmae_nmi_notifier); | |
d8902adc NI |
1434 | } |
1435 | module_exit(sh_dmae_exit); | |
1436 | ||
1437 | MODULE_AUTHOR("Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>"); | |
1438 | MODULE_DESCRIPTION("Renesas SH DMA Engine driver"); | |
1439 | MODULE_LICENSE("GPL"); | |
e5843341 | 1440 | MODULE_ALIAS("platform:sh-dma-engine"); |