Commit | Line | Data |
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d8902adc NI |
1 | /* |
2 | * Renesas SuperH DMA Engine support | |
3 | * | |
4 | * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
5 | * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved. | |
6 | * | |
7 | * This is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | */ | |
13 | #ifndef __DMA_SHDMA_H | |
14 | #define __DMA_SHDMA_H | |
15 | ||
d8902adc | 16 | #include <linux/dmaengine.h> |
3542a113 GL |
17 | #include <linux/interrupt.h> |
18 | #include <linux/list.h> | |
d8902adc | 19 | |
d026e00e | 20 | #define SH_DMAC_MAX_CHANNELS 20 |
02ca5083 | 21 | #define SH_DMA_SLAVE_NUMBER 256 |
d8902adc NI |
22 | #define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */ |
23 | ||
3542a113 GL |
24 | struct device; |
25 | ||
d8902adc NI |
26 | struct sh_dmae_chan { |
27 | dma_cookie_t completed_cookie; /* The maximum cookie completed */ | |
86d61b33 GL |
28 | spinlock_t desc_lock; /* Descriptor operation lock */ |
29 | struct list_head ld_queue; /* Link descriptors queue */ | |
30 | struct list_head ld_free; /* Link descriptors free */ | |
31 | struct dma_chan common; /* DMA common channel */ | |
32 | struct device *dev; /* Channel device */ | |
d8902adc | 33 | struct tasklet_struct tasklet; /* Tasklet */ |
86d61b33 | 34 | int descs_allocated; /* desc count */ |
cfefe997 | 35 | int xmit_shift; /* log_2(bytes_per_xfer) */ |
027811b9 | 36 | int irq; |
d8902adc | 37 | int id; /* Raw id of this channel */ |
027811b9 | 38 | u32 __iomem *base; |
86d61b33 | 39 | char dev_id[16]; /* unique name per DMAC of channel */ |
467017b8 | 40 | int pm_error; |
d8902adc NI |
41 | }; |
42 | ||
43 | struct sh_dmae_device { | |
44 | struct dma_device common; | |
8b1935e6 | 45 | struct sh_dmae_chan *chan[SH_DMAC_MAX_CHANNELS]; |
027811b9 | 46 | struct sh_dmae_pdata *pdata; |
03aa18f5 | 47 | struct list_head node; |
027811b9 GL |
48 | u32 __iomem *chan_reg; |
49 | u16 __iomem *dmars; | |
5899a723 | 50 | unsigned int chcr_offset; |
67c6269e | 51 | u32 chcr_ie_bit; |
d8902adc NI |
52 | }; |
53 | ||
54 | #define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common) | |
55 | #define to_sh_desc(lh) container_of(lh, struct sh_desc, node) | |
56 | #define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx) | |
c4e0dd78 KM |
57 | #define to_sh_dev(chan) container_of(chan->common.device,\ |
58 | struct sh_dmae_device, common) | |
d8902adc NI |
59 | |
60 | #endif /* __DMA_SHDMA_H */ |