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dmaengine: imx-dma: remove dma_mode member of internal structure.
[deliverable/linux.git] / drivers / dma / ste_dma40.c
CommitLineData
8d318a50 1/*
d49278e3
PF		 2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
661385f9 4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675 5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50 6 * License terms: GNU General Public License (GPL) version 2
8d318a50
LW		 7 */
8
b7f080cf 9#include <linux/dma-mapping.h>
8d318a50
LW		 10#include <linux/kernel.h>
11#include <linux/slab.h>
f492b210 12#include <linux/export.h>
8d318a50
LW		 13#include <linux/dmaengine.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
7fb3e75e
N		 17#include <linux/pm.h>
18#include <linux/pm_runtime.h>
698e4732 19#include <linux/err.h>
f4b89764 20#include <linux/amba/bus.h>
8d318a50
LW		 21
22#include <plat/ste_dma40.h>
23
d2ebfb33 24#include "dmaengine.h"
8d318a50
LW		 25#include "ste_dma40_ll.h"
26
27#define D40_NAME "dma40"
28
29#define D40_PHY_CHAN -1
30
31/* For masking out/in 2 bit channel positions */
32#define D40_CHAN_POS(chan) (2 * (chan / 2))
33#define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
34
35/* Maximum iterations taken before giving up suspending a channel */
36#define D40_SUSPEND_MAX_IT 500
37
7fb3e75e
N		 38/* Milliseconds */
39#define DMA40_AUTOSUSPEND_DELAY 100
40
508849ad
LW		 41/* Hardware requirement on LCLA alignment */
42#define LCLA_ALIGNMENT 0x40000
698e4732
JA		 43
44/* Max number of links per event group */
45#define D40_LCLA_LINK_PER_EVENT_GRP 128
46#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
47
508849ad
LW		 48/* Attempts before giving up to trying to get pages that are aligned */
49#define MAX_LCLA_ALLOC_ATTEMPTS 256
50
51/* Bit markings for allocation map */
8d318a50
LW		 52#define D40_ALLOC_FREE (1 << 31)
53#define D40_ALLOC_PHY (1 << 30)
54#define D40_ALLOC_LOG_FREE 0
55
8d318a50
LW		 56/**
57 * enum 40_command - The different commands and/or statuses.
58 *
59 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
60 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
61 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
62 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
63 */
64enum d40_command {
65 D40_DMA_STOP = 0,
66 D40_DMA_RUN = 1,
67 D40_DMA_SUSPEND_REQ = 2,
68 D40_DMA_SUSPENDED = 3
69};
70
7fb3e75e
N		 71/*
72 * These are the registers that has to be saved and later restored
73 * when the DMA hw is powered off.
74 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
75 */
76static u32 d40_backup_regs[] = {
77 D40_DREG_LCPA,
78 D40_DREG_LCLA,
79 D40_DREG_PRMSE,
80 D40_DREG_PRMSO,
81 D40_DREG_PRMOE,
82 D40_DREG_PRMOO,
83};
84
85#define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
86
87/* TODO: Check if all these registers have to be saved/restored on dma40 v3 */
88static u32 d40_backup_regs_v3[] = {
89 D40_DREG_PSEG1,
90 D40_DREG_PSEG2,
91 D40_DREG_PSEG3,
92 D40_DREG_PSEG4,
93 D40_DREG_PCEG1,
94 D40_DREG_PCEG2,
95 D40_DREG_PCEG3,
96 D40_DREG_PCEG4,
97 D40_DREG_RSEG1,
98 D40_DREG_RSEG2,
99 D40_DREG_RSEG3,
100 D40_DREG_RSEG4,
101 D40_DREG_RCEG1,
102 D40_DREG_RCEG2,
103 D40_DREG_RCEG3,
104 D40_DREG_RCEG4,
105};
106
107#define BACKUP_REGS_SZ_V3 ARRAY_SIZE(d40_backup_regs_v3)
108
109static u32 d40_backup_regs_chan[] = {
110 D40_CHAN_REG_SSCFG,
111 D40_CHAN_REG_SSELT,
112 D40_CHAN_REG_SSPTR,
113 D40_CHAN_REG_SSLNK,
114 D40_CHAN_REG_SDCFG,
115 D40_CHAN_REG_SDELT,
116 D40_CHAN_REG_SDPTR,
117 D40_CHAN_REG_SDLNK,
118};
119
8d318a50
LW		 120/**
121 * struct d40_lli_pool - Structure for keeping LLIs in memory
122 *
123 * @base: Pointer to memory area when the pre_alloc_lli's are not large
124 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
125 * pre_alloc_lli is used.
b00f938c 126 * @dma_addr: DMA address, if mapped
8d318a50
LW		 127 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
128 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
129 * one buffer to one buffer.
130 */
131struct d40_lli_pool {
132 void *base;
508849ad 133 int size;
b00f938c 134 dma_addr_t dma_addr;
8d318a50 135 /* Space for dst and src, plus an extra for padding */
508849ad 136 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
8d318a50
LW		 137};
138
139/**
140 * struct d40_desc - A descriptor is one DMA job.
141 *
142 * @lli_phy: LLI settings for physical channel. Both src and dst=
143 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
144 * lli_len equals one.
145 * @lli_log: Same as above but for logical channels.
146 * @lli_pool: The pool with two entries pre-allocated.
941b77a3 147 * @lli_len: Number of llis of current descriptor.
25985edc 148 * @lli_current: Number of transferred llis.
698e4732 149 * @lcla_alloc: Number of LCLA entries allocated.
8d318a50
LW		 150 * @txd: DMA engine struct. Used for among other things for communication
151 * during a transfer.
152 * @node: List entry.
8d318a50 153 * @is_in_client_list: true if the client owns this descriptor.
7fb3e75e 154 * @cyclic: true if this is a cyclic job
8d318a50
LW		 155 *
156 * This descriptor is used for both logical and physical transfers.
157 */
8d318a50
LW		 158struct d40_desc {
159 /* LLI physical */
160 struct d40_phy_lli_bidir lli_phy;
161 /* LLI logical */
162 struct d40_log_lli_bidir lli_log;
163
164 struct d40_lli_pool lli_pool;
941b77a3 165 int lli_len;
698e4732
JA		 166 int lli_current;
167 int lcla_alloc;
8d318a50
LW		 168
169 struct dma_async_tx_descriptor txd;
170 struct list_head node;
171
8d318a50 172 bool is_in_client_list;
0c842b55 173 bool cyclic;
8d318a50
LW		 174};
175
176/**
177 * struct d40_lcla_pool - LCLA pool settings and data.
178 *
508849ad
LW		 179 * @base: The virtual address of LCLA. 18 bit aligned.
180 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
181 * This pointer is only there for clean-up on error.
182 * @pages: The number of pages needed for all physical channels.
183 * Only used later for clean-up on error
8d318a50 184 * @lock: Lock to protect the content in this struct.
698e4732 185 * @alloc_map: big map over which LCLA entry is own by which job.
8d318a50
LW		 186 */
187struct d40_lcla_pool {
188 void *base;
026cbc42 189 dma_addr_t dma_addr;
508849ad
LW		 190 void *base_unaligned;
191 int pages;
8d318a50 192 spinlock_t lock;
698e4732 193 struct d40_desc **alloc_map;
8d318a50
LW		 194};
195
196/**
197 * struct d40_phy_res - struct for handling eventlines mapped to physical
198 * channels.
199 *
200 * @lock: A lock protection this entity.
7fb3e75e 201 * @reserved: True if used by secure world or otherwise.
8d318a50
LW		 202 * @num: The physical channel number of this entity.
203 * @allocated_src: Bit mapped to show which src event line's are mapped to
204 * this physical channel. Can also be free or physically allocated.
205 * @allocated_dst: Same as for src but is dst.
206 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
767a9675 207 * event line number.
8d318a50
LW		 208 */
209struct d40_phy_res {
210 spinlock_t lock;
7fb3e75e 211 bool reserved;
8d318a50
LW		 212 int num;
213 u32 allocated_src;
214 u32 allocated_dst;
215};
216
217struct d40_base;
218
219/**
220 * struct d40_chan - Struct that describes a channel.
221 *
222 * @lock: A spinlock to protect this struct.
223 * @log_num: The logical number, if any of this channel.
8d318a50
LW		 224 * @pending_tx: The number of pending transfers. Used between interrupt handler
225 * and tasklet.
226 * @busy: Set to true when transfer is ongoing on this channel.
2a614340
JA		 227 * @phy_chan: Pointer to physical channel which this instance runs on. If this
228 * point is NULL, then the channel is not allocated.
8d318a50
LW		 229 * @chan: DMA engine handle.
230 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
231 * transfer and call client callback.
232 * @client: Cliented owned descriptor list.
da063d26 233 * @pending_queue: Submitted jobs, to be issued by issue_pending()
8d318a50
LW		 234 * @active: Active descriptor.
235 * @queue: Queued jobs.
82babbb3 236 * @prepare_queue: Prepared jobs.
8d318a50 237 * @dma_cfg: The client configuration of this dma channel.
ce2ca125 238 * @configured: whether the dma_cfg configuration is valid
8d318a50
LW		 239 * @base: Pointer to the device instance struct.
240 * @src_def_cfg: Default cfg register setting for src.
241 * @dst_def_cfg: Default cfg register setting for dst.
242 * @log_def: Default logical channel settings.
8d318a50 243 * @lcpa: Pointer to dst and src lcpa settings.
ae752bf4 244 * @runtime_addr: runtime configured address.
245 * @runtime_direction: runtime configured direction.
8d318a50
LW		 246 *
247 * This struct can either "be" a logical or a physical channel.
248 */
249struct d40_chan {
250 spinlock_t lock;
251 int log_num;
8d318a50
LW		 252 int pending_tx;
253 bool busy;
254 struct d40_phy_res *phy_chan;
255 struct dma_chan chan;
256 struct tasklet_struct tasklet;
257 struct list_head client;
a8f3067b 258 struct list_head pending_queue;
8d318a50
LW		 259 struct list_head active;
260 struct list_head queue;
82babbb3 261 struct list_head prepare_queue;
8d318a50 262 struct stedma40_chan_cfg dma_cfg;
ce2ca125 263 bool configured;
8d318a50
LW		 264 struct d40_base *base;
265 /* Default register configurations */
266 u32 src_def_cfg;
267 u32 dst_def_cfg;
268 struct d40_def_lcsp log_def;
8d318a50 269 struct d40_log_lli_full *lcpa;
95e1400f
LW		 270 /* Runtime reconfiguration */
271 dma_addr_t runtime_addr;
db8196df 272 enum dma_transfer_direction runtime_direction;
8d318a50
LW		 273};
274
275/**
276 * struct d40_base - The big global struct, one for each probe'd instance.
277 *
278 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
279 * @execmd_lock: Lock for execute command usage since several channels share
280 * the same physical register.
281 * @dev: The device structure.
282 * @virtbase: The virtual base address of the DMA's register.
f4185592 283 * @rev: silicon revision detected.
8d318a50
LW		 284 * @clk: Pointer to the DMA clock structure.
285 * @phy_start: Physical memory start of the DMA registers.
286 * @phy_size: Size of the DMA register map.
287 * @irq: The IRQ number.
288 * @num_phy_chans: The number of physical channels. Read from HW. This
289 * is the number of available channels for this driver, not counting "Secure
290 * mode" allocated physical channels.
291 * @num_log_chans: The number of logical channels. Calculated from
292 * num_phy_chans.
293 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
294 * @dma_slave: dma_device channels that can do only do slave transfers.
295 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
7fb3e75e 296 * @phy_chans: Room for all possible physical channels in system.
8d318a50
LW		 297 * @log_chans: Room for all possible logical channels in system.
298 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
299 * to log_chans entries.
300 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
301 * to phy_chans entries.
302 * @plat_data: Pointer to provided platform_data which is the driver
303 * configuration.
28c7a19d 304 * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
8d318a50
LW		 305 * @phy_res: Vector containing all physical channels.
306 * @lcla_pool: lcla pool settings and data.
307 * @lcpa_base: The virtual mapped address of LCPA.
308 * @phy_lcpa: The physical address of the LCPA.
309 * @lcpa_size: The size of the LCPA area.
c675b1b4 310 * @desc_slab: cache for descriptors.
7fb3e75e
N		 311 * @reg_val_backup: Here the values of some hardware registers are stored
312 * before the DMA is powered off. They are restored when the power is back on.
313 * @reg_val_backup_v3: Backup of registers that only exits on dma40 v3 and
314 * later.
315 * @reg_val_backup_chan: Backup data for standard channel parameter registers.
316 * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
317 * @initialized: true if the dma has been initialized
8d318a50
LW		 318 */
319struct d40_base {
320 spinlock_t interrupt_lock;
321 spinlock_t execmd_lock;
322 struct device *dev;
323 void __iomem *virtbase;
f4185592 324 u8 rev:4;
8d318a50
LW		 325 struct clk *clk;
326 phys_addr_t phy_start;
327 resource_size_t phy_size;
328 int irq;
329 int num_phy_chans;
330 int num_log_chans;
331 struct dma_device dma_both;
332 struct dma_device dma_slave;
333 struct dma_device dma_memcpy;
334 struct d40_chan *phy_chans;
335 struct d40_chan *log_chans;
336 struct d40_chan **lookup_log_chans;
337 struct d40_chan **lookup_phy_chans;
338 struct stedma40_platform_data *plat_data;
28c7a19d 339 struct regulator *lcpa_regulator;
8d318a50
LW		 340 /* Physical half channels */
341 struct d40_phy_res *phy_res;
342 struct d40_lcla_pool lcla_pool;
343 void *lcpa_base;
344 dma_addr_t phy_lcpa;
345 resource_size_t lcpa_size;
c675b1b4 346 struct kmem_cache *desc_slab;
7fb3e75e
N		 347 u32 reg_val_backup[BACKUP_REGS_SZ];
348 u32 reg_val_backup_v3[BACKUP_REGS_SZ_V3];
349 u32 *reg_val_backup_chan;
350 u16 gcc_pwr_off_mask;
351 bool initialized;
8d318a50
LW		 352};
353
354/**
355 * struct d40_interrupt_lookup - lookup table for interrupt handler
356 *
357 * @src: Interrupt mask register.
358 * @clr: Interrupt clear register.
359 * @is_error: true if this is an error interrupt.
360 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
361 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
362 */
363struct d40_interrupt_lookup {
364 u32 src;
365 u32 clr;
366 bool is_error;
367 int offset;
368};
369
370/**
371 * struct d40_reg_val - simple lookup struct
372 *
373 * @reg: The register.
374 * @val: The value that belongs to the register in reg.
375 */
376struct d40_reg_val {
377 unsigned int reg;
378 unsigned int val;
379};
380
262d2915
RV		 381static struct device *chan2dev(struct d40_chan *d40c)
382{
383 return &d40c->chan.dev->device;
384}
385
724a8577
RV		 386static bool chan_is_physical(struct d40_chan *chan)
387{
388 return chan->log_num == D40_PHY_CHAN;
389}
390
391static bool chan_is_logical(struct d40_chan *chan)
392{
393 return !chan_is_physical(chan);
394}
395
8ca84687
RV		 396static void __iomem *chan_base(struct d40_chan *chan)
397{
398 return chan->base->virtbase + D40_DREG_PCBASE +
399 chan->phy_chan->num * D40_DREG_PCDELTA;
400}
401
6db5a8ba
RV		 402#define d40_err(dev, format, arg...) \
403 dev_err(dev, "[%s] " format, __func__, ## arg)
404
405#define chan_err(d40c, format, arg...) \
406 d40_err(chan2dev(d40c), format, ## arg)
407
b00f938c 408static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
dbd88788 409 int lli_len)
8d318a50 410{
dbd88788 411 bool is_log = chan_is_logical(d40c);
8d318a50
LW		 412 u32 align;
413 void *base;
414
415 if (is_log)
416 align = sizeof(struct d40_log_lli);
417 else
418 align = sizeof(struct d40_phy_lli);
419
420 if (lli_len == 1) {
421 base = d40d->lli_pool.pre_alloc_lli;
422 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
423 d40d->lli_pool.base = NULL;
424 } else {
594ece4d 425 d40d->lli_pool.size = lli_len * 2 * align;
8d318a50
LW		 426
427 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
428 d40d->lli_pool.base = base;
429
430 if (d40d->lli_pool.base == NULL)
431 return -ENOMEM;
432 }
433
434 if (is_log) {
d924abad 435 d40d->lli_log.src = PTR_ALIGN(base, align);
594ece4d 436 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
b00f938c
RV		 437
438 d40d->lli_pool.dma_addr = 0;
8d318a50 439 } else {
d924abad 440 d40d->lli_phy.src = PTR_ALIGN(base, align);
594ece4d 441 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
b00f938c
RV		 442
443 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
444 d40d->lli_phy.src,
445 d40d->lli_pool.size,
446 DMA_TO_DEVICE);
447
448 if (dma_mapping_error(d40c->base->dev,
449 d40d->lli_pool.dma_addr)) {
450 kfree(d40d->lli_pool.base);
451 d40d->lli_pool.base = NULL;
452 d40d->lli_pool.dma_addr = 0;
453 return -ENOMEM;
454 }
8d318a50
LW		 455 }
456
457 return 0;
458}
459
b00f938c 460static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
8d318a50 461{
b00f938c
RV		 462 if (d40d->lli_pool.dma_addr)
463 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
464 d40d->lli_pool.size, DMA_TO_DEVICE);
465
8d318a50
LW		 466 kfree(d40d->lli_pool.base);
467 d40d->lli_pool.base = NULL;
468 d40d->lli_pool.size = 0;
469 d40d->lli_log.src = NULL;
470 d40d->lli_log.dst = NULL;
471 d40d->lli_phy.src = NULL;
472 d40d->lli_phy.dst = NULL;
8d318a50
LW		 473}
474
698e4732
JA		 475static int d40_lcla_alloc_one(struct d40_chan *d40c,
476 struct d40_desc *d40d)
477{
478 unsigned long flags;
479 int i;
480 int ret = -EINVAL;
481 int p;
482
483 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
484
485 p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
486
487 /*
488 * Allocate both src and dst at the same time, therefore the half
489 * start on 1 since 0 can't be used since zero is used as end marker.
490 */
491 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
492 if (!d40c->base->lcla_pool.alloc_map[p + i]) {
493 d40c->base->lcla_pool.alloc_map[p + i] = d40d;
494 d40d->lcla_alloc++;
495 ret = i;
496 break;
497 }
498 }
499
500 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
501
502 return ret;
503}
504
505static int d40_lcla_free_all(struct d40_chan *d40c,
506 struct d40_desc *d40d)
507{
508 unsigned long flags;
509 int i;
510 int ret = -EINVAL;
511
724a8577 512 if (chan_is_physical(d40c))
698e4732
JA		 513 return 0;
514
515 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
516
517 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
518 if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
519 D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
520 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
521 D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
522 d40d->lcla_alloc--;
523 if (d40d->lcla_alloc == 0) {
524 ret = 0;
525 break;
526 }
527 }
528 }
529
530 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
531
532 return ret;
533
534}
535
8d318a50
LW		 536static void d40_desc_remove(struct d40_desc *d40d)
537{
538 list_del(&d40d->node);
539}
540
541static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
542{
a2c15fa4 543 struct d40_desc *desc = NULL;
8d318a50
LW		 544
545 if (!list_empty(&d40c->client)) {
a2c15fa4
RV		 546 struct d40_desc *d;
547 struct d40_desc *_d;
548
7fb3e75e 549 list_for_each_entry_safe(d, _d, &d40c->client, node) {
8d318a50 550 if (async_tx_test_ack(&d->txd)) {
8d318a50 551 d40_desc_remove(d);
a2c15fa4
RV		 552 desc = d;
553 memset(desc, 0, sizeof(*desc));
c675b1b4 554 break;
8d318a50 555 }
7fb3e75e 556 }
8d318a50 557 }
a2c15fa4
RV		 558
559 if (!desc)
560 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
561
562 if (desc)
563 INIT_LIST_HEAD(&desc->node);
564
565 return desc;
8d318a50
LW		 566}
567
568static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
569{
698e4732 570
b00f938c 571 d40_pool_lli_free(d40c, d40d);
698e4732 572 d40_lcla_free_all(d40c, d40d);
c675b1b4 573 kmem_cache_free(d40c->base->desc_slab, d40d);
8d318a50
LW		 574}
575
576static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
577{
578 list_add_tail(&desc->node, &d40c->active);
579}
580
1c4b0927
RV		 581static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
582{
583 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
584 struct d40_phy_lli *lli_src = desc->lli_phy.src;
585 void __iomem *base = chan_base(chan);
586
587 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
588 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
589 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
590 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
591
592 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
593 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
594 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
595 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
596}
597
e65889c7 598static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
698e4732 599{
e65889c7
RV		 600 struct d40_lcla_pool *pool = &chan->base->lcla_pool;
601 struct d40_log_lli_bidir *lli = &desc->lli_log;
602 int lli_current = desc->lli_current;
603 int lli_len = desc->lli_len;
0c842b55 604 bool cyclic = desc->cyclic;
e65889c7 605 int curr_lcla = -EINVAL;
0c842b55 606 int first_lcla = 0;
28c7a19d 607 bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
0c842b55 608 bool linkback;
e65889c7 609
0c842b55
RV		 610 /*
611 * We may have partially running cyclic transfers, in case we did't get
612 * enough LCLA entries.
613 */
614 linkback = cyclic && lli_current == 0;
615
616 /*
617 * For linkback, we need one LCLA even with only one link, because we
618 * can't link back to the one in LCPA space
619 */
620 if (linkback || (lli_len - lli_current > 1)) {
e65889c7 621 curr_lcla = d40_lcla_alloc_one(chan, desc);
0c842b55
RV		 622 first_lcla = curr_lcla;
623 }
624
625 /*
626 * For linkback, we normally load the LCPA in the loop since we need to
627 * link it to the second LCLA and not the first. However, if we
628 * couldn't even get a first LCLA, then we have to run in LCPA and
629 * reload manually.
630 */
631 if (!linkback || curr_lcla == -EINVAL) {
632 unsigned int flags = 0;
e65889c7 633
0c842b55
RV		 634 if (curr_lcla == -EINVAL)
635 flags |= LLI_TERM_INT;
e65889c7 636
0c842b55
RV		 637 d40_log_lli_lcpa_write(chan->lcpa,
638 &lli->dst[lli_current],
639 &lli->src[lli_current],
640 curr_lcla,
641 flags);
642 lli_current++;
643 }
6045f0bb
RV		 644
645 if (curr_lcla < 0)
646 goto out;
647
e65889c7
RV		 648 for (; lli_current < lli_len; lli_current++) {
649 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
650 8 * curr_lcla * 2;
651 struct d40_log_lli *lcla = pool->base + lcla_offset;
0c842b55 652 unsigned int flags = 0;
e65889c7
RV		 653 int next_lcla;
654
655 if (lli_current + 1 < lli_len)
656 next_lcla = d40_lcla_alloc_one(chan, desc);
657 else
0c842b55
RV		 658 next_lcla = linkback ? first_lcla : -EINVAL;
659
660 if (cyclic || next_lcla == -EINVAL)
661 flags |= LLI_TERM_INT;
e65889c7 662
0c842b55
RV		 663 if (linkback && curr_lcla == first_lcla) {
664 /* First link goes in both LCPA and LCLA */
665 d40_log_lli_lcpa_write(chan->lcpa,
666 &lli->dst[lli_current],
667 &lli->src[lli_current],
668 next_lcla, flags);
669 }
670
671 /*
672 * One unused LCLA in the cyclic case if the very first
673 * next_lcla fails...
674 */
e65889c7
RV		 675 d40_log_lli_lcla_write(lcla,
676 &lli->dst[lli_current],
677 &lli->src[lli_current],
0c842b55 678 next_lcla, flags);
e65889c7 679
28c7a19d
N		 680 /*
681 * Cache maintenance is not needed if lcla is
682 * mapped in esram
683 */
684 if (!use_esram_lcla) {
685 dma_sync_single_range_for_device(chan->base->dev,
686 pool->dma_addr, lcla_offset,
687 2 * sizeof(struct d40_log_lli),
688 DMA_TO_DEVICE);
689 }
e65889c7
RV		 690 curr_lcla = next_lcla;
691
0c842b55 692 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
e65889c7
RV		 693 lli_current++;
694 break;
695 }
696 }
697
6045f0bb 698out:
e65889c7
RV		 699 desc->lli_current = lli_current;
700}
698e4732 701
e65889c7
RV		 702static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
703{
724a8577 704 if (chan_is_physical(d40c)) {
1c4b0927 705 d40_phy_lli_load(d40c, d40d);
698e4732 706 d40d->lli_current = d40d->lli_len;
e65889c7
RV		 707 } else
708 d40_log_lli_to_lcxa(d40c, d40d);
698e4732
JA		 709}
710
8d318a50
LW		 711static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
712{
713 struct d40_desc *d;
714
715 if (list_empty(&d40c->active))
716 return NULL;
717
718 d = list_first_entry(&d40c->active,
719 struct d40_desc,
720 node);
721 return d;
722}
723
7404368c 724/* remove desc from current queue and add it to the pending_queue */
8d318a50
LW		 725static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
726{
7404368c
PF		 727 d40_desc_remove(desc);
728 desc->is_in_client_list = false;
a8f3067b
PF		 729 list_add_tail(&desc->node, &d40c->pending_queue);
730}
731
732static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
733{
734 struct d40_desc *d;
735
736 if (list_empty(&d40c->pending_queue))
737 return NULL;
738
739 d = list_first_entry(&d40c->pending_queue,
740 struct d40_desc,
741 node);
742 return d;
8d318a50
LW		 743}
744
745static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
746{
747 struct d40_desc *d;
748
749 if (list_empty(&d40c->queue))
750 return NULL;
751
752 d = list_first_entry(&d40c->queue,
753 struct d40_desc,
754 node);
755 return d;
756}
757
d49278e3
PF		 758static int d40_psize_2_burst_size(bool is_log, int psize)
759{
760 if (is_log) {
761 if (psize == STEDMA40_PSIZE_LOG_1)
762 return 1;
763 } else {
764 if (psize == STEDMA40_PSIZE_PHY_1)
765 return 1;
766 }
767
768 return 2 << psize;
769}
770
771/*
772 * The dma only supports transmitting packages up to
773 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
774 * dma elements required to send the entire sg list
775 */
776static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
777{
778 int dmalen;
779 u32 max_w = max(data_width1, data_width2);
780 u32 min_w = min(data_width1, data_width2);
781 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
782
783 if (seg_max > STEDMA40_MAX_SEG_SIZE)
784 seg_max -= (1 << max_w);
785
786 if (!IS_ALIGNED(size, 1 << max_w))
787 return -EINVAL;
788
789 if (size <= seg_max)
790 dmalen = 1;
791 else {
792 dmalen = size / seg_max;
793 if (dmalen * seg_max < size)
794 dmalen++;
795 }
796 return dmalen;
797}
798
799static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
800 u32 data_width1, u32 data_width2)
801{
802 struct scatterlist *sg;
803 int i;
804 int len = 0;
805 int ret;
806
807 for_each_sg(sgl, sg, sg_len, i) {
808 ret = d40_size_2_dmalen(sg_dma_len(sg),
809 data_width1, data_width2);
810 if (ret < 0)
811 return ret;
812 len += ret;
813 }
814 return len;
815}
8d318a50 816
7fb3e75e
N		 817
818#ifdef CONFIG_PM
819static void dma40_backup(void __iomem *baseaddr, u32 *backup,
820 u32 *regaddr, int num, bool save)
821{
822 int i;
823
824 for (i = 0; i < num; i++) {
825 void __iomem *addr = baseaddr + regaddr[i];
826
827 if (save)
828 backup[i] = readl_relaxed(addr);
829 else
830 writel_relaxed(backup[i], addr);
831 }
832}
833
834static void d40_save_restore_registers(struct d40_base *base, bool save)
835{
836 int i;
837
838 /* Save/Restore channel specific registers */
839 for (i = 0; i < base->num_phy_chans; i++) {
840 void __iomem *addr;
841 int idx;
842
843 if (base->phy_res[i].reserved)
844 continue;
845
846 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
847 idx = i * ARRAY_SIZE(d40_backup_regs_chan);
848
849 dma40_backup(addr, &base->reg_val_backup_chan[idx],
850 d40_backup_regs_chan,
851 ARRAY_SIZE(d40_backup_regs_chan),
852 save);
853 }
854
855 /* Save/Restore global registers */
856 dma40_backup(base->virtbase, base->reg_val_backup,
857 d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
858 save);
859
860 /* Save/Restore registers only existing on dma40 v3 and later */
861 if (base->rev >= 3)
862 dma40_backup(base->virtbase, base->reg_val_backup_v3,
863 d40_backup_regs_v3,
864 ARRAY_SIZE(d40_backup_regs_v3),
865 save);
866}
867#else
868static void d40_save_restore_registers(struct d40_base *base, bool save)
869{
870}
871#endif
8d318a50
LW		 872
873static int d40_channel_execute_command(struct d40_chan *d40c,
874 enum d40_command command)
875{
767a9675
JA		 876 u32 status;
877 int i;
8d318a50
LW		 878 void __iomem *active_reg;
879 int ret = 0;
880 unsigned long flags;
1d392a7b 881 u32 wmask;
8d318a50
LW		 882
883 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
884
885 if (d40c->phy_chan->num % 2 == 0)
886 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
887 else
888 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
889
890 if (command == D40_DMA_SUSPEND_REQ) {
891 status = (readl(active_reg) &
892 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
893 D40_CHAN_POS(d40c->phy_chan->num);
894
895 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
896 goto done;
897 }
898
1d392a7b
JA		 899 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
900 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
901 active_reg);
8d318a50
LW		 902
903 if (command == D40_DMA_SUSPEND_REQ) {
904
905 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
906 status = (readl(active_reg) &
907 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
908 D40_CHAN_POS(d40c->phy_chan->num);
909
910 cpu_relax();
911 /*
912 * Reduce the number of bus accesses while
913 * waiting for the DMA to suspend.
914 */
915 udelay(3);
916
917 if (status == D40_DMA_STOP ||
918 status == D40_DMA_SUSPENDED)
919 break;
920 }
921
922 if (i == D40_SUSPEND_MAX_IT) {
6db5a8ba
RV		 923 chan_err(d40c,
924 "unable to suspend the chl %d (log: %d) status %x\n",
925 d40c->phy_chan->num, d40c->log_num,
8d318a50
LW		 926 status);
927 dump_stack();
928 ret = -EBUSY;
929 }
930
931 }
932done:
933 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
934 return ret;
935}
936
937static void d40_term_all(struct d40_chan *d40c)
938{
939 struct d40_desc *d40d;
7404368c 940 struct d40_desc *_d;
8d318a50
LW		 941
942 /* Release active descriptors */
943 while ((d40d = d40_first_active_get(d40c))) {
944 d40_desc_remove(d40d);
8d318a50
LW		 945 d40_desc_free(d40c, d40d);
946 }
947
948 /* Release queued descriptors waiting for transfer */
949 while ((d40d = d40_first_queued(d40c))) {
950 d40_desc_remove(d40d);
8d318a50
LW		 951 d40_desc_free(d40c, d40d);
952 }
953
a8f3067b
PF		 954 /* Release pending descriptors */
955 while ((d40d = d40_first_pending(d40c))) {
956 d40_desc_remove(d40d);
957 d40_desc_free(d40c, d40d);
958 }
8d318a50 959
7404368c
PF		 960 /* Release client owned descriptors */
961 if (!list_empty(&d40c->client))
962 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
963 d40_desc_remove(d40d);
964 d40_desc_free(d40c, d40d);
965 }
966
82babbb3
PF		 967 /* Release descriptors in prepare queue */
968 if (!list_empty(&d40c->prepare_queue))
969 list_for_each_entry_safe(d40d, _d,
970 &d40c->prepare_queue, node) {
971 d40_desc_remove(d40d);
972 d40_desc_free(d40c, d40d);
973 }
7404368c 974
8d318a50
LW		 975 d40c->pending_tx = 0;
976 d40c->busy = false;
977}
978
262d2915
RV		 979static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
980 u32 event, int reg)
981{
8ca84687 982 void __iomem *addr = chan_base(d40c) + reg;
262d2915
RV		 983 int tries;
984
985 if (!enable) {
986 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
987 | ~D40_EVENTLINE_MASK(event), addr);
988 return;
989 }
990
991 /*
992 * The hardware sometimes doesn't register the enable when src and dst
993 * event lines are active on the same logical channel. Retry to ensure
994 * it does. Usually only one retry is sufficient.
995 */
996 tries = 100;
997 while (--tries) {
998 writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
999 | ~D40_EVENTLINE_MASK(event), addr);
1000
1001 if (readl(addr) & D40_EVENTLINE_MASK(event))
1002 break;
1003 }
1004
1005 if (tries != 99)
1006 dev_dbg(chan2dev(d40c),
1007 "[%s] workaround enable S%cLNK (%d tries)\n",
1008 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1009 100 - tries);
1010
1011 WARN_ON(!tries);
1012}
1013
8d318a50
LW		 1014static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
1015{
8d318a50
LW		 1016 unsigned long flags;
1017
8d318a50
LW		 1018 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1019
1020 /* Enable event line connected to device (or memcpy) */
1021 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
1022 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
1023 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1024
262d2915
RV		 1025 __d40_config_set_event(d40c, do_enable, event,
1026 D40_CHAN_REG_SSLNK);
8d318a50 1027 }
262d2915 1028
8d318a50
LW		 1029 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
1030 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1031
262d2915
RV		 1032 __d40_config_set_event(d40c, do_enable, event,
1033 D40_CHAN_REG_SDLNK);
8d318a50
LW		 1034 }
1035
1036 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1037}
1038
a5ebca47 1039static u32 d40_chan_has_events(struct d40_chan *d40c)
8d318a50 1040{
8ca84687 1041 void __iomem *chanbase = chan_base(d40c);
be8cb7df 1042 u32 val;
8d318a50 1043
8ca84687
RV		 1044 val = readl(chanbase + D40_CHAN_REG_SSLNK);
1045 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
be8cb7df 1046
a5ebca47 1047 return val;
8d318a50
LW		 1048}
1049
20a5b6d0
RV		 1050static u32 d40_get_prmo(struct d40_chan *d40c)
1051{
1052 static const unsigned int phy_map[] = {
1053 [STEDMA40_PCHAN_BASIC_MODE]
1054 = D40_DREG_PRMO_PCHAN_BASIC,
1055 [STEDMA40_PCHAN_MODULO_MODE]
1056 = D40_DREG_PRMO_PCHAN_MODULO,
1057 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1058 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1059 };
1060 static const unsigned int log_map[] = {
1061 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1062 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1063 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1064 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1065 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1066 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1067 };
1068
724a8577 1069 if (chan_is_physical(d40c))
20a5b6d0
RV		 1070 return phy_map[d40c->dma_cfg.mode_opt];
1071 else
1072 return log_map[d40c->dma_cfg.mode_opt];
1073}
1074
b55912c6 1075static void d40_config_write(struct d40_chan *d40c)
8d318a50
LW		 1076{
1077 u32 addr_base;
1078 u32 var;
8d318a50
LW		 1079
1080 /* Odd addresses are even addresses + 4 */
1081 addr_base = (d40c->phy_chan->num % 2) * 4;
1082 /* Setup channel mode to logical or physical */
724a8577 1083 var = ((u32)(chan_is_logical(d40c)) + 1) <<
8d318a50
LW		 1084 D40_CHAN_POS(d40c->phy_chan->num);
1085 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1086
1087 /* Setup operational mode option register */
20a5b6d0 1088 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
8d318a50
LW		 1089
1090 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1091
724a8577 1092 if (chan_is_logical(d40c)) {
8ca84687
RV		 1093 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1094 & D40_SREG_ELEM_LOG_LIDX_MASK;
1095 void __iomem *chanbase = chan_base(d40c);
1096
8d318a50 1097 /* Set default config for CFG reg */
8ca84687
RV		 1098 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1099 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
8d318a50 1100
b55912c6 1101 /* Set LIDX for lcla */
8ca84687
RV		 1102 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1103 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
e9f3a49c
RV		 1104
1105 /* Clear LNK which will be used by d40_chan_has_events() */
1106 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1107 writel(0, chanbase + D40_CHAN_REG_SDLNK);
8d318a50 1108 }
8d318a50
LW		 1109}
1110
aa182ae2
JA		 1111static u32 d40_residue(struct d40_chan *d40c)
1112{
1113 u32 num_elt;
1114
724a8577 1115 if (chan_is_logical(d40c))
aa182ae2
JA		 1116 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1117 >> D40_MEM_LCSP2_ECNT_POS;
8ca84687
RV		 1118 else {
1119 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1120 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1121 >> D40_SREG_ELEM_PHY_ECNT_POS;
1122 }
1123
aa182ae2
JA		 1124 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
1125}
1126
1127static bool d40_tx_is_linked(struct d40_chan *d40c)
1128{
1129 bool is_link;
1130
724a8577 1131 if (chan_is_logical(d40c))
aa182ae2
JA		 1132 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
1133 else
8ca84687
RV		 1134 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1135 & D40_SREG_LNK_PHYS_LNK_MASK;
1136
aa182ae2
JA		 1137 return is_link;
1138}
1139
86eb5fb6 1140static int d40_pause(struct d40_chan *d40c)
aa182ae2 1141{
aa182ae2
JA		 1142 int res = 0;
1143 unsigned long flags;
1144
3ac012af
JA		 1145 if (!d40c->busy)
1146 return 0;
1147
7fb3e75e 1148 pm_runtime_get_sync(d40c->base->dev);
aa182ae2
JA		 1149 spin_lock_irqsave(&d40c->lock, flags);
1150
1151 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1152 if (res == 0) {
724a8577 1153 if (chan_is_logical(d40c)) {
aa182ae2
JA		 1154 d40_config_set_event(d40c, false);
1155 /* Resume the other logical channels if any */
1156 if (d40_chan_has_events(d40c))
1157 res = d40_channel_execute_command(d40c,
1158 D40_DMA_RUN);
1159 }
1160 }
7fb3e75e
N		 1161 pm_runtime_mark_last_busy(d40c->base->dev);
1162 pm_runtime_put_autosuspend(d40c->base->dev);
aa182ae2
JA		 1163 spin_unlock_irqrestore(&d40c->lock, flags);
1164 return res;
1165}
1166
86eb5fb6 1167static int d40_resume(struct d40_chan *d40c)
aa182ae2 1168{
aa182ae2
JA		 1169 int res = 0;
1170 unsigned long flags;
1171
3ac012af
JA		 1172 if (!d40c->busy)
1173 return 0;
1174
aa182ae2 1175 spin_lock_irqsave(&d40c->lock, flags);
7fb3e75e 1176 pm_runtime_get_sync(d40c->base->dev);
aa182ae2 1177 if (d40c->base->rev == 0)
724a8577 1178 if (chan_is_logical(d40c)) {
aa182ae2
JA		 1179 res = d40_channel_execute_command(d40c,
1180 D40_DMA_SUSPEND_REQ);
1181 goto no_suspend;
1182 }
1183
1184 /* If bytes left to transfer or linked tx resume job */
1185 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
1186
724a8577 1187 if (chan_is_logical(d40c))
aa182ae2
JA		 1188 d40_config_set_event(d40c, true);
1189
1190 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1191 }
1192
1193no_suspend:
7fb3e75e
N		 1194 pm_runtime_mark_last_busy(d40c->base->dev);
1195 pm_runtime_put_autosuspend(d40c->base->dev);
aa182ae2
JA		 1196 spin_unlock_irqrestore(&d40c->lock, flags);
1197 return res;
1198}
1199
86eb5fb6
RV		 1200static int d40_terminate_all(struct d40_chan *chan)
1201{
1202 unsigned long flags;
1203 int ret = 0;
1204
1205 ret = d40_pause(chan);
1206 if (!ret && chan_is_physical(chan))
1207 ret = d40_channel_execute_command(chan, D40_DMA_STOP);
1208
1209 spin_lock_irqsave(&chan->lock, flags);
1210 d40_term_all(chan);
1211 spin_unlock_irqrestore(&chan->lock, flags);
1212
1213 return ret;
1214}
1215
8d318a50
LW		 1216static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1217{
1218 struct d40_chan *d40c = container_of(tx->chan,
1219 struct d40_chan,
1220 chan);
1221 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1222 unsigned long flags;
884485e1 1223 dma_cookie_t cookie;
8d318a50
LW		 1224
1225 spin_lock_irqsave(&d40c->lock, flags);
884485e1 1226 cookie = dma_cookie_assign(tx);
8d318a50 1227 d40_desc_queue(d40c, d40d);
8d318a50
LW		 1228 spin_unlock_irqrestore(&d40c->lock, flags);
1229
884485e1 1230 return cookie;
8d318a50
LW		 1231}
1232
1233static int d40_start(struct d40_chan *d40c)
1234{
f4185592
LW		 1235 if (d40c->base->rev == 0) {
1236 int err;
1237
724a8577 1238 if (chan_is_logical(d40c)) {
f4185592
LW		 1239 err = d40_channel_execute_command(d40c,
1240 D40_DMA_SUSPEND_REQ);
1241 if (err)
1242 return err;
1243 }
1244 }
1245
724a8577 1246 if (chan_is_logical(d40c))
8d318a50 1247 d40_config_set_event(d40c, true);
8d318a50 1248
0c32269d 1249 return d40_channel_execute_command(d40c, D40_DMA_RUN);
8d318a50
LW		 1250}
1251
1252static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1253{
1254 struct d40_desc *d40d;
1255 int err;
1256
1257 /* Start queued jobs, if any */
1258 d40d = d40_first_queued(d40c);
1259
1260 if (d40d != NULL) {
7fb3e75e
N		 1261 if (!d40c->busy)
1262 d40c->busy = true;
1263
1264 pm_runtime_get_sync(d40c->base->dev);
8d318a50
LW		 1265
1266 /* Remove from queue */
1267 d40_desc_remove(d40d);
1268
1269 /* Add to active queue */
1270 d40_desc_submit(d40c, d40d);
1271
7d83a854
RV		 1272 /* Initiate DMA job */
1273 d40_desc_load(d40c, d40d);
8d318a50 1274
7d83a854
RV		 1275 /* Start dma job */
1276 err = d40_start(d40c);
8d318a50 1277
7d83a854
RV		 1278 if (err)
1279 return NULL;
8d318a50
LW		 1280 }
1281
1282 return d40d;
1283}
1284
1285/* called from interrupt context */
1286static void dma_tc_handle(struct d40_chan *d40c)
1287{
1288 struct d40_desc *d40d;
1289
8d318a50
LW		 1290 /* Get first active entry from list */
1291 d40d = d40_first_active_get(d40c);
1292
1293 if (d40d == NULL)
1294 return;
1295
0c842b55
RV		 1296 if (d40d->cyclic) {
1297 /*
1298 * If this was a paritially loaded list, we need to reloaded
1299 * it, and only when the list is completed. We need to check
1300 * for done because the interrupt will hit for every link, and
1301 * not just the last one.
1302 */
1303 if (d40d->lli_current < d40d->lli_len
1304 && !d40_tx_is_linked(d40c)
1305 && !d40_residue(d40c)) {
1306 d40_lcla_free_all(d40c, d40d);
1307 d40_desc_load(d40c, d40d);
1308 (void) d40_start(d40c);
8d318a50 1309
0c842b55
RV		 1310 if (d40d->lli_current == d40d->lli_len)
1311 d40d->lli_current = 0;
1312 }
1313 } else {
1314 d40_lcla_free_all(d40c, d40d);
8d318a50 1315
0c842b55
RV		 1316 if (d40d->lli_current < d40d->lli_len) {
1317 d40_desc_load(d40c, d40d);
1318 /* Start dma job */
1319 (void) d40_start(d40c);
1320 return;
1321 }
1322
1323 if (d40_queue_start(d40c) == NULL)
1324 d40c->busy = false;
7fb3e75e
N		 1325 pm_runtime_mark_last_busy(d40c->base->dev);
1326 pm_runtime_put_autosuspend(d40c->base->dev);
0c842b55 1327 }
8d318a50
LW		 1328
1329 d40c->pending_tx++;
1330 tasklet_schedule(&d40c->tasklet);
1331
1332}
1333
1334static void dma_tasklet(unsigned long data)
1335{
1336 struct d40_chan *d40c = (struct d40_chan *) data;
767a9675 1337 struct d40_desc *d40d;
8d318a50
LW		 1338 unsigned long flags;
1339 dma_async_tx_callback callback;
1340 void *callback_param;
1341
1342 spin_lock_irqsave(&d40c->lock, flags);
1343
1344 /* Get first active entry from list */
767a9675 1345 d40d = d40_first_active_get(d40c);
767a9675 1346 if (d40d == NULL)
8d318a50
LW		 1347 goto err;
1348
0c842b55 1349 if (!d40d->cyclic)
f7fbce07 1350 dma_cookie_complete(&d40d->txd);
8d318a50
LW		 1351
1352 /*
1353 * If terminating a channel pending_tx is set to zero.
1354 * This prevents any finished active jobs to return to the client.
1355 */
1356 if (d40c->pending_tx == 0) {
1357 spin_unlock_irqrestore(&d40c->lock, flags);
1358 return;
1359 }
1360
1361 /* Callback to client */
767a9675
JA		 1362 callback = d40d->txd.callback;
1363 callback_param = d40d->txd.callback_param;
1364
0c842b55
RV		 1365 if (!d40d->cyclic) {
1366 if (async_tx_test_ack(&d40d->txd)) {
767a9675 1367 d40_desc_remove(d40d);
0c842b55
RV		 1368 d40_desc_free(d40c, d40d);
1369 } else {
1370 if (!d40d->is_in_client_list) {
1371 d40_desc_remove(d40d);
1372 d40_lcla_free_all(d40c, d40d);
1373 list_add_tail(&d40d->node, &d40c->client);
1374 d40d->is_in_client_list = true;
1375 }
8d318a50
LW		 1376 }
1377 }
1378
1379 d40c->pending_tx--;
1380
1381 if (d40c->pending_tx)
1382 tasklet_schedule(&d40c->tasklet);
1383
1384 spin_unlock_irqrestore(&d40c->lock, flags);
1385
767a9675 1386 if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
8d318a50
LW		 1387 callback(callback_param);
1388
1389 return;
1390
1391 err:
25985edc 1392 /* Rescue manoeuvre if receiving double interrupts */
8d318a50
LW		 1393 if (d40c->pending_tx > 0)
1394 d40c->pending_tx--;
1395 spin_unlock_irqrestore(&d40c->lock, flags);
1396}
1397
1398static irqreturn_t d40_handle_interrupt(int irq, void *data)
1399{
1400 static const struct d40_interrupt_lookup il[] = {
1401 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
1402 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
1403 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
1404 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
1405 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
1406 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
1407 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
1408 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
1409 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
1410 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
1411 };
1412
1413 int i;
1414 u32 regs[ARRAY_SIZE(il)];
8d318a50
LW		 1415 u32 idx;
1416 u32 row;
1417 long chan = -1;
1418 struct d40_chan *d40c;
1419 unsigned long flags;
1420 struct d40_base *base = data;
1421
1422 spin_lock_irqsave(&base->interrupt_lock, flags);
1423
1424 /* Read interrupt status of both logical and physical channels */
1425 for (i = 0; i < ARRAY_SIZE(il); i++)
1426 regs[i] = readl(base->virtbase + il[i].src);
1427
1428 for (;;) {
1429
1430 chan = find_next_bit((unsigned long *)regs,
1431 BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
1432
1433 /* No more set bits found? */
1434 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
1435 break;
1436
1437 row = chan / BITS_PER_LONG;
1438 idx = chan & (BITS_PER_LONG - 1);
1439
1440 /* ACK interrupt */
1b00348d 1441 writel(1 << idx, base->virtbase + il[row].clr);
8d318a50
LW		 1442
1443 if (il[row].offset == D40_PHY_CHAN)
1444 d40c = base->lookup_phy_chans[idx];
1445 else
1446 d40c = base->lookup_log_chans[il[row].offset + idx];
1447 spin_lock(&d40c->lock);
1448
1449 if (!il[row].is_error)
1450 dma_tc_handle(d40c);
1451 else
6db5a8ba
RV		 1452 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1453 chan, il[row].offset, idx);
8d318a50
LW		 1454
1455 spin_unlock(&d40c->lock);
1456 }
1457
1458 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1459
1460 return IRQ_HANDLED;
1461}
1462
8d318a50
LW		 1463static int d40_validate_conf(struct d40_chan *d40c,
1464 struct stedma40_chan_cfg *conf)
1465{
1466 int res = 0;
1467 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1468 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
38bdbf02 1469 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
8d318a50 1470
0747c7ba 1471 if (!conf->dir) {
6db5a8ba 1472 chan_err(d40c, "Invalid direction.\n");
0747c7ba
LW		 1473 res = -EINVAL;
1474 }
1475
1476 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1477 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1478 d40c->runtime_addr == 0) {
1479
6db5a8ba
RV		 1480 chan_err(d40c, "Invalid TX channel address (%d)\n",
1481 conf->dst_dev_type);
0747c7ba
LW		 1482 res = -EINVAL;
1483 }
1484
1485 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1486 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1487 d40c->runtime_addr == 0) {
6db5a8ba
RV		 1488 chan_err(d40c, "Invalid RX channel address (%d)\n",
1489 conf->src_dev_type);
0747c7ba
LW		 1490 res = -EINVAL;
1491 }
1492
1493 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
8d318a50 1494 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
6db5a8ba 1495 chan_err(d40c, "Invalid dst\n");
8d318a50
LW		 1496 res = -EINVAL;
1497 }
1498
0747c7ba 1499 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
8d318a50 1500 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
6db5a8ba 1501 chan_err(d40c, "Invalid src\n");
8d318a50
LW		 1502 res = -EINVAL;
1503 }
1504
1505 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1506 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
6db5a8ba 1507 chan_err(d40c, "No event line\n");
8d318a50
LW		 1508 res = -EINVAL;
1509 }
1510
1511 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1512 (src_event_group != dst_event_group)) {
6db5a8ba 1513 chan_err(d40c, "Invalid event group\n");
8d318a50
LW		 1514 res = -EINVAL;
1515 }
1516
1517 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1518 /*
1519 * DMAC HW supports it. Will be added to this driver,
1520 * in case any dma client requires it.
1521 */
6db5a8ba 1522 chan_err(d40c, "periph to periph not supported\n");
8d318a50
LW		 1523 res = -EINVAL;
1524 }
1525
d49278e3
PF		 1526 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1527 (1 << conf->src_info.data_width) !=
1528 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1529 (1 << conf->dst_info.data_width)) {
1530 /*
1531 * The DMAC hardware only supports
1532 * src (burst x width) == dst (burst x width)
1533 */
1534
6db5a8ba 1535 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
d49278e3
PF		 1536 res = -EINVAL;
1537 }
1538
8d318a50
LW		 1539 return res;
1540}
1541
5cd326fd
N		 1542static bool d40_alloc_mask_set(struct d40_phy_res *phy,
1543 bool is_src, int log_event_line, bool is_log,
1544 bool *first_user)
8d318a50
LW		 1545{
1546 unsigned long flags;
1547 spin_lock_irqsave(&phy->lock, flags);
5cd326fd
N		 1548
1549 *first_user = ((phy->allocated_src | phy->allocated_dst)
1550 == D40_ALLOC_FREE);
1551
4aed79b2 1552 if (!is_log) {
8d318a50
LW		 1553 /* Physical interrupts are masked per physical full channel */
1554 if (phy->allocated_src == D40_ALLOC_FREE &&
1555 phy->allocated_dst == D40_ALLOC_FREE) {
1556 phy->allocated_dst = D40_ALLOC_PHY;
1557 phy->allocated_src = D40_ALLOC_PHY;
1558 goto found;
1559 } else
1560 goto not_found;
1561 }
1562
1563 /* Logical channel */
1564 if (is_src) {
1565 if (phy->allocated_src == D40_ALLOC_PHY)
1566 goto not_found;
1567
1568 if (phy->allocated_src == D40_ALLOC_FREE)
1569 phy->allocated_src = D40_ALLOC_LOG_FREE;
1570
1571 if (!(phy->allocated_src & (1 << log_event_line))) {
1572 phy->allocated_src |= 1 << log_event_line;
1573 goto found;
1574 } else
1575 goto not_found;
1576 } else {
1577 if (phy->allocated_dst == D40_ALLOC_PHY)
1578 goto not_found;
1579
1580 if (phy->allocated_dst == D40_ALLOC_FREE)
1581 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1582
1583 if (!(phy->allocated_dst & (1 << log_event_line))) {
1584 phy->allocated_dst |= 1 << log_event_line;
1585 goto found;
1586 } else
1587 goto not_found;
1588 }
1589
1590not_found:
1591 spin_unlock_irqrestore(&phy->lock, flags);
1592 return false;
1593found:
1594 spin_unlock_irqrestore(&phy->lock, flags);
1595 return true;
1596}
1597
1598static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1599 int log_event_line)
1600{
1601 unsigned long flags;
1602 bool is_free = false;
1603
1604 spin_lock_irqsave(&phy->lock, flags);
1605 if (!log_event_line) {
8d318a50
LW		 1606 phy->allocated_dst = D40_ALLOC_FREE;
1607 phy->allocated_src = D40_ALLOC_FREE;
1608 is_free = true;
1609 goto out;
1610 }
1611
1612 /* Logical channel */
1613 if (is_src) {
1614 phy->allocated_src &= ~(1 << log_event_line);
1615 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1616 phy->allocated_src = D40_ALLOC_FREE;
1617 } else {
1618 phy->allocated_dst &= ~(1 << log_event_line);
1619 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1620 phy->allocated_dst = D40_ALLOC_FREE;
1621 }
1622
1623 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1624 D40_ALLOC_FREE);
1625
1626out:
1627 spin_unlock_irqrestore(&phy->lock, flags);
1628
1629 return is_free;
1630}
1631
5cd326fd 1632static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
8d318a50
LW		 1633{
1634 int dev_type;
1635 int event_group;
1636 int event_line;
1637 struct d40_phy_res *phys;
1638 int i;
1639 int j;
1640 int log_num;
1641 bool is_src;
38bdbf02 1642 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
8d318a50
LW		 1643
1644 phys = d40c->base->phy_res;
1645
1646 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1647 dev_type = d40c->dma_cfg.src_dev_type;
1648 log_num = 2 * dev_type;
1649 is_src = true;
1650 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1651 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1652 /* dst event lines are used for logical memcpy */
1653 dev_type = d40c->dma_cfg.dst_dev_type;
1654 log_num = 2 * dev_type + 1;
1655 is_src = false;
1656 } else
1657 return -EINVAL;
1658
1659 event_group = D40_TYPE_TO_GROUP(dev_type);
1660 event_line = D40_TYPE_TO_EVENT(dev_type);
1661
1662 if (!is_log) {
1663 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1664 /* Find physical half channel */
1665 for (i = 0; i < d40c->base->num_phy_chans; i++) {
1666
4aed79b2 1667 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1668 0, is_log,
1669 first_phy_user))
8d318a50
LW		 1670 goto found_phy;
1671 }
1672 } else
1673 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1674 int phy_num = j + event_group * 2;
1675 for (i = phy_num; i < phy_num + 2; i++) {
508849ad
LW		 1676 if (d40_alloc_mask_set(&phys[i],
1677 is_src,
1678 0,
5cd326fd
N		 1679 is_log,
1680 first_phy_user))
8d318a50
LW		 1681 goto found_phy;
1682 }
1683 }
1684 return -EINVAL;
1685found_phy:
1686 d40c->phy_chan = &phys[i];
1687 d40c->log_num = D40_PHY_CHAN;
1688 goto out;
1689 }
1690 if (dev_type == -1)
1691 return -EINVAL;
1692
1693 /* Find logical channel */
1694 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1695 int phy_num = j + event_group * 2;
5cd326fd
N		 1696
1697 if (d40c->dma_cfg.use_fixed_channel) {
1698 i = d40c->dma_cfg.phy_channel;
1699
1700 if ((i != phy_num) && (i != phy_num + 1)) {
1701 dev_err(chan2dev(d40c),
1702 "invalid fixed phy channel %d\n", i);
1703 return -EINVAL;
1704 }
1705
1706 if (d40_alloc_mask_set(&phys[i], is_src, event_line,
1707 is_log, first_phy_user))
1708 goto found_log;
1709
1710 dev_err(chan2dev(d40c),
1711 "could not allocate fixed phy channel %d\n", i);
1712 return -EINVAL;
1713 }
1714
8d318a50
LW		 1715 /*
1716 * Spread logical channels across all available physical rather
1717 * than pack every logical channel at the first available phy
1718 * channels.
1719 */
1720 if (is_src) {
1721 for (i = phy_num; i < phy_num + 2; i++) {
1722 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1723 event_line, is_log,
1724 first_phy_user))
8d318a50
LW		 1725 goto found_log;
1726 }
1727 } else {
1728 for (i = phy_num + 1; i >= phy_num; i--) {
1729 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1730 event_line, is_log,
1731 first_phy_user))
8d318a50
LW		 1732 goto found_log;
1733 }
1734 }
1735 }
1736 return -EINVAL;
1737
1738found_log:
1739 d40c->phy_chan = &phys[i];
1740 d40c->log_num = log_num;
1741out:
1742
1743 if (is_log)
1744 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1745 else
1746 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1747
1748 return 0;
1749
1750}
1751
8d318a50
LW		 1752static int d40_config_memcpy(struct d40_chan *d40c)
1753{
1754 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1755
1756 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1757 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1758 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1759 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1760 memcpy[d40c->chan.chan_id];
1761
1762 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1763 dma_has_cap(DMA_SLAVE, cap)) {
1764 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1765 } else {
6db5a8ba 1766 chan_err(d40c, "No memcpy\n");
8d318a50
LW		 1767 return -EINVAL;
1768 }
1769
1770 return 0;
1771}
1772
1773
1774static int d40_free_dma(struct d40_chan *d40c)
1775{
1776
1777 int res = 0;
d181b3a8 1778 u32 event;
8d318a50
LW		 1779 struct d40_phy_res *phy = d40c->phy_chan;
1780 bool is_src;
1781
1782 /* Terminate all queued and active transfers */
1783 d40_term_all(d40c);
1784
1785 if (phy == NULL) {
6db5a8ba 1786 chan_err(d40c, "phy == null\n");
8d318a50
LW		 1787 return -EINVAL;
1788 }
1789
1790 if (phy->allocated_src == D40_ALLOC_FREE &&
1791 phy->allocated_dst == D40_ALLOC_FREE) {
6db5a8ba 1792 chan_err(d40c, "channel already free\n");
8d318a50
LW		 1793 return -EINVAL;
1794 }
1795
8d318a50
LW		 1796 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1797 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1798 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8d318a50
LW		 1799 is_src = false;
1800 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1801 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8d318a50
LW		 1802 is_src = true;
1803 } else {
6db5a8ba 1804 chan_err(d40c, "Unknown direction\n");
8d318a50
LW		 1805 return -EINVAL;
1806 }
1807
7fb3e75e 1808 pm_runtime_get_sync(d40c->base->dev);
d181b3a8
JA		 1809 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1810 if (res) {
6db5a8ba 1811 chan_err(d40c, "suspend failed\n");
7fb3e75e 1812 goto out;
d181b3a8
JA		 1813 }
1814
724a8577 1815 if (chan_is_logical(d40c)) {
d181b3a8 1816 /* Release logical channel, deactivate the event line */
8d318a50 1817
d181b3a8 1818 d40_config_set_event(d40c, false);
8d318a50
LW		 1819 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1820
1821 /*
1822 * Check if there are more logical allocation
1823 * on this phy channel.
1824 */
1825 if (!d40_alloc_mask_free(phy, is_src, event)) {
1826 /* Resume the other logical channels if any */
1827 if (d40_chan_has_events(d40c)) {
1828 res = d40_channel_execute_command(d40c,
1829 D40_DMA_RUN);
7fb3e75e 1830 if (res)
6db5a8ba
RV		 1831 chan_err(d40c,
1832 "Executing RUN command\n");
8d318a50 1833 }
7fb3e75e 1834 goto out;
8d318a50 1835 }
d181b3a8
JA		 1836 } else {
1837 (void) d40_alloc_mask_free(phy, is_src, 0);
1838 }
8d318a50
LW		 1839
1840 /* Release physical channel */
1841 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1842 if (res) {
6db5a8ba 1843 chan_err(d40c, "Failed to stop channel\n");
7fb3e75e 1844 goto out;
8d318a50 1845 }
7fb3e75e
N		 1846
1847 if (d40c->busy) {
1848 pm_runtime_mark_last_busy(d40c->base->dev);
1849 pm_runtime_put_autosuspend(d40c->base->dev);
1850 }
1851
1852 d40c->busy = false;
8d318a50 1853 d40c->phy_chan = NULL;
ce2ca125 1854 d40c->configured = false;
8d318a50 1855 d40c->base->lookup_phy_chans[phy->num] = NULL;
7fb3e75e 1856out:
8d318a50 1857
7fb3e75e
N		 1858 pm_runtime_mark_last_busy(d40c->base->dev);
1859 pm_runtime_put_autosuspend(d40c->base->dev);
1860 return res;
8d318a50
LW		 1861}
1862
a5ebca47
JA		 1863static bool d40_is_paused(struct d40_chan *d40c)
1864{
8ca84687 1865 void __iomem *chanbase = chan_base(d40c);
a5ebca47
JA		 1866 bool is_paused = false;
1867 unsigned long flags;
1868 void __iomem *active_reg;
1869 u32 status;
1870 u32 event;
a5ebca47
JA		 1871
1872 spin_lock_irqsave(&d40c->lock, flags);
1873
724a8577 1874 if (chan_is_physical(d40c)) {
a5ebca47
JA		 1875 if (d40c->phy_chan->num % 2 == 0)
1876 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1877 else
1878 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1879
1880 status = (readl(active_reg) &
1881 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1882 D40_CHAN_POS(d40c->phy_chan->num);
1883 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1884 is_paused = true;
1885
1886 goto _exit;
1887 }
1888
a5ebca47 1889 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
9dbfbd35 1890 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
a5ebca47 1891 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8ca84687 1892 status = readl(chanbase + D40_CHAN_REG_SDLNK);
9dbfbd35 1893 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
a5ebca47 1894 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8ca84687 1895 status = readl(chanbase + D40_CHAN_REG_SSLNK);
9dbfbd35 1896 } else {
6db5a8ba 1897 chan_err(d40c, "Unknown direction\n");
a5ebca47
JA		 1898 goto _exit;
1899 }
9dbfbd35 1900
a5ebca47
JA		 1901 status = (status & D40_EVENTLINE_MASK(event)) >>
1902 D40_EVENTLINE_POS(event);
1903
1904 if (status != D40_DMA_RUN)
1905 is_paused = true;
a5ebca47
JA		 1906_exit:
1907 spin_unlock_irqrestore(&d40c->lock, flags);
1908 return is_paused;
1909
1910}
1911
1912
8d318a50
LW		 1913static u32 stedma40_residue(struct dma_chan *chan)
1914{
1915 struct d40_chan *d40c =
1916 container_of(chan, struct d40_chan, chan);
1917 u32 bytes_left;
1918 unsigned long flags;
1919
1920 spin_lock_irqsave(&d40c->lock, flags);
1921 bytes_left = d40_residue(d40c);
1922 spin_unlock_irqrestore(&d40c->lock, flags);
1923
1924 return bytes_left;
1925}
1926
3e3a0763
RV		 1927static int
1928d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
1929 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 1930 unsigned int sg_len, dma_addr_t src_dev_addr,
1931 dma_addr_t dst_dev_addr)
3e3a0763
RV		 1932{
1933 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1934 struct stedma40_half_channel_info *src_info = &cfg->src_info;
1935 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
5ed04b85 1936 int ret;
3e3a0763 1937
5ed04b85
RV		 1938 ret = d40_log_sg_to_lli(sg_src, sg_len,
1939 src_dev_addr,
1940 desc->lli_log.src,
1941 chan->log_def.lcsp1,
1942 src_info->data_width,
1943 dst_info->data_width);
1944
1945 ret = d40_log_sg_to_lli(sg_dst, sg_len,
1946 dst_dev_addr,
1947 desc->lli_log.dst,
1948 chan->log_def.lcsp3,
1949 dst_info->data_width,
1950 src_info->data_width);
1951
1952 return ret < 0 ? ret : 0;
3e3a0763
RV		 1953}
1954
1955static int
1956d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
1957 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 1958 unsigned int sg_len, dma_addr_t src_dev_addr,
1959 dma_addr_t dst_dev_addr)
3e3a0763 1960{
3e3a0763
RV		 1961 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1962 struct stedma40_half_channel_info *src_info = &cfg->src_info;
1963 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
0c842b55 1964 unsigned long flags = 0;
3e3a0763
RV		 1965 int ret;
1966
0c842b55
RV		 1967 if (desc->cyclic)
1968 flags |= LLI_CYCLIC | LLI_TERM_INT;
1969
3e3a0763
RV		 1970 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
1971 desc->lli_phy.src,
1972 virt_to_phys(desc->lli_phy.src),
1973 chan->src_def_cfg,
0c842b55 1974 src_info, dst_info, flags);
3e3a0763
RV		 1975
1976 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
1977 desc->lli_phy.dst,
1978 virt_to_phys(desc->lli_phy.dst),
1979 chan->dst_def_cfg,
0c842b55 1980 dst_info, src_info, flags);
3e3a0763
RV		 1981
1982 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
1983 desc->lli_pool.size, DMA_TO_DEVICE);
1984
1985 return ret < 0 ? ret : 0;
1986}
1987
1988
5f81158f
RV		 1989static struct d40_desc *
1990d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
1991 unsigned int sg_len, unsigned long dma_flags)
1992{
1993 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1994 struct d40_desc *desc;
dbd88788 1995 int ret;
5f81158f
RV		 1996
1997 desc = d40_desc_get(chan);
1998 if (!desc)
1999 return NULL;
2000
2001 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
2002 cfg->dst_info.data_width);
2003 if (desc->lli_len < 0) {
2004 chan_err(chan, "Unaligned size\n");
dbd88788
RV		 2005 goto err;
2006 }
5f81158f 2007
dbd88788
RV		 2008 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2009 if (ret < 0) {
2010 chan_err(chan, "Could not allocate lli\n");
2011 goto err;
5f81158f
RV		 2012 }
2013
dbd88788 2014
5f81158f
RV		 2015 desc->lli_current = 0;
2016 desc->txd.flags = dma_flags;
2017 desc->txd.tx_submit = d40_tx_submit;
2018
2019 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
2020
2021 return desc;
dbd88788
RV		 2022
2023err:
2024 d40_desc_free(chan, desc);
2025 return NULL;
5f81158f
RV		 2026}
2027
cade1d30 2028static dma_addr_t
db8196df 2029d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
8d318a50 2030{
cade1d30
RV		 2031 struct stedma40_platform_data *plat = chan->base->plat_data;
2032 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
711b9cea 2033 dma_addr_t addr = 0;
cade1d30
RV		 2034
2035 if (chan->runtime_addr)
2036 return chan->runtime_addr;
2037
db8196df 2038 if (direction == DMA_DEV_TO_MEM)
cade1d30 2039 addr = plat->dev_rx[cfg->src_dev_type];
db8196df 2040 else if (direction == DMA_MEM_TO_DEV)
cade1d30
RV		 2041 addr = plat->dev_tx[cfg->dst_dev_type];
2042
2043 return addr;
2044}
2045
2046static struct dma_async_tx_descriptor *
2047d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2048 struct scatterlist *sg_dst, unsigned int sg_len,
db8196df 2049 enum dma_transfer_direction direction, unsigned long dma_flags)
cade1d30
RV		 2050{
2051 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
822c5676
RV		 2052 dma_addr_t src_dev_addr = 0;
2053 dma_addr_t dst_dev_addr = 0;
cade1d30 2054 struct d40_desc *desc;
2a614340 2055 unsigned long flags;
cade1d30 2056 int ret;
8d318a50 2057
cade1d30
RV		 2058 if (!chan->phy_chan) {
2059 chan_err(chan, "Cannot prepare unallocated channel\n");
2060 return NULL;
0d0f6b8b
JA		 2061 }
2062
0c842b55 2063
cade1d30 2064 spin_lock_irqsave(&chan->lock, flags);
8d318a50 2065
cade1d30
RV		 2066 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
2067 if (desc == NULL)
8d318a50
LW		 2068 goto err;
2069
0c842b55
RV		 2070 if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2071 desc->cyclic = true;
2072
822c5676
RV		 2073 if (direction != DMA_NONE) {
2074 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
2075
db8196df 2076 if (direction == DMA_DEV_TO_MEM)
822c5676 2077 src_dev_addr = dev_addr;
db8196df 2078 else if (direction == DMA_MEM_TO_DEV)
822c5676
RV		 2079 dst_dev_addr = dev_addr;
2080 }
cade1d30
RV		 2081
2082 if (chan_is_logical(chan))
2083 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
822c5676 2084 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 2085 else
2086 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
822c5676 2087 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 2088
2089 if (ret) {
2090 chan_err(chan, "Failed to prepare %s sg job: %d\n",
2091 chan_is_logical(chan) ? "log" : "phy", ret);
2092 goto err;
8d318a50
LW		 2093 }
2094
82babbb3
PF		 2095 /*
2096 * add descriptor to the prepare queue in order to be able
2097 * to free them later in terminate_all
2098 */
2099 list_add_tail(&desc->node, &chan->prepare_queue);
2100
cade1d30
RV		 2101 spin_unlock_irqrestore(&chan->lock, flags);
2102
2103 return &desc->txd;
8d318a50 2104
8d318a50 2105err:
cade1d30
RV		 2106 if (desc)
2107 d40_desc_free(chan, desc);
2108 spin_unlock_irqrestore(&chan->lock, flags);
8d318a50
LW		 2109 return NULL;
2110}
8d318a50
LW		 2111
2112bool stedma40_filter(struct dma_chan *chan, void *data)
2113{
2114 struct stedma40_chan_cfg *info = data;
2115 struct d40_chan *d40c =
2116 container_of(chan, struct d40_chan, chan);
2117 int err;
2118
2119 if (data) {
2120 err = d40_validate_conf(d40c, info);
2121 if (!err)
2122 d40c->dma_cfg = *info;
2123 } else
2124 err = d40_config_memcpy(d40c);
2125
ce2ca125
RV		 2126 if (!err)
2127 d40c->configured = true;
2128
8d318a50
LW		 2129 return err == 0;
2130}
2131EXPORT_SYMBOL(stedma40_filter);
2132
ac2c0a38
RV		 2133static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
2134{
2135 bool realtime = d40c->dma_cfg.realtime;
2136 bool highprio = d40c->dma_cfg.high_priority;
2137 u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
2138 u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
2139 u32 event = D40_TYPE_TO_EVENT(dev_type);
2140 u32 group = D40_TYPE_TO_GROUP(dev_type);
2141 u32 bit = 1 << event;
2142
2143 /* Destination event lines are stored in the upper halfword */
2144 if (!src)
2145 bit <<= 16;
2146
2147 writel(bit, d40c->base->virtbase + prioreg + group * 4);
2148 writel(bit, d40c->base->virtbase + rtreg + group * 4);
2149}
2150
2151static void d40_set_prio_realtime(struct d40_chan *d40c)
2152{
2153 if (d40c->base->rev < 3)
2154 return;
2155
2156 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
2157 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
2158 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
2159
2160 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
2161 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
2162 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
2163}
2164
8d318a50
LW		 2165/* DMA ENGINE functions */
2166static int d40_alloc_chan_resources(struct dma_chan *chan)
2167{
2168 int err;
2169 unsigned long flags;
2170 struct d40_chan *d40c =
2171 container_of(chan, struct d40_chan, chan);
ef1872ec 2172 bool is_free_phy;
8d318a50
LW		 2173 spin_lock_irqsave(&d40c->lock, flags);
2174
d3ee98cd 2175 dma_cookie_init(chan);
8d318a50 2176
ce2ca125
RV		 2177 /* If no dma configuration is set use default configuration (memcpy) */
2178 if (!d40c->configured) {
8d318a50 2179 err = d40_config_memcpy(d40c);
ff0b12ba 2180 if (err) {
6db5a8ba 2181 chan_err(d40c, "Failed to configure memcpy channel\n");
ff0b12ba
JA		 2182 goto fail;
2183 }
8d318a50
LW		 2184 }
2185
5cd326fd 2186 err = d40_allocate_channel(d40c, &is_free_phy);
8d318a50 2187 if (err) {
6db5a8ba 2188 chan_err(d40c, "Failed to allocate channel\n");
7fb3e75e 2189 d40c->configured = false;
ff0b12ba 2190 goto fail;
8d318a50
LW		 2191 }
2192
7fb3e75e 2193 pm_runtime_get_sync(d40c->base->dev);
ef1872ec
LW		 2194 /* Fill in basic CFG register values */
2195 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
724a8577 2196 &d40c->dst_def_cfg, chan_is_logical(d40c));
ef1872ec 2197
ac2c0a38
RV		 2198 d40_set_prio_realtime(d40c);
2199
724a8577 2200 if (chan_is_logical(d40c)) {
ef1872ec
LW		 2201 d40_log_cfg(&d40c->dma_cfg,
2202 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2203
2204 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
2205 d40c->lcpa = d40c->base->lcpa_base +
2206 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
2207 else
2208 d40c->lcpa = d40c->base->lcpa_base +
2209 d40c->dma_cfg.dst_dev_type *
2210 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
2211 }
2212
5cd326fd
N		 2213 dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
2214 chan_is_logical(d40c) ? "logical" : "physical",
2215 d40c->phy_chan->num,
2216 d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2217
2218
ef1872ec
LW		 2219 /*
2220 * Only write channel configuration to the DMA if the physical
2221 * resource is free. In case of multiple logical channels
2222 * on the same physical resource, only the first write is necessary.
2223 */
b55912c6
JA		 2224 if (is_free_phy)
2225 d40_config_write(d40c);
ff0b12ba 2226fail:
7fb3e75e
N		 2227 pm_runtime_mark_last_busy(d40c->base->dev);
2228 pm_runtime_put_autosuspend(d40c->base->dev);
8d318a50 2229 spin_unlock_irqrestore(&d40c->lock, flags);
ff0b12ba 2230 return err;
8d318a50
LW		 2231}
2232
2233static void d40_free_chan_resources(struct dma_chan *chan)
2234{
2235 struct d40_chan *d40c =
2236 container_of(chan, struct d40_chan, chan);
2237 int err;
2238 unsigned long flags;
2239
0d0f6b8b 2240 if (d40c->phy_chan == NULL) {
6db5a8ba 2241 chan_err(d40c, "Cannot free unallocated channel\n");
0d0f6b8b
JA		 2242 return;
2243 }
2244
2245
8d318a50
LW		 2246 spin_lock_irqsave(&d40c->lock, flags);
2247
2248 err = d40_free_dma(d40c);
2249
2250 if (err)
6db5a8ba 2251 chan_err(d40c, "Failed to free channel\n");
8d318a50
LW		 2252 spin_unlock_irqrestore(&d40c->lock, flags);
2253}
2254
2255static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2256 dma_addr_t dst,
2257 dma_addr_t src,
2258 size_t size,
2a614340 2259 unsigned long dma_flags)
8d318a50 2260{
95944c6e
RV		 2261 struct scatterlist dst_sg;
2262 struct scatterlist src_sg;
8d318a50 2263
95944c6e
RV		 2264 sg_init_table(&dst_sg, 1);
2265 sg_init_table(&src_sg, 1);
8d318a50 2266
95944c6e
RV		 2267 sg_dma_address(&dst_sg) = dst;
2268 sg_dma_address(&src_sg) = src;
8d318a50 2269
95944c6e
RV		 2270 sg_dma_len(&dst_sg) = size;
2271 sg_dma_len(&src_sg) = size;
8d318a50 2272
cade1d30 2273 return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
8d318a50
LW		 2274}
2275
0d688662 2276static struct dma_async_tx_descriptor *
cade1d30
RV		 2277d40_prep_memcpy_sg(struct dma_chan *chan,
2278 struct scatterlist *dst_sg, unsigned int dst_nents,
2279 struct scatterlist *src_sg, unsigned int src_nents,
2280 unsigned long dma_flags)
0d688662
IS		 2281{
2282 if (dst_nents != src_nents)
2283 return NULL;
2284
cade1d30 2285 return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
00ac0341
RV		 2286}
2287
8d318a50
LW		 2288static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2289 struct scatterlist *sgl,
2290 unsigned int sg_len,
db8196df 2291 enum dma_transfer_direction direction,
185ecb5f
AB		 2292 unsigned long dma_flags,
2293 void *context)
8d318a50 2294{
db8196df 2295 if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV)
00ac0341
RV		 2296 return NULL;
2297
cade1d30 2298 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
8d318a50
LW		 2299}
2300
0c842b55
RV		 2301static struct dma_async_tx_descriptor *
2302dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2303 size_t buf_len, size_t period_len,
185ecb5f 2304 enum dma_transfer_direction direction, void *context)
0c842b55
RV		 2305{
2306 unsigned int periods = buf_len / period_len;
2307 struct dma_async_tx_descriptor *txd;
2308 struct scatterlist *sg;
2309 int i;
2310
79ca7ec3 2311 sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
0c842b55
RV		 2312 for (i = 0; i < periods; i++) {
2313 sg_dma_address(&sg[i]) = dma_addr;
2314 sg_dma_len(&sg[i]) = period_len;
2315 dma_addr += period_len;
2316 }
2317
2318 sg[periods].offset = 0;
2319 sg[periods].length = 0;
2320 sg[periods].page_link =
2321 ((unsigned long)sg | 0x01) & ~0x02;
2322
2323 txd = d40_prep_sg(chan, sg, sg, periods, direction,
2324 DMA_PREP_INTERRUPT);
2325
2326 kfree(sg);
2327
2328 return txd;
2329}
2330
8d318a50
LW		 2331static enum dma_status d40_tx_status(struct dma_chan *chan,
2332 dma_cookie_t cookie,
2333 struct dma_tx_state *txstate)
2334{
2335 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
96a2af41 2336 enum dma_status ret;
8d318a50 2337
0d0f6b8b 2338 if (d40c->phy_chan == NULL) {
6db5a8ba 2339 chan_err(d40c, "Cannot read status of unallocated channel\n");
0d0f6b8b
JA		 2340 return -EINVAL;
2341 }
2342
96a2af41
RKAL		 2343 ret = dma_cookie_status(chan, cookie, txstate);
2344 if (ret != DMA_SUCCESS)
2345 dma_set_residue(txstate, stedma40_residue(chan));
8d318a50 2346
a5ebca47
JA		 2347 if (d40_is_paused(d40c))
2348 ret = DMA_PAUSED;
8d318a50
LW		 2349
2350 return ret;
2351}
2352
2353static void d40_issue_pending(struct dma_chan *chan)
2354{
2355 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2356 unsigned long flags;
2357
0d0f6b8b 2358 if (d40c->phy_chan == NULL) {
6db5a8ba 2359 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2360 return;
2361 }
2362
8d318a50
LW		 2363 spin_lock_irqsave(&d40c->lock, flags);
2364
a8f3067b
PF		 2365 list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2366
2367 /* Busy means that queued jobs are already being processed */
8d318a50
LW		 2368 if (!d40c->busy)
2369 (void) d40_queue_start(d40c);
2370
2371 spin_unlock_irqrestore(&d40c->lock, flags);
2372}
2373
98ca5289
RV		 2374static int
2375dma40_config_to_halfchannel(struct d40_chan *d40c,
2376 struct stedma40_half_channel_info *info,
2377 enum dma_slave_buswidth width,
2378 u32 maxburst)
2379{
2380 enum stedma40_periph_data_width addr_width;
2381 int psize;
2382
2383 switch (width) {
2384 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2385 addr_width = STEDMA40_BYTE_WIDTH;
2386 break;
2387 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2388 addr_width = STEDMA40_HALFWORD_WIDTH;
2389 break;
2390 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2391 addr_width = STEDMA40_WORD_WIDTH;
2392 break;
2393 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2394 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2395 break;
2396 default:
2397 dev_err(d40c->base->dev,
2398 "illegal peripheral address width "
2399 "requested (%d)\n",
2400 width);
2401 return -EINVAL;
2402 }
2403
2404 if (chan_is_logical(d40c)) {
2405 if (maxburst >= 16)
2406 psize = STEDMA40_PSIZE_LOG_16;
2407 else if (maxburst >= 8)
2408 psize = STEDMA40_PSIZE_LOG_8;
2409 else if (maxburst >= 4)
2410 psize = STEDMA40_PSIZE_LOG_4;
2411 else
2412 psize = STEDMA40_PSIZE_LOG_1;
2413 } else {
2414 if (maxburst >= 16)
2415 psize = STEDMA40_PSIZE_PHY_16;
2416 else if (maxburst >= 8)
2417 psize = STEDMA40_PSIZE_PHY_8;
2418 else if (maxburst >= 4)
2419 psize = STEDMA40_PSIZE_PHY_4;
2420 else
2421 psize = STEDMA40_PSIZE_PHY_1;
2422 }
2423
2424 info->data_width = addr_width;
2425 info->psize = psize;
2426 info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2427
2428 return 0;
2429}
2430
95e1400f 2431/* Runtime reconfiguration extension */
98ca5289
RV		 2432static int d40_set_runtime_config(struct dma_chan *chan,
2433 struct dma_slave_config *config)
95e1400f
LW		 2434{
2435 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2436 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
98ca5289 2437 enum dma_slave_buswidth src_addr_width, dst_addr_width;
95e1400f 2438 dma_addr_t config_addr;
98ca5289
RV		 2439 u32 src_maxburst, dst_maxburst;
2440 int ret;
2441
2442 src_addr_width = config->src_addr_width;
2443 src_maxburst = config->src_maxburst;
2444 dst_addr_width = config->dst_addr_width;
2445 dst_maxburst = config->dst_maxburst;
95e1400f 2446
db8196df 2447 if (config->direction == DMA_DEV_TO_MEM) {
95e1400f
LW		 2448 dma_addr_t dev_addr_rx =
2449 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2450
2451 config_addr = config->src_addr;
2452 if (dev_addr_rx)
2453 dev_dbg(d40c->base->dev,
2454 "channel has a pre-wired RX address %08x "
2455 "overriding with %08x\n",
2456 dev_addr_rx, config_addr);
2457 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2458 dev_dbg(d40c->base->dev,
2459 "channel was not configured for peripheral "
2460 "to memory transfer (%d) overriding\n",
2461 cfg->dir);
2462 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2463
98ca5289
RV		 2464 /* Configure the memory side */
2465 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2466 dst_addr_width = src_addr_width;
2467 if (dst_maxburst == 0)
2468 dst_maxburst = src_maxburst;
95e1400f 2469
db8196df 2470 } else if (config->direction == DMA_MEM_TO_DEV) {
95e1400f
LW		 2471 dma_addr_t dev_addr_tx =
2472 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2473
2474 config_addr = config->dst_addr;
2475 if (dev_addr_tx)
2476 dev_dbg(d40c->base->dev,
2477 "channel has a pre-wired TX address %08x "
2478 "overriding with %08x\n",
2479 dev_addr_tx, config_addr);
2480 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2481 dev_dbg(d40c->base->dev,
2482 "channel was not configured for memory "
2483 "to peripheral transfer (%d) overriding\n",
2484 cfg->dir);
2485 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2486
98ca5289
RV		 2487 /* Configure the memory side */
2488 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2489 src_addr_width = dst_addr_width;
2490 if (src_maxburst == 0)
2491 src_maxburst = dst_maxburst;
95e1400f
LW		 2492 } else {
2493 dev_err(d40c->base->dev,
2494 "unrecognized channel direction %d\n",
2495 config->direction);
98ca5289 2496 return -EINVAL;
95e1400f
LW		 2497 }
2498
98ca5289 2499 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
95e1400f 2500 dev_err(d40c->base->dev,
98ca5289
RV		 2501 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2502 src_maxburst,
2503 src_addr_width,
2504 dst_maxburst,
2505 dst_addr_width);
2506 return -EINVAL;
95e1400f
LW		 2507 }
2508
98ca5289
RV		 2509 ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
2510 src_addr_width,
2511 src_maxburst);
2512 if (ret)
2513 return ret;
95e1400f 2514
98ca5289
RV		 2515 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
2516 dst_addr_width,
2517 dst_maxburst);
2518 if (ret)
2519 return ret;
95e1400f 2520
a59670a4 2521 /* Fill in register values */
724a8577 2522 if (chan_is_logical(d40c))
a59670a4
PF		 2523 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2524 else
2525 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2526 &d40c->dst_def_cfg, false);
2527
95e1400f
LW		 2528 /* These settings will take precedence later */
2529 d40c->runtime_addr = config_addr;
2530 d40c->runtime_direction = config->direction;
2531 dev_dbg(d40c->base->dev,
98ca5289
RV		 2532 "configured channel %s for %s, data width %d/%d, "
2533 "maxburst %d/%d elements, LE, no flow control\n",
95e1400f 2534 dma_chan_name(chan),
db8196df 2535 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
98ca5289
RV		 2536 src_addr_width, dst_addr_width,
2537 src_maxburst, dst_maxburst);
2538
2539 return 0;
95e1400f
LW		 2540}
2541
05827630
LW		 2542static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2543 unsigned long arg)
8d318a50 2544{
8d318a50
LW		 2545 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2546
0d0f6b8b 2547 if (d40c->phy_chan == NULL) {
6db5a8ba 2548 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2549 return -EINVAL;
2550 }
2551
8d318a50
LW		 2552 switch (cmd) {
2553 case DMA_TERMINATE_ALL:
86eb5fb6 2554 return d40_terminate_all(d40c);
8d318a50 2555 case DMA_PAUSE:
86eb5fb6 2556 return d40_pause(d40c);
8d318a50 2557 case DMA_RESUME:
86eb5fb6 2558 return d40_resume(d40c);
95e1400f 2559 case DMA_SLAVE_CONFIG:
98ca5289 2560 return d40_set_runtime_config(chan,
95e1400f 2561 (struct dma_slave_config *) arg);
95e1400f
LW		 2562 default:
2563 break;
8d318a50
LW		 2564 }
2565
2566 /* Other commands are unimplemented */
2567 return -ENXIO;
2568}
2569
2570/* Initialization functions */
2571
2572static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2573 struct d40_chan *chans, int offset,
2574 int num_chans)
2575{
2576 int i = 0;
2577 struct d40_chan *d40c;
2578
2579 INIT_LIST_HEAD(&dma->channels);
2580
2581 for (i = offset; i < offset + num_chans; i++) {
2582 d40c = &chans[i];
2583 d40c->base = base;
2584 d40c->chan.device = dma;
2585
8d318a50
LW		 2586 spin_lock_init(&d40c->lock);
2587
2588 d40c->log_num = D40_PHY_CHAN;
2589
8d318a50
LW		 2590 INIT_LIST_HEAD(&d40c->active);
2591 INIT_LIST_HEAD(&d40c->queue);
a8f3067b 2592 INIT_LIST_HEAD(&d40c->pending_queue);
8d318a50 2593 INIT_LIST_HEAD(&d40c->client);
82babbb3 2594 INIT_LIST_HEAD(&d40c->prepare_queue);
8d318a50 2595
8d318a50
LW		 2596 tasklet_init(&d40c->tasklet, dma_tasklet,
2597 (unsigned long) d40c);
2598
2599 list_add_tail(&d40c->chan.device_node,
2600 &dma->channels);
2601 }
2602}
2603
7ad74a7c
RV		 2604static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2605{
2606 if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2607 dev->device_prep_slave_sg = d40_prep_slave_sg;
2608
2609 if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2610 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2611
2612 /*
2613 * This controller can only access address at even
2614 * 32bit boundaries, i.e. 2^2
2615 */
2616 dev->copy_align = 2;
2617 }
2618
2619 if (dma_has_cap(DMA_SG, dev->cap_mask))
2620 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2621
0c842b55
RV		 2622 if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2623 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2624
7ad74a7c
RV		 2625 dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2626 dev->device_free_chan_resources = d40_free_chan_resources;
2627 dev->device_issue_pending = d40_issue_pending;
2628 dev->device_tx_status = d40_tx_status;
2629 dev->device_control = d40_control;
2630 dev->dev = base->dev;
2631}
2632
8d318a50
LW		 2633static int __init d40_dmaengine_init(struct d40_base *base,
2634 int num_reserved_chans)
2635{
2636 int err ;
2637
2638 d40_chan_init(base, &base->dma_slave, base->log_chans,
2639 0, base->num_log_chans);
2640
2641 dma_cap_zero(base->dma_slave.cap_mask);
2642 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
0c842b55 2643 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
8d318a50 2644
7ad74a7c 2645 d40_ops_init(base, &base->dma_slave);
8d318a50
LW		 2646
2647 err = dma_async_device_register(&base->dma_slave);
2648
2649 if (err) {
6db5a8ba 2650 d40_err(base->dev, "Failed to register slave channels\n");
8d318a50
LW		 2651 goto failure1;
2652 }
2653
2654 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2655 base->num_log_chans, base->plat_data->memcpy_len);
2656
2657 dma_cap_zero(base->dma_memcpy.cap_mask);
2658 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
7ad74a7c
RV		 2659 dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
2660
2661 d40_ops_init(base, &base->dma_memcpy);
8d318a50
LW		 2662
2663 err = dma_async_device_register(&base->dma_memcpy);
2664
2665 if (err) {
6db5a8ba
RV		 2666 d40_err(base->dev,
2667 "Failed to regsiter memcpy only channels\n");
8d318a50
LW		 2668 goto failure2;
2669 }
2670
2671 d40_chan_init(base, &base->dma_both, base->phy_chans,
2672 0, num_reserved_chans);
2673
2674 dma_cap_zero(base->dma_both.cap_mask);
2675 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2676 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
7ad74a7c 2677 dma_cap_set(DMA_SG, base->dma_both.cap_mask);
0c842b55 2678 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
7ad74a7c
RV		 2679
2680 d40_ops_init(base, &base->dma_both);
8d318a50
LW		 2681 err = dma_async_device_register(&base->dma_both);
2682
2683 if (err) {
6db5a8ba
RV		 2684 d40_err(base->dev,
2685 "Failed to register logical and physical capable channels\n");
8d318a50
LW		 2686 goto failure3;
2687 }
2688 return 0;
2689failure3:
2690 dma_async_device_unregister(&base->dma_memcpy);
2691failure2:
2692 dma_async_device_unregister(&base->dma_slave);
2693failure1:
2694 return err;
2695}
2696
7fb3e75e
N		 2697/* Suspend resume functionality */
2698#ifdef CONFIG_PM
2699static int dma40_pm_suspend(struct device *dev)
2700{
28c7a19d
N		 2701 struct platform_device *pdev = to_platform_device(dev);
2702 struct d40_base *base = platform_get_drvdata(pdev);
2703 int ret = 0;
7fb3e75e
N		 2704 if (!pm_runtime_suspended(dev))
2705 return -EBUSY;
2706
28c7a19d
N		 2707 if (base->lcpa_regulator)
2708 ret = regulator_disable(base->lcpa_regulator);
2709 return ret;
7fb3e75e
N		 2710}
2711
2712static int dma40_runtime_suspend(struct device *dev)
2713{
2714 struct platform_device *pdev = to_platform_device(dev);
2715 struct d40_base *base = platform_get_drvdata(pdev);
2716
2717 d40_save_restore_registers(base, true);
2718
2719 /* Don't disable/enable clocks for v1 due to HW bugs */
2720 if (base->rev != 1)
2721 writel_relaxed(base->gcc_pwr_off_mask,
2722 base->virtbase + D40_DREG_GCC);
2723
2724 return 0;
2725}
2726
2727static int dma40_runtime_resume(struct device *dev)
2728{
2729 struct platform_device *pdev = to_platform_device(dev);
2730 struct d40_base *base = platform_get_drvdata(pdev);
2731
2732 if (base->initialized)
2733 d40_save_restore_registers(base, false);
2734
2735 writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
2736 base->virtbase + D40_DREG_GCC);
2737 return 0;
2738}
2739
28c7a19d
N		 2740static int dma40_resume(struct device *dev)
2741{
2742 struct platform_device *pdev = to_platform_device(dev);
2743 struct d40_base *base = platform_get_drvdata(pdev);
2744 int ret = 0;
2745
2746 if (base->lcpa_regulator)
2747 ret = regulator_enable(base->lcpa_regulator);
2748
2749 return ret;
2750}
7fb3e75e
N		 2751
2752static const struct dev_pm_ops dma40_pm_ops = {
2753 .suspend = dma40_pm_suspend,
2754 .runtime_suspend = dma40_runtime_suspend,
2755 .runtime_resume = dma40_runtime_resume,
28c7a19d 2756 .resume = dma40_resume,
7fb3e75e
N		 2757};
2758#define DMA40_PM_OPS (&dma40_pm_ops)
2759#else
2760#define DMA40_PM_OPS NULL
2761#endif
2762
8d318a50
LW		 2763/* Initialization functions. */
2764
2765static int __init d40_phy_res_init(struct d40_base *base)
2766{
2767 int i;
2768 int num_phy_chans_avail = 0;
2769 u32 val[2];
2770 int odd_even_bit = -2;
7fb3e75e 2771 int gcc = D40_DREG_GCC_ENA;
8d318a50
LW		 2772
2773 val[0] = readl(base->virtbase + D40_DREG_PRSME);
2774 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2775
2776 for (i = 0; i < base->num_phy_chans; i++) {
2777 base->phy_res[i].num = i;
2778 odd_even_bit += 2 * ((i % 2) == 0);
2779 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2780 /* Mark security only channels as occupied */
2781 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2782 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
7fb3e75e
N		 2783 base->phy_res[i].reserved = true;
2784 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
2785 D40_DREG_GCC_SRC);
2786 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
2787 D40_DREG_GCC_DST);
2788
2789
8d318a50
LW		 2790 } else {
2791 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2792 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
7fb3e75e 2793 base->phy_res[i].reserved = false;
8d318a50
LW		 2794 num_phy_chans_avail++;
2795 }
2796 spin_lock_init(&base->phy_res[i].lock);
2797 }
6b7acd84
JA		 2798
2799 /* Mark disabled channels as occupied */
2800 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
f57b407c
RV		 2801 int chan = base->plat_data->disabled_channels[i];
2802
2803 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
2804 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
7fb3e75e
N		 2805 base->phy_res[chan].reserved = true;
2806 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
2807 D40_DREG_GCC_SRC);
2808 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
2809 D40_DREG_GCC_DST);
f57b407c 2810 num_phy_chans_avail--;
6b7acd84
JA		 2811 }
2812
8d318a50
LW		 2813 dev_info(base->dev, "%d of %d physical DMA channels available\n",
2814 num_phy_chans_avail, base->num_phy_chans);
2815
2816 /* Verify settings extended vs standard */
2817 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2818
2819 for (i = 0; i < base->num_phy_chans; i++) {
2820
2821 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2822 (val[0] & 0x3) != 1)
2823 dev_info(base->dev,
2824 "[%s] INFO: channel %d is misconfigured (%d)\n",
2825 __func__, i, val[0] & 0x3);
2826
2827 val[0] = val[0] >> 2;
2828 }
2829
7fb3e75e
N		 2830 /*
2831 * To keep things simple, Enable all clocks initially.
2832 * The clocks will get managed later post channel allocation.
2833 * The clocks for the event lines on which reserved channels exists
2834 * are not managed here.
2835 */
2836 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
2837 base->gcc_pwr_off_mask = gcc;
2838
8d318a50
LW		 2839 return num_phy_chans_avail;
2840}
2841
2842static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2843{
8d318a50
LW		 2844 struct stedma40_platform_data *plat_data;
2845 struct clk *clk = NULL;
2846 void __iomem *virtbase = NULL;
2847 struct resource *res = NULL;
2848 struct d40_base *base = NULL;
2849 int num_log_chans = 0;
2850 int num_phy_chans;
2851 int i;
f4b89764
LW		 2852 u32 pid;
2853 u32 cid;
2854 u8 rev;
8d318a50
LW		 2855
2856 clk = clk_get(&pdev->dev, NULL);
2857
2858 if (IS_ERR(clk)) {
6db5a8ba 2859 d40_err(&pdev->dev, "No matching clock found\n");
8d318a50
LW		 2860 goto failure;
2861 }
2862
2863 clk_enable(clk);
2864
2865 /* Get IO for DMAC base address */
2866 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2867 if (!res)
2868 goto failure;
2869
2870 if (request_mem_region(res->start, resource_size(res),
2871 D40_NAME " I/O base") == NULL)
2872 goto failure;
2873
2874 virtbase = ioremap(res->start, resource_size(res));
2875 if (!virtbase)
2876 goto failure;
2877
f4b89764
LW		 2878 /* This is just a regular AMBA PrimeCell ID actually */
2879 for (pid = 0, i = 0; i < 4; i++)
2880 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
2881 & 255) << (i * 8);
2882 for (cid = 0, i = 0; i < 4; i++)
2883 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
2884 & 255) << (i * 8);
8d318a50 2885
f4b89764
LW		 2886 if (cid != AMBA_CID) {
2887 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
2888 goto failure;
2889 }
2890 if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
6db5a8ba 2891 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
f4b89764
LW		 2892 AMBA_MANF_BITS(pid),
2893 AMBA_VENDOR_ST);
8d318a50
LW		 2894 goto failure;
2895 }
f4b89764
LW		 2896 /*
2897 * HW revision:
2898 * DB8500ed has revision 0
2899 * ? has revision 1
2900 * DB8500v1 has revision 2
2901 * DB8500v2 has revision 3
2902 */
2903 rev = AMBA_REV_BITS(pid);
3ae0267f 2904
8d318a50
LW		 2905 /* The number of physical channels on this HW */
2906 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2907
2908 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
3ae0267f 2909 rev, res->start);
8d318a50
LW		 2910
2911 plat_data = pdev->dev.platform_data;
2912
2913 /* Count the number of logical channels in use */
2914 for (i = 0; i < plat_data->dev_len; i++)
2915 if (plat_data->dev_rx[i] != 0)
2916 num_log_chans++;
2917
2918 for (i = 0; i < plat_data->dev_len; i++)
2919 if (plat_data->dev_tx[i] != 0)
2920 num_log_chans++;
2921
2922 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2923 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2924 sizeof(struct d40_chan), GFP_KERNEL);
2925
2926 if (base == NULL) {
6db5a8ba 2927 d40_err(&pdev->dev, "Out of memory\n");
8d318a50
LW		 2928 goto failure;
2929 }
2930
3ae0267f 2931 base->rev = rev;
8d318a50
LW		 2932 base->clk = clk;
2933 base->num_phy_chans = num_phy_chans;
2934 base->num_log_chans = num_log_chans;
2935 base->phy_start = res->start;
2936 base->phy_size = resource_size(res);
2937 base->virtbase = virtbase;
2938 base->plat_data = plat_data;
2939 base->dev = &pdev->dev;
2940 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2941 base->log_chans = &base->phy_chans[num_phy_chans];
2942
2943 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2944 GFP_KERNEL);
2945 if (!base->phy_res)
2946 goto failure;
2947
2948 base->lookup_phy_chans = kzalloc(num_phy_chans *
2949 sizeof(struct d40_chan *),
2950 GFP_KERNEL);
2951 if (!base->lookup_phy_chans)
2952 goto failure;
2953
2954 if (num_log_chans + plat_data->memcpy_len) {
2955 /*
2956 * The max number of logical channels are event lines for all
2957 * src devices and dst devices
2958 */
2959 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2960 sizeof(struct d40_chan *),
2961 GFP_KERNEL);
2962 if (!base->lookup_log_chans)
2963 goto failure;
2964 }
698e4732 2965
7fb3e75e
N		 2966 base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
2967 sizeof(d40_backup_regs_chan),
8d318a50 2968 GFP_KERNEL);
7fb3e75e
N		 2969 if (!base->reg_val_backup_chan)
2970 goto failure;
2971
2972 base->lcla_pool.alloc_map =
2973 kzalloc(num_phy_chans * sizeof(struct d40_desc *)
2974 * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
8d318a50
LW		 2975 if (!base->lcla_pool.alloc_map)
2976 goto failure;
2977
c675b1b4
JA		 2978 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2979 0, SLAB_HWCACHE_ALIGN,
2980 NULL);
2981 if (base->desc_slab == NULL)
2982 goto failure;
2983
8d318a50
LW		 2984 return base;
2985
2986failure:
c6134c96 2987 if (!IS_ERR(clk)) {
8d318a50
LW		 2988 clk_disable(clk);
2989 clk_put(clk);
2990 }
2991 if (virtbase)
2992 iounmap(virtbase);
2993 if (res)
2994 release_mem_region(res->start,
2995 resource_size(res));
2996 if (virtbase)
2997 iounmap(virtbase);
2998
2999 if (base) {
3000 kfree(base->lcla_pool.alloc_map);
3001 kfree(base->lookup_log_chans);
3002 kfree(base->lookup_phy_chans);
3003 kfree(base->phy_res);
3004 kfree(base);
3005 }
3006
3007 return NULL;
3008}
3009
3010static void __init d40_hw_init(struct d40_base *base)
3011{
3012
7fb3e75e 3013 static struct d40_reg_val dma_init_reg[] = {
8d318a50 3014 /* Clock every part of the DMA block from start */
7fb3e75e 3015 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
8d318a50
LW		 3016
3017 /* Interrupts on all logical channels */
3018 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
3019 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
3020 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
3021 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
3022 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
3023 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
3024 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
3025 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
3026 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
3027 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
3028 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
3029 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
3030 };
3031 int i;
3032 u32 prmseo[2] = {0, 0};
3033 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3034 u32 pcmis = 0;
3035 u32 pcicr = 0;
3036
3037 for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
3038 writel(dma_init_reg[i].val,
3039 base->virtbase + dma_init_reg[i].reg);
3040
3041 /* Configure all our dma channels to default settings */
3042 for (i = 0; i < base->num_phy_chans; i++) {
3043
3044 activeo[i % 2] = activeo[i % 2] << 2;
3045
3046 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
3047 == D40_ALLOC_PHY) {
3048 activeo[i % 2] |= 3;
3049 continue;
3050 }
3051
3052 /* Enable interrupt # */
3053 pcmis = (pcmis << 1) | 1;
3054
3055 /* Clear interrupt # */
3056 pcicr = (pcicr << 1) | 1;
3057
3058 /* Set channel to physical mode */
3059 prmseo[i % 2] = prmseo[i % 2] << 2;
3060 prmseo[i % 2] |= 1;
3061
3062 }
3063
3064 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3065 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3066 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3067 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3068
3069 /* Write which interrupt to enable */
3070 writel(pcmis, base->virtbase + D40_DREG_PCMIS);
3071
3072 /* Write which interrupt to clear */
3073 writel(pcicr, base->virtbase + D40_DREG_PCICR);
3074
3075}
3076
508849ad
LW		 3077static int __init d40_lcla_allocate(struct d40_base *base)
3078{
026cbc42 3079 struct d40_lcla_pool *pool = &base->lcla_pool;
508849ad
LW		 3080 unsigned long *page_list;
3081 int i, j;
3082 int ret = 0;
3083
3084 /*
3085 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3086 * To full fill this hardware requirement without wasting 256 kb
3087 * we allocate pages until we get an aligned one.
3088 */
3089 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
3090 GFP_KERNEL);
3091
3092 if (!page_list) {
3093 ret = -ENOMEM;
3094 goto failure;
3095 }
3096
3097 /* Calculating how many pages that are required */
3098 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
3099
3100 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
3101 page_list[i] = __get_free_pages(GFP_KERNEL,
3102 base->lcla_pool.pages);
3103 if (!page_list[i]) {
3104
6db5a8ba
RV		 3105 d40_err(base->dev, "Failed to allocate %d pages.\n",
3106 base->lcla_pool.pages);
508849ad
LW		 3107
3108 for (j = 0; j < i; j++)
3109 free_pages(page_list[j], base->lcla_pool.pages);
3110 goto failure;
3111 }
3112
3113 if ((virt_to_phys((void *)page_list[i]) &
3114 (LCLA_ALIGNMENT - 1)) == 0)
3115 break;
3116 }
3117
3118 for (j = 0; j < i; j++)
3119 free_pages(page_list[j], base->lcla_pool.pages);
3120
3121 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
3122 base->lcla_pool.base = (void *)page_list[i];
3123 } else {
767a9675
JA		 3124 /*
3125 * After many attempts and no succees with finding the correct
3126 * alignment, try with allocating a big buffer.
3127 */
508849ad
LW		 3128 dev_warn(base->dev,
3129 "[%s] Failed to get %d pages @ 18 bit align.\n",
3130 __func__, base->lcla_pool.pages);
3131 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
3132 base->num_phy_chans +
3133 LCLA_ALIGNMENT,
3134 GFP_KERNEL);
3135 if (!base->lcla_pool.base_unaligned) {
3136 ret = -ENOMEM;
3137 goto failure;
3138 }
3139
3140 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
3141 LCLA_ALIGNMENT);
3142 }
3143
026cbc42
RV		 3144 pool->dma_addr = dma_map_single(base->dev, pool->base,
3145 SZ_1K * base->num_phy_chans,
3146 DMA_TO_DEVICE);
3147 if (dma_mapping_error(base->dev, pool->dma_addr)) {
3148 pool->dma_addr = 0;
3149 ret = -ENOMEM;
3150 goto failure;
3151 }
3152
508849ad
LW		 3153 writel(virt_to_phys(base->lcla_pool.base),
3154 base->virtbase + D40_DREG_LCLA);
3155failure:
3156 kfree(page_list);
3157 return ret;
3158}
3159
8d318a50
LW		 3160static int __init d40_probe(struct platform_device *pdev)
3161{
3162 int err;
3163 int ret = -ENOENT;
3164 struct d40_base *base;
3165 struct resource *res = NULL;
3166 int num_reserved_chans;
3167 u32 val;
3168
3169 base = d40_hw_detect_init(pdev);
3170
3171 if (!base)
3172 goto failure;
3173
3174 num_reserved_chans = d40_phy_res_init(base);
3175
3176 platform_set_drvdata(pdev, base);
3177
3178 spin_lock_init(&base->interrupt_lock);
3179 spin_lock_init(&base->execmd_lock);
3180
3181 /* Get IO for logical channel parameter address */
3182 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
3183 if (!res) {
3184 ret = -ENOENT;
6db5a8ba 3185 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
8d318a50
LW		 3186 goto failure;
3187 }
3188 base->lcpa_size = resource_size(res);
3189 base->phy_lcpa = res->start;
3190
3191 if (request_mem_region(res->start, resource_size(res),
3192 D40_NAME " I/O lcpa") == NULL) {
3193 ret = -EBUSY;
6db5a8ba
RV		 3194 d40_err(&pdev->dev,
3195 "Failed to request LCPA region 0x%x-0x%x\n",
3196 res->start, res->end);
8d318a50
LW		 3197 goto failure;
3198 }
3199
3200 /* We make use of ESRAM memory for this. */
3201 val = readl(base->virtbase + D40_DREG_LCPA);
3202 if (res->start != val && val != 0) {
3203 dev_warn(&pdev->dev,
3204 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
3205 __func__, val, res->start);
3206 } else
3207 writel(res->start, base->virtbase + D40_DREG_LCPA);
3208
3209 base->lcpa_base = ioremap(res->start, resource_size(res));
3210 if (!base->lcpa_base) {
3211 ret = -ENOMEM;
6db5a8ba 3212 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
8d318a50
LW		 3213 goto failure;
3214 }
28c7a19d
N		 3215 /* If lcla has to be located in ESRAM we don't need to allocate */
3216 if (base->plat_data->use_esram_lcla) {
3217 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3218 "lcla_esram");
3219 if (!res) {
3220 ret = -ENOENT;
3221 d40_err(&pdev->dev,
3222 "No \"lcla_esram\" memory resource\n");
3223 goto failure;
3224 }
3225 base->lcla_pool.base = ioremap(res->start,
3226 resource_size(res));
3227 if (!base->lcla_pool.base) {
3228 ret = -ENOMEM;
3229 d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
3230 goto failure;
3231 }
3232 writel(res->start, base->virtbase + D40_DREG_LCLA);
8d318a50 3233
28c7a19d
N		 3234 } else {
3235 ret = d40_lcla_allocate(base);
3236 if (ret) {
3237 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
3238 goto failure;
3239 }
8d318a50
LW		 3240 }
3241
3242 spin_lock_init(&base->lcla_pool.lock);
3243
8d318a50
LW		 3244 base->irq = platform_get_irq(pdev, 0);
3245
3246 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
8d318a50 3247 if (ret) {
6db5a8ba 3248 d40_err(&pdev->dev, "No IRQ defined\n");
8d318a50
LW		 3249 goto failure;
3250 }
3251
7fb3e75e
N		 3252 pm_runtime_irq_safe(base->dev);
3253 pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
3254 pm_runtime_use_autosuspend(base->dev);
3255 pm_runtime_enable(base->dev);
3256 pm_runtime_resume(base->dev);
28c7a19d
N		 3257
3258 if (base->plat_data->use_esram_lcla) {
3259
3260 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
3261 if (IS_ERR(base->lcpa_regulator)) {
3262 d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
3263 base->lcpa_regulator = NULL;
3264 goto failure;
3265 }
3266
3267 ret = regulator_enable(base->lcpa_regulator);
3268 if (ret) {
3269 d40_err(&pdev->dev,
3270 "Failed to enable lcpa_regulator\n");
3271 regulator_put(base->lcpa_regulator);
3272 base->lcpa_regulator = NULL;
3273 goto failure;
3274 }
3275 }
3276
7fb3e75e 3277 base->initialized = true;
8d318a50
LW		 3278 err = d40_dmaengine_init(base, num_reserved_chans);
3279 if (err)
3280 goto failure;
3281
3282 d40_hw_init(base);
3283
3284 dev_info(base->dev, "initialized\n");
3285 return 0;
3286
3287failure:
3288 if (base) {
c675b1b4
JA		 3289 if (base->desc_slab)
3290 kmem_cache_destroy(base->desc_slab);
8d318a50
LW		 3291 if (base->virtbase)
3292 iounmap(base->virtbase);
026cbc42 3293
28c7a19d
N		 3294 if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
3295 iounmap(base->lcla_pool.base);
3296 base->lcla_pool.base = NULL;
3297 }
3298
026cbc42
RV		 3299 if (base->lcla_pool.dma_addr)
3300 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
3301 SZ_1K * base->num_phy_chans,
3302 DMA_TO_DEVICE);
3303
508849ad
LW		 3304 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
3305 free_pages((unsigned long)base->lcla_pool.base,
3306 base->lcla_pool.pages);
767a9675
JA		 3307
3308 kfree(base->lcla_pool.base_unaligned);
3309
8d318a50
LW		 3310 if (base->phy_lcpa)
3311 release_mem_region(base->phy_lcpa,
3312 base->lcpa_size);
3313 if (base->phy_start)
3314 release_mem_region(base->phy_start,
3315 base->phy_size);
3316 if (base->clk) {
3317 clk_disable(base->clk);
3318 clk_put(base->clk);
3319 }
3320
28c7a19d
N		 3321 if (base->lcpa_regulator) {
3322 regulator_disable(base->lcpa_regulator);
3323 regulator_put(base->lcpa_regulator);
3324 }
3325
8d318a50
LW		 3326 kfree(base->lcla_pool.alloc_map);
3327 kfree(base->lookup_log_chans);
3328 kfree(base->lookup_phy_chans);
3329 kfree(base->phy_res);
3330 kfree(base);
3331 }
3332
6db5a8ba 3333 d40_err(&pdev->dev, "probe failed\n");
8d318a50
LW		 3334 return ret;
3335}
3336
3337static struct platform_driver d40_driver = {
3338 .driver = {
3339 .owner = THIS_MODULE,
3340 .name = D40_NAME,
7fb3e75e 3341 .pm = DMA40_PM_OPS,
8d318a50
LW		 3342 },
3343};
3344
cb9ab2d8 3345static int __init stedma40_init(void)
8d318a50
LW		 3346{
3347 return platform_driver_probe(&d40_driver, d40_probe);
3348}
a0eb221a 3349subsys_initcall(stedma40_init);
Linux kernel - Deliverables
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