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dmaengine: ste_dma40: physical channels number correction
[deliverable/linux.git] / drivers / dma / ste_dma40.c
CommitLineData
8d318a50 1/*
d49278e3
PF		 2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
661385f9 4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675 5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50 6 * License terms: GNU General Public License (GPL) version 2
8d318a50
LW		 7 */
8
b7f080cf 9#include <linux/dma-mapping.h>
8d318a50
LW		 10#include <linux/kernel.h>
11#include <linux/slab.h>
f492b210 12#include <linux/export.h>
8d318a50
LW		 13#include <linux/dmaengine.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
7fb3e75e
N		 17#include <linux/pm.h>
18#include <linux/pm_runtime.h>
698e4732 19#include <linux/err.h>
f4b89764 20#include <linux/amba/bus.h>
15e4b78d 21#include <linux/regulator/consumer.h>
865fab60 22#include <linux/platform_data/dma-ste-dma40.h>
8d318a50 23
d2ebfb33 24#include "dmaengine.h"
8d318a50
LW		 25#include "ste_dma40_ll.h"
26
27#define D40_NAME "dma40"
28
29#define D40_PHY_CHAN -1
30
31/* For masking out/in 2 bit channel positions */
32#define D40_CHAN_POS(chan) (2 * (chan / 2))
33#define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
34
35/* Maximum iterations taken before giving up suspending a channel */
36#define D40_SUSPEND_MAX_IT 500
37
7fb3e75e
N		 38/* Milliseconds */
39#define DMA40_AUTOSUSPEND_DELAY 100
40
508849ad
LW		 41/* Hardware requirement on LCLA alignment */
42#define LCLA_ALIGNMENT 0x40000
698e4732
JA		 43
44/* Max number of links per event group */
45#define D40_LCLA_LINK_PER_EVENT_GRP 128
46#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
47
508849ad
LW		 48/* Attempts before giving up to trying to get pages that are aligned */
49#define MAX_LCLA_ALLOC_ATTEMPTS 256
50
51/* Bit markings for allocation map */
8d318a50
LW		 52#define D40_ALLOC_FREE (1 << 31)
53#define D40_ALLOC_PHY (1 << 30)
54#define D40_ALLOC_LOG_FREE 0
55
8d318a50
LW		 56/**
57 * enum 40_command - The different commands and/or statuses.
58 *
59 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
60 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
61 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
62 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
63 */
64enum d40_command {
65 D40_DMA_STOP = 0,
66 D40_DMA_RUN = 1,
67 D40_DMA_SUSPEND_REQ = 2,
68 D40_DMA_SUSPENDED = 3
69};
70
1bdae6f4
N		 71/*
72 * enum d40_events - The different Event Enables for the event lines.
73 *
74 * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
75 * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
76 * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
77 * @D40_ROUND_EVENTLINE: Status check for event line.
78 */
79
80enum d40_events {
81 D40_DEACTIVATE_EVENTLINE = 0,
82 D40_ACTIVATE_EVENTLINE = 1,
83 D40_SUSPEND_REQ_EVENTLINE = 2,
84 D40_ROUND_EVENTLINE = 3
85};
86
7fb3e75e
N		 87/*
88 * These are the registers that has to be saved and later restored
89 * when the DMA hw is powered off.
90 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
91 */
92static u32 d40_backup_regs[] = {
93 D40_DREG_LCPA,
94 D40_DREG_LCLA,
95 D40_DREG_PRMSE,
96 D40_DREG_PRMSO,
97 D40_DREG_PRMOE,
98 D40_DREG_PRMOO,
99};
100
101#define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
102
103/* TODO: Check if all these registers have to be saved/restored on dma40 v3 */
104static u32 d40_backup_regs_v3[] = {
105 D40_DREG_PSEG1,
106 D40_DREG_PSEG2,
107 D40_DREG_PSEG3,
108 D40_DREG_PSEG4,
109 D40_DREG_PCEG1,
110 D40_DREG_PCEG2,
111 D40_DREG_PCEG3,
112 D40_DREG_PCEG4,
113 D40_DREG_RSEG1,
114 D40_DREG_RSEG2,
115 D40_DREG_RSEG3,
116 D40_DREG_RSEG4,
117 D40_DREG_RCEG1,
118 D40_DREG_RCEG2,
119 D40_DREG_RCEG3,
120 D40_DREG_RCEG4,
121};
122
123#define BACKUP_REGS_SZ_V3 ARRAY_SIZE(d40_backup_regs_v3)
124
125static u32 d40_backup_regs_chan[] = {
126 D40_CHAN_REG_SSCFG,
127 D40_CHAN_REG_SSELT,
128 D40_CHAN_REG_SSPTR,
129 D40_CHAN_REG_SSLNK,
130 D40_CHAN_REG_SDCFG,
131 D40_CHAN_REG_SDELT,
132 D40_CHAN_REG_SDPTR,
133 D40_CHAN_REG_SDLNK,
134};
135
8d318a50
LW		 136/**
137 * struct d40_lli_pool - Structure for keeping LLIs in memory
138 *
139 * @base: Pointer to memory area when the pre_alloc_lli's are not large
140 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
141 * pre_alloc_lli is used.
b00f938c 142 * @dma_addr: DMA address, if mapped
8d318a50
LW		 143 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
144 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
145 * one buffer to one buffer.
146 */
147struct d40_lli_pool {
148 void *base;
508849ad 149 int size;
b00f938c 150 dma_addr_t dma_addr;
8d318a50 151 /* Space for dst and src, plus an extra for padding */
508849ad 152 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
8d318a50
LW		 153};
154
155/**
156 * struct d40_desc - A descriptor is one DMA job.
157 *
158 * @lli_phy: LLI settings for physical channel. Both src and dst=
159 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
160 * lli_len equals one.
161 * @lli_log: Same as above but for logical channels.
162 * @lli_pool: The pool with two entries pre-allocated.
941b77a3 163 * @lli_len: Number of llis of current descriptor.
25985edc 164 * @lli_current: Number of transferred llis.
698e4732 165 * @lcla_alloc: Number of LCLA entries allocated.
8d318a50
LW		 166 * @txd: DMA engine struct. Used for among other things for communication
167 * during a transfer.
168 * @node: List entry.
8d318a50 169 * @is_in_client_list: true if the client owns this descriptor.
7fb3e75e 170 * @cyclic: true if this is a cyclic job
8d318a50
LW		 171 *
172 * This descriptor is used for both logical and physical transfers.
173 */
8d318a50
LW		 174struct d40_desc {
175 /* LLI physical */
176 struct d40_phy_lli_bidir lli_phy;
177 /* LLI logical */
178 struct d40_log_lli_bidir lli_log;
179
180 struct d40_lli_pool lli_pool;
941b77a3 181 int lli_len;
698e4732
JA		 182 int lli_current;
183 int lcla_alloc;
8d318a50
LW		 184
185 struct dma_async_tx_descriptor txd;
186 struct list_head node;
187
8d318a50 188 bool is_in_client_list;
0c842b55 189 bool cyclic;
8d318a50
LW		 190};
191
192/**
193 * struct d40_lcla_pool - LCLA pool settings and data.
194 *
508849ad
LW		 195 * @base: The virtual address of LCLA. 18 bit aligned.
196 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
197 * This pointer is only there for clean-up on error.
198 * @pages: The number of pages needed for all physical channels.
199 * Only used later for clean-up on error
8d318a50 200 * @lock: Lock to protect the content in this struct.
698e4732 201 * @alloc_map: big map over which LCLA entry is own by which job.
8d318a50
LW		 202 */
203struct d40_lcla_pool {
204 void *base;
026cbc42 205 dma_addr_t dma_addr;
508849ad
LW		 206 void *base_unaligned;
207 int pages;
8d318a50 208 spinlock_t lock;
698e4732 209 struct d40_desc **alloc_map;
8d318a50
LW		 210};
211
212/**
213 * struct d40_phy_res - struct for handling eventlines mapped to physical
214 * channels.
215 *
216 * @lock: A lock protection this entity.
7fb3e75e 217 * @reserved: True if used by secure world or otherwise.
8d318a50
LW		 218 * @num: The physical channel number of this entity.
219 * @allocated_src: Bit mapped to show which src event line's are mapped to
220 * this physical channel. Can also be free or physically allocated.
221 * @allocated_dst: Same as for src but is dst.
222 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
767a9675 223 * event line number.
8d318a50
LW		 224 */
225struct d40_phy_res {
226 spinlock_t lock;
7fb3e75e 227 bool reserved;
8d318a50
LW		 228 int num;
229 u32 allocated_src;
230 u32 allocated_dst;
231};
232
233struct d40_base;
234
235/**
236 * struct d40_chan - Struct that describes a channel.
237 *
238 * @lock: A spinlock to protect this struct.
239 * @log_num: The logical number, if any of this channel.
8d318a50
LW		 240 * @pending_tx: The number of pending transfers. Used between interrupt handler
241 * and tasklet.
242 * @busy: Set to true when transfer is ongoing on this channel.
2a614340
JA		 243 * @phy_chan: Pointer to physical channel which this instance runs on. If this
244 * point is NULL, then the channel is not allocated.
8d318a50
LW		 245 * @chan: DMA engine handle.
246 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
247 * transfer and call client callback.
248 * @client: Cliented owned descriptor list.
da063d26 249 * @pending_queue: Submitted jobs, to be issued by issue_pending()
8d318a50
LW		 250 * @active: Active descriptor.
251 * @queue: Queued jobs.
82babbb3 252 * @prepare_queue: Prepared jobs.
8d318a50 253 * @dma_cfg: The client configuration of this dma channel.
ce2ca125 254 * @configured: whether the dma_cfg configuration is valid
8d318a50
LW		 255 * @base: Pointer to the device instance struct.
256 * @src_def_cfg: Default cfg register setting for src.
257 * @dst_def_cfg: Default cfg register setting for dst.
258 * @log_def: Default logical channel settings.
8d318a50 259 * @lcpa: Pointer to dst and src lcpa settings.
ae752bf4 260 * @runtime_addr: runtime configured address.
261 * @runtime_direction: runtime configured direction.
8d318a50
LW		 262 *
263 * This struct can either "be" a logical or a physical channel.
264 */
265struct d40_chan {
266 spinlock_t lock;
267 int log_num;
8d318a50
LW		 268 int pending_tx;
269 bool busy;
270 struct d40_phy_res *phy_chan;
271 struct dma_chan chan;
272 struct tasklet_struct tasklet;
273 struct list_head client;
a8f3067b 274 struct list_head pending_queue;
8d318a50
LW		 275 struct list_head active;
276 struct list_head queue;
82babbb3 277 struct list_head prepare_queue;
8d318a50 278 struct stedma40_chan_cfg dma_cfg;
ce2ca125 279 bool configured;
8d318a50
LW		 280 struct d40_base *base;
281 /* Default register configurations */
282 u32 src_def_cfg;
283 u32 dst_def_cfg;
284 struct d40_def_lcsp log_def;
8d318a50 285 struct d40_log_lli_full *lcpa;
95e1400f
LW		 286 /* Runtime reconfiguration */
287 dma_addr_t runtime_addr;
db8196df 288 enum dma_transfer_direction runtime_direction;
8d318a50
LW		 289};
290
291/**
292 * struct d40_base - The big global struct, one for each probe'd instance.
293 *
294 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
295 * @execmd_lock: Lock for execute command usage since several channels share
296 * the same physical register.
297 * @dev: The device structure.
298 * @virtbase: The virtual base address of the DMA's register.
f4185592 299 * @rev: silicon revision detected.
8d318a50
LW		 300 * @clk: Pointer to the DMA clock structure.
301 * @phy_start: Physical memory start of the DMA registers.
302 * @phy_size: Size of the DMA register map.
303 * @irq: The IRQ number.
304 * @num_phy_chans: The number of physical channels. Read from HW. This
305 * is the number of available channels for this driver, not counting "Secure
306 * mode" allocated physical channels.
307 * @num_log_chans: The number of logical channels. Calculated from
308 * num_phy_chans.
309 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
310 * @dma_slave: dma_device channels that can do only do slave transfers.
311 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
7fb3e75e 312 * @phy_chans: Room for all possible physical channels in system.
8d318a50
LW		 313 * @log_chans: Room for all possible logical channels in system.
314 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
315 * to log_chans entries.
316 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
317 * to phy_chans entries.
318 * @plat_data: Pointer to provided platform_data which is the driver
319 * configuration.
28c7a19d 320 * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
8d318a50
LW		 321 * @phy_res: Vector containing all physical channels.
322 * @lcla_pool: lcla pool settings and data.
323 * @lcpa_base: The virtual mapped address of LCPA.
324 * @phy_lcpa: The physical address of the LCPA.
325 * @lcpa_size: The size of the LCPA area.
c675b1b4 326 * @desc_slab: cache for descriptors.
7fb3e75e
N		 327 * @reg_val_backup: Here the values of some hardware registers are stored
328 * before the DMA is powered off. They are restored when the power is back on.
329 * @reg_val_backup_v3: Backup of registers that only exits on dma40 v3 and
330 * later.
331 * @reg_val_backup_chan: Backup data for standard channel parameter registers.
332 * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
333 * @initialized: true if the dma has been initialized
8d318a50
LW		 334 */
335struct d40_base {
336 spinlock_t interrupt_lock;
337 spinlock_t execmd_lock;
338 struct device *dev;
339 void __iomem *virtbase;
f4185592 340 u8 rev:4;
8d318a50
LW		 341 struct clk *clk;
342 phys_addr_t phy_start;
343 resource_size_t phy_size;
344 int irq;
345 int num_phy_chans;
346 int num_log_chans;
b96710e5 347 struct device_dma_parameters dma_parms;
8d318a50
LW		 348 struct dma_device dma_both;
349 struct dma_device dma_slave;
350 struct dma_device dma_memcpy;
351 struct d40_chan *phy_chans;
352 struct d40_chan *log_chans;
353 struct d40_chan **lookup_log_chans;
354 struct d40_chan **lookup_phy_chans;
355 struct stedma40_platform_data *plat_data;
28c7a19d 356 struct regulator *lcpa_regulator;
8d318a50
LW		 357 /* Physical half channels */
358 struct d40_phy_res *phy_res;
359 struct d40_lcla_pool lcla_pool;
360 void *lcpa_base;
361 dma_addr_t phy_lcpa;
362 resource_size_t lcpa_size;
c675b1b4 363 struct kmem_cache *desc_slab;
7fb3e75e
N		 364 u32 reg_val_backup[BACKUP_REGS_SZ];
365 u32 reg_val_backup_v3[BACKUP_REGS_SZ_V3];
366 u32 *reg_val_backup_chan;
367 u16 gcc_pwr_off_mask;
368 bool initialized;
8d318a50
LW		 369};
370
371/**
372 * struct d40_interrupt_lookup - lookup table for interrupt handler
373 *
374 * @src: Interrupt mask register.
375 * @clr: Interrupt clear register.
376 * @is_error: true if this is an error interrupt.
377 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
378 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
379 */
380struct d40_interrupt_lookup {
381 u32 src;
382 u32 clr;
383 bool is_error;
384 int offset;
385};
386
387/**
388 * struct d40_reg_val - simple lookup struct
389 *
390 * @reg: The register.
391 * @val: The value that belongs to the register in reg.
392 */
393struct d40_reg_val {
394 unsigned int reg;
395 unsigned int val;
396};
397
262d2915
RV		 398static struct device *chan2dev(struct d40_chan *d40c)
399{
400 return &d40c->chan.dev->device;
401}
402
724a8577
RV		 403static bool chan_is_physical(struct d40_chan *chan)
404{
405 return chan->log_num == D40_PHY_CHAN;
406}
407
408static bool chan_is_logical(struct d40_chan *chan)
409{
410 return !chan_is_physical(chan);
411}
412
8ca84687
RV		 413static void __iomem *chan_base(struct d40_chan *chan)
414{
415 return chan->base->virtbase + D40_DREG_PCBASE +
416 chan->phy_chan->num * D40_DREG_PCDELTA;
417}
418
6db5a8ba
RV		 419#define d40_err(dev, format, arg...) \
420 dev_err(dev, "[%s] " format, __func__, ## arg)
421
422#define chan_err(d40c, format, arg...) \
423 d40_err(chan2dev(d40c), format, ## arg)
424
b00f938c 425static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
dbd88788 426 int lli_len)
8d318a50 427{
dbd88788 428 bool is_log = chan_is_logical(d40c);
8d318a50
LW		 429 u32 align;
430 void *base;
431
432 if (is_log)
433 align = sizeof(struct d40_log_lli);
434 else
435 align = sizeof(struct d40_phy_lli);
436
437 if (lli_len == 1) {
438 base = d40d->lli_pool.pre_alloc_lli;
439 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
440 d40d->lli_pool.base = NULL;
441 } else {
594ece4d 442 d40d->lli_pool.size = lli_len * 2 * align;
8d318a50
LW		 443
444 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
445 d40d->lli_pool.base = base;
446
447 if (d40d->lli_pool.base == NULL)
448 return -ENOMEM;
449 }
450
451 if (is_log) {
d924abad 452 d40d->lli_log.src = PTR_ALIGN(base, align);
594ece4d 453 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
b00f938c
RV		 454
455 d40d->lli_pool.dma_addr = 0;
8d318a50 456 } else {
d924abad 457 d40d->lli_phy.src = PTR_ALIGN(base, align);
594ece4d 458 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
b00f938c
RV		 459
460 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
461 d40d->lli_phy.src,
462 d40d->lli_pool.size,
463 DMA_TO_DEVICE);
464
465 if (dma_mapping_error(d40c->base->dev,
466 d40d->lli_pool.dma_addr)) {
467 kfree(d40d->lli_pool.base);
468 d40d->lli_pool.base = NULL;
469 d40d->lli_pool.dma_addr = 0;
470 return -ENOMEM;
471 }
8d318a50
LW		 472 }
473
474 return 0;
475}
476
b00f938c 477static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
8d318a50 478{
b00f938c
RV		 479 if (d40d->lli_pool.dma_addr)
480 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
481 d40d->lli_pool.size, DMA_TO_DEVICE);
482
8d318a50
LW		 483 kfree(d40d->lli_pool.base);
484 d40d->lli_pool.base = NULL;
485 d40d->lli_pool.size = 0;
486 d40d->lli_log.src = NULL;
487 d40d->lli_log.dst = NULL;
488 d40d->lli_phy.src = NULL;
489 d40d->lli_phy.dst = NULL;
8d318a50
LW		 490}
491
698e4732
JA		 492static int d40_lcla_alloc_one(struct d40_chan *d40c,
493 struct d40_desc *d40d)
494{
495 unsigned long flags;
496 int i;
497 int ret = -EINVAL;
498 int p;
499
500 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
501
502 p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
503
504 /*
505 * Allocate both src and dst at the same time, therefore the half
506 * start on 1 since 0 can't be used since zero is used as end marker.
507 */
508 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
509 if (!d40c->base->lcla_pool.alloc_map[p + i]) {
510 d40c->base->lcla_pool.alloc_map[p + i] = d40d;
511 d40d->lcla_alloc++;
512 ret = i;
513 break;
514 }
515 }
516
517 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
518
519 return ret;
520}
521
522static int d40_lcla_free_all(struct d40_chan *d40c,
523 struct d40_desc *d40d)
524{
525 unsigned long flags;
526 int i;
527 int ret = -EINVAL;
528
724a8577 529 if (chan_is_physical(d40c))
698e4732
JA		 530 return 0;
531
532 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
533
534 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
535 if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
536 D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
537 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
538 D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
539 d40d->lcla_alloc--;
540 if (d40d->lcla_alloc == 0) {
541 ret = 0;
542 break;
543 }
544 }
545 }
546
547 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
548
549 return ret;
550
551}
552
8d318a50
LW		 553static void d40_desc_remove(struct d40_desc *d40d)
554{
555 list_del(&d40d->node);
556}
557
558static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
559{
a2c15fa4 560 struct d40_desc *desc = NULL;
8d318a50
LW		 561
562 if (!list_empty(&d40c->client)) {
a2c15fa4
RV		 563 struct d40_desc *d;
564 struct d40_desc *_d;
565
7fb3e75e 566 list_for_each_entry_safe(d, _d, &d40c->client, node) {
8d318a50 567 if (async_tx_test_ack(&d->txd)) {
8d318a50 568 d40_desc_remove(d);
a2c15fa4
RV		 569 desc = d;
570 memset(desc, 0, sizeof(*desc));
c675b1b4 571 break;
8d318a50 572 }
7fb3e75e 573 }
8d318a50 574 }
a2c15fa4
RV		 575
576 if (!desc)
577 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
578
579 if (desc)
580 INIT_LIST_HEAD(&desc->node);
581
582 return desc;
8d318a50
LW		 583}
584
585static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
586{
698e4732 587
b00f938c 588 d40_pool_lli_free(d40c, d40d);
698e4732 589 d40_lcla_free_all(d40c, d40d);
c675b1b4 590 kmem_cache_free(d40c->base->desc_slab, d40d);
8d318a50
LW		 591}
592
593static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
594{
595 list_add_tail(&desc->node, &d40c->active);
596}
597
1c4b0927
RV		 598static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
599{
600 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
601 struct d40_phy_lli *lli_src = desc->lli_phy.src;
602 void __iomem *base = chan_base(chan);
603
604 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
605 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
606 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
607 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
608
609 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
610 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
611 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
612 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
613}
614
e65889c7 615static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
698e4732 616{
e65889c7
RV		 617 struct d40_lcla_pool *pool = &chan->base->lcla_pool;
618 struct d40_log_lli_bidir *lli = &desc->lli_log;
619 int lli_current = desc->lli_current;
620 int lli_len = desc->lli_len;
0c842b55 621 bool cyclic = desc->cyclic;
e65889c7 622 int curr_lcla = -EINVAL;
0c842b55 623 int first_lcla = 0;
28c7a19d 624 bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
0c842b55 625 bool linkback;
e65889c7 626
0c842b55
RV		 627 /*
628 * We may have partially running cyclic transfers, in case we did't get
629 * enough LCLA entries.
630 */
631 linkback = cyclic && lli_current == 0;
632
633 /*
634 * For linkback, we need one LCLA even with only one link, because we
635 * can't link back to the one in LCPA space
636 */
637 if (linkback || (lli_len - lli_current > 1)) {
e65889c7 638 curr_lcla = d40_lcla_alloc_one(chan, desc);
0c842b55
RV		 639 first_lcla = curr_lcla;
640 }
641
642 /*
643 * For linkback, we normally load the LCPA in the loop since we need to
644 * link it to the second LCLA and not the first. However, if we
645 * couldn't even get a first LCLA, then we have to run in LCPA and
646 * reload manually.
647 */
648 if (!linkback || curr_lcla == -EINVAL) {
649 unsigned int flags = 0;
e65889c7 650
0c842b55
RV		 651 if (curr_lcla == -EINVAL)
652 flags |= LLI_TERM_INT;
e65889c7 653
0c842b55
RV		 654 d40_log_lli_lcpa_write(chan->lcpa,
655 &lli->dst[lli_current],
656 &lli->src[lli_current],
657 curr_lcla,
658 flags);
659 lli_current++;
660 }
6045f0bb
RV		 661
662 if (curr_lcla < 0)
663 goto out;
664
e65889c7
RV		 665 for (; lli_current < lli_len; lli_current++) {
666 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
667 8 * curr_lcla * 2;
668 struct d40_log_lli *lcla = pool->base + lcla_offset;
0c842b55 669 unsigned int flags = 0;
e65889c7
RV		 670 int next_lcla;
671
672 if (lli_current + 1 < lli_len)
673 next_lcla = d40_lcla_alloc_one(chan, desc);
674 else
0c842b55
RV		 675 next_lcla = linkback ? first_lcla : -EINVAL;
676
677 if (cyclic || next_lcla == -EINVAL)
678 flags |= LLI_TERM_INT;
e65889c7 679
0c842b55
RV		 680 if (linkback && curr_lcla == first_lcla) {
681 /* First link goes in both LCPA and LCLA */
682 d40_log_lli_lcpa_write(chan->lcpa,
683 &lli->dst[lli_current],
684 &lli->src[lli_current],
685 next_lcla, flags);
686 }
687
688 /*
689 * One unused LCLA in the cyclic case if the very first
690 * next_lcla fails...
691 */
e65889c7
RV		 692 d40_log_lli_lcla_write(lcla,
693 &lli->dst[lli_current],
694 &lli->src[lli_current],
0c842b55 695 next_lcla, flags);
e65889c7 696
28c7a19d
N		 697 /*
698 * Cache maintenance is not needed if lcla is
699 * mapped in esram
700 */
701 if (!use_esram_lcla) {
702 dma_sync_single_range_for_device(chan->base->dev,
703 pool->dma_addr, lcla_offset,
704 2 * sizeof(struct d40_log_lli),
705 DMA_TO_DEVICE);
706 }
e65889c7
RV		 707 curr_lcla = next_lcla;
708
0c842b55 709 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
e65889c7
RV		 710 lli_current++;
711 break;
712 }
713 }
714
6045f0bb 715out:
e65889c7
RV		 716 desc->lli_current = lli_current;
717}
698e4732 718
e65889c7
RV		 719static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
720{
724a8577 721 if (chan_is_physical(d40c)) {
1c4b0927 722 d40_phy_lli_load(d40c, d40d);
698e4732 723 d40d->lli_current = d40d->lli_len;
e65889c7
RV		 724 } else
725 d40_log_lli_to_lcxa(d40c, d40d);
698e4732
JA		 726}
727
8d318a50
LW		 728static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
729{
730 struct d40_desc *d;
731
732 if (list_empty(&d40c->active))
733 return NULL;
734
735 d = list_first_entry(&d40c->active,
736 struct d40_desc,
737 node);
738 return d;
739}
740
7404368c 741/* remove desc from current queue and add it to the pending_queue */
8d318a50
LW		 742static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
743{
7404368c
PF		 744 d40_desc_remove(desc);
745 desc->is_in_client_list = false;
a8f3067b
PF		 746 list_add_tail(&desc->node, &d40c->pending_queue);
747}
748
749static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
750{
751 struct d40_desc *d;
752
753 if (list_empty(&d40c->pending_queue))
754 return NULL;
755
756 d = list_first_entry(&d40c->pending_queue,
757 struct d40_desc,
758 node);
759 return d;
8d318a50
LW		 760}
761
762static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
763{
764 struct d40_desc *d;
765
766 if (list_empty(&d40c->queue))
767 return NULL;
768
769 d = list_first_entry(&d40c->queue,
770 struct d40_desc,
771 node);
772 return d;
773}
774
d49278e3
PF		 775static int d40_psize_2_burst_size(bool is_log, int psize)
776{
777 if (is_log) {
778 if (psize == STEDMA40_PSIZE_LOG_1)
779 return 1;
780 } else {
781 if (psize == STEDMA40_PSIZE_PHY_1)
782 return 1;
783 }
784
785 return 2 << psize;
786}
787
788/*
789 * The dma only supports transmitting packages up to
790 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
791 * dma elements required to send the entire sg list
792 */
793static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
794{
795 int dmalen;
796 u32 max_w = max(data_width1, data_width2);
797 u32 min_w = min(data_width1, data_width2);
798 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
799
800 if (seg_max > STEDMA40_MAX_SEG_SIZE)
801 seg_max -= (1 << max_w);
802
803 if (!IS_ALIGNED(size, 1 << max_w))
804 return -EINVAL;
805
806 if (size <= seg_max)
807 dmalen = 1;
808 else {
809 dmalen = size / seg_max;
810 if (dmalen * seg_max < size)
811 dmalen++;
812 }
813 return dmalen;
814}
815
816static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
817 u32 data_width1, u32 data_width2)
818{
819 struct scatterlist *sg;
820 int i;
821 int len = 0;
822 int ret;
823
824 for_each_sg(sgl, sg, sg_len, i) {
825 ret = d40_size_2_dmalen(sg_dma_len(sg),
826 data_width1, data_width2);
827 if (ret < 0)
828 return ret;
829 len += ret;
830 }
831 return len;
832}
8d318a50 833
7fb3e75e
N		 834
835#ifdef CONFIG_PM
836static void dma40_backup(void __iomem *baseaddr, u32 *backup,
837 u32 *regaddr, int num, bool save)
838{
839 int i;
840
841 for (i = 0; i < num; i++) {
842 void __iomem *addr = baseaddr + regaddr[i];
843
844 if (save)
845 backup[i] = readl_relaxed(addr);
846 else
847 writel_relaxed(backup[i], addr);
848 }
849}
850
851static void d40_save_restore_registers(struct d40_base *base, bool save)
852{
853 int i;
854
855 /* Save/Restore channel specific registers */
856 for (i = 0; i < base->num_phy_chans; i++) {
857 void __iomem *addr;
858 int idx;
859
860 if (base->phy_res[i].reserved)
861 continue;
862
863 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
864 idx = i * ARRAY_SIZE(d40_backup_regs_chan);
865
866 dma40_backup(addr, &base->reg_val_backup_chan[idx],
867 d40_backup_regs_chan,
868 ARRAY_SIZE(d40_backup_regs_chan),
869 save);
870 }
871
872 /* Save/Restore global registers */
873 dma40_backup(base->virtbase, base->reg_val_backup,
874 d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
875 save);
876
877 /* Save/Restore registers only existing on dma40 v3 and later */
878 if (base->rev >= 3)
879 dma40_backup(base->virtbase, base->reg_val_backup_v3,
880 d40_backup_regs_v3,
881 ARRAY_SIZE(d40_backup_regs_v3),
882 save);
883}
884#else
885static void d40_save_restore_registers(struct d40_base *base, bool save)
886{
887}
888#endif
8d318a50 889
1bdae6f4
N		 890static int __d40_execute_command_phy(struct d40_chan *d40c,
891 enum d40_command command)
8d318a50 892{
767a9675
JA		 893 u32 status;
894 int i;
8d318a50
LW		 895 void __iomem *active_reg;
896 int ret = 0;
897 unsigned long flags;
1d392a7b 898 u32 wmask;
8d318a50 899
1bdae6f4
N		 900 if (command == D40_DMA_STOP) {
901 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
902 if (ret)
903 return ret;
904 }
905
8d318a50
LW		 906 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
907
908 if (d40c->phy_chan->num % 2 == 0)
909 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
910 else
911 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
912
913 if (command == D40_DMA_SUSPEND_REQ) {
914 status = (readl(active_reg) &
915 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
916 D40_CHAN_POS(d40c->phy_chan->num);
917
918 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
919 goto done;
920 }
921
1d392a7b
JA		 922 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
923 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
924 active_reg);
8d318a50
LW		 925
926 if (command == D40_DMA_SUSPEND_REQ) {
927
928 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
929 status = (readl(active_reg) &
930 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
931 D40_CHAN_POS(d40c->phy_chan->num);
932
933 cpu_relax();
934 /*
935 * Reduce the number of bus accesses while
936 * waiting for the DMA to suspend.
937 */
938 udelay(3);
939
940 if (status == D40_DMA_STOP ||
941 status == D40_DMA_SUSPENDED)
942 break;
943 }
944
945 if (i == D40_SUSPEND_MAX_IT) {
6db5a8ba
RV		 946 chan_err(d40c,
947 "unable to suspend the chl %d (log: %d) status %x\n",
948 d40c->phy_chan->num, d40c->log_num,
8d318a50
LW		 949 status);
950 dump_stack();
951 ret = -EBUSY;
952 }
953
954 }
955done:
956 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
957 return ret;
958}
959
960static void d40_term_all(struct d40_chan *d40c)
961{
962 struct d40_desc *d40d;
7404368c 963 struct d40_desc *_d;
8d318a50
LW		 964
965 /* Release active descriptors */
966 while ((d40d = d40_first_active_get(d40c))) {
967 d40_desc_remove(d40d);
8d318a50
LW		 968 d40_desc_free(d40c, d40d);
969 }
970
971 /* Release queued descriptors waiting for transfer */
972 while ((d40d = d40_first_queued(d40c))) {
973 d40_desc_remove(d40d);
8d318a50
LW		 974 d40_desc_free(d40c, d40d);
975 }
976
a8f3067b
PF		 977 /* Release pending descriptors */
978 while ((d40d = d40_first_pending(d40c))) {
979 d40_desc_remove(d40d);
980 d40_desc_free(d40c, d40d);
981 }
8d318a50 982
7404368c
PF		 983 /* Release client owned descriptors */
984 if (!list_empty(&d40c->client))
985 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
986 d40_desc_remove(d40d);
987 d40_desc_free(d40c, d40d);
988 }
989
82babbb3
PF		 990 /* Release descriptors in prepare queue */
991 if (!list_empty(&d40c->prepare_queue))
992 list_for_each_entry_safe(d40d, _d,
993 &d40c->prepare_queue, node) {
994 d40_desc_remove(d40d);
995 d40_desc_free(d40c, d40d);
996 }
7404368c 997
8d318a50 998 d40c->pending_tx = 0;
8d318a50
LW		 999}
1000
1bdae6f4
N		 1001static void __d40_config_set_event(struct d40_chan *d40c,
1002 enum d40_events event_type, u32 event,
1003 int reg)
262d2915 1004{
8ca84687 1005 void __iomem *addr = chan_base(d40c) + reg;
262d2915 1006 int tries;
1bdae6f4
N		 1007 u32 status;
1008
1009 switch (event_type) {
1010
1011 case D40_DEACTIVATE_EVENTLINE:
262d2915 1012
262d2915
RV		 1013 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
1014 | ~D40_EVENTLINE_MASK(event), addr);
1bdae6f4
N		 1015 break;
1016
1017 case D40_SUSPEND_REQ_EVENTLINE:
1018 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1019 D40_EVENTLINE_POS(event);
1020
1021 if (status == D40_DEACTIVATE_EVENTLINE ||
1022 status == D40_SUSPEND_REQ_EVENTLINE)
1023 break;
262d2915 1024
1bdae6f4
N		 1025 writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
1026 | ~D40_EVENTLINE_MASK(event), addr);
1027
1028 for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
1029
1030 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1031 D40_EVENTLINE_POS(event);
1032
1033 cpu_relax();
1034 /*
1035 * Reduce the number of bus accesses while
1036 * waiting for the DMA to suspend.
1037 */
1038 udelay(3);
1039
1040 if (status == D40_DEACTIVATE_EVENTLINE)
1041 break;
1042 }
1043
1044 if (tries == D40_SUSPEND_MAX_IT) {
1045 chan_err(d40c,
1046 "unable to stop the event_line chl %d (log: %d)"
1047 "status %x\n", d40c->phy_chan->num,
1048 d40c->log_num, status);
1049 }
1050 break;
1051
1052 case D40_ACTIVATE_EVENTLINE:
262d2915
RV		 1053 /*
1054 * The hardware sometimes doesn't register the enable when src and dst
1055 * event lines are active on the same logical channel. Retry to ensure
1056 * it does. Usually only one retry is sufficient.
1057 */
1bdae6f4
N		 1058 tries = 100;
1059 while (--tries) {
1060 writel((D40_ACTIVATE_EVENTLINE <<
1061 D40_EVENTLINE_POS(event)) |
1062 ~D40_EVENTLINE_MASK(event), addr);
262d2915 1063
1bdae6f4
N		 1064 if (readl(addr) & D40_EVENTLINE_MASK(event))
1065 break;
1066 }
262d2915 1067
1bdae6f4
N		 1068 if (tries != 99)
1069 dev_dbg(chan2dev(d40c),
1070 "[%s] workaround enable S%cLNK (%d tries)\n",
1071 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1072 100 - tries);
262d2915 1073
1bdae6f4
N		 1074 WARN_ON(!tries);
1075 break;
262d2915 1076
1bdae6f4
N		 1077 case D40_ROUND_EVENTLINE:
1078 BUG();
1079 break;
8d318a50 1080
1bdae6f4
N		 1081 }
1082}
8d318a50 1083
1bdae6f4
N		 1084static void d40_config_set_event(struct d40_chan *d40c,
1085 enum d40_events event_type)
1086{
8d318a50
LW		 1087 /* Enable event line connected to device (or memcpy) */
1088 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
1089 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
1090 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1091
1bdae6f4 1092 __d40_config_set_event(d40c, event_type, event,
262d2915 1093 D40_CHAN_REG_SSLNK);
8d318a50 1094 }
262d2915 1095
8d318a50
LW		 1096 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
1097 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1098
1bdae6f4 1099 __d40_config_set_event(d40c, event_type, event,
262d2915 1100 D40_CHAN_REG_SDLNK);
8d318a50 1101 }
8d318a50
LW		 1102}
1103
a5ebca47 1104static u32 d40_chan_has_events(struct d40_chan *d40c)
8d318a50 1105{
8ca84687 1106 void __iomem *chanbase = chan_base(d40c);
be8cb7df 1107 u32 val;
8d318a50 1108
8ca84687
RV		 1109 val = readl(chanbase + D40_CHAN_REG_SSLNK);
1110 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
be8cb7df 1111
a5ebca47 1112 return val;
8d318a50
LW		 1113}
1114
1bdae6f4
N		 1115static int
1116__d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
1117{
1118 unsigned long flags;
1119 int ret = 0;
1120 u32 active_status;
1121 void __iomem *active_reg;
1122
1123 if (d40c->phy_chan->num % 2 == 0)
1124 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1125 else
1126 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1127
1128
1129 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1130
1131 switch (command) {
1132 case D40_DMA_STOP:
1133 case D40_DMA_SUSPEND_REQ:
1134
1135 active_status = (readl(active_reg) &
1136 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1137 D40_CHAN_POS(d40c->phy_chan->num);
1138
1139 if (active_status == D40_DMA_RUN)
1140 d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
1141 else
1142 d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
1143
1144 if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
1145 ret = __d40_execute_command_phy(d40c, command);
1146
1147 break;
1148
1149 case D40_DMA_RUN:
1150
1151 d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
1152 ret = __d40_execute_command_phy(d40c, command);
1153 break;
1154
1155 case D40_DMA_SUSPENDED:
1156 BUG();
1157 break;
1158 }
1159
1160 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1161 return ret;
1162}
1163
1164static int d40_channel_execute_command(struct d40_chan *d40c,
1165 enum d40_command command)
1166{
1167 if (chan_is_logical(d40c))
1168 return __d40_execute_command_log(d40c, command);
1169 else
1170 return __d40_execute_command_phy(d40c, command);
1171}
1172
20a5b6d0
RV		 1173static u32 d40_get_prmo(struct d40_chan *d40c)
1174{
1175 static const unsigned int phy_map[] = {
1176 [STEDMA40_PCHAN_BASIC_MODE]
1177 = D40_DREG_PRMO_PCHAN_BASIC,
1178 [STEDMA40_PCHAN_MODULO_MODE]
1179 = D40_DREG_PRMO_PCHAN_MODULO,
1180 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1181 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1182 };
1183 static const unsigned int log_map[] = {
1184 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1185 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1186 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1187 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1188 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1189 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1190 };
1191
724a8577 1192 if (chan_is_physical(d40c))
20a5b6d0
RV		 1193 return phy_map[d40c->dma_cfg.mode_opt];
1194 else
1195 return log_map[d40c->dma_cfg.mode_opt];
1196}
1197
b55912c6 1198static void d40_config_write(struct d40_chan *d40c)
8d318a50
LW		 1199{
1200 u32 addr_base;
1201 u32 var;
8d318a50
LW		 1202
1203 /* Odd addresses are even addresses + 4 */
1204 addr_base = (d40c->phy_chan->num % 2) * 4;
1205 /* Setup channel mode to logical or physical */
724a8577 1206 var = ((u32)(chan_is_logical(d40c)) + 1) <<
8d318a50
LW		 1207 D40_CHAN_POS(d40c->phy_chan->num);
1208 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1209
1210 /* Setup operational mode option register */
20a5b6d0 1211 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
8d318a50
LW		 1212
1213 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1214
724a8577 1215 if (chan_is_logical(d40c)) {
8ca84687
RV		 1216 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1217 & D40_SREG_ELEM_LOG_LIDX_MASK;
1218 void __iomem *chanbase = chan_base(d40c);
1219
8d318a50 1220 /* Set default config for CFG reg */
8ca84687
RV		 1221 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1222 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
8d318a50 1223
b55912c6 1224 /* Set LIDX for lcla */
8ca84687
RV		 1225 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1226 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
e9f3a49c
RV		 1227
1228 /* Clear LNK which will be used by d40_chan_has_events() */
1229 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1230 writel(0, chanbase + D40_CHAN_REG_SDLNK);
8d318a50 1231 }
8d318a50
LW		 1232}
1233
aa182ae2
JA		 1234static u32 d40_residue(struct d40_chan *d40c)
1235{
1236 u32 num_elt;
1237
724a8577 1238 if (chan_is_logical(d40c))
aa182ae2
JA		 1239 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1240 >> D40_MEM_LCSP2_ECNT_POS;
8ca84687
RV		 1241 else {
1242 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1243 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1244 >> D40_SREG_ELEM_PHY_ECNT_POS;
1245 }
1246
aa182ae2
JA		 1247 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
1248}
1249
1250static bool d40_tx_is_linked(struct d40_chan *d40c)
1251{
1252 bool is_link;
1253
724a8577 1254 if (chan_is_logical(d40c))
aa182ae2
JA		 1255 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
1256 else
8ca84687
RV		 1257 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1258 & D40_SREG_LNK_PHYS_LNK_MASK;
1259
aa182ae2
JA		 1260 return is_link;
1261}
1262
86eb5fb6 1263static int d40_pause(struct d40_chan *d40c)
aa182ae2 1264{
aa182ae2
JA		 1265 int res = 0;
1266 unsigned long flags;
1267
3ac012af
JA		 1268 if (!d40c->busy)
1269 return 0;
1270
7fb3e75e 1271 pm_runtime_get_sync(d40c->base->dev);
aa182ae2
JA		 1272 spin_lock_irqsave(&d40c->lock, flags);
1273
1274 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1bdae6f4 1275
7fb3e75e
N		 1276 pm_runtime_mark_last_busy(d40c->base->dev);
1277 pm_runtime_put_autosuspend(d40c->base->dev);
aa182ae2
JA		 1278 spin_unlock_irqrestore(&d40c->lock, flags);
1279 return res;
1280}
1281
86eb5fb6 1282static int d40_resume(struct d40_chan *d40c)
aa182ae2 1283{
aa182ae2
JA		 1284 int res = 0;
1285 unsigned long flags;
1286
3ac012af
JA		 1287 if (!d40c->busy)
1288 return 0;
1289
aa182ae2 1290 spin_lock_irqsave(&d40c->lock, flags);
7fb3e75e 1291 pm_runtime_get_sync(d40c->base->dev);
aa182ae2
JA		 1292
1293 /* If bytes left to transfer or linked tx resume job */
1bdae6f4 1294 if (d40_residue(d40c) || d40_tx_is_linked(d40c))
aa182ae2 1295 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
aa182ae2 1296
7fb3e75e
N		 1297 pm_runtime_mark_last_busy(d40c->base->dev);
1298 pm_runtime_put_autosuspend(d40c->base->dev);
aa182ae2
JA		 1299 spin_unlock_irqrestore(&d40c->lock, flags);
1300 return res;
1301}
1302
8d318a50
LW		 1303static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1304{
1305 struct d40_chan *d40c = container_of(tx->chan,
1306 struct d40_chan,
1307 chan);
1308 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1309 unsigned long flags;
884485e1 1310 dma_cookie_t cookie;
8d318a50
LW		 1311
1312 spin_lock_irqsave(&d40c->lock, flags);
884485e1 1313 cookie = dma_cookie_assign(tx);
8d318a50 1314 d40_desc_queue(d40c, d40d);
8d318a50
LW		 1315 spin_unlock_irqrestore(&d40c->lock, flags);
1316
884485e1 1317 return cookie;
8d318a50
LW		 1318}
1319
1320static int d40_start(struct d40_chan *d40c)
1321{
0c32269d 1322 return d40_channel_execute_command(d40c, D40_DMA_RUN);
8d318a50
LW		 1323}
1324
1325static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1326{
1327 struct d40_desc *d40d;
1328 int err;
1329
1330 /* Start queued jobs, if any */
1331 d40d = d40_first_queued(d40c);
1332
1333 if (d40d != NULL) {
1bdae6f4 1334 if (!d40c->busy) {
7fb3e75e 1335 d40c->busy = true;
1bdae6f4
N		 1336 pm_runtime_get_sync(d40c->base->dev);
1337 }
8d318a50
LW		 1338
1339 /* Remove from queue */
1340 d40_desc_remove(d40d);
1341
1342 /* Add to active queue */
1343 d40_desc_submit(d40c, d40d);
1344
7d83a854
RV		 1345 /* Initiate DMA job */
1346 d40_desc_load(d40c, d40d);
8d318a50 1347
7d83a854
RV		 1348 /* Start dma job */
1349 err = d40_start(d40c);
8d318a50 1350
7d83a854
RV		 1351 if (err)
1352 return NULL;
8d318a50
LW		 1353 }
1354
1355 return d40d;
1356}
1357
1358/* called from interrupt context */
1359static void dma_tc_handle(struct d40_chan *d40c)
1360{
1361 struct d40_desc *d40d;
1362
8d318a50
LW		 1363 /* Get first active entry from list */
1364 d40d = d40_first_active_get(d40c);
1365
1366 if (d40d == NULL)
1367 return;
1368
0c842b55
RV		 1369 if (d40d->cyclic) {
1370 /*
1371 * If this was a paritially loaded list, we need to reloaded
1372 * it, and only when the list is completed. We need to check
1373 * for done because the interrupt will hit for every link, and
1374 * not just the last one.
1375 */
1376 if (d40d->lli_current < d40d->lli_len
1377 && !d40_tx_is_linked(d40c)
1378 && !d40_residue(d40c)) {
1379 d40_lcla_free_all(d40c, d40d);
1380 d40_desc_load(d40c, d40d);
1381 (void) d40_start(d40c);
8d318a50 1382
0c842b55
RV		 1383 if (d40d->lli_current == d40d->lli_len)
1384 d40d->lli_current = 0;
1385 }
1386 } else {
1387 d40_lcla_free_all(d40c, d40d);
8d318a50 1388
0c842b55
RV		 1389 if (d40d->lli_current < d40d->lli_len) {
1390 d40_desc_load(d40c, d40d);
1391 /* Start dma job */
1392 (void) d40_start(d40c);
1393 return;
1394 }
1395
1396 if (d40_queue_start(d40c) == NULL)
1397 d40c->busy = false;
7fb3e75e
N		 1398 pm_runtime_mark_last_busy(d40c->base->dev);
1399 pm_runtime_put_autosuspend(d40c->base->dev);
0c842b55 1400 }
8d318a50
LW		 1401
1402 d40c->pending_tx++;
1403 tasklet_schedule(&d40c->tasklet);
1404
1405}
1406
1407static void dma_tasklet(unsigned long data)
1408{
1409 struct d40_chan *d40c = (struct d40_chan *) data;
767a9675 1410 struct d40_desc *d40d;
8d318a50
LW		 1411 unsigned long flags;
1412 dma_async_tx_callback callback;
1413 void *callback_param;
1414
1415 spin_lock_irqsave(&d40c->lock, flags);
1416
1417 /* Get first active entry from list */
767a9675 1418 d40d = d40_first_active_get(d40c);
767a9675 1419 if (d40d == NULL)
8d318a50
LW		 1420 goto err;
1421
0c842b55 1422 if (!d40d->cyclic)
f7fbce07 1423 dma_cookie_complete(&d40d->txd);
8d318a50
LW		 1424
1425 /*
1426 * If terminating a channel pending_tx is set to zero.
1427 * This prevents any finished active jobs to return to the client.
1428 */
1429 if (d40c->pending_tx == 0) {
1430 spin_unlock_irqrestore(&d40c->lock, flags);
1431 return;
1432 }
1433
1434 /* Callback to client */
767a9675
JA		 1435 callback = d40d->txd.callback;
1436 callback_param = d40d->txd.callback_param;
1437
0c842b55
RV		 1438 if (!d40d->cyclic) {
1439 if (async_tx_test_ack(&d40d->txd)) {
767a9675 1440 d40_desc_remove(d40d);
0c842b55
RV		 1441 d40_desc_free(d40c, d40d);
1442 } else {
1443 if (!d40d->is_in_client_list) {
1444 d40_desc_remove(d40d);
1445 d40_lcla_free_all(d40c, d40d);
1446 list_add_tail(&d40d->node, &d40c->client);
1447 d40d->is_in_client_list = true;
1448 }
8d318a50
LW		 1449 }
1450 }
1451
1452 d40c->pending_tx--;
1453
1454 if (d40c->pending_tx)
1455 tasklet_schedule(&d40c->tasklet);
1456
1457 spin_unlock_irqrestore(&d40c->lock, flags);
1458
767a9675 1459 if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
8d318a50
LW		 1460 callback(callback_param);
1461
1462 return;
1463
1bdae6f4
N		 1464err:
1465 /* Rescue manouver if receiving double interrupts */
8d318a50
LW		 1466 if (d40c->pending_tx > 0)
1467 d40c->pending_tx--;
1468 spin_unlock_irqrestore(&d40c->lock, flags);
1469}
1470
1471static irqreturn_t d40_handle_interrupt(int irq, void *data)
1472{
1473 static const struct d40_interrupt_lookup il[] = {
1474 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
1475 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
1476 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
1477 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
1478 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
1479 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
1480 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
1481 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
1482 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
1483 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
1484 };
1485
1486 int i;
1487 u32 regs[ARRAY_SIZE(il)];
8d318a50
LW		 1488 u32 idx;
1489 u32 row;
1490 long chan = -1;
1491 struct d40_chan *d40c;
1492 unsigned long flags;
1493 struct d40_base *base = data;
1494
1495 spin_lock_irqsave(&base->interrupt_lock, flags);
1496
1497 /* Read interrupt status of both logical and physical channels */
1498 for (i = 0; i < ARRAY_SIZE(il); i++)
1499 regs[i] = readl(base->virtbase + il[i].src);
1500
1501 for (;;) {
1502
1503 chan = find_next_bit((unsigned long *)regs,
1504 BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
1505
1506 /* No more set bits found? */
1507 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
1508 break;
1509
1510 row = chan / BITS_PER_LONG;
1511 idx = chan & (BITS_PER_LONG - 1);
1512
1513 /* ACK interrupt */
1b00348d 1514 writel(1 << idx, base->virtbase + il[row].clr);
8d318a50
LW		 1515
1516 if (il[row].offset == D40_PHY_CHAN)
1517 d40c = base->lookup_phy_chans[idx];
1518 else
1519 d40c = base->lookup_log_chans[il[row].offset + idx];
1520 spin_lock(&d40c->lock);
1521
1522 if (!il[row].is_error)
1523 dma_tc_handle(d40c);
1524 else
6db5a8ba
RV		 1525 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1526 chan, il[row].offset, idx);
8d318a50
LW		 1527
1528 spin_unlock(&d40c->lock);
1529 }
1530
1531 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1532
1533 return IRQ_HANDLED;
1534}
1535
8d318a50
LW		 1536static int d40_validate_conf(struct d40_chan *d40c,
1537 struct stedma40_chan_cfg *conf)
1538{
1539 int res = 0;
1540 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1541 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
38bdbf02 1542 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
8d318a50 1543
0747c7ba 1544 if (!conf->dir) {
6db5a8ba 1545 chan_err(d40c, "Invalid direction.\n");
0747c7ba
LW		 1546 res = -EINVAL;
1547 }
1548
1549 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1550 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1551 d40c->runtime_addr == 0) {
1552
6db5a8ba
RV		 1553 chan_err(d40c, "Invalid TX channel address (%d)\n",
1554 conf->dst_dev_type);
0747c7ba
LW		 1555 res = -EINVAL;
1556 }
1557
1558 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1559 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1560 d40c->runtime_addr == 0) {
6db5a8ba
RV		 1561 chan_err(d40c, "Invalid RX channel address (%d)\n",
1562 conf->src_dev_type);
0747c7ba
LW		 1563 res = -EINVAL;
1564 }
1565
1566 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
8d318a50 1567 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
6db5a8ba 1568 chan_err(d40c, "Invalid dst\n");
8d318a50
LW		 1569 res = -EINVAL;
1570 }
1571
0747c7ba 1572 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
8d318a50 1573 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
6db5a8ba 1574 chan_err(d40c, "Invalid src\n");
8d318a50
LW		 1575 res = -EINVAL;
1576 }
1577
1578 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1579 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
6db5a8ba 1580 chan_err(d40c, "No event line\n");
8d318a50
LW		 1581 res = -EINVAL;
1582 }
1583
1584 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1585 (src_event_group != dst_event_group)) {
6db5a8ba 1586 chan_err(d40c, "Invalid event group\n");
8d318a50
LW		 1587 res = -EINVAL;
1588 }
1589
1590 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1591 /*
1592 * DMAC HW supports it. Will be added to this driver,
1593 * in case any dma client requires it.
1594 */
6db5a8ba 1595 chan_err(d40c, "periph to periph not supported\n");
8d318a50
LW		 1596 res = -EINVAL;
1597 }
1598
d49278e3
PF		 1599 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1600 (1 << conf->src_info.data_width) !=
1601 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1602 (1 << conf->dst_info.data_width)) {
1603 /*
1604 * The DMAC hardware only supports
1605 * src (burst x width) == dst (burst x width)
1606 */
1607
6db5a8ba 1608 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
d49278e3
PF		 1609 res = -EINVAL;
1610 }
1611
8d318a50
LW		 1612 return res;
1613}
1614
5cd326fd
N		 1615static bool d40_alloc_mask_set(struct d40_phy_res *phy,
1616 bool is_src, int log_event_line, bool is_log,
1617 bool *first_user)
8d318a50
LW		 1618{
1619 unsigned long flags;
1620 spin_lock_irqsave(&phy->lock, flags);
5cd326fd
N		 1621
1622 *first_user = ((phy->allocated_src | phy->allocated_dst)
1623 == D40_ALLOC_FREE);
1624
4aed79b2 1625 if (!is_log) {
8d318a50
LW		 1626 /* Physical interrupts are masked per physical full channel */
1627 if (phy->allocated_src == D40_ALLOC_FREE &&
1628 phy->allocated_dst == D40_ALLOC_FREE) {
1629 phy->allocated_dst = D40_ALLOC_PHY;
1630 phy->allocated_src = D40_ALLOC_PHY;
1631 goto found;
1632 } else
1633 goto not_found;
1634 }
1635
1636 /* Logical channel */
1637 if (is_src) {
1638 if (phy->allocated_src == D40_ALLOC_PHY)
1639 goto not_found;
1640
1641 if (phy->allocated_src == D40_ALLOC_FREE)
1642 phy->allocated_src = D40_ALLOC_LOG_FREE;
1643
1644 if (!(phy->allocated_src & (1 << log_event_line))) {
1645 phy->allocated_src |= 1 << log_event_line;
1646 goto found;
1647 } else
1648 goto not_found;
1649 } else {
1650 if (phy->allocated_dst == D40_ALLOC_PHY)
1651 goto not_found;
1652
1653 if (phy->allocated_dst == D40_ALLOC_FREE)
1654 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1655
1656 if (!(phy->allocated_dst & (1 << log_event_line))) {
1657 phy->allocated_dst |= 1 << log_event_line;
1658 goto found;
1659 } else
1660 goto not_found;
1661 }
1662
1663not_found:
1664 spin_unlock_irqrestore(&phy->lock, flags);
1665 return false;
1666found:
1667 spin_unlock_irqrestore(&phy->lock, flags);
1668 return true;
1669}
1670
1671static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1672 int log_event_line)
1673{
1674 unsigned long flags;
1675 bool is_free = false;
1676
1677 spin_lock_irqsave(&phy->lock, flags);
1678 if (!log_event_line) {
8d318a50
LW		 1679 phy->allocated_dst = D40_ALLOC_FREE;
1680 phy->allocated_src = D40_ALLOC_FREE;
1681 is_free = true;
1682 goto out;
1683 }
1684
1685 /* Logical channel */
1686 if (is_src) {
1687 phy->allocated_src &= ~(1 << log_event_line);
1688 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1689 phy->allocated_src = D40_ALLOC_FREE;
1690 } else {
1691 phy->allocated_dst &= ~(1 << log_event_line);
1692 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1693 phy->allocated_dst = D40_ALLOC_FREE;
1694 }
1695
1696 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1697 D40_ALLOC_FREE);
1698
1699out:
1700 spin_unlock_irqrestore(&phy->lock, flags);
1701
1702 return is_free;
1703}
1704
5cd326fd 1705static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
8d318a50
LW		 1706{
1707 int dev_type;
1708 int event_group;
1709 int event_line;
1710 struct d40_phy_res *phys;
1711 int i;
1712 int j;
1713 int log_num;
f000df8c 1714 int num_phy_chans;
8d318a50 1715 bool is_src;
38bdbf02 1716 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
8d318a50
LW		 1717
1718 phys = d40c->base->phy_res;
f000df8c 1719 num_phy_chans = d40c->base->num_phy_chans;
8d318a50
LW		 1720
1721 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1722 dev_type = d40c->dma_cfg.src_dev_type;
1723 log_num = 2 * dev_type;
1724 is_src = true;
1725 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1726 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1727 /* dst event lines are used for logical memcpy */
1728 dev_type = d40c->dma_cfg.dst_dev_type;
1729 log_num = 2 * dev_type + 1;
1730 is_src = false;
1731 } else
1732 return -EINVAL;
1733
1734 event_group = D40_TYPE_TO_GROUP(dev_type);
1735 event_line = D40_TYPE_TO_EVENT(dev_type);
1736
1737 if (!is_log) {
1738 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1739 /* Find physical half channel */
f000df8c
GB		 1740 if (d40c->dma_cfg.use_fixed_channel) {
1741 i = d40c->dma_cfg.phy_channel;
4aed79b2 1742 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1743 0, is_log,
1744 first_phy_user))
8d318a50 1745 goto found_phy;
f000df8c
GB		 1746 } else {
1747 for (i = 0; i < num_phy_chans; i++) {
1748 if (d40_alloc_mask_set(&phys[i], is_src,
1749 0, is_log,
1750 first_phy_user))
1751 goto found_phy;
1752 }
8d318a50
LW		 1753 }
1754 } else
1755 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1756 int phy_num = j + event_group * 2;
1757 for (i = phy_num; i < phy_num + 2; i++) {
508849ad
LW		 1758 if (d40_alloc_mask_set(&phys[i],
1759 is_src,
1760 0,
5cd326fd
N		 1761 is_log,
1762 first_phy_user))
8d318a50
LW		 1763 goto found_phy;
1764 }
1765 }
1766 return -EINVAL;
1767found_phy:
1768 d40c->phy_chan = &phys[i];
1769 d40c->log_num = D40_PHY_CHAN;
1770 goto out;
1771 }
1772 if (dev_type == -1)
1773 return -EINVAL;
1774
1775 /* Find logical channel */
1776 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1777 int phy_num = j + event_group * 2;
5cd326fd
N		 1778
1779 if (d40c->dma_cfg.use_fixed_channel) {
1780 i = d40c->dma_cfg.phy_channel;
1781
1782 if ((i != phy_num) && (i != phy_num + 1)) {
1783 dev_err(chan2dev(d40c),
1784 "invalid fixed phy channel %d\n", i);
1785 return -EINVAL;
1786 }
1787
1788 if (d40_alloc_mask_set(&phys[i], is_src, event_line,
1789 is_log, first_phy_user))
1790 goto found_log;
1791
1792 dev_err(chan2dev(d40c),
1793 "could not allocate fixed phy channel %d\n", i);
1794 return -EINVAL;
1795 }
1796
8d318a50
LW		 1797 /*
1798 * Spread logical channels across all available physical rather
1799 * than pack every logical channel at the first available phy
1800 * channels.
1801 */
1802 if (is_src) {
1803 for (i = phy_num; i < phy_num + 2; i++) {
1804 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1805 event_line, is_log,
1806 first_phy_user))
8d318a50
LW		 1807 goto found_log;
1808 }
1809 } else {
1810 for (i = phy_num + 1; i >= phy_num; i--) {
1811 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1812 event_line, is_log,
1813 first_phy_user))
8d318a50
LW		 1814 goto found_log;
1815 }
1816 }
1817 }
1818 return -EINVAL;
1819
1820found_log:
1821 d40c->phy_chan = &phys[i];
1822 d40c->log_num = log_num;
1823out:
1824
1825 if (is_log)
1826 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1827 else
1828 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1829
1830 return 0;
1831
1832}
1833
8d318a50
LW		 1834static int d40_config_memcpy(struct d40_chan *d40c)
1835{
1836 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1837
1838 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1839 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1840 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1841 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1842 memcpy[d40c->chan.chan_id];
1843
1844 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1845 dma_has_cap(DMA_SLAVE, cap)) {
1846 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1847 } else {
6db5a8ba 1848 chan_err(d40c, "No memcpy\n");
8d318a50
LW		 1849 return -EINVAL;
1850 }
1851
1852 return 0;
1853}
1854
8d318a50
LW		 1855static int d40_free_dma(struct d40_chan *d40c)
1856{
1857
1858 int res = 0;
d181b3a8 1859 u32 event;
8d318a50
LW		 1860 struct d40_phy_res *phy = d40c->phy_chan;
1861 bool is_src;
1862
1863 /* Terminate all queued and active transfers */
1864 d40_term_all(d40c);
1865
1866 if (phy == NULL) {
6db5a8ba 1867 chan_err(d40c, "phy == null\n");
8d318a50
LW		 1868 return -EINVAL;
1869 }
1870
1871 if (phy->allocated_src == D40_ALLOC_FREE &&
1872 phy->allocated_dst == D40_ALLOC_FREE) {
6db5a8ba 1873 chan_err(d40c, "channel already free\n");
8d318a50
LW		 1874 return -EINVAL;
1875 }
1876
8d318a50
LW		 1877 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1878 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1879 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8d318a50
LW		 1880 is_src = false;
1881 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1882 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8d318a50
LW		 1883 is_src = true;
1884 } else {
6db5a8ba 1885 chan_err(d40c, "Unknown direction\n");
8d318a50
LW		 1886 return -EINVAL;
1887 }
1888
7fb3e75e 1889 pm_runtime_get_sync(d40c->base->dev);
1bdae6f4 1890 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
d181b3a8 1891 if (res) {
1bdae6f4 1892 chan_err(d40c, "stop failed\n");
7fb3e75e 1893 goto out;
d181b3a8
JA		 1894 }
1895
1bdae6f4 1896 d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
8d318a50 1897
1bdae6f4 1898 if (chan_is_logical(d40c))
8d318a50 1899 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1bdae6f4
N		 1900 else
1901 d40c->base->lookup_phy_chans[phy->num] = NULL;
7fb3e75e
N		 1902
1903 if (d40c->busy) {
1904 pm_runtime_mark_last_busy(d40c->base->dev);
1905 pm_runtime_put_autosuspend(d40c->base->dev);
1906 }
1907
1908 d40c->busy = false;
8d318a50 1909 d40c->phy_chan = NULL;
ce2ca125 1910 d40c->configured = false;
7fb3e75e 1911out:
8d318a50 1912
7fb3e75e
N		 1913 pm_runtime_mark_last_busy(d40c->base->dev);
1914 pm_runtime_put_autosuspend(d40c->base->dev);
1915 return res;
8d318a50
LW		 1916}
1917
a5ebca47
JA		 1918static bool d40_is_paused(struct d40_chan *d40c)
1919{
8ca84687 1920 void __iomem *chanbase = chan_base(d40c);
a5ebca47
JA		 1921 bool is_paused = false;
1922 unsigned long flags;
1923 void __iomem *active_reg;
1924 u32 status;
1925 u32 event;
a5ebca47
JA		 1926
1927 spin_lock_irqsave(&d40c->lock, flags);
1928
724a8577 1929 if (chan_is_physical(d40c)) {
a5ebca47
JA		 1930 if (d40c->phy_chan->num % 2 == 0)
1931 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1932 else
1933 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1934
1935 status = (readl(active_reg) &
1936 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1937 D40_CHAN_POS(d40c->phy_chan->num);
1938 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1939 is_paused = true;
1940
1941 goto _exit;
1942 }
1943
a5ebca47 1944 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
9dbfbd35 1945 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
a5ebca47 1946 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8ca84687 1947 status = readl(chanbase + D40_CHAN_REG_SDLNK);
9dbfbd35 1948 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
a5ebca47 1949 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8ca84687 1950 status = readl(chanbase + D40_CHAN_REG_SSLNK);
9dbfbd35 1951 } else {
6db5a8ba 1952 chan_err(d40c, "Unknown direction\n");
a5ebca47
JA		 1953 goto _exit;
1954 }
9dbfbd35 1955
a5ebca47
JA		 1956 status = (status & D40_EVENTLINE_MASK(event)) >>
1957 D40_EVENTLINE_POS(event);
1958
1959 if (status != D40_DMA_RUN)
1960 is_paused = true;
a5ebca47
JA		 1961_exit:
1962 spin_unlock_irqrestore(&d40c->lock, flags);
1963 return is_paused;
1964
1965}
1966
1967
8d318a50
LW		 1968static u32 stedma40_residue(struct dma_chan *chan)
1969{
1970 struct d40_chan *d40c =
1971 container_of(chan, struct d40_chan, chan);
1972 u32 bytes_left;
1973 unsigned long flags;
1974
1975 spin_lock_irqsave(&d40c->lock, flags);
1976 bytes_left = d40_residue(d40c);
1977 spin_unlock_irqrestore(&d40c->lock, flags);
1978
1979 return bytes_left;
1980}
1981
3e3a0763
RV		 1982static int
1983d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
1984 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 1985 unsigned int sg_len, dma_addr_t src_dev_addr,
1986 dma_addr_t dst_dev_addr)
3e3a0763
RV		 1987{
1988 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1989 struct stedma40_half_channel_info *src_info = &cfg->src_info;
1990 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
5ed04b85 1991 int ret;
3e3a0763 1992
5ed04b85
RV		 1993 ret = d40_log_sg_to_lli(sg_src, sg_len,
1994 src_dev_addr,
1995 desc->lli_log.src,
1996 chan->log_def.lcsp1,
1997 src_info->data_width,
1998 dst_info->data_width);
1999
2000 ret = d40_log_sg_to_lli(sg_dst, sg_len,
2001 dst_dev_addr,
2002 desc->lli_log.dst,
2003 chan->log_def.lcsp3,
2004 dst_info->data_width,
2005 src_info->data_width);
2006
2007 return ret < 0 ? ret : 0;
3e3a0763
RV		 2008}
2009
2010static int
2011d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
2012 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 2013 unsigned int sg_len, dma_addr_t src_dev_addr,
2014 dma_addr_t dst_dev_addr)
3e3a0763 2015{
3e3a0763
RV		 2016 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2017 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2018 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
0c842b55 2019 unsigned long flags = 0;
3e3a0763
RV		 2020 int ret;
2021
0c842b55
RV		 2022 if (desc->cyclic)
2023 flags |= LLI_CYCLIC | LLI_TERM_INT;
2024
3e3a0763
RV		 2025 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
2026 desc->lli_phy.src,
2027 virt_to_phys(desc->lli_phy.src),
2028 chan->src_def_cfg,
0c842b55 2029 src_info, dst_info, flags);
3e3a0763
RV		 2030
2031 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
2032 desc->lli_phy.dst,
2033 virt_to_phys(desc->lli_phy.dst),
2034 chan->dst_def_cfg,
0c842b55 2035 dst_info, src_info, flags);
3e3a0763
RV		 2036
2037 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
2038 desc->lli_pool.size, DMA_TO_DEVICE);
2039
2040 return ret < 0 ? ret : 0;
2041}
2042
2043
5f81158f
RV		 2044static struct d40_desc *
2045d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
2046 unsigned int sg_len, unsigned long dma_flags)
2047{
2048 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2049 struct d40_desc *desc;
dbd88788 2050 int ret;
5f81158f
RV		 2051
2052 desc = d40_desc_get(chan);
2053 if (!desc)
2054 return NULL;
2055
2056 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
2057 cfg->dst_info.data_width);
2058 if (desc->lli_len < 0) {
2059 chan_err(chan, "Unaligned size\n");
dbd88788
RV		 2060 goto err;
2061 }
5f81158f 2062
dbd88788
RV		 2063 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2064 if (ret < 0) {
2065 chan_err(chan, "Could not allocate lli\n");
2066 goto err;
5f81158f
RV		 2067 }
2068
dbd88788 2069
5f81158f
RV		 2070 desc->lli_current = 0;
2071 desc->txd.flags = dma_flags;
2072 desc->txd.tx_submit = d40_tx_submit;
2073
2074 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
2075
2076 return desc;
dbd88788
RV		 2077
2078err:
2079 d40_desc_free(chan, desc);
2080 return NULL;
5f81158f
RV		 2081}
2082
cade1d30 2083static dma_addr_t
db8196df 2084d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
8d318a50 2085{
cade1d30
RV		 2086 struct stedma40_platform_data *plat = chan->base->plat_data;
2087 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
711b9cea 2088 dma_addr_t addr = 0;
cade1d30
RV		 2089
2090 if (chan->runtime_addr)
2091 return chan->runtime_addr;
2092
db8196df 2093 if (direction == DMA_DEV_TO_MEM)
cade1d30 2094 addr = plat->dev_rx[cfg->src_dev_type];
db8196df 2095 else if (direction == DMA_MEM_TO_DEV)
cade1d30
RV		 2096 addr = plat->dev_tx[cfg->dst_dev_type];
2097
2098 return addr;
2099}
2100
2101static struct dma_async_tx_descriptor *
2102d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2103 struct scatterlist *sg_dst, unsigned int sg_len,
db8196df 2104 enum dma_transfer_direction direction, unsigned long dma_flags)
cade1d30
RV		 2105{
2106 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
822c5676
RV		 2107 dma_addr_t src_dev_addr = 0;
2108 dma_addr_t dst_dev_addr = 0;
cade1d30 2109 struct d40_desc *desc;
2a614340 2110 unsigned long flags;
cade1d30 2111 int ret;
8d318a50 2112
cade1d30
RV		 2113 if (!chan->phy_chan) {
2114 chan_err(chan, "Cannot prepare unallocated channel\n");
2115 return NULL;
0d0f6b8b
JA		 2116 }
2117
0c842b55 2118
cade1d30 2119 spin_lock_irqsave(&chan->lock, flags);
8d318a50 2120
cade1d30
RV		 2121 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
2122 if (desc == NULL)
8d318a50
LW		 2123 goto err;
2124
0c842b55
RV		 2125 if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2126 desc->cyclic = true;
2127
7e426da8 2128 if (direction != DMA_TRANS_NONE) {
822c5676
RV		 2129 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
2130
db8196df 2131 if (direction == DMA_DEV_TO_MEM)
822c5676 2132 src_dev_addr = dev_addr;
db8196df 2133 else if (direction == DMA_MEM_TO_DEV)
822c5676
RV		 2134 dst_dev_addr = dev_addr;
2135 }
cade1d30
RV		 2136
2137 if (chan_is_logical(chan))
2138 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
822c5676 2139 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 2140 else
2141 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
822c5676 2142 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 2143
2144 if (ret) {
2145 chan_err(chan, "Failed to prepare %s sg job: %d\n",
2146 chan_is_logical(chan) ? "log" : "phy", ret);
2147 goto err;
8d318a50
LW		 2148 }
2149
82babbb3
PF		 2150 /*
2151 * add descriptor to the prepare queue in order to be able
2152 * to free them later in terminate_all
2153 */
2154 list_add_tail(&desc->node, &chan->prepare_queue);
2155
cade1d30
RV		 2156 spin_unlock_irqrestore(&chan->lock, flags);
2157
2158 return &desc->txd;
8d318a50 2159
8d318a50 2160err:
cade1d30
RV		 2161 if (desc)
2162 d40_desc_free(chan, desc);
2163 spin_unlock_irqrestore(&chan->lock, flags);
8d318a50
LW		 2164 return NULL;
2165}
8d318a50
LW		 2166
2167bool stedma40_filter(struct dma_chan *chan, void *data)
2168{
2169 struct stedma40_chan_cfg *info = data;
2170 struct d40_chan *d40c =
2171 container_of(chan, struct d40_chan, chan);
2172 int err;
2173
2174 if (data) {
2175 err = d40_validate_conf(d40c, info);
2176 if (!err)
2177 d40c->dma_cfg = *info;
2178 } else
2179 err = d40_config_memcpy(d40c);
2180
ce2ca125
RV		 2181 if (!err)
2182 d40c->configured = true;
2183
8d318a50
LW		 2184 return err == 0;
2185}
2186EXPORT_SYMBOL(stedma40_filter);
2187
ac2c0a38
RV		 2188static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
2189{
2190 bool realtime = d40c->dma_cfg.realtime;
2191 bool highprio = d40c->dma_cfg.high_priority;
ac2c0a38
RV		 2192 u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
2193 u32 event = D40_TYPE_TO_EVENT(dev_type);
2194 u32 group = D40_TYPE_TO_GROUP(dev_type);
2195 u32 bit = 1 << event;
ccc3d697
RV		 2196 u32 prioreg;
2197
2198 /*
2199 * Due to a hardware bug, in some cases a logical channel triggered by
2200 * a high priority destination event line can generate extra packet
2201 * transactions.
2202 *
2203 * The workaround is to not set the high priority level for the
2204 * destination event lines that trigger logical channels.
2205 */
2206 if (!src && chan_is_logical(d40c))
2207 highprio = false;
2208
2209 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
ac2c0a38
RV		 2210
2211 /* Destination event lines are stored in the upper halfword */
2212 if (!src)
2213 bit <<= 16;
2214
2215 writel(bit, d40c->base->virtbase + prioreg + group * 4);
2216 writel(bit, d40c->base->virtbase + rtreg + group * 4);
2217}
2218
2219static void d40_set_prio_realtime(struct d40_chan *d40c)
2220{
2221 if (d40c->base->rev < 3)
2222 return;
2223
2224 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
2225 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
2226 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
2227
2228 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
2229 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
2230 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
2231}
2232
8d318a50
LW		 2233/* DMA ENGINE functions */
2234static int d40_alloc_chan_resources(struct dma_chan *chan)
2235{
2236 int err;
2237 unsigned long flags;
2238 struct d40_chan *d40c =
2239 container_of(chan, struct d40_chan, chan);
ef1872ec 2240 bool is_free_phy;
8d318a50
LW		 2241 spin_lock_irqsave(&d40c->lock, flags);
2242
d3ee98cd 2243 dma_cookie_init(chan);
8d318a50 2244
ce2ca125
RV		 2245 /* If no dma configuration is set use default configuration (memcpy) */
2246 if (!d40c->configured) {
8d318a50 2247 err = d40_config_memcpy(d40c);
ff0b12ba 2248 if (err) {
6db5a8ba 2249 chan_err(d40c, "Failed to configure memcpy channel\n");
ff0b12ba
JA		 2250 goto fail;
2251 }
8d318a50
LW		 2252 }
2253
5cd326fd 2254 err = d40_allocate_channel(d40c, &is_free_phy);
8d318a50 2255 if (err) {
6db5a8ba 2256 chan_err(d40c, "Failed to allocate channel\n");
7fb3e75e 2257 d40c->configured = false;
ff0b12ba 2258 goto fail;
8d318a50
LW		 2259 }
2260
7fb3e75e 2261 pm_runtime_get_sync(d40c->base->dev);
ef1872ec
LW		 2262 /* Fill in basic CFG register values */
2263 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
724a8577 2264 &d40c->dst_def_cfg, chan_is_logical(d40c));
ef1872ec 2265
ac2c0a38
RV		 2266 d40_set_prio_realtime(d40c);
2267
724a8577 2268 if (chan_is_logical(d40c)) {
ef1872ec
LW		 2269 d40_log_cfg(&d40c->dma_cfg,
2270 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2271
2272 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
2273 d40c->lcpa = d40c->base->lcpa_base +
2274 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
2275 else
2276 d40c->lcpa = d40c->base->lcpa_base +
2277 d40c->dma_cfg.dst_dev_type *
2278 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
2279 }
2280
5cd326fd
N		 2281 dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
2282 chan_is_logical(d40c) ? "logical" : "physical",
2283 d40c->phy_chan->num,
2284 d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2285
2286
ef1872ec
LW		 2287 /*
2288 * Only write channel configuration to the DMA if the physical
2289 * resource is free. In case of multiple logical channels
2290 * on the same physical resource, only the first write is necessary.
2291 */
b55912c6
JA		 2292 if (is_free_phy)
2293 d40_config_write(d40c);
ff0b12ba 2294fail:
7fb3e75e
N		 2295 pm_runtime_mark_last_busy(d40c->base->dev);
2296 pm_runtime_put_autosuspend(d40c->base->dev);
8d318a50 2297 spin_unlock_irqrestore(&d40c->lock, flags);
ff0b12ba 2298 return err;
8d318a50
LW		 2299}
2300
2301static void d40_free_chan_resources(struct dma_chan *chan)
2302{
2303 struct d40_chan *d40c =
2304 container_of(chan, struct d40_chan, chan);
2305 int err;
2306 unsigned long flags;
2307
0d0f6b8b 2308 if (d40c->phy_chan == NULL) {
6db5a8ba 2309 chan_err(d40c, "Cannot free unallocated channel\n");
0d0f6b8b
JA		 2310 return;
2311 }
2312
2313
8d318a50
LW		 2314 spin_lock_irqsave(&d40c->lock, flags);
2315
2316 err = d40_free_dma(d40c);
2317
2318 if (err)
6db5a8ba 2319 chan_err(d40c, "Failed to free channel\n");
8d318a50
LW		 2320 spin_unlock_irqrestore(&d40c->lock, flags);
2321}
2322
2323static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2324 dma_addr_t dst,
2325 dma_addr_t src,
2326 size_t size,
2a614340 2327 unsigned long dma_flags)
8d318a50 2328{
95944c6e
RV		 2329 struct scatterlist dst_sg;
2330 struct scatterlist src_sg;
8d318a50 2331
95944c6e
RV		 2332 sg_init_table(&dst_sg, 1);
2333 sg_init_table(&src_sg, 1);
8d318a50 2334
95944c6e
RV		 2335 sg_dma_address(&dst_sg) = dst;
2336 sg_dma_address(&src_sg) = src;
8d318a50 2337
95944c6e
RV		 2338 sg_dma_len(&dst_sg) = size;
2339 sg_dma_len(&src_sg) = size;
8d318a50 2340
cade1d30 2341 return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
8d318a50
LW		 2342}
2343
0d688662 2344static struct dma_async_tx_descriptor *
cade1d30
RV		 2345d40_prep_memcpy_sg(struct dma_chan *chan,
2346 struct scatterlist *dst_sg, unsigned int dst_nents,
2347 struct scatterlist *src_sg, unsigned int src_nents,
2348 unsigned long dma_flags)
0d688662
IS		 2349{
2350 if (dst_nents != src_nents)
2351 return NULL;
2352
cade1d30 2353 return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
00ac0341
RV		 2354}
2355
8d318a50
LW		 2356static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2357 struct scatterlist *sgl,
2358 unsigned int sg_len,
db8196df 2359 enum dma_transfer_direction direction,
185ecb5f
AB		 2360 unsigned long dma_flags,
2361 void *context)
8d318a50 2362{
db8196df 2363 if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV)
00ac0341
RV		 2364 return NULL;
2365
cade1d30 2366 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
8d318a50
LW		 2367}
2368
0c842b55
RV		 2369static struct dma_async_tx_descriptor *
2370dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2371 size_t buf_len, size_t period_len,
ec8b5e48
PU		 2372 enum dma_transfer_direction direction, unsigned long flags,
2373 void *context)
0c842b55
RV		 2374{
2375 unsigned int periods = buf_len / period_len;
2376 struct dma_async_tx_descriptor *txd;
2377 struct scatterlist *sg;
2378 int i;
2379
79ca7ec3 2380 sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
0c842b55
RV		 2381 for (i = 0; i < periods; i++) {
2382 sg_dma_address(&sg[i]) = dma_addr;
2383 sg_dma_len(&sg[i]) = period_len;
2384 dma_addr += period_len;
2385 }
2386
2387 sg[periods].offset = 0;
fdaf9c4b 2388 sg_dma_len(&sg[periods]) = 0;
0c842b55
RV		 2389 sg[periods].page_link =
2390 ((unsigned long)sg | 0x01) & ~0x02;
2391
2392 txd = d40_prep_sg(chan, sg, sg, periods, direction,
2393 DMA_PREP_INTERRUPT);
2394
2395 kfree(sg);
2396
2397 return txd;
2398}
2399
8d318a50
LW		 2400static enum dma_status d40_tx_status(struct dma_chan *chan,
2401 dma_cookie_t cookie,
2402 struct dma_tx_state *txstate)
2403{
2404 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
96a2af41 2405 enum dma_status ret;
8d318a50 2406
0d0f6b8b 2407 if (d40c->phy_chan == NULL) {
6db5a8ba 2408 chan_err(d40c, "Cannot read status of unallocated channel\n");
0d0f6b8b
JA		 2409 return -EINVAL;
2410 }
2411
96a2af41
RKAL		 2412 ret = dma_cookie_status(chan, cookie, txstate);
2413 if (ret != DMA_SUCCESS)
2414 dma_set_residue(txstate, stedma40_residue(chan));
8d318a50 2415
a5ebca47
JA		 2416 if (d40_is_paused(d40c))
2417 ret = DMA_PAUSED;
8d318a50
LW		 2418
2419 return ret;
2420}
2421
2422static void d40_issue_pending(struct dma_chan *chan)
2423{
2424 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2425 unsigned long flags;
2426
0d0f6b8b 2427 if (d40c->phy_chan == NULL) {
6db5a8ba 2428 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2429 return;
2430 }
2431
8d318a50
LW		 2432 spin_lock_irqsave(&d40c->lock, flags);
2433
a8f3067b
PF		 2434 list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2435
2436 /* Busy means that queued jobs are already being processed */
8d318a50
LW		 2437 if (!d40c->busy)
2438 (void) d40_queue_start(d40c);
2439
2440 spin_unlock_irqrestore(&d40c->lock, flags);
2441}
2442
1bdae6f4
N		 2443static void d40_terminate_all(struct dma_chan *chan)
2444{
2445 unsigned long flags;
2446 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2447 int ret;
2448
2449 spin_lock_irqsave(&d40c->lock, flags);
2450
2451 pm_runtime_get_sync(d40c->base->dev);
2452 ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
2453 if (ret)
2454 chan_err(d40c, "Failed to stop channel\n");
2455
2456 d40_term_all(d40c);
2457 pm_runtime_mark_last_busy(d40c->base->dev);
2458 pm_runtime_put_autosuspend(d40c->base->dev);
2459 if (d40c->busy) {
2460 pm_runtime_mark_last_busy(d40c->base->dev);
2461 pm_runtime_put_autosuspend(d40c->base->dev);
2462 }
2463 d40c->busy = false;
2464
2465 spin_unlock_irqrestore(&d40c->lock, flags);
2466}
2467
98ca5289
RV		 2468static int
2469dma40_config_to_halfchannel(struct d40_chan *d40c,
2470 struct stedma40_half_channel_info *info,
2471 enum dma_slave_buswidth width,
2472 u32 maxburst)
2473{
2474 enum stedma40_periph_data_width addr_width;
2475 int psize;
2476
2477 switch (width) {
2478 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2479 addr_width = STEDMA40_BYTE_WIDTH;
2480 break;
2481 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2482 addr_width = STEDMA40_HALFWORD_WIDTH;
2483 break;
2484 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2485 addr_width = STEDMA40_WORD_WIDTH;
2486 break;
2487 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2488 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2489 break;
2490 default:
2491 dev_err(d40c->base->dev,
2492 "illegal peripheral address width "
2493 "requested (%d)\n",
2494 width);
2495 return -EINVAL;
2496 }
2497
2498 if (chan_is_logical(d40c)) {
2499 if (maxburst >= 16)
2500 psize = STEDMA40_PSIZE_LOG_16;
2501 else if (maxburst >= 8)
2502 psize = STEDMA40_PSIZE_LOG_8;
2503 else if (maxburst >= 4)
2504 psize = STEDMA40_PSIZE_LOG_4;
2505 else
2506 psize = STEDMA40_PSIZE_LOG_1;
2507 } else {
2508 if (maxburst >= 16)
2509 psize = STEDMA40_PSIZE_PHY_16;
2510 else if (maxburst >= 8)
2511 psize = STEDMA40_PSIZE_PHY_8;
2512 else if (maxburst >= 4)
2513 psize = STEDMA40_PSIZE_PHY_4;
2514 else
2515 psize = STEDMA40_PSIZE_PHY_1;
2516 }
2517
2518 info->data_width = addr_width;
2519 info->psize = psize;
2520 info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2521
2522 return 0;
2523}
2524
95e1400f 2525/* Runtime reconfiguration extension */
98ca5289
RV		 2526static int d40_set_runtime_config(struct dma_chan *chan,
2527 struct dma_slave_config *config)
95e1400f
LW		 2528{
2529 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2530 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
98ca5289 2531 enum dma_slave_buswidth src_addr_width, dst_addr_width;
95e1400f 2532 dma_addr_t config_addr;
98ca5289
RV		 2533 u32 src_maxburst, dst_maxburst;
2534 int ret;
2535
2536 src_addr_width = config->src_addr_width;
2537 src_maxburst = config->src_maxburst;
2538 dst_addr_width = config->dst_addr_width;
2539 dst_maxburst = config->dst_maxburst;
95e1400f 2540
db8196df 2541 if (config->direction == DMA_DEV_TO_MEM) {
95e1400f
LW		 2542 dma_addr_t dev_addr_rx =
2543 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2544
2545 config_addr = config->src_addr;
2546 if (dev_addr_rx)
2547 dev_dbg(d40c->base->dev,
2548 "channel has a pre-wired RX address %08x "
2549 "overriding with %08x\n",
2550 dev_addr_rx, config_addr);
2551 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2552 dev_dbg(d40c->base->dev,
2553 "channel was not configured for peripheral "
2554 "to memory transfer (%d) overriding\n",
2555 cfg->dir);
2556 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2557
98ca5289
RV		 2558 /* Configure the memory side */
2559 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2560 dst_addr_width = src_addr_width;
2561 if (dst_maxburst == 0)
2562 dst_maxburst = src_maxburst;
95e1400f 2563
db8196df 2564 } else if (config->direction == DMA_MEM_TO_DEV) {
95e1400f
LW		 2565 dma_addr_t dev_addr_tx =
2566 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2567
2568 config_addr = config->dst_addr;
2569 if (dev_addr_tx)
2570 dev_dbg(d40c->base->dev,
2571 "channel has a pre-wired TX address %08x "
2572 "overriding with %08x\n",
2573 dev_addr_tx, config_addr);
2574 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2575 dev_dbg(d40c->base->dev,
2576 "channel was not configured for memory "
2577 "to peripheral transfer (%d) overriding\n",
2578 cfg->dir);
2579 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2580
98ca5289
RV		 2581 /* Configure the memory side */
2582 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2583 src_addr_width = dst_addr_width;
2584 if (src_maxburst == 0)
2585 src_maxburst = dst_maxburst;
95e1400f
LW		 2586 } else {
2587 dev_err(d40c->base->dev,
2588 "unrecognized channel direction %d\n",
2589 config->direction);
98ca5289 2590 return -EINVAL;
95e1400f
LW		 2591 }
2592
98ca5289 2593 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
95e1400f 2594 dev_err(d40c->base->dev,
98ca5289
RV		 2595 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2596 src_maxburst,
2597 src_addr_width,
2598 dst_maxburst,
2599 dst_addr_width);
2600 return -EINVAL;
95e1400f
LW		 2601 }
2602
92bb6cdb
PF		 2603 if (src_maxburst > 16) {
2604 src_maxburst = 16;
2605 dst_maxburst = src_maxburst * src_addr_width / dst_addr_width;
2606 } else if (dst_maxburst > 16) {
2607 dst_maxburst = 16;
2608 src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
2609 }
2610
98ca5289
RV		 2611 ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
2612 src_addr_width,
2613 src_maxburst);
2614 if (ret)
2615 return ret;
95e1400f 2616
98ca5289
RV		 2617 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
2618 dst_addr_width,
2619 dst_maxburst);
2620 if (ret)
2621 return ret;
95e1400f 2622
a59670a4 2623 /* Fill in register values */
724a8577 2624 if (chan_is_logical(d40c))
a59670a4
PF		 2625 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2626 else
2627 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2628 &d40c->dst_def_cfg, false);
2629
95e1400f
LW		 2630 /* These settings will take precedence later */
2631 d40c->runtime_addr = config_addr;
2632 d40c->runtime_direction = config->direction;
2633 dev_dbg(d40c->base->dev,
98ca5289
RV		 2634 "configured channel %s for %s, data width %d/%d, "
2635 "maxburst %d/%d elements, LE, no flow control\n",
95e1400f 2636 dma_chan_name(chan),
db8196df 2637 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
98ca5289
RV		 2638 src_addr_width, dst_addr_width,
2639 src_maxburst, dst_maxburst);
2640
2641 return 0;
95e1400f
LW		 2642}
2643
05827630
LW		 2644static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2645 unsigned long arg)
8d318a50 2646{
8d318a50
LW		 2647 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2648
0d0f6b8b 2649 if (d40c->phy_chan == NULL) {
6db5a8ba 2650 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2651 return -EINVAL;
2652 }
2653
8d318a50
LW		 2654 switch (cmd) {
2655 case DMA_TERMINATE_ALL:
1bdae6f4
N		 2656 d40_terminate_all(chan);
2657 return 0;
8d318a50 2658 case DMA_PAUSE:
86eb5fb6 2659 return d40_pause(d40c);
8d318a50 2660 case DMA_RESUME:
86eb5fb6 2661 return d40_resume(d40c);
95e1400f 2662 case DMA_SLAVE_CONFIG:
98ca5289 2663 return d40_set_runtime_config(chan,
95e1400f 2664 (struct dma_slave_config *) arg);
95e1400f
LW		 2665 default:
2666 break;
8d318a50
LW		 2667 }
2668
2669 /* Other commands are unimplemented */
2670 return -ENXIO;
2671}
2672
2673/* Initialization functions */
2674
2675static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2676 struct d40_chan *chans, int offset,
2677 int num_chans)
2678{
2679 int i = 0;
2680 struct d40_chan *d40c;
2681
2682 INIT_LIST_HEAD(&dma->channels);
2683
2684 for (i = offset; i < offset + num_chans; i++) {
2685 d40c = &chans[i];
2686 d40c->base = base;
2687 d40c->chan.device = dma;
2688
8d318a50
LW		 2689 spin_lock_init(&d40c->lock);
2690
2691 d40c->log_num = D40_PHY_CHAN;
2692
8d318a50
LW		 2693 INIT_LIST_HEAD(&d40c->active);
2694 INIT_LIST_HEAD(&d40c->queue);
a8f3067b 2695 INIT_LIST_HEAD(&d40c->pending_queue);
8d318a50 2696 INIT_LIST_HEAD(&d40c->client);
82babbb3 2697 INIT_LIST_HEAD(&d40c->prepare_queue);
8d318a50 2698
8d318a50
LW		 2699 tasklet_init(&d40c->tasklet, dma_tasklet,
2700 (unsigned long) d40c);
2701
2702 list_add_tail(&d40c->chan.device_node,
2703 &dma->channels);
2704 }
2705}
2706
7ad74a7c
RV		 2707static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2708{
2709 if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2710 dev->device_prep_slave_sg = d40_prep_slave_sg;
2711
2712 if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2713 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2714
2715 /*
2716 * This controller can only access address at even
2717 * 32bit boundaries, i.e. 2^2
2718 */
2719 dev->copy_align = 2;
2720 }
2721
2722 if (dma_has_cap(DMA_SG, dev->cap_mask))
2723 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2724
0c842b55
RV		 2725 if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2726 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2727
7ad74a7c
RV		 2728 dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2729 dev->device_free_chan_resources = d40_free_chan_resources;
2730 dev->device_issue_pending = d40_issue_pending;
2731 dev->device_tx_status = d40_tx_status;
2732 dev->device_control = d40_control;
2733 dev->dev = base->dev;
2734}
2735
8d318a50
LW		 2736static int __init d40_dmaengine_init(struct d40_base *base,
2737 int num_reserved_chans)
2738{
2739 int err ;
2740
2741 d40_chan_init(base, &base->dma_slave, base->log_chans,
2742 0, base->num_log_chans);
2743
2744 dma_cap_zero(base->dma_slave.cap_mask);
2745 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
0c842b55 2746 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
8d318a50 2747
7ad74a7c 2748 d40_ops_init(base, &base->dma_slave);
8d318a50
LW		 2749
2750 err = dma_async_device_register(&base->dma_slave);
2751
2752 if (err) {
6db5a8ba 2753 d40_err(base->dev, "Failed to register slave channels\n");
8d318a50
LW		 2754 goto failure1;
2755 }
2756
2757 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2758 base->num_log_chans, base->plat_data->memcpy_len);
2759
2760 dma_cap_zero(base->dma_memcpy.cap_mask);
2761 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
7ad74a7c
RV		 2762 dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
2763
2764 d40_ops_init(base, &base->dma_memcpy);
8d318a50
LW		 2765
2766 err = dma_async_device_register(&base->dma_memcpy);
2767
2768 if (err) {
6db5a8ba
RV		 2769 d40_err(base->dev,
2770 "Failed to regsiter memcpy only channels\n");
8d318a50
LW		 2771 goto failure2;
2772 }
2773
2774 d40_chan_init(base, &base->dma_both, base->phy_chans,
2775 0, num_reserved_chans);
2776
2777 dma_cap_zero(base->dma_both.cap_mask);
2778 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2779 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
7ad74a7c 2780 dma_cap_set(DMA_SG, base->dma_both.cap_mask);
0c842b55 2781 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
7ad74a7c
RV		 2782
2783 d40_ops_init(base, &base->dma_both);
8d318a50
LW		 2784 err = dma_async_device_register(&base->dma_both);
2785
2786 if (err) {
6db5a8ba
RV		 2787 d40_err(base->dev,
2788 "Failed to register logical and physical capable channels\n");
8d318a50
LW		 2789 goto failure3;
2790 }
2791 return 0;
2792failure3:
2793 dma_async_device_unregister(&base->dma_memcpy);
2794failure2:
2795 dma_async_device_unregister(&base->dma_slave);
2796failure1:
2797 return err;
2798}
2799
7fb3e75e
N		 2800/* Suspend resume functionality */
2801#ifdef CONFIG_PM
2802static int dma40_pm_suspend(struct device *dev)
2803{
28c7a19d
N		 2804 struct platform_device *pdev = to_platform_device(dev);
2805 struct d40_base *base = platform_get_drvdata(pdev);
2806 int ret = 0;
7fb3e75e 2807
28c7a19d
N		 2808 if (base->lcpa_regulator)
2809 ret = regulator_disable(base->lcpa_regulator);
2810 return ret;
7fb3e75e
N		 2811}
2812
2813static int dma40_runtime_suspend(struct device *dev)
2814{
2815 struct platform_device *pdev = to_platform_device(dev);
2816 struct d40_base *base = platform_get_drvdata(pdev);
2817
2818 d40_save_restore_registers(base, true);
2819
2820 /* Don't disable/enable clocks for v1 due to HW bugs */
2821 if (base->rev != 1)
2822 writel_relaxed(base->gcc_pwr_off_mask,
2823 base->virtbase + D40_DREG_GCC);
2824
2825 return 0;
2826}
2827
2828static int dma40_runtime_resume(struct device *dev)
2829{
2830 struct platform_device *pdev = to_platform_device(dev);
2831 struct d40_base *base = platform_get_drvdata(pdev);
2832
2833 if (base->initialized)
2834 d40_save_restore_registers(base, false);
2835
2836 writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
2837 base->virtbase + D40_DREG_GCC);
2838 return 0;
2839}
2840
28c7a19d
N		 2841static int dma40_resume(struct device *dev)
2842{
2843 struct platform_device *pdev = to_platform_device(dev);
2844 struct d40_base *base = platform_get_drvdata(pdev);
2845 int ret = 0;
2846
2847 if (base->lcpa_regulator)
2848 ret = regulator_enable(base->lcpa_regulator);
2849
2850 return ret;
2851}
7fb3e75e
N		 2852
2853static const struct dev_pm_ops dma40_pm_ops = {
2854 .suspend = dma40_pm_suspend,
2855 .runtime_suspend = dma40_runtime_suspend,
2856 .runtime_resume = dma40_runtime_resume,
28c7a19d 2857 .resume = dma40_resume,
7fb3e75e
N		 2858};
2859#define DMA40_PM_OPS (&dma40_pm_ops)
2860#else
2861#define DMA40_PM_OPS NULL
2862#endif
2863
8d318a50
LW		 2864/* Initialization functions. */
2865
2866static int __init d40_phy_res_init(struct d40_base *base)
2867{
2868 int i;
2869 int num_phy_chans_avail = 0;
2870 u32 val[2];
2871 int odd_even_bit = -2;
7fb3e75e 2872 int gcc = D40_DREG_GCC_ENA;
8d318a50
LW		 2873
2874 val[0] = readl(base->virtbase + D40_DREG_PRSME);
2875 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2876
2877 for (i = 0; i < base->num_phy_chans; i++) {
2878 base->phy_res[i].num = i;
2879 odd_even_bit += 2 * ((i % 2) == 0);
2880 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2881 /* Mark security only channels as occupied */
2882 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2883 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
7fb3e75e
N		 2884 base->phy_res[i].reserved = true;
2885 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
2886 D40_DREG_GCC_SRC);
2887 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
2888 D40_DREG_GCC_DST);
2889
2890
8d318a50
LW		 2891 } else {
2892 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2893 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
7fb3e75e 2894 base->phy_res[i].reserved = false;
8d318a50
LW		 2895 num_phy_chans_avail++;
2896 }
2897 spin_lock_init(&base->phy_res[i].lock);
2898 }
6b7acd84
JA		 2899
2900 /* Mark disabled channels as occupied */
2901 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
f57b407c
RV		 2902 int chan = base->plat_data->disabled_channels[i];
2903
2904 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
2905 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
7fb3e75e
N		 2906 base->phy_res[chan].reserved = true;
2907 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
2908 D40_DREG_GCC_SRC);
2909 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
2910 D40_DREG_GCC_DST);
f57b407c 2911 num_phy_chans_avail--;
6b7acd84
JA		 2912 }
2913
8d318a50
LW		 2914 dev_info(base->dev, "%d of %d physical DMA channels available\n",
2915 num_phy_chans_avail, base->num_phy_chans);
2916
2917 /* Verify settings extended vs standard */
2918 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2919
2920 for (i = 0; i < base->num_phy_chans; i++) {
2921
2922 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2923 (val[0] & 0x3) != 1)
2924 dev_info(base->dev,
2925 "[%s] INFO: channel %d is misconfigured (%d)\n",
2926 __func__, i, val[0] & 0x3);
2927
2928 val[0] = val[0] >> 2;
2929 }
2930
7fb3e75e
N		 2931 /*
2932 * To keep things simple, Enable all clocks initially.
2933 * The clocks will get managed later post channel allocation.
2934 * The clocks for the event lines on which reserved channels exists
2935 * are not managed here.
2936 */
2937 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
2938 base->gcc_pwr_off_mask = gcc;
2939
8d318a50
LW		 2940 return num_phy_chans_avail;
2941}
2942
2943static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2944{
8d318a50
LW		 2945 struct stedma40_platform_data *plat_data;
2946 struct clk *clk = NULL;
2947 void __iomem *virtbase = NULL;
2948 struct resource *res = NULL;
2949 struct d40_base *base = NULL;
2950 int num_log_chans = 0;
2951 int num_phy_chans;
b707c658 2952 int clk_ret = -EINVAL;
8d318a50 2953 int i;
f4b89764
LW		 2954 u32 pid;
2955 u32 cid;
2956 u8 rev;
8d318a50
LW		 2957
2958 clk = clk_get(&pdev->dev, NULL);
8d318a50 2959 if (IS_ERR(clk)) {
6db5a8ba 2960 d40_err(&pdev->dev, "No matching clock found\n");
8d318a50
LW		 2961 goto failure;
2962 }
2963
b707c658
UH		 2964 clk_ret = clk_prepare_enable(clk);
2965 if (clk_ret) {
2966 d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
2967 goto failure;
2968 }
8d318a50
LW		 2969
2970 /* Get IO for DMAC base address */
2971 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2972 if (!res)
2973 goto failure;
2974
2975 if (request_mem_region(res->start, resource_size(res),
2976 D40_NAME " I/O base") == NULL)
2977 goto failure;
2978
2979 virtbase = ioremap(res->start, resource_size(res));
2980 if (!virtbase)
2981 goto failure;
2982
f4b89764
LW		 2983 /* This is just a regular AMBA PrimeCell ID actually */
2984 for (pid = 0, i = 0; i < 4; i++)
2985 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
2986 & 255) << (i * 8);
2987 for (cid = 0, i = 0; i < 4; i++)
2988 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
2989 & 255) << (i * 8);
8d318a50 2990
f4b89764
LW		 2991 if (cid != AMBA_CID) {
2992 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
2993 goto failure;
2994 }
2995 if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
6db5a8ba 2996 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
f4b89764
LW		 2997 AMBA_MANF_BITS(pid),
2998 AMBA_VENDOR_ST);
8d318a50
LW		 2999 goto failure;
3000 }
f4b89764
LW		 3001 /*
3002 * HW revision:
3003 * DB8500ed has revision 0
3004 * ? has revision 1
3005 * DB8500v1 has revision 2
3006 * DB8500v2 has revision 3
47db92f4
GB		 3007 * AP9540v1 has revision 4
3008 * DB8540v1 has revision 4
f4b89764
LW		 3009 */
3010 rev = AMBA_REV_BITS(pid);
3ae0267f 3011
47db92f4
GB		 3012 plat_data = pdev->dev.platform_data;
3013
8d318a50 3014 /* The number of physical channels on this HW */
47db92f4
GB		 3015 if (plat_data->num_of_phy_chans)
3016 num_phy_chans = plat_data->num_of_phy_chans;
3017 else
3018 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
8d318a50 3019
47db92f4
GB		 3020 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x with %d physical channels\n",
3021 rev, res->start, num_phy_chans);
8d318a50 3022
1bdae6f4
N		 3023 if (rev < 2) {
3024 d40_err(&pdev->dev, "hardware revision: %d is not supported",
3025 rev);
3026 goto failure;
3027 }
3028
8d318a50
LW		 3029 /* Count the number of logical channels in use */
3030 for (i = 0; i < plat_data->dev_len; i++)
3031 if (plat_data->dev_rx[i] != 0)
3032 num_log_chans++;
3033
3034 for (i = 0; i < plat_data->dev_len; i++)
3035 if (plat_data->dev_tx[i] != 0)
3036 num_log_chans++;
3037
3038 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
3039 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
3040 sizeof(struct d40_chan), GFP_KERNEL);
3041
3042 if (base == NULL) {
6db5a8ba 3043 d40_err(&pdev->dev, "Out of memory\n");
8d318a50
LW		 3044 goto failure;
3045 }
3046
3ae0267f 3047 base->rev = rev;
8d318a50
LW		 3048 base->clk = clk;
3049 base->num_phy_chans = num_phy_chans;
3050 base->num_log_chans = num_log_chans;
3051 base->phy_start = res->start;
3052 base->phy_size = resource_size(res);
3053 base->virtbase = virtbase;
3054 base->plat_data = plat_data;
3055 base->dev = &pdev->dev;
3056 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
3057 base->log_chans = &base->phy_chans[num_phy_chans];
3058
3059 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
3060 GFP_KERNEL);
3061 if (!base->phy_res)
3062 goto failure;
3063
3064 base->lookup_phy_chans = kzalloc(num_phy_chans *
3065 sizeof(struct d40_chan *),
3066 GFP_KERNEL);
3067 if (!base->lookup_phy_chans)
3068 goto failure;
3069
3070 if (num_log_chans + plat_data->memcpy_len) {
3071 /*
3072 * The max number of logical channels are event lines for all
3073 * src devices and dst devices
3074 */
3075 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
3076 sizeof(struct d40_chan *),
3077 GFP_KERNEL);
3078 if (!base->lookup_log_chans)
3079 goto failure;
3080 }
698e4732 3081
7fb3e75e
N		 3082 base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
3083 sizeof(d40_backup_regs_chan),
8d318a50 3084 GFP_KERNEL);
7fb3e75e
N		 3085 if (!base->reg_val_backup_chan)
3086 goto failure;
3087
3088 base->lcla_pool.alloc_map =
3089 kzalloc(num_phy_chans * sizeof(struct d40_desc *)
3090 * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
8d318a50
LW		 3091 if (!base->lcla_pool.alloc_map)
3092 goto failure;
3093
c675b1b4
JA		 3094 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
3095 0, SLAB_HWCACHE_ALIGN,
3096 NULL);
3097 if (base->desc_slab == NULL)
3098 goto failure;
3099
8d318a50
LW		 3100 return base;
3101
3102failure:
b707c658
UH		 3103 if (!clk_ret)
3104 clk_disable_unprepare(clk);
3105 if (!IS_ERR(clk))
8d318a50 3106 clk_put(clk);
8d318a50
LW		 3107 if (virtbase)
3108 iounmap(virtbase);
3109 if (res)
3110 release_mem_region(res->start,
3111 resource_size(res));
3112 if (virtbase)
3113 iounmap(virtbase);
3114
3115 if (base) {
3116 kfree(base->lcla_pool.alloc_map);
1bdae6f4 3117 kfree(base->reg_val_backup_chan);
8d318a50
LW		 3118 kfree(base->lookup_log_chans);
3119 kfree(base->lookup_phy_chans);
3120 kfree(base->phy_res);
3121 kfree(base);
3122 }
3123
3124 return NULL;
3125}
3126
3127static void __init d40_hw_init(struct d40_base *base)
3128{
3129
7fb3e75e 3130 static struct d40_reg_val dma_init_reg[] = {
8d318a50 3131 /* Clock every part of the DMA block from start */
7fb3e75e 3132 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
8d318a50
LW		 3133
3134 /* Interrupts on all logical channels */
3135 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
3136 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
3137 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
3138 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
3139 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
3140 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
3141 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
3142 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
3143 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
3144 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
3145 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
3146 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
3147 };
3148 int i;
3149 u32 prmseo[2] = {0, 0};
3150 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3151 u32 pcmis = 0;
3152 u32 pcicr = 0;
3153
3154 for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
3155 writel(dma_init_reg[i].val,
3156 base->virtbase + dma_init_reg[i].reg);
3157
3158 /* Configure all our dma channels to default settings */
3159 for (i = 0; i < base->num_phy_chans; i++) {
3160
3161 activeo[i % 2] = activeo[i % 2] << 2;
3162
3163 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
3164 == D40_ALLOC_PHY) {
3165 activeo[i % 2] |= 3;
3166 continue;
3167 }
3168
3169 /* Enable interrupt # */
3170 pcmis = (pcmis << 1) | 1;
3171
3172 /* Clear interrupt # */
3173 pcicr = (pcicr << 1) | 1;
3174
3175 /* Set channel to physical mode */
3176 prmseo[i % 2] = prmseo[i % 2] << 2;
3177 prmseo[i % 2] |= 1;
3178
3179 }
3180
3181 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3182 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3183 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3184 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3185
3186 /* Write which interrupt to enable */
3187 writel(pcmis, base->virtbase + D40_DREG_PCMIS);
3188
3189 /* Write which interrupt to clear */
3190 writel(pcicr, base->virtbase + D40_DREG_PCICR);
3191
3192}
3193
508849ad
LW		 3194static int __init d40_lcla_allocate(struct d40_base *base)
3195{
026cbc42 3196 struct d40_lcla_pool *pool = &base->lcla_pool;
508849ad
LW		 3197 unsigned long *page_list;
3198 int i, j;
3199 int ret = 0;
3200
3201 /*
3202 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3203 * To full fill this hardware requirement without wasting 256 kb
3204 * we allocate pages until we get an aligned one.
3205 */
3206 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
3207 GFP_KERNEL);
3208
3209 if (!page_list) {
3210 ret = -ENOMEM;
3211 goto failure;
3212 }
3213
3214 /* Calculating how many pages that are required */
3215 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
3216
3217 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
3218 page_list[i] = __get_free_pages(GFP_KERNEL,
3219 base->lcla_pool.pages);
3220 if (!page_list[i]) {
3221
6db5a8ba
RV		 3222 d40_err(base->dev, "Failed to allocate %d pages.\n",
3223 base->lcla_pool.pages);
508849ad
LW		 3224
3225 for (j = 0; j < i; j++)
3226 free_pages(page_list[j], base->lcla_pool.pages);
3227 goto failure;
3228 }
3229
3230 if ((virt_to_phys((void *)page_list[i]) &
3231 (LCLA_ALIGNMENT - 1)) == 0)
3232 break;
3233 }
3234
3235 for (j = 0; j < i; j++)
3236 free_pages(page_list[j], base->lcla_pool.pages);
3237
3238 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
3239 base->lcla_pool.base = (void *)page_list[i];
3240 } else {
767a9675
JA		 3241 /*
3242 * After many attempts and no succees with finding the correct
3243 * alignment, try with allocating a big buffer.
3244 */
508849ad
LW		 3245 dev_warn(base->dev,
3246 "[%s] Failed to get %d pages @ 18 bit align.\n",
3247 __func__, base->lcla_pool.pages);
3248 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
3249 base->num_phy_chans +
3250 LCLA_ALIGNMENT,
3251 GFP_KERNEL);
3252 if (!base->lcla_pool.base_unaligned) {
3253 ret = -ENOMEM;
3254 goto failure;
3255 }
3256
3257 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
3258 LCLA_ALIGNMENT);
3259 }
3260
026cbc42
RV		 3261 pool->dma_addr = dma_map_single(base->dev, pool->base,
3262 SZ_1K * base->num_phy_chans,
3263 DMA_TO_DEVICE);
3264 if (dma_mapping_error(base->dev, pool->dma_addr)) {
3265 pool->dma_addr = 0;
3266 ret = -ENOMEM;
3267 goto failure;
3268 }
3269
508849ad
LW		 3270 writel(virt_to_phys(base->lcla_pool.base),
3271 base->virtbase + D40_DREG_LCLA);
3272failure:
3273 kfree(page_list);
3274 return ret;
3275}
3276
8d318a50
LW		 3277static int __init d40_probe(struct platform_device *pdev)
3278{
3279 int err;
3280 int ret = -ENOENT;
3281 struct d40_base *base;
3282 struct resource *res = NULL;
3283 int num_reserved_chans;
3284 u32 val;
3285
3286 base = d40_hw_detect_init(pdev);
3287
3288 if (!base)
3289 goto failure;
3290
3291 num_reserved_chans = d40_phy_res_init(base);
3292
3293 platform_set_drvdata(pdev, base);
3294
3295 spin_lock_init(&base->interrupt_lock);
3296 spin_lock_init(&base->execmd_lock);
3297
3298 /* Get IO for logical channel parameter address */
3299 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
3300 if (!res) {
3301 ret = -ENOENT;
6db5a8ba 3302 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
8d318a50
LW		 3303 goto failure;
3304 }
3305 base->lcpa_size = resource_size(res);
3306 base->phy_lcpa = res->start;
3307
3308 if (request_mem_region(res->start, resource_size(res),
3309 D40_NAME " I/O lcpa") == NULL) {
3310 ret = -EBUSY;
6db5a8ba
RV		 3311 d40_err(&pdev->dev,
3312 "Failed to request LCPA region 0x%x-0x%x\n",
3313 res->start, res->end);
8d318a50
LW		 3314 goto failure;
3315 }
3316
3317 /* We make use of ESRAM memory for this. */
3318 val = readl(base->virtbase + D40_DREG_LCPA);
3319 if (res->start != val && val != 0) {
3320 dev_warn(&pdev->dev,
3321 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
3322 __func__, val, res->start);
3323 } else
3324 writel(res->start, base->virtbase + D40_DREG_LCPA);
3325
3326 base->lcpa_base = ioremap(res->start, resource_size(res));
3327 if (!base->lcpa_base) {
3328 ret = -ENOMEM;
6db5a8ba 3329 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
8d318a50
LW		 3330 goto failure;
3331 }
28c7a19d
N		 3332 /* If lcla has to be located in ESRAM we don't need to allocate */
3333 if (base->plat_data->use_esram_lcla) {
3334 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3335 "lcla_esram");
3336 if (!res) {
3337 ret = -ENOENT;
3338 d40_err(&pdev->dev,
3339 "No \"lcla_esram\" memory resource\n");
3340 goto failure;
3341 }
3342 base->lcla_pool.base = ioremap(res->start,
3343 resource_size(res));
3344 if (!base->lcla_pool.base) {
3345 ret = -ENOMEM;
3346 d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
3347 goto failure;
3348 }
3349 writel(res->start, base->virtbase + D40_DREG_LCLA);
8d318a50 3350
28c7a19d
N		 3351 } else {
3352 ret = d40_lcla_allocate(base);
3353 if (ret) {
3354 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
3355 goto failure;
3356 }
8d318a50
LW		 3357 }
3358
3359 spin_lock_init(&base->lcla_pool.lock);
3360
8d318a50
LW		 3361 base->irq = platform_get_irq(pdev, 0);
3362
3363 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
8d318a50 3364 if (ret) {
6db5a8ba 3365 d40_err(&pdev->dev, "No IRQ defined\n");
8d318a50
LW		 3366 goto failure;
3367 }
3368
7fb3e75e
N		 3369 pm_runtime_irq_safe(base->dev);
3370 pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
3371 pm_runtime_use_autosuspend(base->dev);
3372 pm_runtime_enable(base->dev);
3373 pm_runtime_resume(base->dev);
28c7a19d
N		 3374
3375 if (base->plat_data->use_esram_lcla) {
3376
3377 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
3378 if (IS_ERR(base->lcpa_regulator)) {
3379 d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
3380 base->lcpa_regulator = NULL;
3381 goto failure;
3382 }
3383
3384 ret = regulator_enable(base->lcpa_regulator);
3385 if (ret) {
3386 d40_err(&pdev->dev,
3387 "Failed to enable lcpa_regulator\n");
3388 regulator_put(base->lcpa_regulator);
3389 base->lcpa_regulator = NULL;
3390 goto failure;
3391 }
3392 }
3393
7fb3e75e 3394 base->initialized = true;
8d318a50
LW		 3395 err = d40_dmaengine_init(base, num_reserved_chans);
3396 if (err)
3397 goto failure;
3398
b96710e5
PF		 3399 base->dev->dma_parms = &base->dma_parms;
3400 err = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
3401 if (err) {
3402 d40_err(&pdev->dev, "Failed to set dma max seg size\n");
3403 goto failure;
3404 }
3405
8d318a50
LW		 3406 d40_hw_init(base);
3407
3408 dev_info(base->dev, "initialized\n");
3409 return 0;
3410
3411failure:
3412 if (base) {
c675b1b4
JA		 3413 if (base->desc_slab)
3414 kmem_cache_destroy(base->desc_slab);
8d318a50
LW		 3415 if (base->virtbase)
3416 iounmap(base->virtbase);
026cbc42 3417
28c7a19d
N		 3418 if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
3419 iounmap(base->lcla_pool.base);
3420 base->lcla_pool.base = NULL;
3421 }
3422
026cbc42
RV		 3423 if (base->lcla_pool.dma_addr)
3424 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
3425 SZ_1K * base->num_phy_chans,
3426 DMA_TO_DEVICE);
3427
508849ad
LW		 3428 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
3429 free_pages((unsigned long)base->lcla_pool.base,
3430 base->lcla_pool.pages);
767a9675
JA		 3431
3432 kfree(base->lcla_pool.base_unaligned);
3433
8d318a50
LW		 3434 if (base->phy_lcpa)
3435 release_mem_region(base->phy_lcpa,
3436 base->lcpa_size);
3437 if (base->phy_start)
3438 release_mem_region(base->phy_start,
3439 base->phy_size);
3440 if (base->clk) {
3441 clk_disable(base->clk);
3442 clk_put(base->clk);
3443 }
3444
28c7a19d
N		 3445 if (base->lcpa_regulator) {
3446 regulator_disable(base->lcpa_regulator);
3447 regulator_put(base->lcpa_regulator);
3448 }
3449
8d318a50
LW		 3450 kfree(base->lcla_pool.alloc_map);
3451 kfree(base->lookup_log_chans);
3452 kfree(base->lookup_phy_chans);
3453 kfree(base->phy_res);
3454 kfree(base);
3455 }
3456
6db5a8ba 3457 d40_err(&pdev->dev, "probe failed\n");
8d318a50
LW		 3458 return ret;
3459}
3460
3461static struct platform_driver d40_driver = {
3462 .driver = {
3463 .owner = THIS_MODULE,
3464 .name = D40_NAME,
7fb3e75e 3465 .pm = DMA40_PM_OPS,
8d318a50
LW		 3466 },
3467};
3468
cb9ab2d8 3469static int __init stedma40_init(void)
8d318a50
LW		 3470{
3471 return platform_driver_probe(&d40_driver, d40_probe);
3472}
a0eb221a 3473subsys_initcall(stedma40_init);
Linux kernel - Deliverables
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