Commit | Line | Data |
---|---|---|
8d318a50 | 1 | /* |
d49278e3 PF |
2 | * Copyright (C) Ericsson AB 2007-2008 |
3 | * Copyright (C) ST-Ericsson SA 2008-2010 | |
661385f9 | 4 | * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson |
767a9675 | 5 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson |
8d318a50 | 6 | * License terms: GNU General Public License (GPL) version 2 |
8d318a50 LW |
7 | */ |
8 | ||
9 | #include <linux/kernel.h> | |
10 | #include <linux/slab.h> | |
11 | #include <linux/dmaengine.h> | |
12 | #include <linux/platform_device.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
698e4732 | 15 | #include <linux/err.h> |
8d318a50 LW |
16 | |
17 | #include <plat/ste_dma40.h> | |
18 | ||
19 | #include "ste_dma40_ll.h" | |
20 | ||
21 | #define D40_NAME "dma40" | |
22 | ||
23 | #define D40_PHY_CHAN -1 | |
24 | ||
25 | /* For masking out/in 2 bit channel positions */ | |
26 | #define D40_CHAN_POS(chan) (2 * (chan / 2)) | |
27 | #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan)) | |
28 | ||
29 | /* Maximum iterations taken before giving up suspending a channel */ | |
30 | #define D40_SUSPEND_MAX_IT 500 | |
31 | ||
508849ad LW |
32 | /* Hardware requirement on LCLA alignment */ |
33 | #define LCLA_ALIGNMENT 0x40000 | |
698e4732 JA |
34 | |
35 | /* Max number of links per event group */ | |
36 | #define D40_LCLA_LINK_PER_EVENT_GRP 128 | |
37 | #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP | |
38 | ||
508849ad LW |
39 | /* Attempts before giving up to trying to get pages that are aligned */ |
40 | #define MAX_LCLA_ALLOC_ATTEMPTS 256 | |
41 | ||
42 | /* Bit markings for allocation map */ | |
8d318a50 LW |
43 | #define D40_ALLOC_FREE (1 << 31) |
44 | #define D40_ALLOC_PHY (1 << 30) | |
45 | #define D40_ALLOC_LOG_FREE 0 | |
46 | ||
8d318a50 | 47 | /* Hardware designer of the block */ |
3ae0267f | 48 | #define D40_HW_DESIGNER 0x8 |
8d318a50 LW |
49 | |
50 | /** | |
51 | * enum 40_command - The different commands and/or statuses. | |
52 | * | |
53 | * @D40_DMA_STOP: DMA channel command STOP or status STOPPED, | |
54 | * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN. | |
55 | * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible. | |
56 | * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED. | |
57 | */ | |
58 | enum d40_command { | |
59 | D40_DMA_STOP = 0, | |
60 | D40_DMA_RUN = 1, | |
61 | D40_DMA_SUSPEND_REQ = 2, | |
62 | D40_DMA_SUSPENDED = 3 | |
63 | }; | |
64 | ||
65 | /** | |
66 | * struct d40_lli_pool - Structure for keeping LLIs in memory | |
67 | * | |
68 | * @base: Pointer to memory area when the pre_alloc_lli's are not large | |
69 | * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if | |
70 | * pre_alloc_lli is used. | |
b00f938c | 71 | * @dma_addr: DMA address, if mapped |
8d318a50 LW |
72 | * @size: The size in bytes of the memory at base or the size of pre_alloc_lli. |
73 | * @pre_alloc_lli: Pre allocated area for the most common case of transfers, | |
74 | * one buffer to one buffer. | |
75 | */ | |
76 | struct d40_lli_pool { | |
77 | void *base; | |
508849ad | 78 | int size; |
b00f938c | 79 | dma_addr_t dma_addr; |
8d318a50 | 80 | /* Space for dst and src, plus an extra for padding */ |
508849ad | 81 | u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)]; |
8d318a50 LW |
82 | }; |
83 | ||
84 | /** | |
85 | * struct d40_desc - A descriptor is one DMA job. | |
86 | * | |
87 | * @lli_phy: LLI settings for physical channel. Both src and dst= | |
88 | * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if | |
89 | * lli_len equals one. | |
90 | * @lli_log: Same as above but for logical channels. | |
91 | * @lli_pool: The pool with two entries pre-allocated. | |
941b77a3 | 92 | * @lli_len: Number of llis of current descriptor. |
698e4732 JA |
93 | * @lli_current: Number of transfered llis. |
94 | * @lcla_alloc: Number of LCLA entries allocated. | |
8d318a50 LW |
95 | * @txd: DMA engine struct. Used for among other things for communication |
96 | * during a transfer. | |
97 | * @node: List entry. | |
8d318a50 | 98 | * @is_in_client_list: true if the client owns this descriptor. |
aa182ae2 | 99 | * the previous one. |
8d318a50 LW |
100 | * |
101 | * This descriptor is used for both logical and physical transfers. | |
102 | */ | |
8d318a50 LW |
103 | struct d40_desc { |
104 | /* LLI physical */ | |
105 | struct d40_phy_lli_bidir lli_phy; | |
106 | /* LLI logical */ | |
107 | struct d40_log_lli_bidir lli_log; | |
108 | ||
109 | struct d40_lli_pool lli_pool; | |
941b77a3 | 110 | int lli_len; |
698e4732 JA |
111 | int lli_current; |
112 | int lcla_alloc; | |
8d318a50 LW |
113 | |
114 | struct dma_async_tx_descriptor txd; | |
115 | struct list_head node; | |
116 | ||
8d318a50 LW |
117 | bool is_in_client_list; |
118 | }; | |
119 | ||
120 | /** | |
121 | * struct d40_lcla_pool - LCLA pool settings and data. | |
122 | * | |
508849ad LW |
123 | * @base: The virtual address of LCLA. 18 bit aligned. |
124 | * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used. | |
125 | * This pointer is only there for clean-up on error. | |
126 | * @pages: The number of pages needed for all physical channels. | |
127 | * Only used later for clean-up on error | |
8d318a50 | 128 | * @lock: Lock to protect the content in this struct. |
698e4732 | 129 | * @alloc_map: big map over which LCLA entry is own by which job. |
8d318a50 LW |
130 | */ |
131 | struct d40_lcla_pool { | |
132 | void *base; | |
026cbc42 | 133 | dma_addr_t dma_addr; |
508849ad LW |
134 | void *base_unaligned; |
135 | int pages; | |
8d318a50 | 136 | spinlock_t lock; |
698e4732 | 137 | struct d40_desc **alloc_map; |
8d318a50 LW |
138 | }; |
139 | ||
140 | /** | |
141 | * struct d40_phy_res - struct for handling eventlines mapped to physical | |
142 | * channels. | |
143 | * | |
144 | * @lock: A lock protection this entity. | |
145 | * @num: The physical channel number of this entity. | |
146 | * @allocated_src: Bit mapped to show which src event line's are mapped to | |
147 | * this physical channel. Can also be free or physically allocated. | |
148 | * @allocated_dst: Same as for src but is dst. | |
149 | * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as | |
767a9675 | 150 | * event line number. |
8d318a50 LW |
151 | */ |
152 | struct d40_phy_res { | |
153 | spinlock_t lock; | |
154 | int num; | |
155 | u32 allocated_src; | |
156 | u32 allocated_dst; | |
157 | }; | |
158 | ||
159 | struct d40_base; | |
160 | ||
161 | /** | |
162 | * struct d40_chan - Struct that describes a channel. | |
163 | * | |
164 | * @lock: A spinlock to protect this struct. | |
165 | * @log_num: The logical number, if any of this channel. | |
166 | * @completed: Starts with 1, after first interrupt it is set to dma engine's | |
167 | * current cookie. | |
168 | * @pending_tx: The number of pending transfers. Used between interrupt handler | |
169 | * and tasklet. | |
170 | * @busy: Set to true when transfer is ongoing on this channel. | |
2a614340 JA |
171 | * @phy_chan: Pointer to physical channel which this instance runs on. If this |
172 | * point is NULL, then the channel is not allocated. | |
8d318a50 LW |
173 | * @chan: DMA engine handle. |
174 | * @tasklet: Tasklet that gets scheduled from interrupt context to complete a | |
175 | * transfer and call client callback. | |
176 | * @client: Cliented owned descriptor list. | |
177 | * @active: Active descriptor. | |
178 | * @queue: Queued jobs. | |
8d318a50 | 179 | * @dma_cfg: The client configuration of this dma channel. |
ce2ca125 | 180 | * @configured: whether the dma_cfg configuration is valid |
8d318a50 LW |
181 | * @base: Pointer to the device instance struct. |
182 | * @src_def_cfg: Default cfg register setting for src. | |
183 | * @dst_def_cfg: Default cfg register setting for dst. | |
184 | * @log_def: Default logical channel settings. | |
185 | * @lcla: Space for one dst src pair for logical channel transfers. | |
186 | * @lcpa: Pointer to dst and src lcpa settings. | |
187 | * | |
188 | * This struct can either "be" a logical or a physical channel. | |
189 | */ | |
190 | struct d40_chan { | |
191 | spinlock_t lock; | |
192 | int log_num; | |
193 | /* ID of the most recent completed transfer */ | |
194 | int completed; | |
195 | int pending_tx; | |
196 | bool busy; | |
197 | struct d40_phy_res *phy_chan; | |
198 | struct dma_chan chan; | |
199 | struct tasklet_struct tasklet; | |
200 | struct list_head client; | |
201 | struct list_head active; | |
202 | struct list_head queue; | |
8d318a50 | 203 | struct stedma40_chan_cfg dma_cfg; |
ce2ca125 | 204 | bool configured; |
8d318a50 LW |
205 | struct d40_base *base; |
206 | /* Default register configurations */ | |
207 | u32 src_def_cfg; | |
208 | u32 dst_def_cfg; | |
209 | struct d40_def_lcsp log_def; | |
8d318a50 | 210 | struct d40_log_lli_full *lcpa; |
95e1400f LW |
211 | /* Runtime reconfiguration */ |
212 | dma_addr_t runtime_addr; | |
213 | enum dma_data_direction runtime_direction; | |
8d318a50 LW |
214 | }; |
215 | ||
216 | /** | |
217 | * struct d40_base - The big global struct, one for each probe'd instance. | |
218 | * | |
219 | * @interrupt_lock: Lock used to make sure one interrupt is handle a time. | |
220 | * @execmd_lock: Lock for execute command usage since several channels share | |
221 | * the same physical register. | |
222 | * @dev: The device structure. | |
223 | * @virtbase: The virtual base address of the DMA's register. | |
f4185592 | 224 | * @rev: silicon revision detected. |
8d318a50 LW |
225 | * @clk: Pointer to the DMA clock structure. |
226 | * @phy_start: Physical memory start of the DMA registers. | |
227 | * @phy_size: Size of the DMA register map. | |
228 | * @irq: The IRQ number. | |
229 | * @num_phy_chans: The number of physical channels. Read from HW. This | |
230 | * is the number of available channels for this driver, not counting "Secure | |
231 | * mode" allocated physical channels. | |
232 | * @num_log_chans: The number of logical channels. Calculated from | |
233 | * num_phy_chans. | |
234 | * @dma_both: dma_device channels that can do both memcpy and slave transfers. | |
235 | * @dma_slave: dma_device channels that can do only do slave transfers. | |
236 | * @dma_memcpy: dma_device channels that can do only do memcpy transfers. | |
8d318a50 LW |
237 | * @log_chans: Room for all possible logical channels in system. |
238 | * @lookup_log_chans: Used to map interrupt number to logical channel. Points | |
239 | * to log_chans entries. | |
240 | * @lookup_phy_chans: Used to map interrupt number to physical channel. Points | |
241 | * to phy_chans entries. | |
242 | * @plat_data: Pointer to provided platform_data which is the driver | |
243 | * configuration. | |
244 | * @phy_res: Vector containing all physical channels. | |
245 | * @lcla_pool: lcla pool settings and data. | |
246 | * @lcpa_base: The virtual mapped address of LCPA. | |
247 | * @phy_lcpa: The physical address of the LCPA. | |
248 | * @lcpa_size: The size of the LCPA area. | |
c675b1b4 | 249 | * @desc_slab: cache for descriptors. |
8d318a50 LW |
250 | */ |
251 | struct d40_base { | |
252 | spinlock_t interrupt_lock; | |
253 | spinlock_t execmd_lock; | |
254 | struct device *dev; | |
255 | void __iomem *virtbase; | |
f4185592 | 256 | u8 rev:4; |
8d318a50 LW |
257 | struct clk *clk; |
258 | phys_addr_t phy_start; | |
259 | resource_size_t phy_size; | |
260 | int irq; | |
261 | int num_phy_chans; | |
262 | int num_log_chans; | |
263 | struct dma_device dma_both; | |
264 | struct dma_device dma_slave; | |
265 | struct dma_device dma_memcpy; | |
266 | struct d40_chan *phy_chans; | |
267 | struct d40_chan *log_chans; | |
268 | struct d40_chan **lookup_log_chans; | |
269 | struct d40_chan **lookup_phy_chans; | |
270 | struct stedma40_platform_data *plat_data; | |
271 | /* Physical half channels */ | |
272 | struct d40_phy_res *phy_res; | |
273 | struct d40_lcla_pool lcla_pool; | |
274 | void *lcpa_base; | |
275 | dma_addr_t phy_lcpa; | |
276 | resource_size_t lcpa_size; | |
c675b1b4 | 277 | struct kmem_cache *desc_slab; |
8d318a50 LW |
278 | }; |
279 | ||
280 | /** | |
281 | * struct d40_interrupt_lookup - lookup table for interrupt handler | |
282 | * | |
283 | * @src: Interrupt mask register. | |
284 | * @clr: Interrupt clear register. | |
285 | * @is_error: true if this is an error interrupt. | |
286 | * @offset: start delta in the lookup_log_chans in d40_base. If equals to | |
287 | * D40_PHY_CHAN, the lookup_phy_chans shall be used instead. | |
288 | */ | |
289 | struct d40_interrupt_lookup { | |
290 | u32 src; | |
291 | u32 clr; | |
292 | bool is_error; | |
293 | int offset; | |
294 | }; | |
295 | ||
296 | /** | |
297 | * struct d40_reg_val - simple lookup struct | |
298 | * | |
299 | * @reg: The register. | |
300 | * @val: The value that belongs to the register in reg. | |
301 | */ | |
302 | struct d40_reg_val { | |
303 | unsigned int reg; | |
304 | unsigned int val; | |
305 | }; | |
306 | ||
262d2915 RV |
307 | static struct device *chan2dev(struct d40_chan *d40c) |
308 | { | |
309 | return &d40c->chan.dev->device; | |
310 | } | |
311 | ||
724a8577 RV |
312 | static bool chan_is_physical(struct d40_chan *chan) |
313 | { | |
314 | return chan->log_num == D40_PHY_CHAN; | |
315 | } | |
316 | ||
317 | static bool chan_is_logical(struct d40_chan *chan) | |
318 | { | |
319 | return !chan_is_physical(chan); | |
320 | } | |
321 | ||
8ca84687 RV |
322 | static void __iomem *chan_base(struct d40_chan *chan) |
323 | { | |
324 | return chan->base->virtbase + D40_DREG_PCBASE + | |
325 | chan->phy_chan->num * D40_DREG_PCDELTA; | |
326 | } | |
327 | ||
6db5a8ba RV |
328 | #define d40_err(dev, format, arg...) \ |
329 | dev_err(dev, "[%s] " format, __func__, ## arg) | |
330 | ||
331 | #define chan_err(d40c, format, arg...) \ | |
332 | d40_err(chan2dev(d40c), format, ## arg) | |
333 | ||
b00f938c | 334 | static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d, |
dbd88788 | 335 | int lli_len) |
8d318a50 | 336 | { |
dbd88788 | 337 | bool is_log = chan_is_logical(d40c); |
8d318a50 LW |
338 | u32 align; |
339 | void *base; | |
340 | ||
341 | if (is_log) | |
342 | align = sizeof(struct d40_log_lli); | |
343 | else | |
344 | align = sizeof(struct d40_phy_lli); | |
345 | ||
346 | if (lli_len == 1) { | |
347 | base = d40d->lli_pool.pre_alloc_lli; | |
348 | d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli); | |
349 | d40d->lli_pool.base = NULL; | |
350 | } else { | |
594ece4d | 351 | d40d->lli_pool.size = lli_len * 2 * align; |
8d318a50 LW |
352 | |
353 | base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT); | |
354 | d40d->lli_pool.base = base; | |
355 | ||
356 | if (d40d->lli_pool.base == NULL) | |
357 | return -ENOMEM; | |
358 | } | |
359 | ||
360 | if (is_log) { | |
d924abad | 361 | d40d->lli_log.src = PTR_ALIGN(base, align); |
594ece4d | 362 | d40d->lli_log.dst = d40d->lli_log.src + lli_len; |
b00f938c RV |
363 | |
364 | d40d->lli_pool.dma_addr = 0; | |
8d318a50 | 365 | } else { |
d924abad | 366 | d40d->lli_phy.src = PTR_ALIGN(base, align); |
594ece4d | 367 | d40d->lli_phy.dst = d40d->lli_phy.src + lli_len; |
b00f938c RV |
368 | |
369 | d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev, | |
370 | d40d->lli_phy.src, | |
371 | d40d->lli_pool.size, | |
372 | DMA_TO_DEVICE); | |
373 | ||
374 | if (dma_mapping_error(d40c->base->dev, | |
375 | d40d->lli_pool.dma_addr)) { | |
376 | kfree(d40d->lli_pool.base); | |
377 | d40d->lli_pool.base = NULL; | |
378 | d40d->lli_pool.dma_addr = 0; | |
379 | return -ENOMEM; | |
380 | } | |
8d318a50 LW |
381 | } |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
b00f938c | 386 | static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d) |
8d318a50 | 387 | { |
b00f938c RV |
388 | if (d40d->lli_pool.dma_addr) |
389 | dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr, | |
390 | d40d->lli_pool.size, DMA_TO_DEVICE); | |
391 | ||
8d318a50 LW |
392 | kfree(d40d->lli_pool.base); |
393 | d40d->lli_pool.base = NULL; | |
394 | d40d->lli_pool.size = 0; | |
395 | d40d->lli_log.src = NULL; | |
396 | d40d->lli_log.dst = NULL; | |
397 | d40d->lli_phy.src = NULL; | |
398 | d40d->lli_phy.dst = NULL; | |
8d318a50 LW |
399 | } |
400 | ||
698e4732 JA |
401 | static int d40_lcla_alloc_one(struct d40_chan *d40c, |
402 | struct d40_desc *d40d) | |
403 | { | |
404 | unsigned long flags; | |
405 | int i; | |
406 | int ret = -EINVAL; | |
407 | int p; | |
408 | ||
409 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); | |
410 | ||
411 | p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP; | |
412 | ||
413 | /* | |
414 | * Allocate both src and dst at the same time, therefore the half | |
415 | * start on 1 since 0 can't be used since zero is used as end marker. | |
416 | */ | |
417 | for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { | |
418 | if (!d40c->base->lcla_pool.alloc_map[p + i]) { | |
419 | d40c->base->lcla_pool.alloc_map[p + i] = d40d; | |
420 | d40d->lcla_alloc++; | |
421 | ret = i; | |
422 | break; | |
423 | } | |
424 | } | |
425 | ||
426 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); | |
427 | ||
428 | return ret; | |
429 | } | |
430 | ||
431 | static int d40_lcla_free_all(struct d40_chan *d40c, | |
432 | struct d40_desc *d40d) | |
433 | { | |
434 | unsigned long flags; | |
435 | int i; | |
436 | int ret = -EINVAL; | |
437 | ||
724a8577 | 438 | if (chan_is_physical(d40c)) |
698e4732 JA |
439 | return 0; |
440 | ||
441 | spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags); | |
442 | ||
443 | for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) { | |
444 | if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num * | |
445 | D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) { | |
446 | d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num * | |
447 | D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL; | |
448 | d40d->lcla_alloc--; | |
449 | if (d40d->lcla_alloc == 0) { | |
450 | ret = 0; | |
451 | break; | |
452 | } | |
453 | } | |
454 | } | |
455 | ||
456 | spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags); | |
457 | ||
458 | return ret; | |
459 | ||
460 | } | |
461 | ||
8d318a50 LW |
462 | static void d40_desc_remove(struct d40_desc *d40d) |
463 | { | |
464 | list_del(&d40d->node); | |
465 | } | |
466 | ||
467 | static struct d40_desc *d40_desc_get(struct d40_chan *d40c) | |
468 | { | |
a2c15fa4 | 469 | struct d40_desc *desc = NULL; |
8d318a50 LW |
470 | |
471 | if (!list_empty(&d40c->client)) { | |
a2c15fa4 RV |
472 | struct d40_desc *d; |
473 | struct d40_desc *_d; | |
474 | ||
8d318a50 LW |
475 | list_for_each_entry_safe(d, _d, &d40c->client, node) |
476 | if (async_tx_test_ack(&d->txd)) { | |
b00f938c | 477 | d40_pool_lli_free(d40c, d); |
8d318a50 | 478 | d40_desc_remove(d); |
a2c15fa4 RV |
479 | desc = d; |
480 | memset(desc, 0, sizeof(*desc)); | |
c675b1b4 | 481 | break; |
8d318a50 | 482 | } |
8d318a50 | 483 | } |
a2c15fa4 RV |
484 | |
485 | if (!desc) | |
486 | desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT); | |
487 | ||
488 | if (desc) | |
489 | INIT_LIST_HEAD(&desc->node); | |
490 | ||
491 | return desc; | |
8d318a50 LW |
492 | } |
493 | ||
494 | static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d) | |
495 | { | |
698e4732 | 496 | |
b00f938c | 497 | d40_pool_lli_free(d40c, d40d); |
698e4732 | 498 | d40_lcla_free_all(d40c, d40d); |
c675b1b4 | 499 | kmem_cache_free(d40c->base->desc_slab, d40d); |
8d318a50 LW |
500 | } |
501 | ||
502 | static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc) | |
503 | { | |
504 | list_add_tail(&desc->node, &d40c->active); | |
505 | } | |
506 | ||
1c4b0927 RV |
507 | static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc) |
508 | { | |
509 | struct d40_phy_lli *lli_dst = desc->lli_phy.dst; | |
510 | struct d40_phy_lli *lli_src = desc->lli_phy.src; | |
511 | void __iomem *base = chan_base(chan); | |
512 | ||
513 | writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG); | |
514 | writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT); | |
515 | writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR); | |
516 | writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK); | |
517 | ||
518 | writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG); | |
519 | writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT); | |
520 | writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR); | |
521 | writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK); | |
522 | } | |
523 | ||
e65889c7 | 524 | static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc) |
698e4732 | 525 | { |
e65889c7 RV |
526 | struct d40_lcla_pool *pool = &chan->base->lcla_pool; |
527 | struct d40_log_lli_bidir *lli = &desc->lli_log; | |
528 | int lli_current = desc->lli_current; | |
529 | int lli_len = desc->lli_len; | |
530 | int curr_lcla = -EINVAL; | |
531 | ||
532 | if (lli_len - lli_current > 1) | |
533 | curr_lcla = d40_lcla_alloc_one(chan, desc); | |
534 | ||
535 | d40_log_lli_lcpa_write(chan->lcpa, | |
536 | &lli->dst[lli_current], | |
537 | &lli->src[lli_current], | |
538 | curr_lcla); | |
539 | ||
540 | lli_current++; | |
6045f0bb RV |
541 | |
542 | if (curr_lcla < 0) | |
543 | goto out; | |
544 | ||
e65889c7 RV |
545 | for (; lli_current < lli_len; lli_current++) { |
546 | unsigned int lcla_offset = chan->phy_chan->num * 1024 + | |
547 | 8 * curr_lcla * 2; | |
548 | struct d40_log_lli *lcla = pool->base + lcla_offset; | |
549 | int next_lcla; | |
550 | ||
551 | if (lli_current + 1 < lli_len) | |
552 | next_lcla = d40_lcla_alloc_one(chan, desc); | |
553 | else | |
554 | next_lcla = -EINVAL; | |
555 | ||
556 | d40_log_lli_lcla_write(lcla, | |
557 | &lli->dst[lli_current], | |
558 | &lli->src[lli_current], | |
559 | next_lcla); | |
560 | ||
561 | dma_sync_single_range_for_device(chan->base->dev, | |
562 | pool->dma_addr, lcla_offset, | |
563 | 2 * sizeof(struct d40_log_lli), | |
564 | DMA_TO_DEVICE); | |
565 | ||
566 | curr_lcla = next_lcla; | |
567 | ||
568 | if (curr_lcla == -EINVAL) { | |
569 | lli_current++; | |
570 | break; | |
571 | } | |
572 | } | |
573 | ||
6045f0bb | 574 | out: |
e65889c7 RV |
575 | desc->lli_current = lli_current; |
576 | } | |
698e4732 | 577 | |
e65889c7 RV |
578 | static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d) |
579 | { | |
724a8577 | 580 | if (chan_is_physical(d40c)) { |
1c4b0927 | 581 | d40_phy_lli_load(d40c, d40d); |
698e4732 | 582 | d40d->lli_current = d40d->lli_len; |
e65889c7 RV |
583 | } else |
584 | d40_log_lli_to_lcxa(d40c, d40d); | |
698e4732 JA |
585 | } |
586 | ||
8d318a50 LW |
587 | static struct d40_desc *d40_first_active_get(struct d40_chan *d40c) |
588 | { | |
589 | struct d40_desc *d; | |
590 | ||
591 | if (list_empty(&d40c->active)) | |
592 | return NULL; | |
593 | ||
594 | d = list_first_entry(&d40c->active, | |
595 | struct d40_desc, | |
596 | node); | |
597 | return d; | |
598 | } | |
599 | ||
600 | static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc) | |
601 | { | |
602 | list_add_tail(&desc->node, &d40c->queue); | |
603 | } | |
604 | ||
605 | static struct d40_desc *d40_first_queued(struct d40_chan *d40c) | |
606 | { | |
607 | struct d40_desc *d; | |
608 | ||
609 | if (list_empty(&d40c->queue)) | |
610 | return NULL; | |
611 | ||
612 | d = list_first_entry(&d40c->queue, | |
613 | struct d40_desc, | |
614 | node); | |
615 | return d; | |
616 | } | |
617 | ||
d49278e3 PF |
618 | static int d40_psize_2_burst_size(bool is_log, int psize) |
619 | { | |
620 | if (is_log) { | |
621 | if (psize == STEDMA40_PSIZE_LOG_1) | |
622 | return 1; | |
623 | } else { | |
624 | if (psize == STEDMA40_PSIZE_PHY_1) | |
625 | return 1; | |
626 | } | |
627 | ||
628 | return 2 << psize; | |
629 | } | |
630 | ||
631 | /* | |
632 | * The dma only supports transmitting packages up to | |
633 | * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of | |
634 | * dma elements required to send the entire sg list | |
635 | */ | |
636 | static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2) | |
637 | { | |
638 | int dmalen; | |
639 | u32 max_w = max(data_width1, data_width2); | |
640 | u32 min_w = min(data_width1, data_width2); | |
641 | u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w); | |
642 | ||
643 | if (seg_max > STEDMA40_MAX_SEG_SIZE) | |
644 | seg_max -= (1 << max_w); | |
645 | ||
646 | if (!IS_ALIGNED(size, 1 << max_w)) | |
647 | return -EINVAL; | |
648 | ||
649 | if (size <= seg_max) | |
650 | dmalen = 1; | |
651 | else { | |
652 | dmalen = size / seg_max; | |
653 | if (dmalen * seg_max < size) | |
654 | dmalen++; | |
655 | } | |
656 | return dmalen; | |
657 | } | |
658 | ||
659 | static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len, | |
660 | u32 data_width1, u32 data_width2) | |
661 | { | |
662 | struct scatterlist *sg; | |
663 | int i; | |
664 | int len = 0; | |
665 | int ret; | |
666 | ||
667 | for_each_sg(sgl, sg, sg_len, i) { | |
668 | ret = d40_size_2_dmalen(sg_dma_len(sg), | |
669 | data_width1, data_width2); | |
670 | if (ret < 0) | |
671 | return ret; | |
672 | len += ret; | |
673 | } | |
674 | return len; | |
675 | } | |
8d318a50 | 676 | |
d49278e3 | 677 | /* Support functions for logical channels */ |
8d318a50 LW |
678 | |
679 | static int d40_channel_execute_command(struct d40_chan *d40c, | |
680 | enum d40_command command) | |
681 | { | |
767a9675 JA |
682 | u32 status; |
683 | int i; | |
8d318a50 LW |
684 | void __iomem *active_reg; |
685 | int ret = 0; | |
686 | unsigned long flags; | |
1d392a7b | 687 | u32 wmask; |
8d318a50 LW |
688 | |
689 | spin_lock_irqsave(&d40c->base->execmd_lock, flags); | |
690 | ||
691 | if (d40c->phy_chan->num % 2 == 0) | |
692 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; | |
693 | else | |
694 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; | |
695 | ||
696 | if (command == D40_DMA_SUSPEND_REQ) { | |
697 | status = (readl(active_reg) & | |
698 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
699 | D40_CHAN_POS(d40c->phy_chan->num); | |
700 | ||
701 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) | |
702 | goto done; | |
703 | } | |
704 | ||
1d392a7b JA |
705 | wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num)); |
706 | writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)), | |
707 | active_reg); | |
8d318a50 LW |
708 | |
709 | if (command == D40_DMA_SUSPEND_REQ) { | |
710 | ||
711 | for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) { | |
712 | status = (readl(active_reg) & | |
713 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
714 | D40_CHAN_POS(d40c->phy_chan->num); | |
715 | ||
716 | cpu_relax(); | |
717 | /* | |
718 | * Reduce the number of bus accesses while | |
719 | * waiting for the DMA to suspend. | |
720 | */ | |
721 | udelay(3); | |
722 | ||
723 | if (status == D40_DMA_STOP || | |
724 | status == D40_DMA_SUSPENDED) | |
725 | break; | |
726 | } | |
727 | ||
728 | if (i == D40_SUSPEND_MAX_IT) { | |
6db5a8ba RV |
729 | chan_err(d40c, |
730 | "unable to suspend the chl %d (log: %d) status %x\n", | |
731 | d40c->phy_chan->num, d40c->log_num, | |
8d318a50 LW |
732 | status); |
733 | dump_stack(); | |
734 | ret = -EBUSY; | |
735 | } | |
736 | ||
737 | } | |
738 | done: | |
739 | spin_unlock_irqrestore(&d40c->base->execmd_lock, flags); | |
740 | return ret; | |
741 | } | |
742 | ||
743 | static void d40_term_all(struct d40_chan *d40c) | |
744 | { | |
745 | struct d40_desc *d40d; | |
8d318a50 LW |
746 | |
747 | /* Release active descriptors */ | |
748 | while ((d40d = d40_first_active_get(d40c))) { | |
749 | d40_desc_remove(d40d); | |
8d318a50 LW |
750 | d40_desc_free(d40c, d40d); |
751 | } | |
752 | ||
753 | /* Release queued descriptors waiting for transfer */ | |
754 | while ((d40d = d40_first_queued(d40c))) { | |
755 | d40_desc_remove(d40d); | |
8d318a50 LW |
756 | d40_desc_free(d40c, d40d); |
757 | } | |
758 | ||
8d318a50 LW |
759 | |
760 | d40c->pending_tx = 0; | |
761 | d40c->busy = false; | |
762 | } | |
763 | ||
262d2915 RV |
764 | static void __d40_config_set_event(struct d40_chan *d40c, bool enable, |
765 | u32 event, int reg) | |
766 | { | |
8ca84687 | 767 | void __iomem *addr = chan_base(d40c) + reg; |
262d2915 RV |
768 | int tries; |
769 | ||
770 | if (!enable) { | |
771 | writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event)) | |
772 | | ~D40_EVENTLINE_MASK(event), addr); | |
773 | return; | |
774 | } | |
775 | ||
776 | /* | |
777 | * The hardware sometimes doesn't register the enable when src and dst | |
778 | * event lines are active on the same logical channel. Retry to ensure | |
779 | * it does. Usually only one retry is sufficient. | |
780 | */ | |
781 | tries = 100; | |
782 | while (--tries) { | |
783 | writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event)) | |
784 | | ~D40_EVENTLINE_MASK(event), addr); | |
785 | ||
786 | if (readl(addr) & D40_EVENTLINE_MASK(event)) | |
787 | break; | |
788 | } | |
789 | ||
790 | if (tries != 99) | |
791 | dev_dbg(chan2dev(d40c), | |
792 | "[%s] workaround enable S%cLNK (%d tries)\n", | |
793 | __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D', | |
794 | 100 - tries); | |
795 | ||
796 | WARN_ON(!tries); | |
797 | } | |
798 | ||
8d318a50 LW |
799 | static void d40_config_set_event(struct d40_chan *d40c, bool do_enable) |
800 | { | |
8d318a50 LW |
801 | unsigned long flags; |
802 | ||
8d318a50 LW |
803 | spin_lock_irqsave(&d40c->phy_chan->lock, flags); |
804 | ||
805 | /* Enable event line connected to device (or memcpy) */ | |
806 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || | |
807 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) { | |
808 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); | |
809 | ||
262d2915 RV |
810 | __d40_config_set_event(d40c, do_enable, event, |
811 | D40_CHAN_REG_SSLNK); | |
8d318a50 | 812 | } |
262d2915 | 813 | |
8d318a50 LW |
814 | if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) { |
815 | u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); | |
816 | ||
262d2915 RV |
817 | __d40_config_set_event(d40c, do_enable, event, |
818 | D40_CHAN_REG_SDLNK); | |
8d318a50 LW |
819 | } |
820 | ||
821 | spin_unlock_irqrestore(&d40c->phy_chan->lock, flags); | |
822 | } | |
823 | ||
a5ebca47 | 824 | static u32 d40_chan_has_events(struct d40_chan *d40c) |
8d318a50 | 825 | { |
8ca84687 | 826 | void __iomem *chanbase = chan_base(d40c); |
be8cb7df | 827 | u32 val; |
8d318a50 | 828 | |
8ca84687 RV |
829 | val = readl(chanbase + D40_CHAN_REG_SSLNK); |
830 | val |= readl(chanbase + D40_CHAN_REG_SDLNK); | |
be8cb7df | 831 | |
a5ebca47 | 832 | return val; |
8d318a50 LW |
833 | } |
834 | ||
20a5b6d0 RV |
835 | static u32 d40_get_prmo(struct d40_chan *d40c) |
836 | { | |
837 | static const unsigned int phy_map[] = { | |
838 | [STEDMA40_PCHAN_BASIC_MODE] | |
839 | = D40_DREG_PRMO_PCHAN_BASIC, | |
840 | [STEDMA40_PCHAN_MODULO_MODE] | |
841 | = D40_DREG_PRMO_PCHAN_MODULO, | |
842 | [STEDMA40_PCHAN_DOUBLE_DST_MODE] | |
843 | = D40_DREG_PRMO_PCHAN_DOUBLE_DST, | |
844 | }; | |
845 | static const unsigned int log_map[] = { | |
846 | [STEDMA40_LCHAN_SRC_PHY_DST_LOG] | |
847 | = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG, | |
848 | [STEDMA40_LCHAN_SRC_LOG_DST_PHY] | |
849 | = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY, | |
850 | [STEDMA40_LCHAN_SRC_LOG_DST_LOG] | |
851 | = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG, | |
852 | }; | |
853 | ||
724a8577 | 854 | if (chan_is_physical(d40c)) |
20a5b6d0 RV |
855 | return phy_map[d40c->dma_cfg.mode_opt]; |
856 | else | |
857 | return log_map[d40c->dma_cfg.mode_opt]; | |
858 | } | |
859 | ||
b55912c6 | 860 | static void d40_config_write(struct d40_chan *d40c) |
8d318a50 LW |
861 | { |
862 | u32 addr_base; | |
863 | u32 var; | |
8d318a50 LW |
864 | |
865 | /* Odd addresses are even addresses + 4 */ | |
866 | addr_base = (d40c->phy_chan->num % 2) * 4; | |
867 | /* Setup channel mode to logical or physical */ | |
724a8577 | 868 | var = ((u32)(chan_is_logical(d40c)) + 1) << |
8d318a50 LW |
869 | D40_CHAN_POS(d40c->phy_chan->num); |
870 | writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base); | |
871 | ||
872 | /* Setup operational mode option register */ | |
20a5b6d0 | 873 | var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num); |
8d318a50 LW |
874 | |
875 | writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base); | |
876 | ||
724a8577 | 877 | if (chan_is_logical(d40c)) { |
8ca84687 RV |
878 | int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) |
879 | & D40_SREG_ELEM_LOG_LIDX_MASK; | |
880 | void __iomem *chanbase = chan_base(d40c); | |
881 | ||
8d318a50 | 882 | /* Set default config for CFG reg */ |
8ca84687 RV |
883 | writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG); |
884 | writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG); | |
8d318a50 | 885 | |
b55912c6 | 886 | /* Set LIDX for lcla */ |
8ca84687 RV |
887 | writel(lidx, chanbase + D40_CHAN_REG_SSELT); |
888 | writel(lidx, chanbase + D40_CHAN_REG_SDELT); | |
8d318a50 | 889 | } |
8d318a50 LW |
890 | } |
891 | ||
aa182ae2 JA |
892 | static u32 d40_residue(struct d40_chan *d40c) |
893 | { | |
894 | u32 num_elt; | |
895 | ||
724a8577 | 896 | if (chan_is_logical(d40c)) |
aa182ae2 JA |
897 | num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK) |
898 | >> D40_MEM_LCSP2_ECNT_POS; | |
8ca84687 RV |
899 | else { |
900 | u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT); | |
901 | num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK) | |
902 | >> D40_SREG_ELEM_PHY_ECNT_POS; | |
903 | } | |
904 | ||
aa182ae2 JA |
905 | return num_elt * (1 << d40c->dma_cfg.dst_info.data_width); |
906 | } | |
907 | ||
908 | static bool d40_tx_is_linked(struct d40_chan *d40c) | |
909 | { | |
910 | bool is_link; | |
911 | ||
724a8577 | 912 | if (chan_is_logical(d40c)) |
aa182ae2 JA |
913 | is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK; |
914 | else | |
8ca84687 RV |
915 | is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK) |
916 | & D40_SREG_LNK_PHYS_LNK_MASK; | |
917 | ||
aa182ae2 JA |
918 | return is_link; |
919 | } | |
920 | ||
921 | static int d40_pause(struct dma_chan *chan) | |
922 | { | |
923 | struct d40_chan *d40c = | |
924 | container_of(chan, struct d40_chan, chan); | |
925 | int res = 0; | |
926 | unsigned long flags; | |
927 | ||
3ac012af JA |
928 | if (!d40c->busy) |
929 | return 0; | |
930 | ||
aa182ae2 JA |
931 | spin_lock_irqsave(&d40c->lock, flags); |
932 | ||
933 | res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); | |
934 | if (res == 0) { | |
724a8577 | 935 | if (chan_is_logical(d40c)) { |
aa182ae2 JA |
936 | d40_config_set_event(d40c, false); |
937 | /* Resume the other logical channels if any */ | |
938 | if (d40_chan_has_events(d40c)) | |
939 | res = d40_channel_execute_command(d40c, | |
940 | D40_DMA_RUN); | |
941 | } | |
942 | } | |
943 | ||
944 | spin_unlock_irqrestore(&d40c->lock, flags); | |
945 | return res; | |
946 | } | |
947 | ||
948 | static int d40_resume(struct dma_chan *chan) | |
949 | { | |
950 | struct d40_chan *d40c = | |
951 | container_of(chan, struct d40_chan, chan); | |
952 | int res = 0; | |
953 | unsigned long flags; | |
954 | ||
3ac012af JA |
955 | if (!d40c->busy) |
956 | return 0; | |
957 | ||
aa182ae2 JA |
958 | spin_lock_irqsave(&d40c->lock, flags); |
959 | ||
960 | if (d40c->base->rev == 0) | |
724a8577 | 961 | if (chan_is_logical(d40c)) { |
aa182ae2 JA |
962 | res = d40_channel_execute_command(d40c, |
963 | D40_DMA_SUSPEND_REQ); | |
964 | goto no_suspend; | |
965 | } | |
966 | ||
967 | /* If bytes left to transfer or linked tx resume job */ | |
968 | if (d40_residue(d40c) || d40_tx_is_linked(d40c)) { | |
969 | ||
724a8577 | 970 | if (chan_is_logical(d40c)) |
aa182ae2 JA |
971 | d40_config_set_event(d40c, true); |
972 | ||
973 | res = d40_channel_execute_command(d40c, D40_DMA_RUN); | |
974 | } | |
975 | ||
976 | no_suspend: | |
977 | spin_unlock_irqrestore(&d40c->lock, flags); | |
978 | return res; | |
979 | } | |
980 | ||
8d318a50 LW |
981 | static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx) |
982 | { | |
983 | struct d40_chan *d40c = container_of(tx->chan, | |
984 | struct d40_chan, | |
985 | chan); | |
986 | struct d40_desc *d40d = container_of(tx, struct d40_desc, txd); | |
987 | unsigned long flags; | |
988 | ||
989 | spin_lock_irqsave(&d40c->lock, flags); | |
990 | ||
aa182ae2 JA |
991 | d40c->chan.cookie++; |
992 | ||
993 | if (d40c->chan.cookie < 0) | |
994 | d40c->chan.cookie = 1; | |
995 | ||
996 | d40d->txd.cookie = d40c->chan.cookie; | |
997 | ||
8d318a50 LW |
998 | d40_desc_queue(d40c, d40d); |
999 | ||
1000 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1001 | ||
1002 | return tx->cookie; | |
1003 | } | |
1004 | ||
1005 | static int d40_start(struct d40_chan *d40c) | |
1006 | { | |
f4185592 LW |
1007 | if (d40c->base->rev == 0) { |
1008 | int err; | |
1009 | ||
724a8577 | 1010 | if (chan_is_logical(d40c)) { |
f4185592 LW |
1011 | err = d40_channel_execute_command(d40c, |
1012 | D40_DMA_SUSPEND_REQ); | |
1013 | if (err) | |
1014 | return err; | |
1015 | } | |
1016 | } | |
1017 | ||
724a8577 | 1018 | if (chan_is_logical(d40c)) |
8d318a50 | 1019 | d40_config_set_event(d40c, true); |
8d318a50 | 1020 | |
0c32269d | 1021 | return d40_channel_execute_command(d40c, D40_DMA_RUN); |
8d318a50 LW |
1022 | } |
1023 | ||
1024 | static struct d40_desc *d40_queue_start(struct d40_chan *d40c) | |
1025 | { | |
1026 | struct d40_desc *d40d; | |
1027 | int err; | |
1028 | ||
1029 | /* Start queued jobs, if any */ | |
1030 | d40d = d40_first_queued(d40c); | |
1031 | ||
1032 | if (d40d != NULL) { | |
1033 | d40c->busy = true; | |
1034 | ||
1035 | /* Remove from queue */ | |
1036 | d40_desc_remove(d40d); | |
1037 | ||
1038 | /* Add to active queue */ | |
1039 | d40_desc_submit(d40c, d40d); | |
1040 | ||
7d83a854 RV |
1041 | /* Initiate DMA job */ |
1042 | d40_desc_load(d40c, d40d); | |
8d318a50 | 1043 | |
7d83a854 RV |
1044 | /* Start dma job */ |
1045 | err = d40_start(d40c); | |
8d318a50 | 1046 | |
7d83a854 RV |
1047 | if (err) |
1048 | return NULL; | |
8d318a50 LW |
1049 | } |
1050 | ||
1051 | return d40d; | |
1052 | } | |
1053 | ||
1054 | /* called from interrupt context */ | |
1055 | static void dma_tc_handle(struct d40_chan *d40c) | |
1056 | { | |
1057 | struct d40_desc *d40d; | |
1058 | ||
8d318a50 LW |
1059 | /* Get first active entry from list */ |
1060 | d40d = d40_first_active_get(d40c); | |
1061 | ||
1062 | if (d40d == NULL) | |
1063 | return; | |
1064 | ||
698e4732 | 1065 | d40_lcla_free_all(d40c, d40d); |
8d318a50 | 1066 | |
698e4732 | 1067 | if (d40d->lli_current < d40d->lli_len) { |
8d318a50 LW |
1068 | d40_desc_load(d40c, d40d); |
1069 | /* Start dma job */ | |
1070 | (void) d40_start(d40c); | |
1071 | return; | |
1072 | } | |
1073 | ||
1074 | if (d40_queue_start(d40c) == NULL) | |
1075 | d40c->busy = false; | |
1076 | ||
1077 | d40c->pending_tx++; | |
1078 | tasklet_schedule(&d40c->tasklet); | |
1079 | ||
1080 | } | |
1081 | ||
1082 | static void dma_tasklet(unsigned long data) | |
1083 | { | |
1084 | struct d40_chan *d40c = (struct d40_chan *) data; | |
767a9675 | 1085 | struct d40_desc *d40d; |
8d318a50 LW |
1086 | unsigned long flags; |
1087 | dma_async_tx_callback callback; | |
1088 | void *callback_param; | |
1089 | ||
1090 | spin_lock_irqsave(&d40c->lock, flags); | |
1091 | ||
1092 | /* Get first active entry from list */ | |
767a9675 | 1093 | d40d = d40_first_active_get(d40c); |
8d318a50 | 1094 | |
767a9675 | 1095 | if (d40d == NULL) |
8d318a50 LW |
1096 | goto err; |
1097 | ||
767a9675 | 1098 | d40c->completed = d40d->txd.cookie; |
8d318a50 LW |
1099 | |
1100 | /* | |
1101 | * If terminating a channel pending_tx is set to zero. | |
1102 | * This prevents any finished active jobs to return to the client. | |
1103 | */ | |
1104 | if (d40c->pending_tx == 0) { | |
1105 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1106 | return; | |
1107 | } | |
1108 | ||
1109 | /* Callback to client */ | |
767a9675 JA |
1110 | callback = d40d->txd.callback; |
1111 | callback_param = d40d->txd.callback_param; | |
1112 | ||
1113 | if (async_tx_test_ack(&d40d->txd)) { | |
b00f938c | 1114 | d40_pool_lli_free(d40c, d40d); |
767a9675 JA |
1115 | d40_desc_remove(d40d); |
1116 | d40_desc_free(d40c, d40d); | |
8d318a50 | 1117 | } else { |
767a9675 JA |
1118 | if (!d40d->is_in_client_list) { |
1119 | d40_desc_remove(d40d); | |
698e4732 | 1120 | d40_lcla_free_all(d40c, d40d); |
767a9675 JA |
1121 | list_add_tail(&d40d->node, &d40c->client); |
1122 | d40d->is_in_client_list = true; | |
8d318a50 LW |
1123 | } |
1124 | } | |
1125 | ||
1126 | d40c->pending_tx--; | |
1127 | ||
1128 | if (d40c->pending_tx) | |
1129 | tasklet_schedule(&d40c->tasklet); | |
1130 | ||
1131 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1132 | ||
767a9675 | 1133 | if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT)) |
8d318a50 LW |
1134 | callback(callback_param); |
1135 | ||
1136 | return; | |
1137 | ||
1138 | err: | |
1139 | /* Rescue manouver if receiving double interrupts */ | |
1140 | if (d40c->pending_tx > 0) | |
1141 | d40c->pending_tx--; | |
1142 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1143 | } | |
1144 | ||
1145 | static irqreturn_t d40_handle_interrupt(int irq, void *data) | |
1146 | { | |
1147 | static const struct d40_interrupt_lookup il[] = { | |
1148 | {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0}, | |
1149 | {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32}, | |
1150 | {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64}, | |
1151 | {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96}, | |
1152 | {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0}, | |
1153 | {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32}, | |
1154 | {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64}, | |
1155 | {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96}, | |
1156 | {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN}, | |
1157 | {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN}, | |
1158 | }; | |
1159 | ||
1160 | int i; | |
1161 | u32 regs[ARRAY_SIZE(il)]; | |
8d318a50 LW |
1162 | u32 idx; |
1163 | u32 row; | |
1164 | long chan = -1; | |
1165 | struct d40_chan *d40c; | |
1166 | unsigned long flags; | |
1167 | struct d40_base *base = data; | |
1168 | ||
1169 | spin_lock_irqsave(&base->interrupt_lock, flags); | |
1170 | ||
1171 | /* Read interrupt status of both logical and physical channels */ | |
1172 | for (i = 0; i < ARRAY_SIZE(il); i++) | |
1173 | regs[i] = readl(base->virtbase + il[i].src); | |
1174 | ||
1175 | for (;;) { | |
1176 | ||
1177 | chan = find_next_bit((unsigned long *)regs, | |
1178 | BITS_PER_LONG * ARRAY_SIZE(il), chan + 1); | |
1179 | ||
1180 | /* No more set bits found? */ | |
1181 | if (chan == BITS_PER_LONG * ARRAY_SIZE(il)) | |
1182 | break; | |
1183 | ||
1184 | row = chan / BITS_PER_LONG; | |
1185 | idx = chan & (BITS_PER_LONG - 1); | |
1186 | ||
1187 | /* ACK interrupt */ | |
1b00348d | 1188 | writel(1 << idx, base->virtbase + il[row].clr); |
8d318a50 LW |
1189 | |
1190 | if (il[row].offset == D40_PHY_CHAN) | |
1191 | d40c = base->lookup_phy_chans[idx]; | |
1192 | else | |
1193 | d40c = base->lookup_log_chans[il[row].offset + idx]; | |
1194 | spin_lock(&d40c->lock); | |
1195 | ||
1196 | if (!il[row].is_error) | |
1197 | dma_tc_handle(d40c); | |
1198 | else | |
6db5a8ba RV |
1199 | d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n", |
1200 | chan, il[row].offset, idx); | |
8d318a50 LW |
1201 | |
1202 | spin_unlock(&d40c->lock); | |
1203 | } | |
1204 | ||
1205 | spin_unlock_irqrestore(&base->interrupt_lock, flags); | |
1206 | ||
1207 | return IRQ_HANDLED; | |
1208 | } | |
1209 | ||
8d318a50 LW |
1210 | static int d40_validate_conf(struct d40_chan *d40c, |
1211 | struct stedma40_chan_cfg *conf) | |
1212 | { | |
1213 | int res = 0; | |
1214 | u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type); | |
1215 | u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type); | |
38bdbf02 | 1216 | bool is_log = conf->mode == STEDMA40_MODE_LOGICAL; |
8d318a50 | 1217 | |
0747c7ba | 1218 | if (!conf->dir) { |
6db5a8ba | 1219 | chan_err(d40c, "Invalid direction.\n"); |
0747c7ba LW |
1220 | res = -EINVAL; |
1221 | } | |
1222 | ||
1223 | if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY && | |
1224 | d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 && | |
1225 | d40c->runtime_addr == 0) { | |
1226 | ||
6db5a8ba RV |
1227 | chan_err(d40c, "Invalid TX channel address (%d)\n", |
1228 | conf->dst_dev_type); | |
0747c7ba LW |
1229 | res = -EINVAL; |
1230 | } | |
1231 | ||
1232 | if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY && | |
1233 | d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 && | |
1234 | d40c->runtime_addr == 0) { | |
6db5a8ba RV |
1235 | chan_err(d40c, "Invalid RX channel address (%d)\n", |
1236 | conf->src_dev_type); | |
0747c7ba LW |
1237 | res = -EINVAL; |
1238 | } | |
1239 | ||
1240 | if (conf->dir == STEDMA40_MEM_TO_PERIPH && | |
8d318a50 | 1241 | dst_event_group == STEDMA40_DEV_DST_MEMORY) { |
6db5a8ba | 1242 | chan_err(d40c, "Invalid dst\n"); |
8d318a50 LW |
1243 | res = -EINVAL; |
1244 | } | |
1245 | ||
0747c7ba | 1246 | if (conf->dir == STEDMA40_PERIPH_TO_MEM && |
8d318a50 | 1247 | src_event_group == STEDMA40_DEV_SRC_MEMORY) { |
6db5a8ba | 1248 | chan_err(d40c, "Invalid src\n"); |
8d318a50 LW |
1249 | res = -EINVAL; |
1250 | } | |
1251 | ||
1252 | if (src_event_group == STEDMA40_DEV_SRC_MEMORY && | |
1253 | dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) { | |
6db5a8ba | 1254 | chan_err(d40c, "No event line\n"); |
8d318a50 LW |
1255 | res = -EINVAL; |
1256 | } | |
1257 | ||
1258 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH && | |
1259 | (src_event_group != dst_event_group)) { | |
6db5a8ba | 1260 | chan_err(d40c, "Invalid event group\n"); |
8d318a50 LW |
1261 | res = -EINVAL; |
1262 | } | |
1263 | ||
1264 | if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) { | |
1265 | /* | |
1266 | * DMAC HW supports it. Will be added to this driver, | |
1267 | * in case any dma client requires it. | |
1268 | */ | |
6db5a8ba | 1269 | chan_err(d40c, "periph to periph not supported\n"); |
8d318a50 LW |
1270 | res = -EINVAL; |
1271 | } | |
1272 | ||
d49278e3 PF |
1273 | if (d40_psize_2_burst_size(is_log, conf->src_info.psize) * |
1274 | (1 << conf->src_info.data_width) != | |
1275 | d40_psize_2_burst_size(is_log, conf->dst_info.psize) * | |
1276 | (1 << conf->dst_info.data_width)) { | |
1277 | /* | |
1278 | * The DMAC hardware only supports | |
1279 | * src (burst x width) == dst (burst x width) | |
1280 | */ | |
1281 | ||
6db5a8ba | 1282 | chan_err(d40c, "src (burst x width) != dst (burst x width)\n"); |
d49278e3 PF |
1283 | res = -EINVAL; |
1284 | } | |
1285 | ||
8d318a50 LW |
1286 | return res; |
1287 | } | |
1288 | ||
1289 | static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src, | |
4aed79b2 | 1290 | int log_event_line, bool is_log) |
8d318a50 LW |
1291 | { |
1292 | unsigned long flags; | |
1293 | spin_lock_irqsave(&phy->lock, flags); | |
4aed79b2 | 1294 | if (!is_log) { |
8d318a50 LW |
1295 | /* Physical interrupts are masked per physical full channel */ |
1296 | if (phy->allocated_src == D40_ALLOC_FREE && | |
1297 | phy->allocated_dst == D40_ALLOC_FREE) { | |
1298 | phy->allocated_dst = D40_ALLOC_PHY; | |
1299 | phy->allocated_src = D40_ALLOC_PHY; | |
1300 | goto found; | |
1301 | } else | |
1302 | goto not_found; | |
1303 | } | |
1304 | ||
1305 | /* Logical channel */ | |
1306 | if (is_src) { | |
1307 | if (phy->allocated_src == D40_ALLOC_PHY) | |
1308 | goto not_found; | |
1309 | ||
1310 | if (phy->allocated_src == D40_ALLOC_FREE) | |
1311 | phy->allocated_src = D40_ALLOC_LOG_FREE; | |
1312 | ||
1313 | if (!(phy->allocated_src & (1 << log_event_line))) { | |
1314 | phy->allocated_src |= 1 << log_event_line; | |
1315 | goto found; | |
1316 | } else | |
1317 | goto not_found; | |
1318 | } else { | |
1319 | if (phy->allocated_dst == D40_ALLOC_PHY) | |
1320 | goto not_found; | |
1321 | ||
1322 | if (phy->allocated_dst == D40_ALLOC_FREE) | |
1323 | phy->allocated_dst = D40_ALLOC_LOG_FREE; | |
1324 | ||
1325 | if (!(phy->allocated_dst & (1 << log_event_line))) { | |
1326 | phy->allocated_dst |= 1 << log_event_line; | |
1327 | goto found; | |
1328 | } else | |
1329 | goto not_found; | |
1330 | } | |
1331 | ||
1332 | not_found: | |
1333 | spin_unlock_irqrestore(&phy->lock, flags); | |
1334 | return false; | |
1335 | found: | |
1336 | spin_unlock_irqrestore(&phy->lock, flags); | |
1337 | return true; | |
1338 | } | |
1339 | ||
1340 | static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src, | |
1341 | int log_event_line) | |
1342 | { | |
1343 | unsigned long flags; | |
1344 | bool is_free = false; | |
1345 | ||
1346 | spin_lock_irqsave(&phy->lock, flags); | |
1347 | if (!log_event_line) { | |
8d318a50 LW |
1348 | phy->allocated_dst = D40_ALLOC_FREE; |
1349 | phy->allocated_src = D40_ALLOC_FREE; | |
1350 | is_free = true; | |
1351 | goto out; | |
1352 | } | |
1353 | ||
1354 | /* Logical channel */ | |
1355 | if (is_src) { | |
1356 | phy->allocated_src &= ~(1 << log_event_line); | |
1357 | if (phy->allocated_src == D40_ALLOC_LOG_FREE) | |
1358 | phy->allocated_src = D40_ALLOC_FREE; | |
1359 | } else { | |
1360 | phy->allocated_dst &= ~(1 << log_event_line); | |
1361 | if (phy->allocated_dst == D40_ALLOC_LOG_FREE) | |
1362 | phy->allocated_dst = D40_ALLOC_FREE; | |
1363 | } | |
1364 | ||
1365 | is_free = ((phy->allocated_src | phy->allocated_dst) == | |
1366 | D40_ALLOC_FREE); | |
1367 | ||
1368 | out: | |
1369 | spin_unlock_irqrestore(&phy->lock, flags); | |
1370 | ||
1371 | return is_free; | |
1372 | } | |
1373 | ||
1374 | static int d40_allocate_channel(struct d40_chan *d40c) | |
1375 | { | |
1376 | int dev_type; | |
1377 | int event_group; | |
1378 | int event_line; | |
1379 | struct d40_phy_res *phys; | |
1380 | int i; | |
1381 | int j; | |
1382 | int log_num; | |
1383 | bool is_src; | |
38bdbf02 | 1384 | bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL; |
8d318a50 LW |
1385 | |
1386 | phys = d40c->base->phy_res; | |
1387 | ||
1388 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { | |
1389 | dev_type = d40c->dma_cfg.src_dev_type; | |
1390 | log_num = 2 * dev_type; | |
1391 | is_src = true; | |
1392 | } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || | |
1393 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1394 | /* dst event lines are used for logical memcpy */ | |
1395 | dev_type = d40c->dma_cfg.dst_dev_type; | |
1396 | log_num = 2 * dev_type + 1; | |
1397 | is_src = false; | |
1398 | } else | |
1399 | return -EINVAL; | |
1400 | ||
1401 | event_group = D40_TYPE_TO_GROUP(dev_type); | |
1402 | event_line = D40_TYPE_TO_EVENT(dev_type); | |
1403 | ||
1404 | if (!is_log) { | |
1405 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1406 | /* Find physical half channel */ | |
1407 | for (i = 0; i < d40c->base->num_phy_chans; i++) { | |
1408 | ||
4aed79b2 MM |
1409 | if (d40_alloc_mask_set(&phys[i], is_src, |
1410 | 0, is_log)) | |
8d318a50 LW |
1411 | goto found_phy; |
1412 | } | |
1413 | } else | |
1414 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { | |
1415 | int phy_num = j + event_group * 2; | |
1416 | for (i = phy_num; i < phy_num + 2; i++) { | |
508849ad LW |
1417 | if (d40_alloc_mask_set(&phys[i], |
1418 | is_src, | |
1419 | 0, | |
1420 | is_log)) | |
8d318a50 LW |
1421 | goto found_phy; |
1422 | } | |
1423 | } | |
1424 | return -EINVAL; | |
1425 | found_phy: | |
1426 | d40c->phy_chan = &phys[i]; | |
1427 | d40c->log_num = D40_PHY_CHAN; | |
1428 | goto out; | |
1429 | } | |
1430 | if (dev_type == -1) | |
1431 | return -EINVAL; | |
1432 | ||
1433 | /* Find logical channel */ | |
1434 | for (j = 0; j < d40c->base->num_phy_chans; j += 8) { | |
1435 | int phy_num = j + event_group * 2; | |
1436 | /* | |
1437 | * Spread logical channels across all available physical rather | |
1438 | * than pack every logical channel at the first available phy | |
1439 | * channels. | |
1440 | */ | |
1441 | if (is_src) { | |
1442 | for (i = phy_num; i < phy_num + 2; i++) { | |
1443 | if (d40_alloc_mask_set(&phys[i], is_src, | |
4aed79b2 | 1444 | event_line, is_log)) |
8d318a50 LW |
1445 | goto found_log; |
1446 | } | |
1447 | } else { | |
1448 | for (i = phy_num + 1; i >= phy_num; i--) { | |
1449 | if (d40_alloc_mask_set(&phys[i], is_src, | |
4aed79b2 | 1450 | event_line, is_log)) |
8d318a50 LW |
1451 | goto found_log; |
1452 | } | |
1453 | } | |
1454 | } | |
1455 | return -EINVAL; | |
1456 | ||
1457 | found_log: | |
1458 | d40c->phy_chan = &phys[i]; | |
1459 | d40c->log_num = log_num; | |
1460 | out: | |
1461 | ||
1462 | if (is_log) | |
1463 | d40c->base->lookup_log_chans[d40c->log_num] = d40c; | |
1464 | else | |
1465 | d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c; | |
1466 | ||
1467 | return 0; | |
1468 | ||
1469 | } | |
1470 | ||
8d318a50 LW |
1471 | static int d40_config_memcpy(struct d40_chan *d40c) |
1472 | { | |
1473 | dma_cap_mask_t cap = d40c->chan.device->cap_mask; | |
1474 | ||
1475 | if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) { | |
1476 | d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log; | |
1477 | d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY; | |
1478 | d40c->dma_cfg.dst_dev_type = d40c->base->plat_data-> | |
1479 | memcpy[d40c->chan.chan_id]; | |
1480 | ||
1481 | } else if (dma_has_cap(DMA_MEMCPY, cap) && | |
1482 | dma_has_cap(DMA_SLAVE, cap)) { | |
1483 | d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy; | |
1484 | } else { | |
6db5a8ba | 1485 | chan_err(d40c, "No memcpy\n"); |
8d318a50 LW |
1486 | return -EINVAL; |
1487 | } | |
1488 | ||
1489 | return 0; | |
1490 | } | |
1491 | ||
1492 | ||
1493 | static int d40_free_dma(struct d40_chan *d40c) | |
1494 | { | |
1495 | ||
1496 | int res = 0; | |
d181b3a8 | 1497 | u32 event; |
8d318a50 LW |
1498 | struct d40_phy_res *phy = d40c->phy_chan; |
1499 | bool is_src; | |
a8be8627 PF |
1500 | struct d40_desc *d; |
1501 | struct d40_desc *_d; | |
1502 | ||
8d318a50 LW |
1503 | |
1504 | /* Terminate all queued and active transfers */ | |
1505 | d40_term_all(d40c); | |
1506 | ||
a8be8627 PF |
1507 | /* Release client owned descriptors */ |
1508 | if (!list_empty(&d40c->client)) | |
1509 | list_for_each_entry_safe(d, _d, &d40c->client, node) { | |
b00f938c | 1510 | d40_pool_lli_free(d40c, d); |
a8be8627 | 1511 | d40_desc_remove(d); |
a8be8627 PF |
1512 | d40_desc_free(d40c, d); |
1513 | } | |
1514 | ||
8d318a50 | 1515 | if (phy == NULL) { |
6db5a8ba | 1516 | chan_err(d40c, "phy == null\n"); |
8d318a50 LW |
1517 | return -EINVAL; |
1518 | } | |
1519 | ||
1520 | if (phy->allocated_src == D40_ALLOC_FREE && | |
1521 | phy->allocated_dst == D40_ALLOC_FREE) { | |
6db5a8ba | 1522 | chan_err(d40c, "channel already free\n"); |
8d318a50 LW |
1523 | return -EINVAL; |
1524 | } | |
1525 | ||
8d318a50 LW |
1526 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
1527 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { | |
1528 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); | |
8d318a50 LW |
1529 | is_src = false; |
1530 | } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { | |
1531 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); | |
8d318a50 LW |
1532 | is_src = true; |
1533 | } else { | |
6db5a8ba | 1534 | chan_err(d40c, "Unknown direction\n"); |
8d318a50 LW |
1535 | return -EINVAL; |
1536 | } | |
1537 | ||
d181b3a8 JA |
1538 | res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ); |
1539 | if (res) { | |
6db5a8ba | 1540 | chan_err(d40c, "suspend failed\n"); |
d181b3a8 JA |
1541 | return res; |
1542 | } | |
1543 | ||
724a8577 | 1544 | if (chan_is_logical(d40c)) { |
d181b3a8 | 1545 | /* Release logical channel, deactivate the event line */ |
8d318a50 | 1546 | |
d181b3a8 | 1547 | d40_config_set_event(d40c, false); |
8d318a50 LW |
1548 | d40c->base->lookup_log_chans[d40c->log_num] = NULL; |
1549 | ||
1550 | /* | |
1551 | * Check if there are more logical allocation | |
1552 | * on this phy channel. | |
1553 | */ | |
1554 | if (!d40_alloc_mask_free(phy, is_src, event)) { | |
1555 | /* Resume the other logical channels if any */ | |
1556 | if (d40_chan_has_events(d40c)) { | |
1557 | res = d40_channel_execute_command(d40c, | |
1558 | D40_DMA_RUN); | |
1559 | if (res) { | |
6db5a8ba RV |
1560 | chan_err(d40c, |
1561 | "Executing RUN command\n"); | |
8d318a50 LW |
1562 | return res; |
1563 | } | |
1564 | } | |
1565 | return 0; | |
1566 | } | |
d181b3a8 JA |
1567 | } else { |
1568 | (void) d40_alloc_mask_free(phy, is_src, 0); | |
1569 | } | |
8d318a50 LW |
1570 | |
1571 | /* Release physical channel */ | |
1572 | res = d40_channel_execute_command(d40c, D40_DMA_STOP); | |
1573 | if (res) { | |
6db5a8ba | 1574 | chan_err(d40c, "Failed to stop channel\n"); |
8d318a50 LW |
1575 | return res; |
1576 | } | |
1577 | d40c->phy_chan = NULL; | |
ce2ca125 | 1578 | d40c->configured = false; |
8d318a50 LW |
1579 | d40c->base->lookup_phy_chans[phy->num] = NULL; |
1580 | ||
1581 | return 0; | |
8d318a50 LW |
1582 | } |
1583 | ||
a5ebca47 JA |
1584 | static bool d40_is_paused(struct d40_chan *d40c) |
1585 | { | |
8ca84687 | 1586 | void __iomem *chanbase = chan_base(d40c); |
a5ebca47 JA |
1587 | bool is_paused = false; |
1588 | unsigned long flags; | |
1589 | void __iomem *active_reg; | |
1590 | u32 status; | |
1591 | u32 event; | |
a5ebca47 JA |
1592 | |
1593 | spin_lock_irqsave(&d40c->lock, flags); | |
1594 | ||
724a8577 | 1595 | if (chan_is_physical(d40c)) { |
a5ebca47 JA |
1596 | if (d40c->phy_chan->num % 2 == 0) |
1597 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVE; | |
1598 | else | |
1599 | active_reg = d40c->base->virtbase + D40_DREG_ACTIVO; | |
1600 | ||
1601 | status = (readl(active_reg) & | |
1602 | D40_CHAN_POS_MASK(d40c->phy_chan->num)) >> | |
1603 | D40_CHAN_POS(d40c->phy_chan->num); | |
1604 | if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP) | |
1605 | is_paused = true; | |
1606 | ||
1607 | goto _exit; | |
1608 | } | |
1609 | ||
a5ebca47 | 1610 | if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH || |
9dbfbd35 | 1611 | d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) { |
a5ebca47 | 1612 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type); |
8ca84687 | 1613 | status = readl(chanbase + D40_CHAN_REG_SDLNK); |
9dbfbd35 | 1614 | } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) { |
a5ebca47 | 1615 | event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type); |
8ca84687 | 1616 | status = readl(chanbase + D40_CHAN_REG_SSLNK); |
9dbfbd35 | 1617 | } else { |
6db5a8ba | 1618 | chan_err(d40c, "Unknown direction\n"); |
a5ebca47 JA |
1619 | goto _exit; |
1620 | } | |
9dbfbd35 | 1621 | |
a5ebca47 JA |
1622 | status = (status & D40_EVENTLINE_MASK(event)) >> |
1623 | D40_EVENTLINE_POS(event); | |
1624 | ||
1625 | if (status != D40_DMA_RUN) | |
1626 | is_paused = true; | |
a5ebca47 JA |
1627 | _exit: |
1628 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1629 | return is_paused; | |
1630 | ||
1631 | } | |
1632 | ||
1633 | ||
8d318a50 LW |
1634 | static u32 stedma40_residue(struct dma_chan *chan) |
1635 | { | |
1636 | struct d40_chan *d40c = | |
1637 | container_of(chan, struct d40_chan, chan); | |
1638 | u32 bytes_left; | |
1639 | unsigned long flags; | |
1640 | ||
1641 | spin_lock_irqsave(&d40c->lock, flags); | |
1642 | bytes_left = d40_residue(d40c); | |
1643 | spin_unlock_irqrestore(&d40c->lock, flags); | |
1644 | ||
1645 | return bytes_left; | |
1646 | } | |
1647 | ||
3e3a0763 RV |
1648 | static int |
1649 | d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc, | |
1650 | struct scatterlist *sg_src, struct scatterlist *sg_dst, | |
822c5676 RV |
1651 | unsigned int sg_len, dma_addr_t src_dev_addr, |
1652 | dma_addr_t dst_dev_addr) | |
3e3a0763 RV |
1653 | { |
1654 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; | |
1655 | struct stedma40_half_channel_info *src_info = &cfg->src_info; | |
1656 | struct stedma40_half_channel_info *dst_info = &cfg->dst_info; | |
5ed04b85 | 1657 | int ret; |
3e3a0763 | 1658 | |
5ed04b85 RV |
1659 | ret = d40_log_sg_to_lli(sg_src, sg_len, |
1660 | src_dev_addr, | |
1661 | desc->lli_log.src, | |
1662 | chan->log_def.lcsp1, | |
1663 | src_info->data_width, | |
1664 | dst_info->data_width); | |
1665 | ||
1666 | ret = d40_log_sg_to_lli(sg_dst, sg_len, | |
1667 | dst_dev_addr, | |
1668 | desc->lli_log.dst, | |
1669 | chan->log_def.lcsp3, | |
1670 | dst_info->data_width, | |
1671 | src_info->data_width); | |
1672 | ||
1673 | return ret < 0 ? ret : 0; | |
3e3a0763 RV |
1674 | } |
1675 | ||
1676 | static int | |
1677 | d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc, | |
1678 | struct scatterlist *sg_src, struct scatterlist *sg_dst, | |
822c5676 RV |
1679 | unsigned int sg_len, dma_addr_t src_dev_addr, |
1680 | dma_addr_t dst_dev_addr) | |
3e3a0763 | 1681 | { |
3e3a0763 RV |
1682 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; |
1683 | struct stedma40_half_channel_info *src_info = &cfg->src_info; | |
1684 | struct stedma40_half_channel_info *dst_info = &cfg->dst_info; | |
1685 | int ret; | |
1686 | ||
1687 | ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr, | |
1688 | desc->lli_phy.src, | |
1689 | virt_to_phys(desc->lli_phy.src), | |
1690 | chan->src_def_cfg, | |
cc31b6f7 | 1691 | src_info, dst_info); |
3e3a0763 RV |
1692 | |
1693 | ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr, | |
1694 | desc->lli_phy.dst, | |
1695 | virt_to_phys(desc->lli_phy.dst), | |
1696 | chan->dst_def_cfg, | |
cc31b6f7 | 1697 | dst_info, src_info); |
3e3a0763 RV |
1698 | |
1699 | dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr, | |
1700 | desc->lli_pool.size, DMA_TO_DEVICE); | |
1701 | ||
1702 | return ret < 0 ? ret : 0; | |
1703 | } | |
1704 | ||
1705 | ||
5f81158f RV |
1706 | static struct d40_desc * |
1707 | d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg, | |
1708 | unsigned int sg_len, unsigned long dma_flags) | |
1709 | { | |
1710 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; | |
1711 | struct d40_desc *desc; | |
dbd88788 | 1712 | int ret; |
5f81158f RV |
1713 | |
1714 | desc = d40_desc_get(chan); | |
1715 | if (!desc) | |
1716 | return NULL; | |
1717 | ||
1718 | desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width, | |
1719 | cfg->dst_info.data_width); | |
1720 | if (desc->lli_len < 0) { | |
1721 | chan_err(chan, "Unaligned size\n"); | |
dbd88788 RV |
1722 | goto err; |
1723 | } | |
5f81158f | 1724 | |
dbd88788 RV |
1725 | ret = d40_pool_lli_alloc(chan, desc, desc->lli_len); |
1726 | if (ret < 0) { | |
1727 | chan_err(chan, "Could not allocate lli\n"); | |
1728 | goto err; | |
5f81158f RV |
1729 | } |
1730 | ||
dbd88788 | 1731 | |
5f81158f RV |
1732 | desc->lli_current = 0; |
1733 | desc->txd.flags = dma_flags; | |
1734 | desc->txd.tx_submit = d40_tx_submit; | |
1735 | ||
1736 | dma_async_tx_descriptor_init(&desc->txd, &chan->chan); | |
1737 | ||
1738 | return desc; | |
dbd88788 RV |
1739 | |
1740 | err: | |
1741 | d40_desc_free(chan, desc); | |
1742 | return NULL; | |
5f81158f RV |
1743 | } |
1744 | ||
cade1d30 RV |
1745 | static dma_addr_t |
1746 | d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction) | |
8d318a50 | 1747 | { |
cade1d30 RV |
1748 | struct stedma40_platform_data *plat = chan->base->plat_data; |
1749 | struct stedma40_chan_cfg *cfg = &chan->dma_cfg; | |
1750 | dma_addr_t addr; | |
1751 | ||
1752 | if (chan->runtime_addr) | |
1753 | return chan->runtime_addr; | |
1754 | ||
1755 | if (direction == DMA_FROM_DEVICE) | |
1756 | addr = plat->dev_rx[cfg->src_dev_type]; | |
1757 | else if (direction == DMA_TO_DEVICE) | |
1758 | addr = plat->dev_tx[cfg->dst_dev_type]; | |
1759 | ||
1760 | return addr; | |
1761 | } | |
1762 | ||
1763 | static struct dma_async_tx_descriptor * | |
1764 | d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src, | |
1765 | struct scatterlist *sg_dst, unsigned int sg_len, | |
1766 | enum dma_data_direction direction, unsigned long dma_flags) | |
1767 | { | |
1768 | struct d40_chan *chan = container_of(dchan, struct d40_chan, chan); | |
822c5676 RV |
1769 | dma_addr_t src_dev_addr = 0; |
1770 | dma_addr_t dst_dev_addr = 0; | |
cade1d30 | 1771 | struct d40_desc *desc; |
2a614340 | 1772 | unsigned long flags; |
cade1d30 | 1773 | int ret; |
8d318a50 | 1774 | |
cade1d30 RV |
1775 | if (!chan->phy_chan) { |
1776 | chan_err(chan, "Cannot prepare unallocated channel\n"); | |
1777 | return NULL; | |
0d0f6b8b JA |
1778 | } |
1779 | ||
cade1d30 | 1780 | spin_lock_irqsave(&chan->lock, flags); |
8d318a50 | 1781 | |
cade1d30 RV |
1782 | desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags); |
1783 | if (desc == NULL) | |
8d318a50 LW |
1784 | goto err; |
1785 | ||
822c5676 RV |
1786 | if (direction != DMA_NONE) { |
1787 | dma_addr_t dev_addr = d40_get_dev_addr(chan, direction); | |
1788 | ||
1789 | if (direction == DMA_FROM_DEVICE) | |
1790 | src_dev_addr = dev_addr; | |
1791 | else if (direction == DMA_TO_DEVICE) | |
1792 | dst_dev_addr = dev_addr; | |
1793 | } | |
cade1d30 RV |
1794 | |
1795 | if (chan_is_logical(chan)) | |
1796 | ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst, | |
822c5676 | 1797 | sg_len, src_dev_addr, dst_dev_addr); |
cade1d30 RV |
1798 | else |
1799 | ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst, | |
822c5676 | 1800 | sg_len, src_dev_addr, dst_dev_addr); |
cade1d30 RV |
1801 | |
1802 | if (ret) { | |
1803 | chan_err(chan, "Failed to prepare %s sg job: %d\n", | |
1804 | chan_is_logical(chan) ? "log" : "phy", ret); | |
1805 | goto err; | |
8d318a50 LW |
1806 | } |
1807 | ||
cade1d30 RV |
1808 | spin_unlock_irqrestore(&chan->lock, flags); |
1809 | ||
1810 | return &desc->txd; | |
8d318a50 | 1811 | |
8d318a50 | 1812 | err: |
cade1d30 RV |
1813 | if (desc) |
1814 | d40_desc_free(chan, desc); | |
1815 | spin_unlock_irqrestore(&chan->lock, flags); | |
8d318a50 LW |
1816 | return NULL; |
1817 | } | |
8d318a50 LW |
1818 | |
1819 | bool stedma40_filter(struct dma_chan *chan, void *data) | |
1820 | { | |
1821 | struct stedma40_chan_cfg *info = data; | |
1822 | struct d40_chan *d40c = | |
1823 | container_of(chan, struct d40_chan, chan); | |
1824 | int err; | |
1825 | ||
1826 | if (data) { | |
1827 | err = d40_validate_conf(d40c, info); | |
1828 | if (!err) | |
1829 | d40c->dma_cfg = *info; | |
1830 | } else | |
1831 | err = d40_config_memcpy(d40c); | |
1832 | ||
ce2ca125 RV |
1833 | if (!err) |
1834 | d40c->configured = true; | |
1835 | ||
8d318a50 LW |
1836 | return err == 0; |
1837 | } | |
1838 | EXPORT_SYMBOL(stedma40_filter); | |
1839 | ||
ac2c0a38 RV |
1840 | static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src) |
1841 | { | |
1842 | bool realtime = d40c->dma_cfg.realtime; | |
1843 | bool highprio = d40c->dma_cfg.high_priority; | |
1844 | u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1; | |
1845 | u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1; | |
1846 | u32 event = D40_TYPE_TO_EVENT(dev_type); | |
1847 | u32 group = D40_TYPE_TO_GROUP(dev_type); | |
1848 | u32 bit = 1 << event; | |
1849 | ||
1850 | /* Destination event lines are stored in the upper halfword */ | |
1851 | if (!src) | |
1852 | bit <<= 16; | |
1853 | ||
1854 | writel(bit, d40c->base->virtbase + prioreg + group * 4); | |
1855 | writel(bit, d40c->base->virtbase + rtreg + group * 4); | |
1856 | } | |
1857 | ||
1858 | static void d40_set_prio_realtime(struct d40_chan *d40c) | |
1859 | { | |
1860 | if (d40c->base->rev < 3) | |
1861 | return; | |
1862 | ||
1863 | if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) || | |
1864 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) | |
1865 | __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true); | |
1866 | ||
1867 | if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) || | |
1868 | (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) | |
1869 | __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false); | |
1870 | } | |
1871 | ||
8d318a50 LW |
1872 | /* DMA ENGINE functions */ |
1873 | static int d40_alloc_chan_resources(struct dma_chan *chan) | |
1874 | { | |
1875 | int err; | |
1876 | unsigned long flags; | |
1877 | struct d40_chan *d40c = | |
1878 | container_of(chan, struct d40_chan, chan); | |
ef1872ec | 1879 | bool is_free_phy; |
8d318a50 LW |
1880 | spin_lock_irqsave(&d40c->lock, flags); |
1881 | ||
1882 | d40c->completed = chan->cookie = 1; | |
1883 | ||
ce2ca125 RV |
1884 | /* If no dma configuration is set use default configuration (memcpy) */ |
1885 | if (!d40c->configured) { | |
8d318a50 | 1886 | err = d40_config_memcpy(d40c); |
ff0b12ba | 1887 | if (err) { |
6db5a8ba | 1888 | chan_err(d40c, "Failed to configure memcpy channel\n"); |
ff0b12ba JA |
1889 | goto fail; |
1890 | } | |
8d318a50 | 1891 | } |
ef1872ec | 1892 | is_free_phy = (d40c->phy_chan == NULL); |
8d318a50 LW |
1893 | |
1894 | err = d40_allocate_channel(d40c); | |
1895 | if (err) { | |
6db5a8ba | 1896 | chan_err(d40c, "Failed to allocate channel\n"); |
ff0b12ba | 1897 | goto fail; |
8d318a50 LW |
1898 | } |
1899 | ||
ef1872ec LW |
1900 | /* Fill in basic CFG register values */ |
1901 | d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg, | |
724a8577 | 1902 | &d40c->dst_def_cfg, chan_is_logical(d40c)); |
ef1872ec | 1903 | |
ac2c0a38 RV |
1904 | d40_set_prio_realtime(d40c); |
1905 | ||
724a8577 | 1906 | if (chan_is_logical(d40c)) { |
ef1872ec LW |
1907 | d40_log_cfg(&d40c->dma_cfg, |
1908 | &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); | |
1909 | ||
1910 | if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) | |
1911 | d40c->lcpa = d40c->base->lcpa_base + | |
1912 | d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE; | |
1913 | else | |
1914 | d40c->lcpa = d40c->base->lcpa_base + | |
1915 | d40c->dma_cfg.dst_dev_type * | |
1916 | D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA; | |
1917 | } | |
1918 | ||
1919 | /* | |
1920 | * Only write channel configuration to the DMA if the physical | |
1921 | * resource is free. In case of multiple logical channels | |
1922 | * on the same physical resource, only the first write is necessary. | |
1923 | */ | |
b55912c6 JA |
1924 | if (is_free_phy) |
1925 | d40_config_write(d40c); | |
ff0b12ba | 1926 | fail: |
8d318a50 | 1927 | spin_unlock_irqrestore(&d40c->lock, flags); |
ff0b12ba | 1928 | return err; |
8d318a50 LW |
1929 | } |
1930 | ||
1931 | static void d40_free_chan_resources(struct dma_chan *chan) | |
1932 | { | |
1933 | struct d40_chan *d40c = | |
1934 | container_of(chan, struct d40_chan, chan); | |
1935 | int err; | |
1936 | unsigned long flags; | |
1937 | ||
0d0f6b8b | 1938 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 1939 | chan_err(d40c, "Cannot free unallocated channel\n"); |
0d0f6b8b JA |
1940 | return; |
1941 | } | |
1942 | ||
1943 | ||
8d318a50 LW |
1944 | spin_lock_irqsave(&d40c->lock, flags); |
1945 | ||
1946 | err = d40_free_dma(d40c); | |
1947 | ||
1948 | if (err) | |
6db5a8ba | 1949 | chan_err(d40c, "Failed to free channel\n"); |
8d318a50 LW |
1950 | spin_unlock_irqrestore(&d40c->lock, flags); |
1951 | } | |
1952 | ||
1953 | static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan, | |
1954 | dma_addr_t dst, | |
1955 | dma_addr_t src, | |
1956 | size_t size, | |
2a614340 | 1957 | unsigned long dma_flags) |
8d318a50 | 1958 | { |
95944c6e RV |
1959 | struct scatterlist dst_sg; |
1960 | struct scatterlist src_sg; | |
8d318a50 | 1961 | |
95944c6e RV |
1962 | sg_init_table(&dst_sg, 1); |
1963 | sg_init_table(&src_sg, 1); | |
8d318a50 | 1964 | |
95944c6e RV |
1965 | sg_dma_address(&dst_sg) = dst; |
1966 | sg_dma_address(&src_sg) = src; | |
8d318a50 | 1967 | |
95944c6e RV |
1968 | sg_dma_len(&dst_sg) = size; |
1969 | sg_dma_len(&src_sg) = size; | |
8d318a50 | 1970 | |
cade1d30 | 1971 | return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags); |
8d318a50 LW |
1972 | } |
1973 | ||
0d688662 | 1974 | static struct dma_async_tx_descriptor * |
cade1d30 RV |
1975 | d40_prep_memcpy_sg(struct dma_chan *chan, |
1976 | struct scatterlist *dst_sg, unsigned int dst_nents, | |
1977 | struct scatterlist *src_sg, unsigned int src_nents, | |
1978 | unsigned long dma_flags) | |
0d688662 IS |
1979 | { |
1980 | if (dst_nents != src_nents) | |
1981 | return NULL; | |
1982 | ||
cade1d30 | 1983 | return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags); |
00ac0341 RV |
1984 | } |
1985 | ||
8d318a50 LW |
1986 | static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan, |
1987 | struct scatterlist *sgl, | |
1988 | unsigned int sg_len, | |
1989 | enum dma_data_direction direction, | |
2a614340 | 1990 | unsigned long dma_flags) |
8d318a50 | 1991 | { |
00ac0341 RV |
1992 | if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) |
1993 | return NULL; | |
1994 | ||
cade1d30 | 1995 | return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags); |
8d318a50 LW |
1996 | } |
1997 | ||
1998 | static enum dma_status d40_tx_status(struct dma_chan *chan, | |
1999 | dma_cookie_t cookie, | |
2000 | struct dma_tx_state *txstate) | |
2001 | { | |
2002 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2003 | dma_cookie_t last_used; | |
2004 | dma_cookie_t last_complete; | |
2005 | int ret; | |
2006 | ||
0d0f6b8b | 2007 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2008 | chan_err(d40c, "Cannot read status of unallocated channel\n"); |
0d0f6b8b JA |
2009 | return -EINVAL; |
2010 | } | |
2011 | ||
8d318a50 LW |
2012 | last_complete = d40c->completed; |
2013 | last_used = chan->cookie; | |
2014 | ||
a5ebca47 JA |
2015 | if (d40_is_paused(d40c)) |
2016 | ret = DMA_PAUSED; | |
2017 | else | |
2018 | ret = dma_async_is_complete(cookie, last_complete, last_used); | |
8d318a50 | 2019 | |
a5ebca47 JA |
2020 | dma_set_tx_state(txstate, last_complete, last_used, |
2021 | stedma40_residue(chan)); | |
8d318a50 LW |
2022 | |
2023 | return ret; | |
2024 | } | |
2025 | ||
2026 | static void d40_issue_pending(struct dma_chan *chan) | |
2027 | { | |
2028 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2029 | unsigned long flags; | |
2030 | ||
0d0f6b8b | 2031 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2032 | chan_err(d40c, "Channel is not allocated!\n"); |
0d0f6b8b JA |
2033 | return; |
2034 | } | |
2035 | ||
8d318a50 LW |
2036 | spin_lock_irqsave(&d40c->lock, flags); |
2037 | ||
2038 | /* Busy means that pending jobs are already being processed */ | |
2039 | if (!d40c->busy) | |
2040 | (void) d40_queue_start(d40c); | |
2041 | ||
2042 | spin_unlock_irqrestore(&d40c->lock, flags); | |
2043 | } | |
2044 | ||
95e1400f LW |
2045 | /* Runtime reconfiguration extension */ |
2046 | static void d40_set_runtime_config(struct dma_chan *chan, | |
2047 | struct dma_slave_config *config) | |
2048 | { | |
2049 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2050 | struct stedma40_chan_cfg *cfg = &d40c->dma_cfg; | |
2051 | enum dma_slave_buswidth config_addr_width; | |
2052 | dma_addr_t config_addr; | |
2053 | u32 config_maxburst; | |
2054 | enum stedma40_periph_data_width addr_width; | |
2055 | int psize; | |
2056 | ||
2057 | if (config->direction == DMA_FROM_DEVICE) { | |
2058 | dma_addr_t dev_addr_rx = | |
2059 | d40c->base->plat_data->dev_rx[cfg->src_dev_type]; | |
2060 | ||
2061 | config_addr = config->src_addr; | |
2062 | if (dev_addr_rx) | |
2063 | dev_dbg(d40c->base->dev, | |
2064 | "channel has a pre-wired RX address %08x " | |
2065 | "overriding with %08x\n", | |
2066 | dev_addr_rx, config_addr); | |
2067 | if (cfg->dir != STEDMA40_PERIPH_TO_MEM) | |
2068 | dev_dbg(d40c->base->dev, | |
2069 | "channel was not configured for peripheral " | |
2070 | "to memory transfer (%d) overriding\n", | |
2071 | cfg->dir); | |
2072 | cfg->dir = STEDMA40_PERIPH_TO_MEM; | |
2073 | ||
2074 | config_addr_width = config->src_addr_width; | |
2075 | config_maxburst = config->src_maxburst; | |
2076 | ||
2077 | } else if (config->direction == DMA_TO_DEVICE) { | |
2078 | dma_addr_t dev_addr_tx = | |
2079 | d40c->base->plat_data->dev_tx[cfg->dst_dev_type]; | |
2080 | ||
2081 | config_addr = config->dst_addr; | |
2082 | if (dev_addr_tx) | |
2083 | dev_dbg(d40c->base->dev, | |
2084 | "channel has a pre-wired TX address %08x " | |
2085 | "overriding with %08x\n", | |
2086 | dev_addr_tx, config_addr); | |
2087 | if (cfg->dir != STEDMA40_MEM_TO_PERIPH) | |
2088 | dev_dbg(d40c->base->dev, | |
2089 | "channel was not configured for memory " | |
2090 | "to peripheral transfer (%d) overriding\n", | |
2091 | cfg->dir); | |
2092 | cfg->dir = STEDMA40_MEM_TO_PERIPH; | |
2093 | ||
2094 | config_addr_width = config->dst_addr_width; | |
2095 | config_maxburst = config->dst_maxburst; | |
2096 | ||
2097 | } else { | |
2098 | dev_err(d40c->base->dev, | |
2099 | "unrecognized channel direction %d\n", | |
2100 | config->direction); | |
2101 | return; | |
2102 | } | |
2103 | ||
2104 | switch (config_addr_width) { | |
2105 | case DMA_SLAVE_BUSWIDTH_1_BYTE: | |
2106 | addr_width = STEDMA40_BYTE_WIDTH; | |
2107 | break; | |
2108 | case DMA_SLAVE_BUSWIDTH_2_BYTES: | |
2109 | addr_width = STEDMA40_HALFWORD_WIDTH; | |
2110 | break; | |
2111 | case DMA_SLAVE_BUSWIDTH_4_BYTES: | |
2112 | addr_width = STEDMA40_WORD_WIDTH; | |
2113 | break; | |
2114 | case DMA_SLAVE_BUSWIDTH_8_BYTES: | |
2115 | addr_width = STEDMA40_DOUBLEWORD_WIDTH; | |
2116 | break; | |
2117 | default: | |
2118 | dev_err(d40c->base->dev, | |
2119 | "illegal peripheral address width " | |
2120 | "requested (%d)\n", | |
2121 | config->src_addr_width); | |
2122 | return; | |
2123 | } | |
2124 | ||
724a8577 | 2125 | if (chan_is_logical(d40c)) { |
a59670a4 PF |
2126 | if (config_maxburst >= 16) |
2127 | psize = STEDMA40_PSIZE_LOG_16; | |
2128 | else if (config_maxburst >= 8) | |
2129 | psize = STEDMA40_PSIZE_LOG_8; | |
2130 | else if (config_maxburst >= 4) | |
2131 | psize = STEDMA40_PSIZE_LOG_4; | |
2132 | else | |
2133 | psize = STEDMA40_PSIZE_LOG_1; | |
2134 | } else { | |
2135 | if (config_maxburst >= 16) | |
2136 | psize = STEDMA40_PSIZE_PHY_16; | |
2137 | else if (config_maxburst >= 8) | |
2138 | psize = STEDMA40_PSIZE_PHY_8; | |
2139 | else if (config_maxburst >= 4) | |
2140 | psize = STEDMA40_PSIZE_PHY_4; | |
d49278e3 PF |
2141 | else if (config_maxburst >= 2) |
2142 | psize = STEDMA40_PSIZE_PHY_2; | |
a59670a4 PF |
2143 | else |
2144 | psize = STEDMA40_PSIZE_PHY_1; | |
2145 | } | |
95e1400f LW |
2146 | |
2147 | /* Set up all the endpoint configs */ | |
2148 | cfg->src_info.data_width = addr_width; | |
2149 | cfg->src_info.psize = psize; | |
51f5d744 | 2150 | cfg->src_info.big_endian = false; |
95e1400f LW |
2151 | cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL; |
2152 | cfg->dst_info.data_width = addr_width; | |
2153 | cfg->dst_info.psize = psize; | |
51f5d744 | 2154 | cfg->dst_info.big_endian = false; |
95e1400f LW |
2155 | cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL; |
2156 | ||
a59670a4 | 2157 | /* Fill in register values */ |
724a8577 | 2158 | if (chan_is_logical(d40c)) |
a59670a4 PF |
2159 | d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3); |
2160 | else | |
2161 | d40_phy_cfg(cfg, &d40c->src_def_cfg, | |
2162 | &d40c->dst_def_cfg, false); | |
2163 | ||
95e1400f LW |
2164 | /* These settings will take precedence later */ |
2165 | d40c->runtime_addr = config_addr; | |
2166 | d40c->runtime_direction = config->direction; | |
2167 | dev_dbg(d40c->base->dev, | |
2168 | "configured channel %s for %s, data width %d, " | |
2169 | "maxburst %d bytes, LE, no flow control\n", | |
2170 | dma_chan_name(chan), | |
2171 | (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX", | |
2172 | config_addr_width, | |
2173 | config_maxburst); | |
2174 | } | |
2175 | ||
05827630 LW |
2176 | static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
2177 | unsigned long arg) | |
8d318a50 LW |
2178 | { |
2179 | unsigned long flags; | |
2180 | struct d40_chan *d40c = container_of(chan, struct d40_chan, chan); | |
2181 | ||
0d0f6b8b | 2182 | if (d40c->phy_chan == NULL) { |
6db5a8ba | 2183 | chan_err(d40c, "Channel is not allocated!\n"); |
0d0f6b8b JA |
2184 | return -EINVAL; |
2185 | } | |
2186 | ||
8d318a50 LW |
2187 | switch (cmd) { |
2188 | case DMA_TERMINATE_ALL: | |
2189 | spin_lock_irqsave(&d40c->lock, flags); | |
2190 | d40_term_all(d40c); | |
2191 | spin_unlock_irqrestore(&d40c->lock, flags); | |
2192 | return 0; | |
2193 | case DMA_PAUSE: | |
2194 | return d40_pause(chan); | |
2195 | case DMA_RESUME: | |
2196 | return d40_resume(chan); | |
95e1400f LW |
2197 | case DMA_SLAVE_CONFIG: |
2198 | d40_set_runtime_config(chan, | |
2199 | (struct dma_slave_config *) arg); | |
2200 | return 0; | |
2201 | default: | |
2202 | break; | |
8d318a50 LW |
2203 | } |
2204 | ||
2205 | /* Other commands are unimplemented */ | |
2206 | return -ENXIO; | |
2207 | } | |
2208 | ||
2209 | /* Initialization functions */ | |
2210 | ||
2211 | static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma, | |
2212 | struct d40_chan *chans, int offset, | |
2213 | int num_chans) | |
2214 | { | |
2215 | int i = 0; | |
2216 | struct d40_chan *d40c; | |
2217 | ||
2218 | INIT_LIST_HEAD(&dma->channels); | |
2219 | ||
2220 | for (i = offset; i < offset + num_chans; i++) { | |
2221 | d40c = &chans[i]; | |
2222 | d40c->base = base; | |
2223 | d40c->chan.device = dma; | |
2224 | ||
8d318a50 LW |
2225 | spin_lock_init(&d40c->lock); |
2226 | ||
2227 | d40c->log_num = D40_PHY_CHAN; | |
2228 | ||
8d318a50 LW |
2229 | INIT_LIST_HEAD(&d40c->active); |
2230 | INIT_LIST_HEAD(&d40c->queue); | |
2231 | INIT_LIST_HEAD(&d40c->client); | |
2232 | ||
8d318a50 LW |
2233 | tasklet_init(&d40c->tasklet, dma_tasklet, |
2234 | (unsigned long) d40c); | |
2235 | ||
2236 | list_add_tail(&d40c->chan.device_node, | |
2237 | &dma->channels); | |
2238 | } | |
2239 | } | |
2240 | ||
7ad74a7c RV |
2241 | static void d40_ops_init(struct d40_base *base, struct dma_device *dev) |
2242 | { | |
2243 | if (dma_has_cap(DMA_SLAVE, dev->cap_mask)) | |
2244 | dev->device_prep_slave_sg = d40_prep_slave_sg; | |
2245 | ||
2246 | if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) { | |
2247 | dev->device_prep_dma_memcpy = d40_prep_memcpy; | |
2248 | ||
2249 | /* | |
2250 | * This controller can only access address at even | |
2251 | * 32bit boundaries, i.e. 2^2 | |
2252 | */ | |
2253 | dev->copy_align = 2; | |
2254 | } | |
2255 | ||
2256 | if (dma_has_cap(DMA_SG, dev->cap_mask)) | |
2257 | dev->device_prep_dma_sg = d40_prep_memcpy_sg; | |
2258 | ||
2259 | dev->device_alloc_chan_resources = d40_alloc_chan_resources; | |
2260 | dev->device_free_chan_resources = d40_free_chan_resources; | |
2261 | dev->device_issue_pending = d40_issue_pending; | |
2262 | dev->device_tx_status = d40_tx_status; | |
2263 | dev->device_control = d40_control; | |
2264 | dev->dev = base->dev; | |
2265 | } | |
2266 | ||
8d318a50 LW |
2267 | static int __init d40_dmaengine_init(struct d40_base *base, |
2268 | int num_reserved_chans) | |
2269 | { | |
2270 | int err ; | |
2271 | ||
2272 | d40_chan_init(base, &base->dma_slave, base->log_chans, | |
2273 | 0, base->num_log_chans); | |
2274 | ||
2275 | dma_cap_zero(base->dma_slave.cap_mask); | |
2276 | dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask); | |
2277 | ||
7ad74a7c | 2278 | d40_ops_init(base, &base->dma_slave); |
8d318a50 LW |
2279 | |
2280 | err = dma_async_device_register(&base->dma_slave); | |
2281 | ||
2282 | if (err) { | |
6db5a8ba | 2283 | d40_err(base->dev, "Failed to register slave channels\n"); |
8d318a50 LW |
2284 | goto failure1; |
2285 | } | |
2286 | ||
2287 | d40_chan_init(base, &base->dma_memcpy, base->log_chans, | |
2288 | base->num_log_chans, base->plat_data->memcpy_len); | |
2289 | ||
2290 | dma_cap_zero(base->dma_memcpy.cap_mask); | |
2291 | dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask); | |
7ad74a7c RV |
2292 | dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask); |
2293 | ||
2294 | d40_ops_init(base, &base->dma_memcpy); | |
8d318a50 LW |
2295 | |
2296 | err = dma_async_device_register(&base->dma_memcpy); | |
2297 | ||
2298 | if (err) { | |
6db5a8ba RV |
2299 | d40_err(base->dev, |
2300 | "Failed to regsiter memcpy only channels\n"); | |
8d318a50 LW |
2301 | goto failure2; |
2302 | } | |
2303 | ||
2304 | d40_chan_init(base, &base->dma_both, base->phy_chans, | |
2305 | 0, num_reserved_chans); | |
2306 | ||
2307 | dma_cap_zero(base->dma_both.cap_mask); | |
2308 | dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask); | |
2309 | dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask); | |
7ad74a7c RV |
2310 | dma_cap_set(DMA_SG, base->dma_both.cap_mask); |
2311 | ||
2312 | d40_ops_init(base, &base->dma_both); | |
2313 | ||
8d318a50 LW |
2314 | err = dma_async_device_register(&base->dma_both); |
2315 | ||
2316 | if (err) { | |
6db5a8ba RV |
2317 | d40_err(base->dev, |
2318 | "Failed to register logical and physical capable channels\n"); | |
8d318a50 LW |
2319 | goto failure3; |
2320 | } | |
2321 | return 0; | |
2322 | failure3: | |
2323 | dma_async_device_unregister(&base->dma_memcpy); | |
2324 | failure2: | |
2325 | dma_async_device_unregister(&base->dma_slave); | |
2326 | failure1: | |
2327 | return err; | |
2328 | } | |
2329 | ||
2330 | /* Initialization functions. */ | |
2331 | ||
2332 | static int __init d40_phy_res_init(struct d40_base *base) | |
2333 | { | |
2334 | int i; | |
2335 | int num_phy_chans_avail = 0; | |
2336 | u32 val[2]; | |
2337 | int odd_even_bit = -2; | |
2338 | ||
2339 | val[0] = readl(base->virtbase + D40_DREG_PRSME); | |
2340 | val[1] = readl(base->virtbase + D40_DREG_PRSMO); | |
2341 | ||
2342 | for (i = 0; i < base->num_phy_chans; i++) { | |
2343 | base->phy_res[i].num = i; | |
2344 | odd_even_bit += 2 * ((i % 2) == 0); | |
2345 | if (((val[i % 2] >> odd_even_bit) & 3) == 1) { | |
2346 | /* Mark security only channels as occupied */ | |
2347 | base->phy_res[i].allocated_src = D40_ALLOC_PHY; | |
2348 | base->phy_res[i].allocated_dst = D40_ALLOC_PHY; | |
2349 | } else { | |
2350 | base->phy_res[i].allocated_src = D40_ALLOC_FREE; | |
2351 | base->phy_res[i].allocated_dst = D40_ALLOC_FREE; | |
2352 | num_phy_chans_avail++; | |
2353 | } | |
2354 | spin_lock_init(&base->phy_res[i].lock); | |
2355 | } | |
6b7acd84 JA |
2356 | |
2357 | /* Mark disabled channels as occupied */ | |
2358 | for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) { | |
f57b407c RV |
2359 | int chan = base->plat_data->disabled_channels[i]; |
2360 | ||
2361 | base->phy_res[chan].allocated_src = D40_ALLOC_PHY; | |
2362 | base->phy_res[chan].allocated_dst = D40_ALLOC_PHY; | |
2363 | num_phy_chans_avail--; | |
6b7acd84 JA |
2364 | } |
2365 | ||
8d318a50 LW |
2366 | dev_info(base->dev, "%d of %d physical DMA channels available\n", |
2367 | num_phy_chans_avail, base->num_phy_chans); | |
2368 | ||
2369 | /* Verify settings extended vs standard */ | |
2370 | val[0] = readl(base->virtbase + D40_DREG_PRTYP); | |
2371 | ||
2372 | for (i = 0; i < base->num_phy_chans; i++) { | |
2373 | ||
2374 | if (base->phy_res[i].allocated_src == D40_ALLOC_FREE && | |
2375 | (val[0] & 0x3) != 1) | |
2376 | dev_info(base->dev, | |
2377 | "[%s] INFO: channel %d is misconfigured (%d)\n", | |
2378 | __func__, i, val[0] & 0x3); | |
2379 | ||
2380 | val[0] = val[0] >> 2; | |
2381 | } | |
2382 | ||
2383 | return num_phy_chans_avail; | |
2384 | } | |
2385 | ||
2386 | static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) | |
2387 | { | |
2388 | static const struct d40_reg_val dma_id_regs[] = { | |
2389 | /* Peripheral Id */ | |
2390 | { .reg = D40_DREG_PERIPHID0, .val = 0x0040}, | |
2391 | { .reg = D40_DREG_PERIPHID1, .val = 0x0000}, | |
2392 | /* | |
2393 | * D40_DREG_PERIPHID2 Depends on HW revision: | |
4d594900 | 2394 | * DB8500ed has 0x0008, |
8d318a50 | 2395 | * ? has 0x0018, |
4d594900 RV |
2396 | * DB8500v1 has 0x0028 |
2397 | * DB8500v2 has 0x0038 | |
8d318a50 LW |
2398 | */ |
2399 | { .reg = D40_DREG_PERIPHID3, .val = 0x0000}, | |
2400 | ||
2401 | /* PCell Id */ | |
2402 | { .reg = D40_DREG_CELLID0, .val = 0x000d}, | |
2403 | { .reg = D40_DREG_CELLID1, .val = 0x00f0}, | |
2404 | { .reg = D40_DREG_CELLID2, .val = 0x0005}, | |
2405 | { .reg = D40_DREG_CELLID3, .val = 0x00b1} | |
2406 | }; | |
2407 | struct stedma40_platform_data *plat_data; | |
2408 | struct clk *clk = NULL; | |
2409 | void __iomem *virtbase = NULL; | |
2410 | struct resource *res = NULL; | |
2411 | struct d40_base *base = NULL; | |
2412 | int num_log_chans = 0; | |
2413 | int num_phy_chans; | |
2414 | int i; | |
f4185592 | 2415 | u32 val; |
3ae0267f | 2416 | u32 rev; |
8d318a50 LW |
2417 | |
2418 | clk = clk_get(&pdev->dev, NULL); | |
2419 | ||
2420 | if (IS_ERR(clk)) { | |
6db5a8ba | 2421 | d40_err(&pdev->dev, "No matching clock found\n"); |
8d318a50 LW |
2422 | goto failure; |
2423 | } | |
2424 | ||
2425 | clk_enable(clk); | |
2426 | ||
2427 | /* Get IO for DMAC base address */ | |
2428 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base"); | |
2429 | if (!res) | |
2430 | goto failure; | |
2431 | ||
2432 | if (request_mem_region(res->start, resource_size(res), | |
2433 | D40_NAME " I/O base") == NULL) | |
2434 | goto failure; | |
2435 | ||
2436 | virtbase = ioremap(res->start, resource_size(res)); | |
2437 | if (!virtbase) | |
2438 | goto failure; | |
2439 | ||
2440 | /* HW version check */ | |
2441 | for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) { | |
2442 | if (dma_id_regs[i].val != | |
2443 | readl(virtbase + dma_id_regs[i].reg)) { | |
6db5a8ba RV |
2444 | d40_err(&pdev->dev, |
2445 | "Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n", | |
8d318a50 LW |
2446 | dma_id_regs[i].val, |
2447 | dma_id_regs[i].reg, | |
2448 | readl(virtbase + dma_id_regs[i].reg)); | |
2449 | goto failure; | |
2450 | } | |
2451 | } | |
2452 | ||
3ae0267f | 2453 | /* Get silicon revision and designer */ |
f4185592 | 2454 | val = readl(virtbase + D40_DREG_PERIPHID2); |
8d318a50 | 2455 | |
3ae0267f JA |
2456 | if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) != |
2457 | D40_HW_DESIGNER) { | |
6db5a8ba RV |
2458 | d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n", |
2459 | val & D40_DREG_PERIPHID2_DESIGNER_MASK, | |
3ae0267f | 2460 | D40_HW_DESIGNER); |
8d318a50 LW |
2461 | goto failure; |
2462 | } | |
2463 | ||
3ae0267f JA |
2464 | rev = (val & D40_DREG_PERIPHID2_REV_MASK) >> |
2465 | D40_DREG_PERIPHID2_REV_POS; | |
2466 | ||
8d318a50 LW |
2467 | /* The number of physical channels on this HW */ |
2468 | num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4; | |
2469 | ||
2470 | dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n", | |
3ae0267f | 2471 | rev, res->start); |
8d318a50 LW |
2472 | |
2473 | plat_data = pdev->dev.platform_data; | |
2474 | ||
2475 | /* Count the number of logical channels in use */ | |
2476 | for (i = 0; i < plat_data->dev_len; i++) | |
2477 | if (plat_data->dev_rx[i] != 0) | |
2478 | num_log_chans++; | |
2479 | ||
2480 | for (i = 0; i < plat_data->dev_len; i++) | |
2481 | if (plat_data->dev_tx[i] != 0) | |
2482 | num_log_chans++; | |
2483 | ||
2484 | base = kzalloc(ALIGN(sizeof(struct d40_base), 4) + | |
2485 | (num_phy_chans + num_log_chans + plat_data->memcpy_len) * | |
2486 | sizeof(struct d40_chan), GFP_KERNEL); | |
2487 | ||
2488 | if (base == NULL) { | |
6db5a8ba | 2489 | d40_err(&pdev->dev, "Out of memory\n"); |
8d318a50 LW |
2490 | goto failure; |
2491 | } | |
2492 | ||
3ae0267f | 2493 | base->rev = rev; |
8d318a50 LW |
2494 | base->clk = clk; |
2495 | base->num_phy_chans = num_phy_chans; | |
2496 | base->num_log_chans = num_log_chans; | |
2497 | base->phy_start = res->start; | |
2498 | base->phy_size = resource_size(res); | |
2499 | base->virtbase = virtbase; | |
2500 | base->plat_data = plat_data; | |
2501 | base->dev = &pdev->dev; | |
2502 | base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4); | |
2503 | base->log_chans = &base->phy_chans[num_phy_chans]; | |
2504 | ||
2505 | base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res), | |
2506 | GFP_KERNEL); | |
2507 | if (!base->phy_res) | |
2508 | goto failure; | |
2509 | ||
2510 | base->lookup_phy_chans = kzalloc(num_phy_chans * | |
2511 | sizeof(struct d40_chan *), | |
2512 | GFP_KERNEL); | |
2513 | if (!base->lookup_phy_chans) | |
2514 | goto failure; | |
2515 | ||
2516 | if (num_log_chans + plat_data->memcpy_len) { | |
2517 | /* | |
2518 | * The max number of logical channels are event lines for all | |
2519 | * src devices and dst devices | |
2520 | */ | |
2521 | base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 * | |
2522 | sizeof(struct d40_chan *), | |
2523 | GFP_KERNEL); | |
2524 | if (!base->lookup_log_chans) | |
2525 | goto failure; | |
2526 | } | |
698e4732 JA |
2527 | |
2528 | base->lcla_pool.alloc_map = kzalloc(num_phy_chans * | |
2529 | sizeof(struct d40_desc *) * | |
2530 | D40_LCLA_LINK_PER_EVENT_GRP, | |
8d318a50 LW |
2531 | GFP_KERNEL); |
2532 | if (!base->lcla_pool.alloc_map) | |
2533 | goto failure; | |
2534 | ||
c675b1b4 JA |
2535 | base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc), |
2536 | 0, SLAB_HWCACHE_ALIGN, | |
2537 | NULL); | |
2538 | if (base->desc_slab == NULL) | |
2539 | goto failure; | |
2540 | ||
8d318a50 LW |
2541 | return base; |
2542 | ||
2543 | failure: | |
c6134c96 | 2544 | if (!IS_ERR(clk)) { |
8d318a50 LW |
2545 | clk_disable(clk); |
2546 | clk_put(clk); | |
2547 | } | |
2548 | if (virtbase) | |
2549 | iounmap(virtbase); | |
2550 | if (res) | |
2551 | release_mem_region(res->start, | |
2552 | resource_size(res)); | |
2553 | if (virtbase) | |
2554 | iounmap(virtbase); | |
2555 | ||
2556 | if (base) { | |
2557 | kfree(base->lcla_pool.alloc_map); | |
2558 | kfree(base->lookup_log_chans); | |
2559 | kfree(base->lookup_phy_chans); | |
2560 | kfree(base->phy_res); | |
2561 | kfree(base); | |
2562 | } | |
2563 | ||
2564 | return NULL; | |
2565 | } | |
2566 | ||
2567 | static void __init d40_hw_init(struct d40_base *base) | |
2568 | { | |
2569 | ||
2570 | static const struct d40_reg_val dma_init_reg[] = { | |
2571 | /* Clock every part of the DMA block from start */ | |
2572 | { .reg = D40_DREG_GCC, .val = 0x0000ff01}, | |
2573 | ||
2574 | /* Interrupts on all logical channels */ | |
2575 | { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF}, | |
2576 | { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF}, | |
2577 | { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF}, | |
2578 | { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF}, | |
2579 | { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF}, | |
2580 | { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF}, | |
2581 | { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF}, | |
2582 | { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF}, | |
2583 | { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF}, | |
2584 | { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF}, | |
2585 | { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF}, | |
2586 | { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF} | |
2587 | }; | |
2588 | int i; | |
2589 | u32 prmseo[2] = {0, 0}; | |
2590 | u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF}; | |
2591 | u32 pcmis = 0; | |
2592 | u32 pcicr = 0; | |
2593 | ||
2594 | for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++) | |
2595 | writel(dma_init_reg[i].val, | |
2596 | base->virtbase + dma_init_reg[i].reg); | |
2597 | ||
2598 | /* Configure all our dma channels to default settings */ | |
2599 | for (i = 0; i < base->num_phy_chans; i++) { | |
2600 | ||
2601 | activeo[i % 2] = activeo[i % 2] << 2; | |
2602 | ||
2603 | if (base->phy_res[base->num_phy_chans - i - 1].allocated_src | |
2604 | == D40_ALLOC_PHY) { | |
2605 | activeo[i % 2] |= 3; | |
2606 | continue; | |
2607 | } | |
2608 | ||
2609 | /* Enable interrupt # */ | |
2610 | pcmis = (pcmis << 1) | 1; | |
2611 | ||
2612 | /* Clear interrupt # */ | |
2613 | pcicr = (pcicr << 1) | 1; | |
2614 | ||
2615 | /* Set channel to physical mode */ | |
2616 | prmseo[i % 2] = prmseo[i % 2] << 2; | |
2617 | prmseo[i % 2] |= 1; | |
2618 | ||
2619 | } | |
2620 | ||
2621 | writel(prmseo[1], base->virtbase + D40_DREG_PRMSE); | |
2622 | writel(prmseo[0], base->virtbase + D40_DREG_PRMSO); | |
2623 | writel(activeo[1], base->virtbase + D40_DREG_ACTIVE); | |
2624 | writel(activeo[0], base->virtbase + D40_DREG_ACTIVO); | |
2625 | ||
2626 | /* Write which interrupt to enable */ | |
2627 | writel(pcmis, base->virtbase + D40_DREG_PCMIS); | |
2628 | ||
2629 | /* Write which interrupt to clear */ | |
2630 | writel(pcicr, base->virtbase + D40_DREG_PCICR); | |
2631 | ||
2632 | } | |
2633 | ||
508849ad LW |
2634 | static int __init d40_lcla_allocate(struct d40_base *base) |
2635 | { | |
026cbc42 | 2636 | struct d40_lcla_pool *pool = &base->lcla_pool; |
508849ad LW |
2637 | unsigned long *page_list; |
2638 | int i, j; | |
2639 | int ret = 0; | |
2640 | ||
2641 | /* | |
2642 | * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned, | |
2643 | * To full fill this hardware requirement without wasting 256 kb | |
2644 | * we allocate pages until we get an aligned one. | |
2645 | */ | |
2646 | page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS, | |
2647 | GFP_KERNEL); | |
2648 | ||
2649 | if (!page_list) { | |
2650 | ret = -ENOMEM; | |
2651 | goto failure; | |
2652 | } | |
2653 | ||
2654 | /* Calculating how many pages that are required */ | |
2655 | base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE; | |
2656 | ||
2657 | for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) { | |
2658 | page_list[i] = __get_free_pages(GFP_KERNEL, | |
2659 | base->lcla_pool.pages); | |
2660 | if (!page_list[i]) { | |
2661 | ||
6db5a8ba RV |
2662 | d40_err(base->dev, "Failed to allocate %d pages.\n", |
2663 | base->lcla_pool.pages); | |
508849ad LW |
2664 | |
2665 | for (j = 0; j < i; j++) | |
2666 | free_pages(page_list[j], base->lcla_pool.pages); | |
2667 | goto failure; | |
2668 | } | |
2669 | ||
2670 | if ((virt_to_phys((void *)page_list[i]) & | |
2671 | (LCLA_ALIGNMENT - 1)) == 0) | |
2672 | break; | |
2673 | } | |
2674 | ||
2675 | for (j = 0; j < i; j++) | |
2676 | free_pages(page_list[j], base->lcla_pool.pages); | |
2677 | ||
2678 | if (i < MAX_LCLA_ALLOC_ATTEMPTS) { | |
2679 | base->lcla_pool.base = (void *)page_list[i]; | |
2680 | } else { | |
767a9675 JA |
2681 | /* |
2682 | * After many attempts and no succees with finding the correct | |
2683 | * alignment, try with allocating a big buffer. | |
2684 | */ | |
508849ad LW |
2685 | dev_warn(base->dev, |
2686 | "[%s] Failed to get %d pages @ 18 bit align.\n", | |
2687 | __func__, base->lcla_pool.pages); | |
2688 | base->lcla_pool.base_unaligned = kmalloc(SZ_1K * | |
2689 | base->num_phy_chans + | |
2690 | LCLA_ALIGNMENT, | |
2691 | GFP_KERNEL); | |
2692 | if (!base->lcla_pool.base_unaligned) { | |
2693 | ret = -ENOMEM; | |
2694 | goto failure; | |
2695 | } | |
2696 | ||
2697 | base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned, | |
2698 | LCLA_ALIGNMENT); | |
2699 | } | |
2700 | ||
026cbc42 RV |
2701 | pool->dma_addr = dma_map_single(base->dev, pool->base, |
2702 | SZ_1K * base->num_phy_chans, | |
2703 | DMA_TO_DEVICE); | |
2704 | if (dma_mapping_error(base->dev, pool->dma_addr)) { | |
2705 | pool->dma_addr = 0; | |
2706 | ret = -ENOMEM; | |
2707 | goto failure; | |
2708 | } | |
2709 | ||
508849ad LW |
2710 | writel(virt_to_phys(base->lcla_pool.base), |
2711 | base->virtbase + D40_DREG_LCLA); | |
2712 | failure: | |
2713 | kfree(page_list); | |
2714 | return ret; | |
2715 | } | |
2716 | ||
8d318a50 LW |
2717 | static int __init d40_probe(struct platform_device *pdev) |
2718 | { | |
2719 | int err; | |
2720 | int ret = -ENOENT; | |
2721 | struct d40_base *base; | |
2722 | struct resource *res = NULL; | |
2723 | int num_reserved_chans; | |
2724 | u32 val; | |
2725 | ||
2726 | base = d40_hw_detect_init(pdev); | |
2727 | ||
2728 | if (!base) | |
2729 | goto failure; | |
2730 | ||
2731 | num_reserved_chans = d40_phy_res_init(base); | |
2732 | ||
2733 | platform_set_drvdata(pdev, base); | |
2734 | ||
2735 | spin_lock_init(&base->interrupt_lock); | |
2736 | spin_lock_init(&base->execmd_lock); | |
2737 | ||
2738 | /* Get IO for logical channel parameter address */ | |
2739 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa"); | |
2740 | if (!res) { | |
2741 | ret = -ENOENT; | |
6db5a8ba | 2742 | d40_err(&pdev->dev, "No \"lcpa\" memory resource\n"); |
8d318a50 LW |
2743 | goto failure; |
2744 | } | |
2745 | base->lcpa_size = resource_size(res); | |
2746 | base->phy_lcpa = res->start; | |
2747 | ||
2748 | if (request_mem_region(res->start, resource_size(res), | |
2749 | D40_NAME " I/O lcpa") == NULL) { | |
2750 | ret = -EBUSY; | |
6db5a8ba RV |
2751 | d40_err(&pdev->dev, |
2752 | "Failed to request LCPA region 0x%x-0x%x\n", | |
2753 | res->start, res->end); | |
8d318a50 LW |
2754 | goto failure; |
2755 | } | |
2756 | ||
2757 | /* We make use of ESRAM memory for this. */ | |
2758 | val = readl(base->virtbase + D40_DREG_LCPA); | |
2759 | if (res->start != val && val != 0) { | |
2760 | dev_warn(&pdev->dev, | |
2761 | "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n", | |
2762 | __func__, val, res->start); | |
2763 | } else | |
2764 | writel(res->start, base->virtbase + D40_DREG_LCPA); | |
2765 | ||
2766 | base->lcpa_base = ioremap(res->start, resource_size(res)); | |
2767 | if (!base->lcpa_base) { | |
2768 | ret = -ENOMEM; | |
6db5a8ba | 2769 | d40_err(&pdev->dev, "Failed to ioremap LCPA region\n"); |
8d318a50 LW |
2770 | goto failure; |
2771 | } | |
8d318a50 | 2772 | |
508849ad LW |
2773 | ret = d40_lcla_allocate(base); |
2774 | if (ret) { | |
6db5a8ba | 2775 | d40_err(&pdev->dev, "Failed to allocate LCLA area\n"); |
8d318a50 LW |
2776 | goto failure; |
2777 | } | |
2778 | ||
2779 | spin_lock_init(&base->lcla_pool.lock); | |
2780 | ||
8d318a50 LW |
2781 | base->irq = platform_get_irq(pdev, 0); |
2782 | ||
2783 | ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); | |
8d318a50 | 2784 | if (ret) { |
6db5a8ba | 2785 | d40_err(&pdev->dev, "No IRQ defined\n"); |
8d318a50 LW |
2786 | goto failure; |
2787 | } | |
2788 | ||
2789 | err = d40_dmaengine_init(base, num_reserved_chans); | |
2790 | if (err) | |
2791 | goto failure; | |
2792 | ||
2793 | d40_hw_init(base); | |
2794 | ||
2795 | dev_info(base->dev, "initialized\n"); | |
2796 | return 0; | |
2797 | ||
2798 | failure: | |
2799 | if (base) { | |
c675b1b4 JA |
2800 | if (base->desc_slab) |
2801 | kmem_cache_destroy(base->desc_slab); | |
8d318a50 LW |
2802 | if (base->virtbase) |
2803 | iounmap(base->virtbase); | |
026cbc42 RV |
2804 | |
2805 | if (base->lcla_pool.dma_addr) | |
2806 | dma_unmap_single(base->dev, base->lcla_pool.dma_addr, | |
2807 | SZ_1K * base->num_phy_chans, | |
2808 | DMA_TO_DEVICE); | |
2809 | ||
508849ad LW |
2810 | if (!base->lcla_pool.base_unaligned && base->lcla_pool.base) |
2811 | free_pages((unsigned long)base->lcla_pool.base, | |
2812 | base->lcla_pool.pages); | |
767a9675 JA |
2813 | |
2814 | kfree(base->lcla_pool.base_unaligned); | |
2815 | ||
8d318a50 LW |
2816 | if (base->phy_lcpa) |
2817 | release_mem_region(base->phy_lcpa, | |
2818 | base->lcpa_size); | |
2819 | if (base->phy_start) | |
2820 | release_mem_region(base->phy_start, | |
2821 | base->phy_size); | |
2822 | if (base->clk) { | |
2823 | clk_disable(base->clk); | |
2824 | clk_put(base->clk); | |
2825 | } | |
2826 | ||
2827 | kfree(base->lcla_pool.alloc_map); | |
2828 | kfree(base->lookup_log_chans); | |
2829 | kfree(base->lookup_phy_chans); | |
2830 | kfree(base->phy_res); | |
2831 | kfree(base); | |
2832 | } | |
2833 | ||
6db5a8ba | 2834 | d40_err(&pdev->dev, "probe failed\n"); |
8d318a50 LW |
2835 | return ret; |
2836 | } | |
2837 | ||
2838 | static struct platform_driver d40_driver = { | |
2839 | .driver = { | |
2840 | .owner = THIS_MODULE, | |
2841 | .name = D40_NAME, | |
2842 | }, | |
2843 | }; | |
2844 | ||
cb9ab2d8 | 2845 | static int __init stedma40_init(void) |
8d318a50 LW |
2846 | { |
2847 | return platform_driver_probe(&d40_driver, d40_probe); | |
2848 | } | |
2849 | arch_initcall(stedma40_init); |