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dmaengine: ste_dma40_ll: Replace meaningless register set with comment
[deliverable/linux.git] / drivers / dma / ste_dma40.c
CommitLineData
8d318a50 1/*
d49278e3
PF		 2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
661385f9 4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675 5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50 6 * License terms: GNU General Public License (GPL) version 2
8d318a50
LW		 7 */
8
b7f080cf 9#include <linux/dma-mapping.h>
8d318a50
LW		 10#include <linux/kernel.h>
11#include <linux/slab.h>
f492b210 12#include <linux/export.h>
8d318a50
LW		 13#include <linux/dmaengine.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
7fb3e75e
N		 17#include <linux/pm.h>
18#include <linux/pm_runtime.h>
698e4732 19#include <linux/err.h>
1814a170 20#include <linux/of.h>
fa332de5 21#include <linux/of_dma.h>
f4b89764 22#include <linux/amba/bus.h>
15e4b78d 23#include <linux/regulator/consumer.h>
865fab60 24#include <linux/platform_data/dma-ste-dma40.h>
8d318a50 25
d2ebfb33 26#include "dmaengine.h"
8d318a50
LW		 27#include "ste_dma40_ll.h"
28
29#define D40_NAME "dma40"
30
31#define D40_PHY_CHAN -1
32
33/* For masking out/in 2 bit channel positions */
34#define D40_CHAN_POS(chan) (2 * (chan / 2))
35#define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
36
37/* Maximum iterations taken before giving up suspending a channel */
38#define D40_SUSPEND_MAX_IT 500
39
7fb3e75e
N		 40/* Milliseconds */
41#define DMA40_AUTOSUSPEND_DELAY 100
42
508849ad
LW		 43/* Hardware requirement on LCLA alignment */
44#define LCLA_ALIGNMENT 0x40000
698e4732
JA		 45
46/* Max number of links per event group */
47#define D40_LCLA_LINK_PER_EVENT_GRP 128
48#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
49
db72da92
LJ		 50/* Max number of logical channels per physical channel */
51#define D40_MAX_LOG_CHAN_PER_PHY 32
52
508849ad
LW		 53/* Attempts before giving up to trying to get pages that are aligned */
54#define MAX_LCLA_ALLOC_ATTEMPTS 256
55
56/* Bit markings for allocation map */
8a3b6e14
LJ		 57#define D40_ALLOC_FREE BIT(31)
58#define D40_ALLOC_PHY BIT(30)
8d318a50
LW		 59#define D40_ALLOC_LOG_FREE 0
60
664a57ec 61/* Reserved event lines for memcpy only. */
a2acaa21
LW		 62#define DB8500_DMA_MEMCPY_EV_0 51
63#define DB8500_DMA_MEMCPY_EV_1 56
64#define DB8500_DMA_MEMCPY_EV_2 57
65#define DB8500_DMA_MEMCPY_EV_3 58
66#define DB8500_DMA_MEMCPY_EV_4 59
67#define DB8500_DMA_MEMCPY_EV_5 60
68
69static int dma40_memcpy_channels[] = {
70 DB8500_DMA_MEMCPY_EV_0,
71 DB8500_DMA_MEMCPY_EV_1,
72 DB8500_DMA_MEMCPY_EV_2,
73 DB8500_DMA_MEMCPY_EV_3,
74 DB8500_DMA_MEMCPY_EV_4,
75 DB8500_DMA_MEMCPY_EV_5,
76};
664a57ec 77
29027a1e
LJ		 78/* Default configuration for physcial memcpy */
79struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
80 .mode = STEDMA40_MODE_PHYSICAL,
2c2b62d5 81 .dir = DMA_MEM_TO_MEM,
29027a1e 82
43f2e1a3 83 .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
29027a1e
LJ		 84 .src_info.psize = STEDMA40_PSIZE_PHY_1,
85 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
86
43f2e1a3 87 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
29027a1e
LJ		 88 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
89 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
90};
91
92/* Default configuration for logical memcpy */
93struct stedma40_chan_cfg dma40_memcpy_conf_log = {
94 .mode = STEDMA40_MODE_LOGICAL,
2c2b62d5 95 .dir = DMA_MEM_TO_MEM,
29027a1e 96
43f2e1a3 97 .src_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
29027a1e
LJ		 98 .src_info.psize = STEDMA40_PSIZE_LOG_1,
99 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
100
43f2e1a3 101 .dst_info.data_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
29027a1e
LJ		 102 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
103 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
104};
105
8d318a50
LW		 106/**
107 * enum 40_command - The different commands and/or statuses.
108 *
109 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
110 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
111 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
112 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
113 */
114enum d40_command {
115 D40_DMA_STOP = 0,
116 D40_DMA_RUN = 1,
117 D40_DMA_SUSPEND_REQ = 2,
118 D40_DMA_SUSPENDED = 3
119};
120
1bdae6f4
N		 121/*
122 * enum d40_events - The different Event Enables for the event lines.
123 *
124 * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
125 * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
126 * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
127 * @D40_ROUND_EVENTLINE: Status check for event line.
128 */
129
130enum d40_events {
131 D40_DEACTIVATE_EVENTLINE = 0,
132 D40_ACTIVATE_EVENTLINE = 1,
133 D40_SUSPEND_REQ_EVENTLINE = 2,
134 D40_ROUND_EVENTLINE = 3
135};
136
7fb3e75e
N		 137/*
138 * These are the registers that has to be saved and later restored
139 * when the DMA hw is powered off.
140 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
141 */
142static u32 d40_backup_regs[] = {
143 D40_DREG_LCPA,
144 D40_DREG_LCLA,
145 D40_DREG_PRMSE,
146 D40_DREG_PRMSO,
147 D40_DREG_PRMOE,
148 D40_DREG_PRMOO,
149};
150
151#define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
152
3cb645dc
TL		 153/*
154 * since 9540 and 8540 has the same HW revision
155 * use v4a for 9540 or ealier
156 * use v4b for 8540 or later
157 * HW revision:
158 * DB8500ed has revision 0
159 * DB8500v1 has revision 2
160 * DB8500v2 has revision 3
161 * AP9540v1 has revision 4
162 * DB8540v1 has revision 4
163 * TODO: Check if all these registers have to be saved/restored on dma40 v4a
164 */
165static u32 d40_backup_regs_v4a[] = {
7fb3e75e
N		 166 D40_DREG_PSEG1,
167 D40_DREG_PSEG2,
168 D40_DREG_PSEG3,
169 D40_DREG_PSEG4,
170 D40_DREG_PCEG1,
171 D40_DREG_PCEG2,
172 D40_DREG_PCEG3,
173 D40_DREG_PCEG4,
174 D40_DREG_RSEG1,
175 D40_DREG_RSEG2,
176 D40_DREG_RSEG3,
177 D40_DREG_RSEG4,
178 D40_DREG_RCEG1,
179 D40_DREG_RCEG2,
180 D40_DREG_RCEG3,
181 D40_DREG_RCEG4,
182};
183
3cb645dc
TL		 184#define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a)
185
186static u32 d40_backup_regs_v4b[] = {
187 D40_DREG_CPSEG1,
188 D40_DREG_CPSEG2,
189 D40_DREG_CPSEG3,
190 D40_DREG_CPSEG4,
191 D40_DREG_CPSEG5,
192 D40_DREG_CPCEG1,
193 D40_DREG_CPCEG2,
194 D40_DREG_CPCEG3,
195 D40_DREG_CPCEG4,
196 D40_DREG_CPCEG5,
197 D40_DREG_CRSEG1,
198 D40_DREG_CRSEG2,
199 D40_DREG_CRSEG3,
200 D40_DREG_CRSEG4,
201 D40_DREG_CRSEG5,
202 D40_DREG_CRCEG1,
203 D40_DREG_CRCEG2,
204 D40_DREG_CRCEG3,
205 D40_DREG_CRCEG4,
206 D40_DREG_CRCEG5,
207};
208
209#define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b)
7fb3e75e
N		 210
211static u32 d40_backup_regs_chan[] = {
212 D40_CHAN_REG_SSCFG,
213 D40_CHAN_REG_SSELT,
214 D40_CHAN_REG_SSPTR,
215 D40_CHAN_REG_SSLNK,
216 D40_CHAN_REG_SDCFG,
217 D40_CHAN_REG_SDELT,
218 D40_CHAN_REG_SDPTR,
219 D40_CHAN_REG_SDLNK,
220};
221
84b3da14
LJ		 222#define BACKUP_REGS_SZ_MAX ((BACKUP_REGS_SZ_V4A > BACKUP_REGS_SZ_V4B) ? \
223 BACKUP_REGS_SZ_V4A : BACKUP_REGS_SZ_V4B)
224
3cb645dc
TL		 225/**
226 * struct d40_interrupt_lookup - lookup table for interrupt handler
227 *
228 * @src: Interrupt mask register.
229 * @clr: Interrupt clear register.
230 * @is_error: true if this is an error interrupt.
231 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
232 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
233 */
234struct d40_interrupt_lookup {
235 u32 src;
236 u32 clr;
237 bool is_error;
238 int offset;
239};
240
241
242static struct d40_interrupt_lookup il_v4a[] = {
243 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
244 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
245 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
246 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
247 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
248 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
249 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
250 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
251 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
252 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
253};
254
255static struct d40_interrupt_lookup il_v4b[] = {
256 {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false, 0},
257 {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32},
258 {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64},
259 {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96},
260 {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128},
261 {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true, 0},
262 {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true, 32},
263 {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true, 64},
264 {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true, 96},
265 {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true, 128},
266 {D40_DREG_CPCTIS, D40_DREG_CPCICR, false, D40_PHY_CHAN},
267 {D40_DREG_CPCEIS, D40_DREG_CPCICR, true, D40_PHY_CHAN},
268};
269
270/**
271 * struct d40_reg_val - simple lookup struct
272 *
273 * @reg: The register.
274 * @val: The value that belongs to the register in reg.
275 */
276struct d40_reg_val {
277 unsigned int reg;
278 unsigned int val;
279};
280
281static __initdata struct d40_reg_val dma_init_reg_v4a[] = {
282 /* Clock every part of the DMA block from start */
283 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
284
285 /* Interrupts on all logical channels */
286 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
287 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
288 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
289 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
290 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
291 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
292 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
293 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
294 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
295 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
296 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
297 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
298};
299static __initdata struct d40_reg_val dma_init_reg_v4b[] = {
300 /* Clock every part of the DMA block from start */
301 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
302
303 /* Interrupts on all logical channels */
304 { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF},
305 { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF},
306 { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF},
307 { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF},
308 { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF},
309 { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF},
310 { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF},
311 { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF},
312 { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF},
313 { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF},
314 { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF},
315 { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF},
316 { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF},
317 { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF},
318 { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF}
319};
320
8d318a50
LW		 321/**
322 * struct d40_lli_pool - Structure for keeping LLIs in memory
323 *
324 * @base: Pointer to memory area when the pre_alloc_lli's are not large
325 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
326 * pre_alloc_lli is used.
b00f938c 327 * @dma_addr: DMA address, if mapped
8d318a50
LW		 328 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
329 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
330 * one buffer to one buffer.
331 */
332struct d40_lli_pool {
333 void *base;
508849ad 334 int size;
b00f938c 335 dma_addr_t dma_addr;
8d318a50 336 /* Space for dst and src, plus an extra for padding */
508849ad 337 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
8d318a50
LW		 338};
339
340/**
341 * struct d40_desc - A descriptor is one DMA job.
342 *
343 * @lli_phy: LLI settings for physical channel. Both src and dst=
344 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
345 * lli_len equals one.
346 * @lli_log: Same as above but for logical channels.
347 * @lli_pool: The pool with two entries pre-allocated.
941b77a3 348 * @lli_len: Number of llis of current descriptor.
25985edc 349 * @lli_current: Number of transferred llis.
698e4732 350 * @lcla_alloc: Number of LCLA entries allocated.
8d318a50
LW		 351 * @txd: DMA engine struct. Used for among other things for communication
352 * during a transfer.
353 * @node: List entry.
8d318a50 354 * @is_in_client_list: true if the client owns this descriptor.
7fb3e75e 355 * @cyclic: true if this is a cyclic job
8d318a50
LW		 356 *
357 * This descriptor is used for both logical and physical transfers.
358 */
8d318a50
LW		 359struct d40_desc {
360 /* LLI physical */
361 struct d40_phy_lli_bidir lli_phy;
362 /* LLI logical */
363 struct d40_log_lli_bidir lli_log;
364
365 struct d40_lli_pool lli_pool;
941b77a3 366 int lli_len;
698e4732
JA		 367 int lli_current;
368 int lcla_alloc;
8d318a50
LW		 369
370 struct dma_async_tx_descriptor txd;
371 struct list_head node;
372
8d318a50 373 bool is_in_client_list;
0c842b55 374 bool cyclic;
8d318a50
LW		 375};
376
377/**
378 * struct d40_lcla_pool - LCLA pool settings and data.
379 *
508849ad
LW		 380 * @base: The virtual address of LCLA. 18 bit aligned.
381 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
382 * This pointer is only there for clean-up on error.
383 * @pages: The number of pages needed for all physical channels.
384 * Only used later for clean-up on error
8d318a50 385 * @lock: Lock to protect the content in this struct.
698e4732 386 * @alloc_map: big map over which LCLA entry is own by which job.
8d318a50
LW		 387 */
388struct d40_lcla_pool {
389 void *base;
026cbc42 390 dma_addr_t dma_addr;
508849ad
LW		 391 void *base_unaligned;
392 int pages;
8d318a50 393 spinlock_t lock;
698e4732 394 struct d40_desc **alloc_map;
8d318a50
LW		 395};
396
397/**
398 * struct d40_phy_res - struct for handling eventlines mapped to physical
399 * channels.
400 *
401 * @lock: A lock protection this entity.
7fb3e75e 402 * @reserved: True if used by secure world or otherwise.
8d318a50
LW		 403 * @num: The physical channel number of this entity.
404 * @allocated_src: Bit mapped to show which src event line's are mapped to
405 * this physical channel. Can also be free or physically allocated.
406 * @allocated_dst: Same as for src but is dst.
407 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
767a9675 408 * event line number.
7407048b 409 * @use_soft_lli: To mark if the linked lists of channel are managed by SW.
8d318a50
LW		 410 */
411struct d40_phy_res {
412 spinlock_t lock;
7fb3e75e 413 bool reserved;
8d318a50
LW		 414 int num;
415 u32 allocated_src;
416 u32 allocated_dst;
7407048b 417 bool use_soft_lli;
8d318a50
LW		 418};
419
420struct d40_base;
421
422/**
423 * struct d40_chan - Struct that describes a channel.
424 *
425 * @lock: A spinlock to protect this struct.
426 * @log_num: The logical number, if any of this channel.
8d318a50
LW		 427 * @pending_tx: The number of pending transfers. Used between interrupt handler
428 * and tasklet.
429 * @busy: Set to true when transfer is ongoing on this channel.
2a614340
JA		 430 * @phy_chan: Pointer to physical channel which this instance runs on. If this
431 * point is NULL, then the channel is not allocated.
8d318a50
LW		 432 * @chan: DMA engine handle.
433 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
434 * transfer and call client callback.
435 * @client: Cliented owned descriptor list.
da063d26 436 * @pending_queue: Submitted jobs, to be issued by issue_pending()
8d318a50 437 * @active: Active descriptor.
4226dd86 438 * @done: Completed jobs
8d318a50 439 * @queue: Queued jobs.
82babbb3 440 * @prepare_queue: Prepared jobs.
8d318a50 441 * @dma_cfg: The client configuration of this dma channel.
ce2ca125 442 * @configured: whether the dma_cfg configuration is valid
8d318a50
LW		 443 * @base: Pointer to the device instance struct.
444 * @src_def_cfg: Default cfg register setting for src.
445 * @dst_def_cfg: Default cfg register setting for dst.
446 * @log_def: Default logical channel settings.
8d318a50 447 * @lcpa: Pointer to dst and src lcpa settings.
ae752bf4 448 * @runtime_addr: runtime configured address.
449 * @runtime_direction: runtime configured direction.
8d318a50
LW		 450 *
451 * This struct can either "be" a logical or a physical channel.
452 */
453struct d40_chan {
454 spinlock_t lock;
455 int log_num;
8d318a50
LW		 456 int pending_tx;
457 bool busy;
458 struct d40_phy_res *phy_chan;
459 struct dma_chan chan;
460 struct tasklet_struct tasklet;
461 struct list_head client;
a8f3067b 462 struct list_head pending_queue;
8d318a50 463 struct list_head active;
4226dd86 464 struct list_head done;
8d318a50 465 struct list_head queue;
82babbb3 466 struct list_head prepare_queue;
8d318a50 467 struct stedma40_chan_cfg dma_cfg;
ce2ca125 468 bool configured;
8d318a50
LW		 469 struct d40_base *base;
470 /* Default register configurations */
471 u32 src_def_cfg;
472 u32 dst_def_cfg;
473 struct d40_def_lcsp log_def;
8d318a50 474 struct d40_log_lli_full *lcpa;
95e1400f
LW		 475 /* Runtime reconfiguration */
476 dma_addr_t runtime_addr;
db8196df 477 enum dma_transfer_direction runtime_direction;
8d318a50
LW		 478};
479
3cb645dc
TL		 480/**
481 * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA
482 * controller
483 *
484 * @backup: the pointer to the registers address array for backup
485 * @backup_size: the size of the registers address array for backup
486 * @realtime_en: the realtime enable register
487 * @realtime_clear: the realtime clear register
488 * @high_prio_en: the high priority enable register
489 * @high_prio_clear: the high priority clear register
490 * @interrupt_en: the interrupt enable register
491 * @interrupt_clear: the interrupt clear register
492 * @il: the pointer to struct d40_interrupt_lookup
493 * @il_size: the size of d40_interrupt_lookup array
494 * @init_reg: the pointer to the struct d40_reg_val
495 * @init_reg_size: the size of d40_reg_val array
496 */
497struct d40_gen_dmac {
498 u32 *backup;
499 u32 backup_size;
500 u32 realtime_en;
501 u32 realtime_clear;
502 u32 high_prio_en;
503 u32 high_prio_clear;
504 u32 interrupt_en;
505 u32 interrupt_clear;
506 struct d40_interrupt_lookup *il;
507 u32 il_size;
508 struct d40_reg_val *init_reg;
509 u32 init_reg_size;
510};
511
8d318a50
LW		 512/**
513 * struct d40_base - The big global struct, one for each probe'd instance.
514 *
515 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
516 * @execmd_lock: Lock for execute command usage since several channels share
517 * the same physical register.
518 * @dev: The device structure.
519 * @virtbase: The virtual base address of the DMA's register.
f4185592 520 * @rev: silicon revision detected.
8d318a50
LW		 521 * @clk: Pointer to the DMA clock structure.
522 * @phy_start: Physical memory start of the DMA registers.
523 * @phy_size: Size of the DMA register map.
524 * @irq: The IRQ number.
525 * @num_phy_chans: The number of physical channels. Read from HW. This
526 * is the number of available channels for this driver, not counting "Secure
527 * mode" allocated physical channels.
528 * @num_log_chans: The number of logical channels. Calculated from
529 * num_phy_chans.
530 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
531 * @dma_slave: dma_device channels that can do only do slave transfers.
532 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
7fb3e75e 533 * @phy_chans: Room for all possible physical channels in system.
8d318a50
LW		 534 * @log_chans: Room for all possible logical channels in system.
535 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
536 * to log_chans entries.
537 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
538 * to phy_chans entries.
539 * @plat_data: Pointer to provided platform_data which is the driver
540 * configuration.
28c7a19d 541 * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
8d318a50
LW		 542 * @phy_res: Vector containing all physical channels.
543 * @lcla_pool: lcla pool settings and data.
544 * @lcpa_base: The virtual mapped address of LCPA.
545 * @phy_lcpa: The physical address of the LCPA.
546 * @lcpa_size: The size of the LCPA area.
c675b1b4 547 * @desc_slab: cache for descriptors.
7fb3e75e
N		 548 * @reg_val_backup: Here the values of some hardware registers are stored
549 * before the DMA is powered off. They are restored when the power is back on.
3cb645dc
TL		 550 * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and
551 * later
7fb3e75e
N		 552 * @reg_val_backup_chan: Backup data for standard channel parameter registers.
553 * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
554 * @initialized: true if the dma has been initialized
3cb645dc
TL		 555 * @gen_dmac: the struct for generic registers values to represent u8500/8540
556 * DMA controller
8d318a50
LW		 557 */
558struct d40_base {
559 spinlock_t interrupt_lock;
560 spinlock_t execmd_lock;
561 struct device *dev;
562 void __iomem *virtbase;
f4185592 563 u8 rev:4;
8d318a50
LW		 564 struct clk *clk;
565 phys_addr_t phy_start;
566 resource_size_t phy_size;
567 int irq;
568 int num_phy_chans;
569 int num_log_chans;
b96710e5 570 struct device_dma_parameters dma_parms;
8d318a50
LW		 571 struct dma_device dma_both;
572 struct dma_device dma_slave;
573 struct dma_device dma_memcpy;
574 struct d40_chan *phy_chans;
575 struct d40_chan *log_chans;
576 struct d40_chan **lookup_log_chans;
577 struct d40_chan **lookup_phy_chans;
578 struct stedma40_platform_data *plat_data;
28c7a19d 579 struct regulator *lcpa_regulator;
8d318a50
LW		 580 /* Physical half channels */
581 struct d40_phy_res *phy_res;
582 struct d40_lcla_pool lcla_pool;
583 void *lcpa_base;
584 dma_addr_t phy_lcpa;
585 resource_size_t lcpa_size;
c675b1b4 586 struct kmem_cache *desc_slab;
7fb3e75e 587 u32 reg_val_backup[BACKUP_REGS_SZ];
84b3da14 588 u32 reg_val_backup_v4[BACKUP_REGS_SZ_MAX];
7fb3e75e
N		 589 u32 *reg_val_backup_chan;
590 u16 gcc_pwr_off_mask;
591 bool initialized;
3cb645dc 592 struct d40_gen_dmac gen_dmac;
8d318a50
LW		 593};
594
262d2915
RV		 595static struct device *chan2dev(struct d40_chan *d40c)
596{
597 return &d40c->chan.dev->device;
598}
599
724a8577
RV		 600static bool chan_is_physical(struct d40_chan *chan)
601{
602 return chan->log_num == D40_PHY_CHAN;
603}
604
605static bool chan_is_logical(struct d40_chan *chan)
606{
607 return !chan_is_physical(chan);
608}
609
8ca84687
RV		 610static void __iomem *chan_base(struct d40_chan *chan)
611{
612 return chan->base->virtbase + D40_DREG_PCBASE +
613 chan->phy_chan->num * D40_DREG_PCDELTA;
614}
615
6db5a8ba
RV		 616#define d40_err(dev, format, arg...) \
617 dev_err(dev, "[%s] " format, __func__, ## arg)
618
619#define chan_err(d40c, format, arg...) \
620 d40_err(chan2dev(d40c), format, ## arg)
621
b00f938c 622static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
dbd88788 623 int lli_len)
8d318a50 624{
dbd88788 625 bool is_log = chan_is_logical(d40c);
8d318a50
LW		 626 u32 align;
627 void *base;
628
629 if (is_log)
630 align = sizeof(struct d40_log_lli);
631 else
632 align = sizeof(struct d40_phy_lli);
633
634 if (lli_len == 1) {
635 base = d40d->lli_pool.pre_alloc_lli;
636 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
637 d40d->lli_pool.base = NULL;
638 } else {
594ece4d 639 d40d->lli_pool.size = lli_len * 2 * align;
8d318a50
LW		 640
641 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
642 d40d->lli_pool.base = base;
643
644 if (d40d->lli_pool.base == NULL)
645 return -ENOMEM;
646 }
647
648 if (is_log) {
d924abad 649 d40d->lli_log.src = PTR_ALIGN(base, align);
594ece4d 650 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
b00f938c
RV		 651
652 d40d->lli_pool.dma_addr = 0;
8d318a50 653 } else {
d924abad 654 d40d->lli_phy.src = PTR_ALIGN(base, align);
594ece4d 655 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
b00f938c
RV		 656
657 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
658 d40d->lli_phy.src,
659 d40d->lli_pool.size,
660 DMA_TO_DEVICE);
661
662 if (dma_mapping_error(d40c->base->dev,
663 d40d->lli_pool.dma_addr)) {
664 kfree(d40d->lli_pool.base);
665 d40d->lli_pool.base = NULL;
666 d40d->lli_pool.dma_addr = 0;
667 return -ENOMEM;
668 }
8d318a50
LW		 669 }
670
671 return 0;
672}
673
b00f938c 674static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
8d318a50 675{
b00f938c
RV		 676 if (d40d->lli_pool.dma_addr)
677 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
678 d40d->lli_pool.size, DMA_TO_DEVICE);
679
8d318a50
LW		 680 kfree(d40d->lli_pool.base);
681 d40d->lli_pool.base = NULL;
682 d40d->lli_pool.size = 0;
683 d40d->lli_log.src = NULL;
684 d40d->lli_log.dst = NULL;
685 d40d->lli_phy.src = NULL;
686 d40d->lli_phy.dst = NULL;
8d318a50
LW		 687}
688
698e4732
JA		 689static int d40_lcla_alloc_one(struct d40_chan *d40c,
690 struct d40_desc *d40d)
691{
692 unsigned long flags;
693 int i;
694 int ret = -EINVAL;
698e4732
JA		 695
696 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
697
698e4732
JA		 698 /*
699 * Allocate both src and dst at the same time, therefore the half
700 * start on 1 since 0 can't be used since zero is used as end marker.
701 */
702 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
7ce529ef
FB		 703 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
704
705 if (!d40c->base->lcla_pool.alloc_map[idx]) {
706 d40c->base->lcla_pool.alloc_map[idx] = d40d;
698e4732
JA		 707 d40d->lcla_alloc++;
708 ret = i;
709 break;
710 }
711 }
712
713 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
714
715 return ret;
716}
717
718static int d40_lcla_free_all(struct d40_chan *d40c,
719 struct d40_desc *d40d)
720{
721 unsigned long flags;
722 int i;
723 int ret = -EINVAL;
724
724a8577 725 if (chan_is_physical(d40c))
698e4732
JA		 726 return 0;
727
728 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
729
730 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
7ce529ef
FB		 731 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
732
733 if (d40c->base->lcla_pool.alloc_map[idx] == d40d) {
734 d40c->base->lcla_pool.alloc_map[idx] = NULL;
698e4732
JA		 735 d40d->lcla_alloc--;
736 if (d40d->lcla_alloc == 0) {
737 ret = 0;
738 break;
739 }
740 }
741 }
742
743 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
744
745 return ret;
746
747}
748
8d318a50
LW		 749static void d40_desc_remove(struct d40_desc *d40d)
750{
751 list_del(&d40d->node);
752}
753
754static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
755{
a2c15fa4 756 struct d40_desc *desc = NULL;
8d318a50
LW		 757
758 if (!list_empty(&d40c->client)) {
a2c15fa4
RV		 759 struct d40_desc *d;
760 struct d40_desc *_d;
761
7fb3e75e 762 list_for_each_entry_safe(d, _d, &d40c->client, node) {
8d318a50 763 if (async_tx_test_ack(&d->txd)) {
8d318a50 764 d40_desc_remove(d);
a2c15fa4
RV		 765 desc = d;
766 memset(desc, 0, sizeof(*desc));
c675b1b4 767 break;
8d318a50 768 }
7fb3e75e 769 }
8d318a50 770 }
a2c15fa4
RV		 771
772 if (!desc)
773 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
774
775 if (desc)
776 INIT_LIST_HEAD(&desc->node);
777
778 return desc;
8d318a50
LW		 779}
780
781static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
782{
698e4732 783
b00f938c 784 d40_pool_lli_free(d40c, d40d);
698e4732 785 d40_lcla_free_all(d40c, d40d);
c675b1b4 786 kmem_cache_free(d40c->base->desc_slab, d40d);
8d318a50
LW		 787}
788
789static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
790{
791 list_add_tail(&desc->node, &d40c->active);
792}
793
1c4b0927
RV		 794static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
795{
796 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
797 struct d40_phy_lli *lli_src = desc->lli_phy.src;
798 void __iomem *base = chan_base(chan);
799
800 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
801 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
802 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
803 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
804
805 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
806 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
807 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
808 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
809}
810
4226dd86
FB		 811static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc)
812{
813 list_add_tail(&desc->node, &d40c->done);
814}
815
e65889c7 816static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
698e4732 817{
e65889c7
RV		 818 struct d40_lcla_pool *pool = &chan->base->lcla_pool;
819 struct d40_log_lli_bidir *lli = &desc->lli_log;
820 int lli_current = desc->lli_current;
821 int lli_len = desc->lli_len;
0c842b55 822 bool cyclic = desc->cyclic;
e65889c7 823 int curr_lcla = -EINVAL;
0c842b55 824 int first_lcla = 0;
28c7a19d 825 bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
0c842b55 826 bool linkback;
e65889c7 827
0c842b55
RV		 828 /*
829 * We may have partially running cyclic transfers, in case we did't get
830 * enough LCLA entries.
831 */
832 linkback = cyclic && lli_current == 0;
833
834 /*
835 * For linkback, we need one LCLA even with only one link, because we
836 * can't link back to the one in LCPA space
837 */
838 if (linkback || (lli_len - lli_current > 1)) {
7407048b
FB		 839 /*
840 * If the channel is expected to use only soft_lli don't
841 * allocate a lcla. This is to avoid a HW issue that exists
842 * in some controller during a peripheral to memory transfer
843 * that uses linked lists.
844 */
845 if (!(chan->phy_chan->use_soft_lli &&
2c2b62d5 846 chan->dma_cfg.dir == DMA_DEV_TO_MEM))
7407048b
FB		 847 curr_lcla = d40_lcla_alloc_one(chan, desc);
848
0c842b55
RV		 849 first_lcla = curr_lcla;
850 }
851
852 /*
853 * For linkback, we normally load the LCPA in the loop since we need to
854 * link it to the second LCLA and not the first. However, if we
855 * couldn't even get a first LCLA, then we have to run in LCPA and
856 * reload manually.
857 */
858 if (!linkback || curr_lcla == -EINVAL) {
859 unsigned int flags = 0;
e65889c7 860
0c842b55
RV		 861 if (curr_lcla == -EINVAL)
862 flags |= LLI_TERM_INT;
e65889c7 863
0c842b55
RV		 864 d40_log_lli_lcpa_write(chan->lcpa,
865 &lli->dst[lli_current],
866 &lli->src[lli_current],
867 curr_lcla,
868 flags);
869 lli_current++;
870 }
6045f0bb
RV		 871
872 if (curr_lcla < 0)
873 goto out;
874
e65889c7
RV		 875 for (; lli_current < lli_len; lli_current++) {
876 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
877 8 * curr_lcla * 2;
878 struct d40_log_lli *lcla = pool->base + lcla_offset;
0c842b55 879 unsigned int flags = 0;
e65889c7
RV		 880 int next_lcla;
881
882 if (lli_current + 1 < lli_len)
883 next_lcla = d40_lcla_alloc_one(chan, desc);
884 else
0c842b55
RV		 885 next_lcla = linkback ? first_lcla : -EINVAL;
886
887 if (cyclic || next_lcla == -EINVAL)
888 flags |= LLI_TERM_INT;
e65889c7 889
0c842b55
RV		 890 if (linkback && curr_lcla == first_lcla) {
891 /* First link goes in both LCPA and LCLA */
892 d40_log_lli_lcpa_write(chan->lcpa,
893 &lli->dst[lli_current],
894 &lli->src[lli_current],
895 next_lcla, flags);
896 }
897
898 /*
899 * One unused LCLA in the cyclic case if the very first
900 * next_lcla fails...
901 */
e65889c7
RV		 902 d40_log_lli_lcla_write(lcla,
903 &lli->dst[lli_current],
904 &lli->src[lli_current],
0c842b55 905 next_lcla, flags);
e65889c7 906
28c7a19d
N		 907 /*
908 * Cache maintenance is not needed if lcla is
909 * mapped in esram
910 */
911 if (!use_esram_lcla) {
912 dma_sync_single_range_for_device(chan->base->dev,
913 pool->dma_addr, lcla_offset,
914 2 * sizeof(struct d40_log_lli),
915 DMA_TO_DEVICE);
916 }
e65889c7
RV		 917 curr_lcla = next_lcla;
918
0c842b55 919 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
e65889c7
RV		 920 lli_current++;
921 break;
922 }
923 }
924
6045f0bb 925out:
e65889c7
RV		 926 desc->lli_current = lli_current;
927}
698e4732 928
e65889c7
RV		 929static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
930{
724a8577 931 if (chan_is_physical(d40c)) {
1c4b0927 932 d40_phy_lli_load(d40c, d40d);
698e4732 933 d40d->lli_current = d40d->lli_len;
e65889c7
RV		 934 } else
935 d40_log_lli_to_lcxa(d40c, d40d);
698e4732
JA		 936}
937
8d318a50
LW		 938static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
939{
940 struct d40_desc *d;
941
942 if (list_empty(&d40c->active))
943 return NULL;
944
945 d = list_first_entry(&d40c->active,
946 struct d40_desc,
947 node);
948 return d;
949}
950
7404368c 951/* remove desc from current queue and add it to the pending_queue */
8d318a50
LW		 952static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
953{
7404368c
PF		 954 d40_desc_remove(desc);
955 desc->is_in_client_list = false;
a8f3067b
PF		 956 list_add_tail(&desc->node, &d40c->pending_queue);
957}
958
959static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
960{
961 struct d40_desc *d;
962
963 if (list_empty(&d40c->pending_queue))
964 return NULL;
965
966 d = list_first_entry(&d40c->pending_queue,
967 struct d40_desc,
968 node);
969 return d;
8d318a50
LW		 970}
971
972static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
973{
974 struct d40_desc *d;
975
976 if (list_empty(&d40c->queue))
977 return NULL;
978
979 d = list_first_entry(&d40c->queue,
980 struct d40_desc,
981 node);
982 return d;
983}
984
4226dd86
FB		 985static struct d40_desc *d40_first_done(struct d40_chan *d40c)
986{
987 if (list_empty(&d40c->done))
988 return NULL;
989
990 return list_first_entry(&d40c->done, struct d40_desc, node);
991}
992
d49278e3
PF		 993static int d40_psize_2_burst_size(bool is_log, int psize)
994{
995 if (is_log) {
996 if (psize == STEDMA40_PSIZE_LOG_1)
997 return 1;
998 } else {
999 if (psize == STEDMA40_PSIZE_PHY_1)
1000 return 1;
1001 }
1002
1003 return 2 << psize;
1004}
1005
1006/*
1007 * The dma only supports transmitting packages up to
43f2e1a3
LJ		 1008 * STEDMA40_MAX_SEG_SIZE * data_width, where data_width is stored in Bytes.
1009 *
1010 * Calculate the total number of dma elements required to send the entire sg list.
d49278e3
PF		 1011 */
1012static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
1013{
1014 int dmalen;
1015 u32 max_w = max(data_width1, data_width2);
1016 u32 min_w = min(data_width1, data_width2);
43f2e1a3 1017 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE * min_w, max_w);
d49278e3
PF		 1018
1019 if (seg_max > STEDMA40_MAX_SEG_SIZE)
43f2e1a3 1020 seg_max -= max_w;
d49278e3 1021
43f2e1a3 1022 if (!IS_ALIGNED(size, max_w))
d49278e3
PF		 1023 return -EINVAL;
1024
1025 if (size <= seg_max)
1026 dmalen = 1;
1027 else {
1028 dmalen = size / seg_max;
1029 if (dmalen * seg_max < size)
1030 dmalen++;
1031 }
1032 return dmalen;
1033}
1034
1035static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
1036 u32 data_width1, u32 data_width2)
1037{
1038 struct scatterlist *sg;
1039 int i;
1040 int len = 0;
1041 int ret;
1042
1043 for_each_sg(sgl, sg, sg_len, i) {
1044 ret = d40_size_2_dmalen(sg_dma_len(sg),
1045 data_width1, data_width2);
1046 if (ret < 0)
1047 return ret;
1048 len += ret;
1049 }
1050 return len;
1051}
8d318a50 1052
7fb3e75e
N		 1053
1054#ifdef CONFIG_PM
1055static void dma40_backup(void __iomem *baseaddr, u32 *backup,
1056 u32 *regaddr, int num, bool save)
1057{
1058 int i;
1059
1060 for (i = 0; i < num; i++) {
1061 void __iomem *addr = baseaddr + regaddr[i];
1062
1063 if (save)
1064 backup[i] = readl_relaxed(addr);
1065 else
1066 writel_relaxed(backup[i], addr);
1067 }
1068}
1069
1070static void d40_save_restore_registers(struct d40_base *base, bool save)
1071{
1072 int i;
1073
1074 /* Save/Restore channel specific registers */
1075 for (i = 0; i < base->num_phy_chans; i++) {
1076 void __iomem *addr;
1077 int idx;
1078
1079 if (base->phy_res[i].reserved)
1080 continue;
1081
1082 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
1083 idx = i * ARRAY_SIZE(d40_backup_regs_chan);
1084
1085 dma40_backup(addr, &base->reg_val_backup_chan[idx],
1086 d40_backup_regs_chan,
1087 ARRAY_SIZE(d40_backup_regs_chan),
1088 save);
1089 }
1090
1091 /* Save/Restore global registers */
1092 dma40_backup(base->virtbase, base->reg_val_backup,
1093 d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
1094 save);
1095
1096 /* Save/Restore registers only existing on dma40 v3 and later */
3cb645dc
TL		 1097 if (base->gen_dmac.backup)
1098 dma40_backup(base->virtbase, base->reg_val_backup_v4,
1099 base->gen_dmac.backup,
1100 base->gen_dmac.backup_size,
1101 save);
7fb3e75e
N		 1102}
1103#else
1104static void d40_save_restore_registers(struct d40_base *base, bool save)
1105{
1106}
1107#endif
8d318a50 1108
1bdae6f4
N		 1109static int __d40_execute_command_phy(struct d40_chan *d40c,
1110 enum d40_command command)
8d318a50 1111{
767a9675
JA		 1112 u32 status;
1113 int i;
8d318a50
LW		 1114 void __iomem *active_reg;
1115 int ret = 0;
1116 unsigned long flags;
1d392a7b 1117 u32 wmask;
8d318a50 1118
1bdae6f4
N		 1119 if (command == D40_DMA_STOP) {
1120 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
1121 if (ret)
1122 return ret;
1123 }
1124
8d318a50
LW		 1125 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
1126
1127 if (d40c->phy_chan->num % 2 == 0)
1128 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1129 else
1130 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1131
1132 if (command == D40_DMA_SUSPEND_REQ) {
1133 status = (readl(active_reg) &
1134 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1135 D40_CHAN_POS(d40c->phy_chan->num);
1136
1137 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1138 goto done;
1139 }
1140
1d392a7b
JA		 1141 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
1142 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
1143 active_reg);
8d318a50
LW		 1144
1145 if (command == D40_DMA_SUSPEND_REQ) {
1146
1147 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
1148 status = (readl(active_reg) &
1149 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1150 D40_CHAN_POS(d40c->phy_chan->num);
1151
1152 cpu_relax();
1153 /*
1154 * Reduce the number of bus accesses while
1155 * waiting for the DMA to suspend.
1156 */
1157 udelay(3);
1158
1159 if (status == D40_DMA_STOP ||
1160 status == D40_DMA_SUSPENDED)
1161 break;
1162 }
1163
1164 if (i == D40_SUSPEND_MAX_IT) {
6db5a8ba
RV		 1165 chan_err(d40c,
1166 "unable to suspend the chl %d (log: %d) status %x\n",
1167 d40c->phy_chan->num, d40c->log_num,
8d318a50
LW		 1168 status);
1169 dump_stack();
1170 ret = -EBUSY;
1171 }
1172
1173 }
1174done:
1175 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
1176 return ret;
1177}
1178
1179static void d40_term_all(struct d40_chan *d40c)
1180{
1181 struct d40_desc *d40d;
7404368c 1182 struct d40_desc *_d;
8d318a50 1183
4226dd86
FB		 1184 /* Release completed descriptors */
1185 while ((d40d = d40_first_done(d40c))) {
1186 d40_desc_remove(d40d);
1187 d40_desc_free(d40c, d40d);
1188 }
1189
8d318a50
LW		 1190 /* Release active descriptors */
1191 while ((d40d = d40_first_active_get(d40c))) {
1192 d40_desc_remove(d40d);
8d318a50
LW		 1193 d40_desc_free(d40c, d40d);
1194 }
1195
1196 /* Release queued descriptors waiting for transfer */
1197 while ((d40d = d40_first_queued(d40c))) {
1198 d40_desc_remove(d40d);
8d318a50
LW		 1199 d40_desc_free(d40c, d40d);
1200 }
1201
a8f3067b
PF		 1202 /* Release pending descriptors */
1203 while ((d40d = d40_first_pending(d40c))) {
1204 d40_desc_remove(d40d);
1205 d40_desc_free(d40c, d40d);
1206 }
8d318a50 1207
7404368c
PF		 1208 /* Release client owned descriptors */
1209 if (!list_empty(&d40c->client))
1210 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
1211 d40_desc_remove(d40d);
1212 d40_desc_free(d40c, d40d);
1213 }
1214
82babbb3
PF		 1215 /* Release descriptors in prepare queue */
1216 if (!list_empty(&d40c->prepare_queue))
1217 list_for_each_entry_safe(d40d, _d,
1218 &d40c->prepare_queue, node) {
1219 d40_desc_remove(d40d);
1220 d40_desc_free(d40c, d40d);
1221 }
7404368c 1222
8d318a50 1223 d40c->pending_tx = 0;
8d318a50
LW		 1224}
1225
1bdae6f4
N		 1226static void __d40_config_set_event(struct d40_chan *d40c,
1227 enum d40_events event_type, u32 event,
1228 int reg)
262d2915 1229{
8ca84687 1230 void __iomem *addr = chan_base(d40c) + reg;
262d2915 1231 int tries;
1bdae6f4
N		 1232 u32 status;
1233
1234 switch (event_type) {
1235
1236 case D40_DEACTIVATE_EVENTLINE:
262d2915 1237
262d2915
RV		 1238 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
1239 | ~D40_EVENTLINE_MASK(event), addr);
1bdae6f4
N		 1240 break;
1241
1242 case D40_SUSPEND_REQ_EVENTLINE:
1243 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1244 D40_EVENTLINE_POS(event);
1245
1246 if (status == D40_DEACTIVATE_EVENTLINE ||
1247 status == D40_SUSPEND_REQ_EVENTLINE)
1248 break;
262d2915 1249
1bdae6f4
N		 1250 writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
1251 | ~D40_EVENTLINE_MASK(event), addr);
1252
1253 for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
1254
1255 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1256 D40_EVENTLINE_POS(event);
1257
1258 cpu_relax();
1259 /*
1260 * Reduce the number of bus accesses while
1261 * waiting for the DMA to suspend.
1262 */
1263 udelay(3);
1264
1265 if (status == D40_DEACTIVATE_EVENTLINE)
1266 break;
1267 }
1268
1269 if (tries == D40_SUSPEND_MAX_IT) {
1270 chan_err(d40c,
1271 "unable to stop the event_line chl %d (log: %d)"
1272 "status %x\n", d40c->phy_chan->num,
1273 d40c->log_num, status);
1274 }
1275 break;
1276
1277 case D40_ACTIVATE_EVENTLINE:
262d2915
RV		 1278 /*
1279 * The hardware sometimes doesn't register the enable when src and dst
1280 * event lines are active on the same logical channel. Retry to ensure
1281 * it does. Usually only one retry is sufficient.
1282 */
1bdae6f4
N		 1283 tries = 100;
1284 while (--tries) {
1285 writel((D40_ACTIVATE_EVENTLINE <<
1286 D40_EVENTLINE_POS(event)) |
1287 ~D40_EVENTLINE_MASK(event), addr);
262d2915 1288
1bdae6f4
N		 1289 if (readl(addr) & D40_EVENTLINE_MASK(event))
1290 break;
1291 }
262d2915 1292
1bdae6f4
N		 1293 if (tries != 99)
1294 dev_dbg(chan2dev(d40c),
1295 "[%s] workaround enable S%cLNK (%d tries)\n",
1296 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1297 100 - tries);
262d2915 1298
1bdae6f4
N		 1299 WARN_ON(!tries);
1300 break;
262d2915 1301
1bdae6f4
N		 1302 case D40_ROUND_EVENTLINE:
1303 BUG();
1304 break;
8d318a50 1305
1bdae6f4
N		 1306 }
1307}
8d318a50 1308
1bdae6f4
N		 1309static void d40_config_set_event(struct d40_chan *d40c,
1310 enum d40_events event_type)
1311{
26955c07
LJ		 1312 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
1313
8d318a50 1314 /* Enable event line connected to device (or memcpy) */
2c2b62d5
LJ		 1315 if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
1316 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
1bdae6f4 1317 __d40_config_set_event(d40c, event_type, event,
262d2915 1318 D40_CHAN_REG_SSLNK);
8d318a50 1319
2c2b62d5 1320 if (d40c->dma_cfg.dir != DMA_DEV_TO_MEM)
1bdae6f4 1321 __d40_config_set_event(d40c, event_type, event,
262d2915 1322 D40_CHAN_REG_SDLNK);
8d318a50
LW		 1323}
1324
a5ebca47 1325static u32 d40_chan_has_events(struct d40_chan *d40c)
8d318a50 1326{
8ca84687 1327 void __iomem *chanbase = chan_base(d40c);
be8cb7df 1328 u32 val;
8d318a50 1329
8ca84687
RV		 1330 val = readl(chanbase + D40_CHAN_REG_SSLNK);
1331 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
be8cb7df 1332
a5ebca47 1333 return val;
8d318a50
LW		 1334}
1335
1bdae6f4
N		 1336static int
1337__d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
1338{
1339 unsigned long flags;
1340 int ret = 0;
1341 u32 active_status;
1342 void __iomem *active_reg;
1343
1344 if (d40c->phy_chan->num % 2 == 0)
1345 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1346 else
1347 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1348
1349
1350 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1351
1352 switch (command) {
1353 case D40_DMA_STOP:
1354 case D40_DMA_SUSPEND_REQ:
1355
1356 active_status = (readl(active_reg) &
1357 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1358 D40_CHAN_POS(d40c->phy_chan->num);
1359
1360 if (active_status == D40_DMA_RUN)
1361 d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
1362 else
1363 d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
1364
1365 if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
1366 ret = __d40_execute_command_phy(d40c, command);
1367
1368 break;
1369
1370 case D40_DMA_RUN:
1371
1372 d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
1373 ret = __d40_execute_command_phy(d40c, command);
1374 break;
1375
1376 case D40_DMA_SUSPENDED:
1377 BUG();
1378 break;
1379 }
1380
1381 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1382 return ret;
1383}
1384
1385static int d40_channel_execute_command(struct d40_chan *d40c,
1386 enum d40_command command)
1387{
1388 if (chan_is_logical(d40c))
1389 return __d40_execute_command_log(d40c, command);
1390 else
1391 return __d40_execute_command_phy(d40c, command);
1392}
1393
20a5b6d0
RV		 1394static u32 d40_get_prmo(struct d40_chan *d40c)
1395{
1396 static const unsigned int phy_map[] = {
1397 [STEDMA40_PCHAN_BASIC_MODE]
1398 = D40_DREG_PRMO_PCHAN_BASIC,
1399 [STEDMA40_PCHAN_MODULO_MODE]
1400 = D40_DREG_PRMO_PCHAN_MODULO,
1401 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1402 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1403 };
1404 static const unsigned int log_map[] = {
1405 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1406 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1407 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1408 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1409 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1410 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1411 };
1412
724a8577 1413 if (chan_is_physical(d40c))
20a5b6d0
RV		 1414 return phy_map[d40c->dma_cfg.mode_opt];
1415 else
1416 return log_map[d40c->dma_cfg.mode_opt];
1417}
1418
b55912c6 1419static void d40_config_write(struct d40_chan *d40c)
8d318a50
LW		 1420{
1421 u32 addr_base;
1422 u32 var;
8d318a50
LW		 1423
1424 /* Odd addresses are even addresses + 4 */
1425 addr_base = (d40c->phy_chan->num % 2) * 4;
1426 /* Setup channel mode to logical or physical */
724a8577 1427 var = ((u32)(chan_is_logical(d40c)) + 1) <<
8d318a50
LW		 1428 D40_CHAN_POS(d40c->phy_chan->num);
1429 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1430
1431 /* Setup operational mode option register */
20a5b6d0 1432 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
8d318a50
LW		 1433
1434 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1435
724a8577 1436 if (chan_is_logical(d40c)) {
8ca84687
RV		 1437 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1438 & D40_SREG_ELEM_LOG_LIDX_MASK;
1439 void __iomem *chanbase = chan_base(d40c);
1440
8d318a50 1441 /* Set default config for CFG reg */
8ca84687
RV		 1442 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1443 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
8d318a50 1444
b55912c6 1445 /* Set LIDX for lcla */
8ca84687
RV		 1446 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1447 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
e9f3a49c
RV		 1448
1449 /* Clear LNK which will be used by d40_chan_has_events() */
1450 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1451 writel(0, chanbase + D40_CHAN_REG_SDLNK);
8d318a50 1452 }
8d318a50
LW		 1453}
1454
aa182ae2
JA		 1455static u32 d40_residue(struct d40_chan *d40c)
1456{
1457 u32 num_elt;
1458
724a8577 1459 if (chan_is_logical(d40c))
aa182ae2
JA		 1460 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1461 >> D40_MEM_LCSP2_ECNT_POS;
8ca84687
RV		 1462 else {
1463 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1464 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1465 >> D40_SREG_ELEM_PHY_ECNT_POS;
1466 }
1467
43f2e1a3 1468 return num_elt * d40c->dma_cfg.dst_info.data_width;
aa182ae2
JA		 1469}
1470
1471static bool d40_tx_is_linked(struct d40_chan *d40c)
1472{
1473 bool is_link;
1474
724a8577 1475 if (chan_is_logical(d40c))
aa182ae2
JA		 1476 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
1477 else
8ca84687
RV		 1478 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1479 & D40_SREG_LNK_PHYS_LNK_MASK;
1480
aa182ae2
JA		 1481 return is_link;
1482}
1483
86eb5fb6 1484static int d40_pause(struct d40_chan *d40c)
aa182ae2 1485{
aa182ae2
JA		 1486 int res = 0;
1487 unsigned long flags;
1488
3ac012af
JA		 1489 if (!d40c->busy)
1490 return 0;
1491
7fb3e75e 1492 pm_runtime_get_sync(d40c->base->dev);
aa182ae2
JA		 1493 spin_lock_irqsave(&d40c->lock, flags);
1494
1495 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1bdae6f4 1496
7fb3e75e
N		 1497 pm_runtime_mark_last_busy(d40c->base->dev);
1498 pm_runtime_put_autosuspend(d40c->base->dev);
aa182ae2
JA		 1499 spin_unlock_irqrestore(&d40c->lock, flags);
1500 return res;
1501}
1502
86eb5fb6 1503static int d40_resume(struct d40_chan *d40c)
aa182ae2 1504{
aa182ae2
JA		 1505 int res = 0;
1506 unsigned long flags;
1507
3ac012af
JA		 1508 if (!d40c->busy)
1509 return 0;
1510
aa182ae2 1511 spin_lock_irqsave(&d40c->lock, flags);
7fb3e75e 1512 pm_runtime_get_sync(d40c->base->dev);
aa182ae2
JA		 1513
1514 /* If bytes left to transfer or linked tx resume job */
1bdae6f4 1515 if (d40_residue(d40c) || d40_tx_is_linked(d40c))
aa182ae2 1516 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
aa182ae2 1517
7fb3e75e
N		 1518 pm_runtime_mark_last_busy(d40c->base->dev);
1519 pm_runtime_put_autosuspend(d40c->base->dev);
aa182ae2
JA		 1520 spin_unlock_irqrestore(&d40c->lock, flags);
1521 return res;
1522}
1523
8d318a50
LW		 1524static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1525{
1526 struct d40_chan *d40c = container_of(tx->chan,
1527 struct d40_chan,
1528 chan);
1529 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1530 unsigned long flags;
884485e1 1531 dma_cookie_t cookie;
8d318a50
LW		 1532
1533 spin_lock_irqsave(&d40c->lock, flags);
884485e1 1534 cookie = dma_cookie_assign(tx);
8d318a50 1535 d40_desc_queue(d40c, d40d);
8d318a50
LW		 1536 spin_unlock_irqrestore(&d40c->lock, flags);
1537
884485e1 1538 return cookie;
8d318a50
LW		 1539}
1540
1541static int d40_start(struct d40_chan *d40c)
1542{
0c32269d 1543 return d40_channel_execute_command(d40c, D40_DMA_RUN);
8d318a50
LW		 1544}
1545
1546static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1547{
1548 struct d40_desc *d40d;
1549 int err;
1550
1551 /* Start queued jobs, if any */
1552 d40d = d40_first_queued(d40c);
1553
1554 if (d40d != NULL) {
1bdae6f4 1555 if (!d40c->busy) {
7fb3e75e 1556 d40c->busy = true;
1bdae6f4
N		 1557 pm_runtime_get_sync(d40c->base->dev);
1558 }
8d318a50
LW		 1559
1560 /* Remove from queue */
1561 d40_desc_remove(d40d);
1562
1563 /* Add to active queue */
1564 d40_desc_submit(d40c, d40d);
1565
7d83a854
RV		 1566 /* Initiate DMA job */
1567 d40_desc_load(d40c, d40d);
8d318a50 1568
7d83a854
RV		 1569 /* Start dma job */
1570 err = d40_start(d40c);
8d318a50 1571
7d83a854
RV		 1572 if (err)
1573 return NULL;
8d318a50
LW		 1574 }
1575
1576 return d40d;
1577}
1578
1579/* called from interrupt context */
1580static void dma_tc_handle(struct d40_chan *d40c)
1581{
1582 struct d40_desc *d40d;
1583
8d318a50
LW		 1584 /* Get first active entry from list */
1585 d40d = d40_first_active_get(d40c);
1586
1587 if (d40d == NULL)
1588 return;
1589
0c842b55
RV		 1590 if (d40d->cyclic) {
1591 /*
1592 * If this was a paritially loaded list, we need to reloaded
1593 * it, and only when the list is completed. We need to check
1594 * for done because the interrupt will hit for every link, and
1595 * not just the last one.
1596 */
1597 if (d40d->lli_current < d40d->lli_len
1598 && !d40_tx_is_linked(d40c)
1599 && !d40_residue(d40c)) {
1600 d40_lcla_free_all(d40c, d40d);
1601 d40_desc_load(d40c, d40d);
1602 (void) d40_start(d40c);
8d318a50 1603
0c842b55
RV		 1604 if (d40d->lli_current == d40d->lli_len)
1605 d40d->lli_current = 0;
1606 }
1607 } else {
1608 d40_lcla_free_all(d40c, d40d);
8d318a50 1609
0c842b55
RV		 1610 if (d40d->lli_current < d40d->lli_len) {
1611 d40_desc_load(d40c, d40d);
1612 /* Start dma job */
1613 (void) d40_start(d40c);
1614 return;
1615 }
1616
1617 if (d40_queue_start(d40c) == NULL)
1618 d40c->busy = false;
7fb3e75e
N		 1619 pm_runtime_mark_last_busy(d40c->base->dev);
1620 pm_runtime_put_autosuspend(d40c->base->dev);
8d318a50 1621
7dd14525
FB		 1622 d40_desc_remove(d40d);
1623 d40_desc_done(d40c, d40d);
1624 }
4226dd86 1625
8d318a50
LW		 1626 d40c->pending_tx++;
1627 tasklet_schedule(&d40c->tasklet);
1628
1629}
1630
1631static void dma_tasklet(unsigned long data)
1632{
1633 struct d40_chan *d40c = (struct d40_chan *) data;
767a9675 1634 struct d40_desc *d40d;
8d318a50
LW		 1635 unsigned long flags;
1636 dma_async_tx_callback callback;
1637 void *callback_param;
1638
1639 spin_lock_irqsave(&d40c->lock, flags);
1640
4226dd86
FB		 1641 /* Get first entry from the done list */
1642 d40d = d40_first_done(d40c);
1643 if (d40d == NULL) {
1644 /* Check if we have reached here for cyclic job */
1645 d40d = d40_first_active_get(d40c);
1646 if (d40d == NULL || !d40d->cyclic)
1647 goto err;
1648 }
8d318a50 1649
0c842b55 1650 if (!d40d->cyclic)
f7fbce07 1651 dma_cookie_complete(&d40d->txd);
8d318a50
LW		 1652
1653 /*
1654 * If terminating a channel pending_tx is set to zero.
1655 * This prevents any finished active jobs to return to the client.
1656 */
1657 if (d40c->pending_tx == 0) {
1658 spin_unlock_irqrestore(&d40c->lock, flags);
1659 return;
1660 }
1661
1662 /* Callback to client */
767a9675
JA		 1663 callback = d40d->txd.callback;
1664 callback_param = d40d->txd.callback_param;
1665
0c842b55
RV		 1666 if (!d40d->cyclic) {
1667 if (async_tx_test_ack(&d40d->txd)) {
767a9675 1668 d40_desc_remove(d40d);
0c842b55 1669 d40_desc_free(d40c, d40d);
f26e03ad
FB		 1670 } else if (!d40d->is_in_client_list) {
1671 d40_desc_remove(d40d);
1672 d40_lcla_free_all(d40c, d40d);
1673 list_add_tail(&d40d->node, &d40c->client);
1674 d40d->is_in_client_list = true;
8d318a50
LW		 1675 }
1676 }
1677
1678 d40c->pending_tx--;
1679
1680 if (d40c->pending_tx)
1681 tasklet_schedule(&d40c->tasklet);
1682
1683 spin_unlock_irqrestore(&d40c->lock, flags);
1684
767a9675 1685 if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
8d318a50
LW		 1686 callback(callback_param);
1687
1688 return;
1689
1bdae6f4
N		 1690err:
1691 /* Rescue manouver if receiving double interrupts */
8d318a50
LW		 1692 if (d40c->pending_tx > 0)
1693 d40c->pending_tx--;
1694 spin_unlock_irqrestore(&d40c->lock, flags);
1695}
1696
1697static irqreturn_t d40_handle_interrupt(int irq, void *data)
1698{
8d318a50 1699 int i;
8d318a50
LW		 1700 u32 idx;
1701 u32 row;
1702 long chan = -1;
1703 struct d40_chan *d40c;
1704 unsigned long flags;
1705 struct d40_base *base = data;
3cb645dc
TL		 1706 u32 regs[base->gen_dmac.il_size];
1707 struct d40_interrupt_lookup *il = base->gen_dmac.il;
1708 u32 il_size = base->gen_dmac.il_size;
8d318a50
LW		 1709
1710 spin_lock_irqsave(&base->interrupt_lock, flags);
1711
1712 /* Read interrupt status of both logical and physical channels */
3cb645dc 1713 for (i = 0; i < il_size; i++)
8d318a50
LW		 1714 regs[i] = readl(base->virtbase + il[i].src);
1715
1716 for (;;) {
1717
1718 chan = find_next_bit((unsigned long *)regs,
3cb645dc 1719 BITS_PER_LONG * il_size, chan + 1);
8d318a50
LW		 1720
1721 /* No more set bits found? */
3cb645dc 1722 if (chan == BITS_PER_LONG * il_size)
8d318a50
LW		 1723 break;
1724
1725 row = chan / BITS_PER_LONG;
1726 idx = chan & (BITS_PER_LONG - 1);
1727
8d318a50
LW		 1728 if (il[row].offset == D40_PHY_CHAN)
1729 d40c = base->lookup_phy_chans[idx];
1730 else
1731 d40c = base->lookup_log_chans[il[row].offset + idx];
53d6d68f
FB		 1732
1733 if (!d40c) {
1734 /*
1735 * No error because this can happen if something else
1736 * in the system is using the channel.
1737 */
1738 continue;
1739 }
1740
1741 /* ACK interrupt */
8a3b6e14 1742 writel(BIT(idx), base->virtbase + il[row].clr);
53d6d68f 1743
8d318a50
LW		 1744 spin_lock(&d40c->lock);
1745
1746 if (!il[row].is_error)
1747 dma_tc_handle(d40c);
1748 else
6db5a8ba
RV		 1749 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1750 chan, il[row].offset, idx);
8d318a50
LW		 1751
1752 spin_unlock(&d40c->lock);
1753 }
1754
1755 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1756
1757 return IRQ_HANDLED;
1758}
1759
8d318a50
LW		 1760static int d40_validate_conf(struct d40_chan *d40c,
1761 struct stedma40_chan_cfg *conf)
1762{
1763 int res = 0;
38bdbf02 1764 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
8d318a50 1765
0747c7ba 1766 if (!conf->dir) {
6db5a8ba 1767 chan_err(d40c, "Invalid direction.\n");
0747c7ba
LW		 1768 res = -EINVAL;
1769 }
1770
26955c07
LJ		 1771 if ((is_log && conf->dev_type > d40c->base->num_log_chans) ||
1772 (!is_log && conf->dev_type > d40c->base->num_phy_chans) ||
1773 (conf->dev_type < 0)) {
1774 chan_err(d40c, "Invalid device type (%d)\n", conf->dev_type);
0747c7ba
LW		 1775 res = -EINVAL;
1776 }
1777
2c2b62d5 1778 if (conf->dir == DMA_DEV_TO_DEV) {
8d318a50
LW		 1779 /*
1780 * DMAC HW supports it. Will be added to this driver,
1781 * in case any dma client requires it.
1782 */
6db5a8ba 1783 chan_err(d40c, "periph to periph not supported\n");
8d318a50
LW		 1784 res = -EINVAL;
1785 }
1786
d49278e3 1787 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
43f2e1a3 1788 conf->src_info.data_width !=
d49278e3 1789 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
43f2e1a3 1790 conf->dst_info.data_width) {
d49278e3
PF		 1791 /*
1792 * The DMAC hardware only supports
1793 * src (burst x width) == dst (burst x width)
1794 */
1795
6db5a8ba 1796 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
d49278e3
PF		 1797 res = -EINVAL;
1798 }
1799
8d318a50
LW		 1800 return res;
1801}
1802
5cd326fd
N		 1803static bool d40_alloc_mask_set(struct d40_phy_res *phy,
1804 bool is_src, int log_event_line, bool is_log,
1805 bool *first_user)
8d318a50
LW		 1806{
1807 unsigned long flags;
1808 spin_lock_irqsave(&phy->lock, flags);
5cd326fd
N		 1809
1810 *first_user = ((phy->allocated_src | phy->allocated_dst)
1811 == D40_ALLOC_FREE);
1812
4aed79b2 1813 if (!is_log) {
8d318a50
LW		 1814 /* Physical interrupts are masked per physical full channel */
1815 if (phy->allocated_src == D40_ALLOC_FREE &&
1816 phy->allocated_dst == D40_ALLOC_FREE) {
1817 phy->allocated_dst = D40_ALLOC_PHY;
1818 phy->allocated_src = D40_ALLOC_PHY;
1819 goto found;
1820 } else
1821 goto not_found;
1822 }
1823
1824 /* Logical channel */
1825 if (is_src) {
1826 if (phy->allocated_src == D40_ALLOC_PHY)
1827 goto not_found;
1828
1829 if (phy->allocated_src == D40_ALLOC_FREE)
1830 phy->allocated_src = D40_ALLOC_LOG_FREE;
1831
8a3b6e14
LJ		 1832 if (!(phy->allocated_src & BIT(log_event_line))) {
1833 phy->allocated_src |= BIT(log_event_line);
8d318a50
LW		 1834 goto found;
1835 } else
1836 goto not_found;
1837 } else {
1838 if (phy->allocated_dst == D40_ALLOC_PHY)
1839 goto not_found;
1840
1841 if (phy->allocated_dst == D40_ALLOC_FREE)
1842 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1843
8a3b6e14
LJ		 1844 if (!(phy->allocated_dst & BIT(log_event_line))) {
1845 phy->allocated_dst |= BIT(log_event_line);
8d318a50
LW		 1846 goto found;
1847 } else
1848 goto not_found;
1849 }
1850
1851not_found:
1852 spin_unlock_irqrestore(&phy->lock, flags);
1853 return false;
1854found:
1855 spin_unlock_irqrestore(&phy->lock, flags);
1856 return true;
1857}
1858
1859static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1860 int log_event_line)
1861{
1862 unsigned long flags;
1863 bool is_free = false;
1864
1865 spin_lock_irqsave(&phy->lock, flags);
1866 if (!log_event_line) {
8d318a50
LW		 1867 phy->allocated_dst = D40_ALLOC_FREE;
1868 phy->allocated_src = D40_ALLOC_FREE;
1869 is_free = true;
1870 goto out;
1871 }
1872
1873 /* Logical channel */
1874 if (is_src) {
8a3b6e14 1875 phy->allocated_src &= ~BIT(log_event_line);
8d318a50
LW		 1876 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1877 phy->allocated_src = D40_ALLOC_FREE;
1878 } else {
8a3b6e14 1879 phy->allocated_dst &= ~BIT(log_event_line);
8d318a50
LW		 1880 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1881 phy->allocated_dst = D40_ALLOC_FREE;
1882 }
1883
1884 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1885 D40_ALLOC_FREE);
1886
1887out:
1888 spin_unlock_irqrestore(&phy->lock, flags);
1889
1890 return is_free;
1891}
1892
5cd326fd 1893static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
8d318a50 1894{
26955c07 1895 int dev_type = d40c->dma_cfg.dev_type;
8d318a50
LW		 1896 int event_group;
1897 int event_line;
1898 struct d40_phy_res *phys;
1899 int i;
1900 int j;
1901 int log_num;
f000df8c 1902 int num_phy_chans;
8d318a50 1903 bool is_src;
38bdbf02 1904 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
8d318a50
LW		 1905
1906 phys = d40c->base->phy_res;
f000df8c 1907 num_phy_chans = d40c->base->num_phy_chans;
8d318a50 1908
2c2b62d5 1909 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
8d318a50
LW		 1910 log_num = 2 * dev_type;
1911 is_src = true;
2c2b62d5
LJ		 1912 } else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
1913 d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
8d318a50 1914 /* dst event lines are used for logical memcpy */
8d318a50
LW		 1915 log_num = 2 * dev_type + 1;
1916 is_src = false;
1917 } else
1918 return -EINVAL;
1919
1920 event_group = D40_TYPE_TO_GROUP(dev_type);
1921 event_line = D40_TYPE_TO_EVENT(dev_type);
1922
1923 if (!is_log) {
2c2b62d5 1924 if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
8d318a50 1925 /* Find physical half channel */
f000df8c
GB		 1926 if (d40c->dma_cfg.use_fixed_channel) {
1927 i = d40c->dma_cfg.phy_channel;
4aed79b2 1928 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1929 0, is_log,
1930 first_phy_user))
8d318a50 1931 goto found_phy;
f000df8c
GB		 1932 } else {
1933 for (i = 0; i < num_phy_chans; i++) {
1934 if (d40_alloc_mask_set(&phys[i], is_src,
1935 0, is_log,
1936 first_phy_user))
1937 goto found_phy;
1938 }
8d318a50
LW		 1939 }
1940 } else
1941 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1942 int phy_num = j + event_group * 2;
1943 for (i = phy_num; i < phy_num + 2; i++) {
508849ad
LW		 1944 if (d40_alloc_mask_set(&phys[i],
1945 is_src,
1946 0,
5cd326fd
N		 1947 is_log,
1948 first_phy_user))
8d318a50
LW		 1949 goto found_phy;
1950 }
1951 }
1952 return -EINVAL;
1953found_phy:
1954 d40c->phy_chan = &phys[i];
1955 d40c->log_num = D40_PHY_CHAN;
1956 goto out;
1957 }
1958 if (dev_type == -1)
1959 return -EINVAL;
1960
1961 /* Find logical channel */
1962 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1963 int phy_num = j + event_group * 2;
5cd326fd
N		 1964
1965 if (d40c->dma_cfg.use_fixed_channel) {
1966 i = d40c->dma_cfg.phy_channel;
1967
1968 if ((i != phy_num) && (i != phy_num + 1)) {
1969 dev_err(chan2dev(d40c),
1970 "invalid fixed phy channel %d\n", i);
1971 return -EINVAL;
1972 }
1973
1974 if (d40_alloc_mask_set(&phys[i], is_src, event_line,
1975 is_log, first_phy_user))
1976 goto found_log;
1977
1978 dev_err(chan2dev(d40c),
1979 "could not allocate fixed phy channel %d\n", i);
1980 return -EINVAL;
1981 }
1982
8d318a50
LW		 1983 /*
1984 * Spread logical channels across all available physical rather
1985 * than pack every logical channel at the first available phy
1986 * channels.
1987 */
1988 if (is_src) {
1989 for (i = phy_num; i < phy_num + 2; i++) {
1990 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1991 event_line, is_log,
1992 first_phy_user))
8d318a50
LW		 1993 goto found_log;
1994 }
1995 } else {
1996 for (i = phy_num + 1; i >= phy_num; i--) {
1997 if (d40_alloc_mask_set(&phys[i], is_src,
5cd326fd
N		 1998 event_line, is_log,
1999 first_phy_user))
8d318a50
LW		 2000 goto found_log;
2001 }
2002 }
2003 }
2004 return -EINVAL;
2005
2006found_log:
2007 d40c->phy_chan = &phys[i];
2008 d40c->log_num = log_num;
2009out:
2010
2011 if (is_log)
2012 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
2013 else
2014 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
2015
2016 return 0;
2017
2018}
2019
8d318a50
LW		 2020static int d40_config_memcpy(struct d40_chan *d40c)
2021{
2022 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
2023
2024 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
29027a1e 2025 d40c->dma_cfg = dma40_memcpy_conf_log;
26955c07 2026 d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
8d318a50 2027
9b233f9b
LJ		 2028 d40_log_cfg(&d40c->dma_cfg,
2029 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2030
8d318a50
LW		 2031 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
2032 dma_has_cap(DMA_SLAVE, cap)) {
29027a1e 2033 d40c->dma_cfg = dma40_memcpy_conf_phy;
57e65ad7
LJ		 2034
2035 /* Generate interrrupt at end of transfer or relink. */
2036 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_TIM_POS);
2037
2038 /* Generate interrupt on error. */
2039 d40c->src_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
2040 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_EIM_POS);
2041
8d318a50 2042 } else {
6db5a8ba 2043 chan_err(d40c, "No memcpy\n");
8d318a50
LW		 2044 return -EINVAL;
2045 }
2046
2047 return 0;
2048}
2049
8d318a50
LW		 2050static int d40_free_dma(struct d40_chan *d40c)
2051{
2052
2053 int res = 0;
26955c07 2054 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
8d318a50
LW		 2055 struct d40_phy_res *phy = d40c->phy_chan;
2056 bool is_src;
2057
2058 /* Terminate all queued and active transfers */
2059 d40_term_all(d40c);
2060
2061 if (phy == NULL) {
6db5a8ba 2062 chan_err(d40c, "phy == null\n");
8d318a50
LW		 2063 return -EINVAL;
2064 }
2065
2066 if (phy->allocated_src == D40_ALLOC_FREE &&
2067 phy->allocated_dst == D40_ALLOC_FREE) {
6db5a8ba 2068 chan_err(d40c, "channel already free\n");
8d318a50
LW		 2069 return -EINVAL;
2070 }
2071
2c2b62d5
LJ		 2072 if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2073 d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
8d318a50 2074 is_src = false;
2c2b62d5 2075 else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
8d318a50 2076 is_src = true;
26955c07 2077 else {
6db5a8ba 2078 chan_err(d40c, "Unknown direction\n");
8d318a50
LW		 2079 return -EINVAL;
2080 }
2081
7fb3e75e 2082 pm_runtime_get_sync(d40c->base->dev);
1bdae6f4 2083 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
d181b3a8 2084 if (res) {
1bdae6f4 2085 chan_err(d40c, "stop failed\n");
7fb3e75e 2086 goto out;
d181b3a8
JA		 2087 }
2088
1bdae6f4 2089 d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
8d318a50 2090
1bdae6f4 2091 if (chan_is_logical(d40c))
8d318a50 2092 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1bdae6f4
N		 2093 else
2094 d40c->base->lookup_phy_chans[phy->num] = NULL;
7fb3e75e
N		 2095
2096 if (d40c->busy) {
2097 pm_runtime_mark_last_busy(d40c->base->dev);
2098 pm_runtime_put_autosuspend(d40c->base->dev);
2099 }
2100
2101 d40c->busy = false;
8d318a50 2102 d40c->phy_chan = NULL;
ce2ca125 2103 d40c->configured = false;
7fb3e75e 2104out:
8d318a50 2105
7fb3e75e
N		 2106 pm_runtime_mark_last_busy(d40c->base->dev);
2107 pm_runtime_put_autosuspend(d40c->base->dev);
2108 return res;
8d318a50
LW		 2109}
2110
a5ebca47
JA		 2111static bool d40_is_paused(struct d40_chan *d40c)
2112{
8ca84687 2113 void __iomem *chanbase = chan_base(d40c);
a5ebca47
JA		 2114 bool is_paused = false;
2115 unsigned long flags;
2116 void __iomem *active_reg;
2117 u32 status;
26955c07 2118 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
a5ebca47
JA		 2119
2120 spin_lock_irqsave(&d40c->lock, flags);
2121
724a8577 2122 if (chan_is_physical(d40c)) {
a5ebca47
JA		 2123 if (d40c->phy_chan->num % 2 == 0)
2124 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
2125 else
2126 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
2127
2128 status = (readl(active_reg) &
2129 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
2130 D40_CHAN_POS(d40c->phy_chan->num);
2131 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
2132 is_paused = true;
2133
2134 goto _exit;
2135 }
2136
2c2b62d5
LJ		 2137 if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2138 d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
8ca84687 2139 status = readl(chanbase + D40_CHAN_REG_SDLNK);
2c2b62d5 2140 } else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
8ca84687 2141 status = readl(chanbase + D40_CHAN_REG_SSLNK);
9dbfbd35 2142 } else {
6db5a8ba 2143 chan_err(d40c, "Unknown direction\n");
a5ebca47
JA		 2144 goto _exit;
2145 }
9dbfbd35 2146
a5ebca47
JA		 2147 status = (status & D40_EVENTLINE_MASK(event)) >>
2148 D40_EVENTLINE_POS(event);
2149
2150 if (status != D40_DMA_RUN)
2151 is_paused = true;
a5ebca47
JA		 2152_exit:
2153 spin_unlock_irqrestore(&d40c->lock, flags);
2154 return is_paused;
2155
2156}
2157
8d318a50
LW		 2158static u32 stedma40_residue(struct dma_chan *chan)
2159{
2160 struct d40_chan *d40c =
2161 container_of(chan, struct d40_chan, chan);
2162 u32 bytes_left;
2163 unsigned long flags;
2164
2165 spin_lock_irqsave(&d40c->lock, flags);
2166 bytes_left = d40_residue(d40c);
2167 spin_unlock_irqrestore(&d40c->lock, flags);
2168
2169 return bytes_left;
2170}
2171
3e3a0763
RV		 2172static int
2173d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
2174 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 2175 unsigned int sg_len, dma_addr_t src_dev_addr,
2176 dma_addr_t dst_dev_addr)
3e3a0763
RV		 2177{
2178 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2179 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2180 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
5ed04b85 2181 int ret;
3e3a0763 2182
5ed04b85
RV		 2183 ret = d40_log_sg_to_lli(sg_src, sg_len,
2184 src_dev_addr,
2185 desc->lli_log.src,
2186 chan->log_def.lcsp1,
2187 src_info->data_width,
2188 dst_info->data_width);
2189
2190 ret = d40_log_sg_to_lli(sg_dst, sg_len,
2191 dst_dev_addr,
2192 desc->lli_log.dst,
2193 chan->log_def.lcsp3,
2194 dst_info->data_width,
2195 src_info->data_width);
2196
2197 return ret < 0 ? ret : 0;
3e3a0763
RV		 2198}
2199
2200static int
2201d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
2202 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 2203 unsigned int sg_len, dma_addr_t src_dev_addr,
2204 dma_addr_t dst_dev_addr)
3e3a0763 2205{
3e3a0763
RV		 2206 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2207 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2208 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
0c842b55 2209 unsigned long flags = 0;
3e3a0763
RV		 2210 int ret;
2211
0c842b55
RV		 2212 if (desc->cyclic)
2213 flags |= LLI_CYCLIC | LLI_TERM_INT;
2214
3e3a0763
RV		 2215 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
2216 desc->lli_phy.src,
2217 virt_to_phys(desc->lli_phy.src),
2218 chan->src_def_cfg,
0c842b55 2219 src_info, dst_info, flags);
3e3a0763
RV		 2220
2221 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
2222 desc->lli_phy.dst,
2223 virt_to_phys(desc->lli_phy.dst),
2224 chan->dst_def_cfg,
0c842b55 2225 dst_info, src_info, flags);
3e3a0763
RV		 2226
2227 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
2228 desc->lli_pool.size, DMA_TO_DEVICE);
2229
2230 return ret < 0 ? ret : 0;
2231}
2232
5f81158f
RV		 2233static struct d40_desc *
2234d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
2235 unsigned int sg_len, unsigned long dma_flags)
2236{
2237 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2238 struct d40_desc *desc;
dbd88788 2239 int ret;
5f81158f
RV		 2240
2241 desc = d40_desc_get(chan);
2242 if (!desc)
2243 return NULL;
2244
2245 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
2246 cfg->dst_info.data_width);
2247 if (desc->lli_len < 0) {
2248 chan_err(chan, "Unaligned size\n");
dbd88788
RV		 2249 goto err;
2250 }
5f81158f 2251
dbd88788
RV		 2252 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2253 if (ret < 0) {
2254 chan_err(chan, "Could not allocate lli\n");
2255 goto err;
5f81158f
RV		 2256 }
2257
2258 desc->lli_current = 0;
2259 desc->txd.flags = dma_flags;
2260 desc->txd.tx_submit = d40_tx_submit;
2261
2262 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
2263
2264 return desc;
dbd88788
RV		 2265
2266err:
2267 d40_desc_free(chan, desc);
2268 return NULL;
5f81158f
RV		 2269}
2270
cade1d30
RV		 2271static struct dma_async_tx_descriptor *
2272d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2273 struct scatterlist *sg_dst, unsigned int sg_len,
db8196df 2274 enum dma_transfer_direction direction, unsigned long dma_flags)
cade1d30
RV		 2275{
2276 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
822c5676
RV		 2277 dma_addr_t src_dev_addr = 0;
2278 dma_addr_t dst_dev_addr = 0;
cade1d30 2279 struct d40_desc *desc;
2a614340 2280 unsigned long flags;
cade1d30 2281 int ret;
8d318a50 2282
cade1d30
RV		 2283 if (!chan->phy_chan) {
2284 chan_err(chan, "Cannot prepare unallocated channel\n");
2285 return NULL;
0d0f6b8b
JA		 2286 }
2287
cade1d30 2288 spin_lock_irqsave(&chan->lock, flags);
8d318a50 2289
cade1d30
RV		 2290 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
2291 if (desc == NULL)
8d318a50
LW		 2292 goto err;
2293
0c842b55
RV		 2294 if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2295 desc->cyclic = true;
2296
ef9c89b3
LJ		 2297 if (direction == DMA_DEV_TO_MEM)
2298 src_dev_addr = chan->runtime_addr;
2299 else if (direction == DMA_MEM_TO_DEV)
2300 dst_dev_addr = chan->runtime_addr;
cade1d30
RV		 2301
2302 if (chan_is_logical(chan))
2303 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
822c5676 2304 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 2305 else
2306 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
822c5676 2307 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 2308
2309 if (ret) {
2310 chan_err(chan, "Failed to prepare %s sg job: %d\n",
2311 chan_is_logical(chan) ? "log" : "phy", ret);
2312 goto err;
8d318a50
LW		 2313 }
2314
82babbb3
PF		 2315 /*
2316 * add descriptor to the prepare queue in order to be able
2317 * to free them later in terminate_all
2318 */
2319 list_add_tail(&desc->node, &chan->prepare_queue);
2320
cade1d30
RV		 2321 spin_unlock_irqrestore(&chan->lock, flags);
2322
2323 return &desc->txd;
8d318a50 2324
8d318a50 2325err:
cade1d30
RV		 2326 if (desc)
2327 d40_desc_free(chan, desc);
2328 spin_unlock_irqrestore(&chan->lock, flags);
8d318a50
LW		 2329 return NULL;
2330}
8d318a50
LW		 2331
2332bool stedma40_filter(struct dma_chan *chan, void *data)
2333{
2334 struct stedma40_chan_cfg *info = data;
2335 struct d40_chan *d40c =
2336 container_of(chan, struct d40_chan, chan);
2337 int err;
2338
2339 if (data) {
2340 err = d40_validate_conf(d40c, info);
2341 if (!err)
2342 d40c->dma_cfg = *info;
2343 } else
2344 err = d40_config_memcpy(d40c);
2345
ce2ca125
RV		 2346 if (!err)
2347 d40c->configured = true;
2348
8d318a50
LW		 2349 return err == 0;
2350}
2351EXPORT_SYMBOL(stedma40_filter);
2352
ac2c0a38
RV		 2353static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
2354{
2355 bool realtime = d40c->dma_cfg.realtime;
2356 bool highprio = d40c->dma_cfg.high_priority;
3cb645dc 2357 u32 rtreg;
ac2c0a38
RV		 2358 u32 event = D40_TYPE_TO_EVENT(dev_type);
2359 u32 group = D40_TYPE_TO_GROUP(dev_type);
8a3b6e14 2360 u32 bit = BIT(event);
ccc3d697 2361 u32 prioreg;
3cb645dc 2362 struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
ccc3d697 2363
3cb645dc 2364 rtreg = realtime ? dmac->realtime_en : dmac->realtime_clear;
ccc3d697
RV		 2365 /*
2366 * Due to a hardware bug, in some cases a logical channel triggered by
2367 * a high priority destination event line can generate extra packet
2368 * transactions.
2369 *
2370 * The workaround is to not set the high priority level for the
2371 * destination event lines that trigger logical channels.
2372 */
2373 if (!src && chan_is_logical(d40c))
2374 highprio = false;
2375
3cb645dc 2376 prioreg = highprio ? dmac->high_prio_en : dmac->high_prio_clear;
ac2c0a38
RV		 2377
2378 /* Destination event lines are stored in the upper halfword */
2379 if (!src)
2380 bit <<= 16;
2381
2382 writel(bit, d40c->base->virtbase + prioreg + group * 4);
2383 writel(bit, d40c->base->virtbase + rtreg + group * 4);
2384}
2385
2386static void d40_set_prio_realtime(struct d40_chan *d40c)
2387{
2388 if (d40c->base->rev < 3)
2389 return;
2390
2c2b62d5
LJ		 2391 if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
2392 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
26955c07 2393 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
ac2c0a38 2394
2c2b62d5
LJ		 2395 if ((d40c->dma_cfg.dir == DMA_MEM_TO_DEV) ||
2396 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
26955c07 2397 __d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
ac2c0a38
RV		 2398}
2399
fa332de5
LJ		 2400#define D40_DT_FLAGS_MODE(flags) ((flags >> 0) & 0x1)
2401#define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1)
2402#define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
2403#define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
2404
2405static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
2406 struct of_dma *ofdma)
2407{
2408 struct stedma40_chan_cfg cfg;
2409 dma_cap_mask_t cap;
2410 u32 flags;
2411
2412 memset(&cfg, 0, sizeof(struct stedma40_chan_cfg));
2413
2414 dma_cap_zero(cap);
2415 dma_cap_set(DMA_SLAVE, cap);
2416
2417 cfg.dev_type = dma_spec->args[0];
2418 flags = dma_spec->args[2];
2419
2420 switch (D40_DT_FLAGS_MODE(flags)) {
2421 case 0: cfg.mode = STEDMA40_MODE_LOGICAL; break;
2422 case 1: cfg.mode = STEDMA40_MODE_PHYSICAL; break;
2423 }
2424
2425 switch (D40_DT_FLAGS_DIR(flags)) {
2426 case 0:
2c2b62d5 2427 cfg.dir = DMA_MEM_TO_DEV;
fa332de5
LJ		 2428 cfg.dst_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2429 break;
2430 case 1:
2c2b62d5 2431 cfg.dir = DMA_DEV_TO_MEM;
fa332de5
LJ		 2432 cfg.src_info.big_endian = D40_DT_FLAGS_BIG_ENDIAN(flags);
2433 break;
2434 }
2435
2436 if (D40_DT_FLAGS_FIXED_CHAN(flags)) {
2437 cfg.phy_channel = dma_spec->args[1];
2438 cfg.use_fixed_channel = true;
2439 }
2440
2441 return dma_request_channel(cap, stedma40_filter, &cfg);
2442}
2443
8d318a50
LW		 2444/* DMA ENGINE functions */
2445static int d40_alloc_chan_resources(struct dma_chan *chan)
2446{
2447 int err;
2448 unsigned long flags;
2449 struct d40_chan *d40c =
2450 container_of(chan, struct d40_chan, chan);
ef1872ec 2451 bool is_free_phy;
8d318a50
LW		 2452 spin_lock_irqsave(&d40c->lock, flags);
2453
d3ee98cd 2454 dma_cookie_init(chan);
8d318a50 2455
ce2ca125
RV		 2456 /* If no dma configuration is set use default configuration (memcpy) */
2457 if (!d40c->configured) {
8d318a50 2458 err = d40_config_memcpy(d40c);
ff0b12ba 2459 if (err) {
6db5a8ba 2460 chan_err(d40c, "Failed to configure memcpy channel\n");
ff0b12ba
JA		 2461 goto fail;
2462 }
8d318a50
LW		 2463 }
2464
5cd326fd 2465 err = d40_allocate_channel(d40c, &is_free_phy);
8d318a50 2466 if (err) {
6db5a8ba 2467 chan_err(d40c, "Failed to allocate channel\n");
7fb3e75e 2468 d40c->configured = false;
ff0b12ba 2469 goto fail;
8d318a50
LW		 2470 }
2471
7fb3e75e 2472 pm_runtime_get_sync(d40c->base->dev);
ef1872ec 2473
ac2c0a38
RV		 2474 d40_set_prio_realtime(d40c);
2475
724a8577 2476 if (chan_is_logical(d40c)) {
2c2b62d5 2477 if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
ef1872ec 2478 d40c->lcpa = d40c->base->lcpa_base +
26955c07 2479 d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
ef1872ec
LW		 2480 else
2481 d40c->lcpa = d40c->base->lcpa_base +
26955c07 2482 d40c->dma_cfg.dev_type *
f26e03ad 2483 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
9778256b
LJ		 2484
2485 /* Unmask the Global Interrupt Mask. */
2486 d40c->src_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
2487 d40c->dst_def_cfg |= BIT(D40_SREG_CFG_LOG_GIM_POS);
ef1872ec
LW		 2488 }
2489
5cd326fd
N		 2490 dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
2491 chan_is_logical(d40c) ? "logical" : "physical",
2492 d40c->phy_chan->num,
2493 d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2494
2495
ef1872ec
LW		 2496 /*
2497 * Only write channel configuration to the DMA if the physical
2498 * resource is free. In case of multiple logical channels
2499 * on the same physical resource, only the first write is necessary.
2500 */
b55912c6
JA		 2501 if (is_free_phy)
2502 d40_config_write(d40c);
ff0b12ba 2503fail:
7fb3e75e
N		 2504 pm_runtime_mark_last_busy(d40c->base->dev);
2505 pm_runtime_put_autosuspend(d40c->base->dev);
8d318a50 2506 spin_unlock_irqrestore(&d40c->lock, flags);
ff0b12ba 2507 return err;
8d318a50
LW		 2508}
2509
2510static void d40_free_chan_resources(struct dma_chan *chan)
2511{
2512 struct d40_chan *d40c =
2513 container_of(chan, struct d40_chan, chan);
2514 int err;
2515 unsigned long flags;
2516
0d0f6b8b 2517 if (d40c->phy_chan == NULL) {
6db5a8ba 2518 chan_err(d40c, "Cannot free unallocated channel\n");
0d0f6b8b
JA		 2519 return;
2520 }
2521
8d318a50
LW		 2522 spin_lock_irqsave(&d40c->lock, flags);
2523
2524 err = d40_free_dma(d40c);
2525
2526 if (err)
6db5a8ba 2527 chan_err(d40c, "Failed to free channel\n");
8d318a50
LW		 2528 spin_unlock_irqrestore(&d40c->lock, flags);
2529}
2530
2531static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2532 dma_addr_t dst,
2533 dma_addr_t src,
2534 size_t size,
2a614340 2535 unsigned long dma_flags)
8d318a50 2536{
95944c6e
RV		 2537 struct scatterlist dst_sg;
2538 struct scatterlist src_sg;
8d318a50 2539
95944c6e
RV		 2540 sg_init_table(&dst_sg, 1);
2541 sg_init_table(&src_sg, 1);
8d318a50 2542
95944c6e
RV		 2543 sg_dma_address(&dst_sg) = dst;
2544 sg_dma_address(&src_sg) = src;
8d318a50 2545
95944c6e
RV		 2546 sg_dma_len(&dst_sg) = size;
2547 sg_dma_len(&src_sg) = size;
8d318a50 2548
cade1d30 2549 return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
8d318a50
LW		 2550}
2551
0d688662 2552static struct dma_async_tx_descriptor *
cade1d30
RV		 2553d40_prep_memcpy_sg(struct dma_chan *chan,
2554 struct scatterlist *dst_sg, unsigned int dst_nents,
2555 struct scatterlist *src_sg, unsigned int src_nents,
2556 unsigned long dma_flags)
0d688662
IS		 2557{
2558 if (dst_nents != src_nents)
2559 return NULL;
2560
cade1d30 2561 return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
00ac0341
RV		 2562}
2563
f26e03ad
FB		 2564static struct dma_async_tx_descriptor *
2565d40_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2566 unsigned int sg_len, enum dma_transfer_direction direction,
2567 unsigned long dma_flags, void *context)
8d318a50 2568{
a725dcc0 2569 if (!is_slave_direction(direction))
00ac0341
RV		 2570 return NULL;
2571
cade1d30 2572 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
8d318a50
LW		 2573}
2574
0c842b55
RV		 2575static struct dma_async_tx_descriptor *
2576dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2577 size_t buf_len, size_t period_len,
ec8b5e48
PU		 2578 enum dma_transfer_direction direction, unsigned long flags,
2579 void *context)
0c842b55
RV		 2580{
2581 unsigned int periods = buf_len / period_len;
2582 struct dma_async_tx_descriptor *txd;
2583 struct scatterlist *sg;
2584 int i;
2585
79ca7ec3 2586 sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
0c842b55
RV		 2587 for (i = 0; i < periods; i++) {
2588 sg_dma_address(&sg[i]) = dma_addr;
2589 sg_dma_len(&sg[i]) = period_len;
2590 dma_addr += period_len;
2591 }
2592
2593 sg[periods].offset = 0;
fdaf9c4b 2594 sg_dma_len(&sg[periods]) = 0;
0c842b55
RV		 2595 sg[periods].page_link =
2596 ((unsigned long)sg | 0x01) & ~0x02;
2597
2598 txd = d40_prep_sg(chan, sg, sg, periods, direction,
2599 DMA_PREP_INTERRUPT);
2600
2601 kfree(sg);
2602
2603 return txd;
2604}
2605
8d318a50
LW		 2606static enum dma_status d40_tx_status(struct dma_chan *chan,
2607 dma_cookie_t cookie,
2608 struct dma_tx_state *txstate)
2609{
2610 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
96a2af41 2611 enum dma_status ret;
8d318a50 2612
0d0f6b8b 2613 if (d40c->phy_chan == NULL) {
6db5a8ba 2614 chan_err(d40c, "Cannot read status of unallocated channel\n");
0d0f6b8b
JA		 2615 return -EINVAL;
2616 }
2617
96a2af41
RKAL		 2618 ret = dma_cookie_status(chan, cookie, txstate);
2619 if (ret != DMA_SUCCESS)
2620 dma_set_residue(txstate, stedma40_residue(chan));
8d318a50 2621
a5ebca47
JA		 2622 if (d40_is_paused(d40c))
2623 ret = DMA_PAUSED;
8d318a50
LW		 2624
2625 return ret;
2626}
2627
2628static void d40_issue_pending(struct dma_chan *chan)
2629{
2630 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2631 unsigned long flags;
2632
0d0f6b8b 2633 if (d40c->phy_chan == NULL) {
6db5a8ba 2634 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2635 return;
2636 }
2637
8d318a50
LW		 2638 spin_lock_irqsave(&d40c->lock, flags);
2639
a8f3067b
PF		 2640 list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2641
2642 /* Busy means that queued jobs are already being processed */
8d318a50
LW		 2643 if (!d40c->busy)
2644 (void) d40_queue_start(d40c);
2645
2646 spin_unlock_irqrestore(&d40c->lock, flags);
2647}
2648
1bdae6f4
N		 2649static void d40_terminate_all(struct dma_chan *chan)
2650{
2651 unsigned long flags;
2652 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2653 int ret;
2654
2655 spin_lock_irqsave(&d40c->lock, flags);
2656
2657 pm_runtime_get_sync(d40c->base->dev);
2658 ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
2659 if (ret)
2660 chan_err(d40c, "Failed to stop channel\n");
2661
2662 d40_term_all(d40c);
2663 pm_runtime_mark_last_busy(d40c->base->dev);
2664 pm_runtime_put_autosuspend(d40c->base->dev);
2665 if (d40c->busy) {
2666 pm_runtime_mark_last_busy(d40c->base->dev);
2667 pm_runtime_put_autosuspend(d40c->base->dev);
2668 }
2669 d40c->busy = false;
2670
2671 spin_unlock_irqrestore(&d40c->lock, flags);
2672}
2673
98ca5289
RV		 2674static int
2675dma40_config_to_halfchannel(struct d40_chan *d40c,
2676 struct stedma40_half_channel_info *info,
98ca5289
RV		 2677 u32 maxburst)
2678{
98ca5289
RV		 2679 int psize;
2680
98ca5289
RV		 2681 if (chan_is_logical(d40c)) {
2682 if (maxburst >= 16)
2683 psize = STEDMA40_PSIZE_LOG_16;
2684 else if (maxburst >= 8)
2685 psize = STEDMA40_PSIZE_LOG_8;
2686 else if (maxburst >= 4)
2687 psize = STEDMA40_PSIZE_LOG_4;
2688 else
2689 psize = STEDMA40_PSIZE_LOG_1;
2690 } else {
2691 if (maxburst >= 16)
2692 psize = STEDMA40_PSIZE_PHY_16;
2693 else if (maxburst >= 8)
2694 psize = STEDMA40_PSIZE_PHY_8;
2695 else if (maxburst >= 4)
2696 psize = STEDMA40_PSIZE_PHY_4;
2697 else
2698 psize = STEDMA40_PSIZE_PHY_1;
2699 }
2700
98ca5289
RV		 2701 info->psize = psize;
2702 info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2703
2704 return 0;
2705}
2706
95e1400f 2707/* Runtime reconfiguration extension */
98ca5289
RV		 2708static int d40_set_runtime_config(struct dma_chan *chan,
2709 struct dma_slave_config *config)
95e1400f
LW		 2710{
2711 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2712 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
98ca5289 2713 enum dma_slave_buswidth src_addr_width, dst_addr_width;
95e1400f 2714 dma_addr_t config_addr;
98ca5289
RV		 2715 u32 src_maxburst, dst_maxburst;
2716 int ret;
2717
2718 src_addr_width = config->src_addr_width;
2719 src_maxburst = config->src_maxburst;
2720 dst_addr_width = config->dst_addr_width;
2721 dst_maxburst = config->dst_maxburst;
95e1400f 2722
db8196df 2723 if (config->direction == DMA_DEV_TO_MEM) {
95e1400f 2724 config_addr = config->src_addr;
ef9c89b3 2725
2c2b62d5 2726 if (cfg->dir != DMA_DEV_TO_MEM)
95e1400f
LW		 2727 dev_dbg(d40c->base->dev,
2728 "channel was not configured for peripheral "
2729 "to memory transfer (%d) overriding\n",
2730 cfg->dir);
2c2b62d5 2731 cfg->dir = DMA_DEV_TO_MEM;
95e1400f 2732
98ca5289
RV		 2733 /* Configure the memory side */
2734 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2735 dst_addr_width = src_addr_width;
2736 if (dst_maxburst == 0)
2737 dst_maxburst = src_maxburst;
95e1400f 2738
db8196df 2739 } else if (config->direction == DMA_MEM_TO_DEV) {
95e1400f 2740 config_addr = config->dst_addr;
ef9c89b3 2741
2c2b62d5 2742 if (cfg->dir != DMA_MEM_TO_DEV)
95e1400f
LW		 2743 dev_dbg(d40c->base->dev,
2744 "channel was not configured for memory "
2745 "to peripheral transfer (%d) overriding\n",
2746 cfg->dir);
2c2b62d5 2747 cfg->dir = DMA_MEM_TO_DEV;
95e1400f 2748
98ca5289
RV		 2749 /* Configure the memory side */
2750 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2751 src_addr_width = dst_addr_width;
2752 if (src_maxburst == 0)
2753 src_maxburst = dst_maxburst;
95e1400f
LW		 2754 } else {
2755 dev_err(d40c->base->dev,
2756 "unrecognized channel direction %d\n",
2757 config->direction);
98ca5289 2758 return -EINVAL;
95e1400f
LW		 2759 }
2760
ef9c89b3
LJ		 2761 if (config_addr <= 0) {
2762 dev_err(d40c->base->dev, "no address supplied\n");
2763 return -EINVAL;
2764 }
2765
98ca5289 2766 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
95e1400f 2767 dev_err(d40c->base->dev,
98ca5289
RV		 2768 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2769 src_maxburst,
2770 src_addr_width,
2771 dst_maxburst,
2772 dst_addr_width);
2773 return -EINVAL;
95e1400f
LW		 2774 }
2775
92bb6cdb
PF		 2776 if (src_maxburst > 16) {
2777 src_maxburst = 16;
2778 dst_maxburst = src_maxburst * src_addr_width / dst_addr_width;
2779 } else if (dst_maxburst > 16) {
2780 dst_maxburst = 16;
2781 src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
2782 }
2783
43f2e1a3
LJ		 2784 /* Only valid widths are; 1, 2, 4 and 8. */
2785 if (src_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2786 src_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
2787 dst_addr_width <= DMA_SLAVE_BUSWIDTH_UNDEFINED ||
2788 dst_addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES ||
2789 ((src_addr_width > 1) && (src_addr_width & 1)) ||
2790 ((dst_addr_width > 1) && (dst_addr_width & 1)))
2791 return -EINVAL;
2792
2793 cfg->src_info.data_width = src_addr_width;
2794 cfg->dst_info.data_width = dst_addr_width;
2795
98ca5289 2796 ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
98ca5289
RV		 2797 src_maxburst);
2798 if (ret)
2799 return ret;
95e1400f 2800
98ca5289 2801 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
98ca5289
RV		 2802 dst_maxburst);
2803 if (ret)
2804 return ret;
95e1400f 2805
a59670a4 2806 /* Fill in register values */
724a8577 2807 if (chan_is_logical(d40c))
a59670a4
PF		 2808 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2809 else
57e65ad7 2810 d40_phy_cfg(cfg, &d40c->src_def_cfg, &d40c->dst_def_cfg);
a59670a4 2811
95e1400f
LW		 2812 /* These settings will take precedence later */
2813 d40c->runtime_addr = config_addr;
2814 d40c->runtime_direction = config->direction;
2815 dev_dbg(d40c->base->dev,
98ca5289
RV		 2816 "configured channel %s for %s, data width %d/%d, "
2817 "maxburst %d/%d elements, LE, no flow control\n",
95e1400f 2818 dma_chan_name(chan),
db8196df 2819 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
98ca5289
RV		 2820 src_addr_width, dst_addr_width,
2821 src_maxburst, dst_maxburst);
2822
2823 return 0;
95e1400f
LW		 2824}
2825
05827630
LW		 2826static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2827 unsigned long arg)
8d318a50 2828{
8d318a50
LW		 2829 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2830
0d0f6b8b 2831 if (d40c->phy_chan == NULL) {
6db5a8ba 2832 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2833 return -EINVAL;
2834 }
2835
8d318a50
LW		 2836 switch (cmd) {
2837 case DMA_TERMINATE_ALL:
1bdae6f4
N		 2838 d40_terminate_all(chan);
2839 return 0;
8d318a50 2840 case DMA_PAUSE:
86eb5fb6 2841 return d40_pause(d40c);
8d318a50 2842 case DMA_RESUME:
86eb5fb6 2843 return d40_resume(d40c);
95e1400f 2844 case DMA_SLAVE_CONFIG:
98ca5289 2845 return d40_set_runtime_config(chan,
95e1400f 2846 (struct dma_slave_config *) arg);
95e1400f
LW		 2847 default:
2848 break;
8d318a50
LW		 2849 }
2850
2851 /* Other commands are unimplemented */
2852 return -ENXIO;
2853}
2854
2855/* Initialization functions */
2856
2857static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2858 struct d40_chan *chans, int offset,
2859 int num_chans)
2860{
2861 int i = 0;
2862 struct d40_chan *d40c;
2863
2864 INIT_LIST_HEAD(&dma->channels);
2865
2866 for (i = offset; i < offset + num_chans; i++) {
2867 d40c = &chans[i];
2868 d40c->base = base;
2869 d40c->chan.device = dma;
2870
8d318a50
LW		 2871 spin_lock_init(&d40c->lock);
2872
2873 d40c->log_num = D40_PHY_CHAN;
2874
4226dd86 2875 INIT_LIST_HEAD(&d40c->done);
8d318a50
LW		 2876 INIT_LIST_HEAD(&d40c->active);
2877 INIT_LIST_HEAD(&d40c->queue);
a8f3067b 2878 INIT_LIST_HEAD(&d40c->pending_queue);
8d318a50 2879 INIT_LIST_HEAD(&d40c->client);
82babbb3 2880 INIT_LIST_HEAD(&d40c->prepare_queue);
8d318a50 2881
8d318a50
LW		 2882 tasklet_init(&d40c->tasklet, dma_tasklet,
2883 (unsigned long) d40c);
2884
2885 list_add_tail(&d40c->chan.device_node,
2886 &dma->channels);
2887 }
2888}
2889
7ad74a7c
RV		 2890static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2891{
2892 if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2893 dev->device_prep_slave_sg = d40_prep_slave_sg;
2894
2895 if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2896 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2897
2898 /*
2899 * This controller can only access address at even
2900 * 32bit boundaries, i.e. 2^2
2901 */
2902 dev->copy_align = 2;
2903 }
2904
2905 if (dma_has_cap(DMA_SG, dev->cap_mask))
2906 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2907
0c842b55
RV		 2908 if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2909 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2910
7ad74a7c
RV		 2911 dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2912 dev->device_free_chan_resources = d40_free_chan_resources;
2913 dev->device_issue_pending = d40_issue_pending;
2914 dev->device_tx_status = d40_tx_status;
2915 dev->device_control = d40_control;
2916 dev->dev = base->dev;
2917}
2918
8d318a50
LW		 2919static int __init d40_dmaengine_init(struct d40_base *base,
2920 int num_reserved_chans)
2921{
2922 int err ;
2923
2924 d40_chan_init(base, &base->dma_slave, base->log_chans,
2925 0, base->num_log_chans);
2926
2927 dma_cap_zero(base->dma_slave.cap_mask);
2928 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
0c842b55 2929 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
8d318a50 2930
7ad74a7c 2931 d40_ops_init(base, &base->dma_slave);
8d318a50
LW		 2932
2933 err = dma_async_device_register(&base->dma_slave);
2934
2935 if (err) {
6db5a8ba 2936 d40_err(base->dev, "Failed to register slave channels\n");
8d318a50
LW		 2937 goto failure1;
2938 }
2939
2940 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
664a57ec 2941 base->num_log_chans, ARRAY_SIZE(dma40_memcpy_channels));
8d318a50
LW		 2942
2943 dma_cap_zero(base->dma_memcpy.cap_mask);
2944 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
7ad74a7c
RV		 2945 dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
2946
2947 d40_ops_init(base, &base->dma_memcpy);
8d318a50
LW		 2948
2949 err = dma_async_device_register(&base->dma_memcpy);
2950
2951 if (err) {
6db5a8ba
RV		 2952 d40_err(base->dev,
2953 "Failed to regsiter memcpy only channels\n");
8d318a50
LW		 2954 goto failure2;
2955 }
2956
2957 d40_chan_init(base, &base->dma_both, base->phy_chans,
2958 0, num_reserved_chans);
2959
2960 dma_cap_zero(base->dma_both.cap_mask);
2961 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2962 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
7ad74a7c 2963 dma_cap_set(DMA_SG, base->dma_both.cap_mask);
0c842b55 2964 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
7ad74a7c
RV		 2965
2966 d40_ops_init(base, &base->dma_both);
8d318a50
LW		 2967 err = dma_async_device_register(&base->dma_both);
2968
2969 if (err) {
6db5a8ba
RV		 2970 d40_err(base->dev,
2971 "Failed to register logical and physical capable channels\n");
8d318a50
LW		 2972 goto failure3;
2973 }
2974 return 0;
2975failure3:
2976 dma_async_device_unregister(&base->dma_memcpy);
2977failure2:
2978 dma_async_device_unregister(&base->dma_slave);
2979failure1:
2980 return err;
2981}
2982
7fb3e75e
N		 2983/* Suspend resume functionality */
2984#ifdef CONFIG_PM
2985static int dma40_pm_suspend(struct device *dev)
2986{
28c7a19d
N		 2987 struct platform_device *pdev = to_platform_device(dev);
2988 struct d40_base *base = platform_get_drvdata(pdev);
2989 int ret = 0;
7fb3e75e 2990
28c7a19d
N		 2991 if (base->lcpa_regulator)
2992 ret = regulator_disable(base->lcpa_regulator);
2993 return ret;
7fb3e75e
N		 2994}
2995
2996static int dma40_runtime_suspend(struct device *dev)
2997{
2998 struct platform_device *pdev = to_platform_device(dev);
2999 struct d40_base *base = platform_get_drvdata(pdev);
3000
3001 d40_save_restore_registers(base, true);
3002
3003 /* Don't disable/enable clocks for v1 due to HW bugs */
3004 if (base->rev != 1)
3005 writel_relaxed(base->gcc_pwr_off_mask,
3006 base->virtbase + D40_DREG_GCC);
3007
3008 return 0;
3009}
3010
3011static int dma40_runtime_resume(struct device *dev)
3012{
3013 struct platform_device *pdev = to_platform_device(dev);
3014 struct d40_base *base = platform_get_drvdata(pdev);
3015
3016 if (base->initialized)
3017 d40_save_restore_registers(base, false);
3018
3019 writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
3020 base->virtbase + D40_DREG_GCC);
3021 return 0;
3022}
3023
28c7a19d
N		 3024static int dma40_resume(struct device *dev)
3025{
3026 struct platform_device *pdev = to_platform_device(dev);
3027 struct d40_base *base = platform_get_drvdata(pdev);
3028 int ret = 0;
3029
3030 if (base->lcpa_regulator)
3031 ret = regulator_enable(base->lcpa_regulator);
3032
3033 return ret;
3034}
7fb3e75e
N		 3035
3036static const struct dev_pm_ops dma40_pm_ops = {
3037 .suspend = dma40_pm_suspend,
3038 .runtime_suspend = dma40_runtime_suspend,
3039 .runtime_resume = dma40_runtime_resume,
28c7a19d 3040 .resume = dma40_resume,
7fb3e75e
N		 3041};
3042#define DMA40_PM_OPS (&dma40_pm_ops)
3043#else
3044#define DMA40_PM_OPS NULL
3045#endif
3046
8d318a50
LW		 3047/* Initialization functions. */
3048
3049static int __init d40_phy_res_init(struct d40_base *base)
3050{
3051 int i;
3052 int num_phy_chans_avail = 0;
3053 u32 val[2];
3054 int odd_even_bit = -2;
7fb3e75e 3055 int gcc = D40_DREG_GCC_ENA;
8d318a50
LW		 3056
3057 val[0] = readl(base->virtbase + D40_DREG_PRSME);
3058 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
3059
3060 for (i = 0; i < base->num_phy_chans; i++) {
3061 base->phy_res[i].num = i;
3062 odd_even_bit += 2 * ((i % 2) == 0);
3063 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
3064 /* Mark security only channels as occupied */
3065 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
3066 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
7fb3e75e
N		 3067 base->phy_res[i].reserved = true;
3068 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3069 D40_DREG_GCC_SRC);
3070 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3071 D40_DREG_GCC_DST);
3072
3073
8d318a50
LW		 3074 } else {
3075 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
3076 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
7fb3e75e 3077 base->phy_res[i].reserved = false;
8d318a50
LW		 3078 num_phy_chans_avail++;
3079 }
3080 spin_lock_init(&base->phy_res[i].lock);
3081 }
6b7acd84
JA		 3082
3083 /* Mark disabled channels as occupied */
3084 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
f57b407c
RV		 3085 int chan = base->plat_data->disabled_channels[i];
3086
3087 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
3088 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
7fb3e75e
N		 3089 base->phy_res[chan].reserved = true;
3090 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3091 D40_DREG_GCC_SRC);
3092 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3093 D40_DREG_GCC_DST);
f57b407c 3094 num_phy_chans_avail--;
6b7acd84
JA		 3095 }
3096
7407048b
FB		 3097 /* Mark soft_lli channels */
3098 for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) {
3099 int chan = base->plat_data->soft_lli_chans[i];
3100
3101 base->phy_res[chan].use_soft_lli = true;
3102 }
3103
8d318a50
LW		 3104 dev_info(base->dev, "%d of %d physical DMA channels available\n",
3105 num_phy_chans_avail, base->num_phy_chans);
3106
3107 /* Verify settings extended vs standard */
3108 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
3109
3110 for (i = 0; i < base->num_phy_chans; i++) {
3111
3112 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
3113 (val[0] & 0x3) != 1)
3114 dev_info(base->dev,
3115 "[%s] INFO: channel %d is misconfigured (%d)\n",
3116 __func__, i, val[0] & 0x3);
3117
3118 val[0] = val[0] >> 2;
3119 }
3120
7fb3e75e
N		 3121 /*
3122 * To keep things simple, Enable all clocks initially.
3123 * The clocks will get managed later post channel allocation.
3124 * The clocks for the event lines on which reserved channels exists
3125 * are not managed here.
3126 */
3127 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3128 base->gcc_pwr_off_mask = gcc;
3129
8d318a50
LW		 3130 return num_phy_chans_avail;
3131}
3132
3133static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3134{
bb75d93b 3135 struct stedma40_platform_data *plat_data = pdev->dev.platform_data;
8d318a50
LW		 3136 struct clk *clk = NULL;
3137 void __iomem *virtbase = NULL;
3138 struct resource *res = NULL;
3139 struct d40_base *base = NULL;
3140 int num_log_chans = 0;
3141 int num_phy_chans;
b707c658 3142 int clk_ret = -EINVAL;
8d318a50 3143 int i;
f4b89764
LW		 3144 u32 pid;
3145 u32 cid;
3146 u8 rev;
8d318a50
LW		 3147
3148 clk = clk_get(&pdev->dev, NULL);
8d318a50 3149 if (IS_ERR(clk)) {
6db5a8ba 3150 d40_err(&pdev->dev, "No matching clock found\n");
8d318a50
LW		 3151 goto failure;
3152 }
3153
b707c658
UH		 3154 clk_ret = clk_prepare_enable(clk);
3155 if (clk_ret) {
3156 d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
3157 goto failure;
3158 }
8d318a50
LW		 3159
3160 /* Get IO for DMAC base address */
3161 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
3162 if (!res)
3163 goto failure;
3164
3165 if (request_mem_region(res->start, resource_size(res),
3166 D40_NAME " I/O base") == NULL)
3167 goto failure;
3168
3169 virtbase = ioremap(res->start, resource_size(res));
3170 if (!virtbase)
3171 goto failure;
3172
f4b89764
LW		 3173 /* This is just a regular AMBA PrimeCell ID actually */
3174 for (pid = 0, i = 0; i < 4; i++)
3175 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
3176 & 255) << (i * 8);
3177 for (cid = 0, i = 0; i < 4; i++)
3178 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
3179 & 255) << (i * 8);
8d318a50 3180
f4b89764
LW		 3181 if (cid != AMBA_CID) {
3182 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
3183 goto failure;
3184 }
3185 if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
6db5a8ba 3186 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
f4b89764
LW		 3187 AMBA_MANF_BITS(pid),
3188 AMBA_VENDOR_ST);
8d318a50
LW		 3189 goto failure;
3190 }
f4b89764
LW		 3191 /*
3192 * HW revision:
3193 * DB8500ed has revision 0
3194 * ? has revision 1
3195 * DB8500v1 has revision 2
3196 * DB8500v2 has revision 3
47db92f4
GB		 3197 * AP9540v1 has revision 4
3198 * DB8540v1 has revision 4
f4b89764
LW		 3199 */
3200 rev = AMBA_REV_BITS(pid);
8b2fe9b6
LJ		 3201 if (rev < 2) {
3202 d40_err(&pdev->dev, "hardware revision: %d is not supported", rev);
3203 goto failure;
3204 }
3ae0267f 3205
8d318a50 3206 /* The number of physical channels on this HW */
47db92f4
GB		 3207 if (plat_data->num_of_phy_chans)
3208 num_phy_chans = plat_data->num_of_phy_chans;
3209 else
3210 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
8d318a50 3211
db72da92
LJ		 3212 num_log_chans = num_phy_chans * D40_MAX_LOG_CHAN_PER_PHY;
3213
b2abb249
LJ		 3214 dev_info(&pdev->dev,
3215 "hardware rev: %d @ 0x%x with %d physical and %d logical channels\n",
3216 rev, res->start, num_phy_chans, num_log_chans);
8d318a50 3217
8d318a50 3218 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
664a57ec 3219 (num_phy_chans + num_log_chans + ARRAY_SIZE(dma40_memcpy_channels)) *
8d318a50
LW		 3220 sizeof(struct d40_chan), GFP_KERNEL);
3221
3222 if (base == NULL) {
6db5a8ba 3223 d40_err(&pdev->dev, "Out of memory\n");
8d318a50
LW		 3224 goto failure;
3225 }
3226
3ae0267f 3227 base->rev = rev;
8d318a50
LW		 3228 base->clk = clk;
3229 base->num_phy_chans = num_phy_chans;
3230 base->num_log_chans = num_log_chans;
3231 base->phy_start = res->start;
3232 base->phy_size = resource_size(res);
3233 base->virtbase = virtbase;
3234 base->plat_data = plat_data;
3235 base->dev = &pdev->dev;
3236 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
3237 base->log_chans = &base->phy_chans[num_phy_chans];
3238
3cb645dc
TL		 3239 if (base->plat_data->num_of_phy_chans == 14) {
3240 base->gen_dmac.backup = d40_backup_regs_v4b;
3241 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;
3242 base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;
3243 base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;
3244 base->gen_dmac.realtime_en = D40_DREG_CRSEG1;
3245 base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;
3246 base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;
3247 base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;
3248 base->gen_dmac.il = il_v4b;
3249 base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);
3250 base->gen_dmac.init_reg = dma_init_reg_v4b;
3251 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);
3252 } else {
3253 if (base->rev >= 3) {
3254 base->gen_dmac.backup = d40_backup_regs_v4a;
3255 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;
3256 }
3257 base->gen_dmac.interrupt_en = D40_DREG_PCMIS;
3258 base->gen_dmac.interrupt_clear = D40_DREG_PCICR;
3259 base->gen_dmac.realtime_en = D40_DREG_RSEG1;
3260 base->gen_dmac.realtime_clear = D40_DREG_RCEG1;
3261 base->gen_dmac.high_prio_en = D40_DREG_PSEG1;
3262 base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;
3263 base->gen_dmac.il = il_v4a;
3264 base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);
3265 base->gen_dmac.init_reg = dma_init_reg_v4a;
3266 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
3267 }
3268
8d318a50
LW		 3269 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
3270 GFP_KERNEL);
3271 if (!base->phy_res)
3272 goto failure;
3273
3274 base->lookup_phy_chans = kzalloc(num_phy_chans *
3275 sizeof(struct d40_chan *),
3276 GFP_KERNEL);
3277 if (!base->lookup_phy_chans)
3278 goto failure;
3279
8a59fed3
LJ		 3280 base->lookup_log_chans = kzalloc(num_log_chans *
3281 sizeof(struct d40_chan *),
3282 GFP_KERNEL);
3283 if (!base->lookup_log_chans)
3284 goto failure;
698e4732 3285
7fb3e75e
N		 3286 base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
3287 sizeof(d40_backup_regs_chan),
8d318a50 3288 GFP_KERNEL);
7fb3e75e
N		 3289 if (!base->reg_val_backup_chan)
3290 goto failure;
3291
3292 base->lcla_pool.alloc_map =
3293 kzalloc(num_phy_chans * sizeof(struct d40_desc *)
3294 * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
8d318a50
LW		 3295 if (!base->lcla_pool.alloc_map)
3296 goto failure;
3297
c675b1b4
JA		 3298 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
3299 0, SLAB_HWCACHE_ALIGN,
3300 NULL);
3301 if (base->desc_slab == NULL)
3302 goto failure;
3303
8d318a50
LW		 3304 return base;
3305
3306failure:
b707c658
UH		 3307 if (!clk_ret)
3308 clk_disable_unprepare(clk);
3309 if (!IS_ERR(clk))
8d318a50 3310 clk_put(clk);
8d318a50
LW		 3311 if (virtbase)
3312 iounmap(virtbase);
3313 if (res)
3314 release_mem_region(res->start,
3315 resource_size(res));
3316 if (virtbase)
3317 iounmap(virtbase);
3318
3319 if (base) {
3320 kfree(base->lcla_pool.alloc_map);
1bdae6f4 3321 kfree(base->reg_val_backup_chan);
8d318a50
LW		 3322 kfree(base->lookup_log_chans);
3323 kfree(base->lookup_phy_chans);
3324 kfree(base->phy_res);
3325 kfree(base);
3326 }
3327
3328 return NULL;
3329}
3330
3331static void __init d40_hw_init(struct d40_base *base)
3332{
3333
8d318a50
LW		 3334 int i;
3335 u32 prmseo[2] = {0, 0};
3336 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3337 u32 pcmis = 0;
3338 u32 pcicr = 0;
3cb645dc
TL		 3339 struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;
3340 u32 reg_size = base->gen_dmac.init_reg_size;
8d318a50 3341
3cb645dc 3342 for (i = 0; i < reg_size; i++)
8d318a50
LW		 3343 writel(dma_init_reg[i].val,
3344 base->virtbase + dma_init_reg[i].reg);
3345
3346 /* Configure all our dma channels to default settings */
3347 for (i = 0; i < base->num_phy_chans; i++) {
3348
3349 activeo[i % 2] = activeo[i % 2] << 2;
3350
3351 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
3352 == D40_ALLOC_PHY) {
3353 activeo[i % 2] |= 3;
3354 continue;
3355 }
3356
3357 /* Enable interrupt # */
3358 pcmis = (pcmis << 1) | 1;
3359
3360 /* Clear interrupt # */
3361 pcicr = (pcicr << 1) | 1;
3362
3363 /* Set channel to physical mode */
3364 prmseo[i % 2] = prmseo[i % 2] << 2;
3365 prmseo[i % 2] |= 1;
3366
3367 }
3368
3369 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3370 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3371 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3372 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3373
3374 /* Write which interrupt to enable */
3cb645dc 3375 writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
8d318a50
LW		 3376
3377 /* Write which interrupt to clear */
3cb645dc 3378 writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
8d318a50 3379
3cb645dc
TL		 3380 /* These are __initdata and cannot be accessed after init */
3381 base->gen_dmac.init_reg = NULL;
3382 base->gen_dmac.init_reg_size = 0;
8d318a50
LW		 3383}
3384
508849ad
LW		 3385static int __init d40_lcla_allocate(struct d40_base *base)
3386{
026cbc42 3387 struct d40_lcla_pool *pool = &base->lcla_pool;
508849ad
LW		 3388 unsigned long *page_list;
3389 int i, j;
3390 int ret = 0;
3391
3392 /*
3393 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3394 * To full fill this hardware requirement without wasting 256 kb
3395 * we allocate pages until we get an aligned one.
3396 */
3397 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
3398 GFP_KERNEL);
3399
3400 if (!page_list) {
3401 ret = -ENOMEM;
3402 goto failure;
3403 }
3404
3405 /* Calculating how many pages that are required */
3406 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
3407
3408 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
3409 page_list[i] = __get_free_pages(GFP_KERNEL,
3410 base->lcla_pool.pages);
3411 if (!page_list[i]) {
3412
6db5a8ba
RV		 3413 d40_err(base->dev, "Failed to allocate %d pages.\n",
3414 base->lcla_pool.pages);
508849ad
LW		 3415
3416 for (j = 0; j < i; j++)
3417 free_pages(page_list[j], base->lcla_pool.pages);
3418 goto failure;
3419 }
3420
3421 if ((virt_to_phys((void *)page_list[i]) &
3422 (LCLA_ALIGNMENT - 1)) == 0)
3423 break;
3424 }
3425
3426 for (j = 0; j < i; j++)
3427 free_pages(page_list[j], base->lcla_pool.pages);
3428
3429 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
3430 base->lcla_pool.base = (void *)page_list[i];
3431 } else {
767a9675
JA		 3432 /*
3433 * After many attempts and no succees with finding the correct
3434 * alignment, try with allocating a big buffer.
3435 */
508849ad
LW		 3436 dev_warn(base->dev,
3437 "[%s] Failed to get %d pages @ 18 bit align.\n",
3438 __func__, base->lcla_pool.pages);
3439 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
3440 base->num_phy_chans +
3441 LCLA_ALIGNMENT,
3442 GFP_KERNEL);
3443 if (!base->lcla_pool.base_unaligned) {
3444 ret = -ENOMEM;
3445 goto failure;
3446 }
3447
3448 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
3449 LCLA_ALIGNMENT);
3450 }
3451
026cbc42
RV		 3452 pool->dma_addr = dma_map_single(base->dev, pool->base,
3453 SZ_1K * base->num_phy_chans,
3454 DMA_TO_DEVICE);
3455 if (dma_mapping_error(base->dev, pool->dma_addr)) {
3456 pool->dma_addr = 0;
3457 ret = -ENOMEM;
3458 goto failure;
3459 }
3460
508849ad
LW		 3461 writel(virt_to_phys(base->lcla_pool.base),
3462 base->virtbase + D40_DREG_LCLA);
3463failure:
3464 kfree(page_list);
3465 return ret;
3466}
3467
1814a170
LJ		 3468static int __init d40_of_probe(struct platform_device *pdev,
3469 struct device_node *np)
3470{
3471 struct stedma40_platform_data *pdata;
3472
3473 /*
3474 * FIXME: Fill in this routine as more support is added.
3475 * First platform enabled (u8500) doens't need any extra
3476 * properties to run, so this is fairly sparce currently.
3477 */
3478
3479 pdata = devm_kzalloc(&pdev->dev,
3480 sizeof(struct stedma40_platform_data),
3481 GFP_KERNEL);
3482 if (!pdata)
3483 return -ENOMEM;
3484
3485 pdev->dev.platform_data = pdata;
3486
3487 return 0;
3488}
3489
8d318a50
LW		 3490static int __init d40_probe(struct platform_device *pdev)
3491{
1814a170
LJ		 3492 struct stedma40_platform_data *plat_data = pdev->dev.platform_data;
3493 struct device_node *np = pdev->dev.of_node;
8d318a50
LW		 3494 int err;
3495 int ret = -ENOENT;
1814a170 3496 struct d40_base *base = NULL;
8d318a50
LW		 3497 struct resource *res = NULL;
3498 int num_reserved_chans;
3499 u32 val;
3500
1814a170
LJ		 3501 if (!plat_data) {
3502 if (np) {
3503 if(d40_of_probe(pdev, np)) {
3504 ret = -ENOMEM;
3505 goto failure;
3506 }
3507 } else {
3508 d40_err(&pdev->dev, "No pdata or Device Tree provided\n");
3509 goto failure;
3510 }
3511 }
8d318a50 3512
1814a170 3513 base = d40_hw_detect_init(pdev);
8d318a50
LW		 3514 if (!base)
3515 goto failure;
3516
3517 num_reserved_chans = d40_phy_res_init(base);
3518
3519 platform_set_drvdata(pdev, base);
3520
3521 spin_lock_init(&base->interrupt_lock);
3522 spin_lock_init(&base->execmd_lock);
3523
3524 /* Get IO for logical channel parameter address */
3525 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
3526 if (!res) {
3527 ret = -ENOENT;
6db5a8ba 3528 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
8d318a50
LW		 3529 goto failure;
3530 }
3531 base->lcpa_size = resource_size(res);
3532 base->phy_lcpa = res->start;
3533
3534 if (request_mem_region(res->start, resource_size(res),
3535 D40_NAME " I/O lcpa") == NULL) {
3536 ret = -EBUSY;
6db5a8ba
RV		 3537 d40_err(&pdev->dev,
3538 "Failed to request LCPA region 0x%x-0x%x\n",
3539 res->start, res->end);
8d318a50
LW		 3540 goto failure;
3541 }
3542
3543 /* We make use of ESRAM memory for this. */
3544 val = readl(base->virtbase + D40_DREG_LCPA);
3545 if (res->start != val && val != 0) {
3546 dev_warn(&pdev->dev,
3547 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
3548 __func__, val, res->start);
3549 } else
3550 writel(res->start, base->virtbase + D40_DREG_LCPA);
3551
3552 base->lcpa_base = ioremap(res->start, resource_size(res));
3553 if (!base->lcpa_base) {
3554 ret = -ENOMEM;
6db5a8ba 3555 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
8d318a50
LW		 3556 goto failure;
3557 }
28c7a19d
N		 3558 /* If lcla has to be located in ESRAM we don't need to allocate */
3559 if (base->plat_data->use_esram_lcla) {
3560 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3561 "lcla_esram");
3562 if (!res) {
3563 ret = -ENOENT;
3564 d40_err(&pdev->dev,
3565 "No \"lcla_esram\" memory resource\n");
3566 goto failure;
3567 }
3568 base->lcla_pool.base = ioremap(res->start,
3569 resource_size(res));
3570 if (!base->lcla_pool.base) {
3571 ret = -ENOMEM;
3572 d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
3573 goto failure;
3574 }
3575 writel(res->start, base->virtbase + D40_DREG_LCLA);
8d318a50 3576
28c7a19d
N		 3577 } else {
3578 ret = d40_lcla_allocate(base);
3579 if (ret) {
3580 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
3581 goto failure;
3582 }
8d318a50
LW		 3583 }
3584
3585 spin_lock_init(&base->lcla_pool.lock);
3586
8d318a50
LW		 3587 base->irq = platform_get_irq(pdev, 0);
3588
3589 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
8d318a50 3590 if (ret) {
6db5a8ba 3591 d40_err(&pdev->dev, "No IRQ defined\n");
8d318a50
LW		 3592 goto failure;
3593 }
3594
7fb3e75e
N		 3595 pm_runtime_irq_safe(base->dev);
3596 pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
3597 pm_runtime_use_autosuspend(base->dev);
3598 pm_runtime_enable(base->dev);
3599 pm_runtime_resume(base->dev);
28c7a19d
N		 3600
3601 if (base->plat_data->use_esram_lcla) {
3602
3603 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
3604 if (IS_ERR(base->lcpa_regulator)) {
3605 d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
3606 base->lcpa_regulator = NULL;
3607 goto failure;
3608 }
3609
3610 ret = regulator_enable(base->lcpa_regulator);
3611 if (ret) {
3612 d40_err(&pdev->dev,
3613 "Failed to enable lcpa_regulator\n");
3614 regulator_put(base->lcpa_regulator);
3615 base->lcpa_regulator = NULL;
3616 goto failure;
3617 }
3618 }
3619
7fb3e75e 3620 base->initialized = true;
8d318a50
LW		 3621 err = d40_dmaengine_init(base, num_reserved_chans);
3622 if (err)
3623 goto failure;
3624
b96710e5
PF		 3625 base->dev->dma_parms = &base->dma_parms;
3626 err = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
3627 if (err) {
3628 d40_err(&pdev->dev, "Failed to set dma max seg size\n");
3629 goto failure;
3630 }
3631
8d318a50
LW		 3632 d40_hw_init(base);
3633
fa332de5
LJ		 3634 if (np) {
3635 err = of_dma_controller_register(np, d40_xlate, NULL);
3636 if (err && err != -ENODEV)
3637 dev_err(&pdev->dev,
3638 "could not register of_dma_controller\n");
3639 }
3640
8d318a50
LW		 3641 dev_info(base->dev, "initialized\n");
3642 return 0;
3643
3644failure:
3645 if (base) {
c675b1b4
JA		 3646 if (base->desc_slab)
3647 kmem_cache_destroy(base->desc_slab);
8d318a50
LW		 3648 if (base->virtbase)
3649 iounmap(base->virtbase);
026cbc42 3650
28c7a19d
N		 3651 if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
3652 iounmap(base->lcla_pool.base);
3653 base->lcla_pool.base = NULL;
3654 }
3655
026cbc42
RV		 3656 if (base->lcla_pool.dma_addr)
3657 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
3658 SZ_1K * base->num_phy_chans,
3659 DMA_TO_DEVICE);
3660
508849ad
LW		 3661 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
3662 free_pages((unsigned long)base->lcla_pool.base,
3663 base->lcla_pool.pages);
767a9675
JA		 3664
3665 kfree(base->lcla_pool.base_unaligned);
3666
8d318a50
LW		 3667 if (base->phy_lcpa)
3668 release_mem_region(base->phy_lcpa,
3669 base->lcpa_size);
3670 if (base->phy_start)
3671 release_mem_region(base->phy_start,
3672 base->phy_size);
3673 if (base->clk) {
da2ac56a 3674 clk_disable_unprepare(base->clk);
8d318a50
LW		 3675 clk_put(base->clk);
3676 }
3677
28c7a19d
N		 3678 if (base->lcpa_regulator) {
3679 regulator_disable(base->lcpa_regulator);
3680 regulator_put(base->lcpa_regulator);
3681 }
3682
8d318a50
LW		 3683 kfree(base->lcla_pool.alloc_map);
3684 kfree(base->lookup_log_chans);
3685 kfree(base->lookup_phy_chans);
3686 kfree(base->phy_res);
3687 kfree(base);
3688 }
3689
6db5a8ba 3690 d40_err(&pdev->dev, "probe failed\n");
8d318a50
LW		 3691 return ret;
3692}
3693
1814a170
LJ		 3694static const struct of_device_id d40_match[] = {
3695 { .compatible = "stericsson,dma40", },
3696 {}
3697};
3698
8d318a50
LW		 3699static struct platform_driver d40_driver = {
3700 .driver = {
3701 .owner = THIS_MODULE,
3702 .name = D40_NAME,
7fb3e75e 3703 .pm = DMA40_PM_OPS,
1814a170 3704 .of_match_table = d40_match,
8d318a50
LW		 3705 },
3706};
3707
cb9ab2d8 3708static int __init stedma40_init(void)
8d318a50
LW		 3709{
3710 return platform_driver_probe(&d40_driver, d40_probe);
3711}
a0eb221a 3712subsys_initcall(stedma40_init);
Linux kernel - Deliverables
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