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dmaengine/ste_dma40: fix missing kernel-doc
[deliverable/linux.git] / drivers / dma / ste_dma40.c
CommitLineData
8d318a50 1/*
d49278e3
PF		 2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
661385f9 4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675 5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50 6 * License terms: GNU General Public License (GPL) version 2
8d318a50
LW		 7 */
8
9#include <linux/kernel.h>
10#include <linux/slab.h>
11#include <linux/dmaengine.h>
12#include <linux/platform_device.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
698e4732 15#include <linux/err.h>
8d318a50
LW		 16
17#include <plat/ste_dma40.h>
18
19#include "ste_dma40_ll.h"
20
21#define D40_NAME "dma40"
22
23#define D40_PHY_CHAN -1
24
25/* For masking out/in 2 bit channel positions */
26#define D40_CHAN_POS(chan) (2 * (chan / 2))
27#define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
28
29/* Maximum iterations taken before giving up suspending a channel */
30#define D40_SUSPEND_MAX_IT 500
31
508849ad
LW		 32/* Hardware requirement on LCLA alignment */
33#define LCLA_ALIGNMENT 0x40000
698e4732
JA		 34
35/* Max number of links per event group */
36#define D40_LCLA_LINK_PER_EVENT_GRP 128
37#define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
38
508849ad
LW		 39/* Attempts before giving up to trying to get pages that are aligned */
40#define MAX_LCLA_ALLOC_ATTEMPTS 256
41
42/* Bit markings for allocation map */
8d318a50
LW		 43#define D40_ALLOC_FREE (1 << 31)
44#define D40_ALLOC_PHY (1 << 30)
45#define D40_ALLOC_LOG_FREE 0
46
8d318a50 47/* Hardware designer of the block */
3ae0267f 48#define D40_HW_DESIGNER 0x8
8d318a50
LW		 49
50/**
51 * enum 40_command - The different commands and/or statuses.
52 *
53 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
54 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
55 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
56 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
57 */
58enum d40_command {
59 D40_DMA_STOP = 0,
60 D40_DMA_RUN = 1,
61 D40_DMA_SUSPEND_REQ = 2,
62 D40_DMA_SUSPENDED = 3
63};
64
65/**
66 * struct d40_lli_pool - Structure for keeping LLIs in memory
67 *
68 * @base: Pointer to memory area when the pre_alloc_lli's are not large
69 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
70 * pre_alloc_lli is used.
b00f938c 71 * @dma_addr: DMA address, if mapped
8d318a50
LW		 72 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
73 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
74 * one buffer to one buffer.
75 */
76struct d40_lli_pool {
77 void *base;
508849ad 78 int size;
b00f938c 79 dma_addr_t dma_addr;
8d318a50 80 /* Space for dst and src, plus an extra for padding */
508849ad 81 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
8d318a50
LW		 82};
83
84/**
85 * struct d40_desc - A descriptor is one DMA job.
86 *
87 * @lli_phy: LLI settings for physical channel. Both src and dst=
88 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
89 * lli_len equals one.
90 * @lli_log: Same as above but for logical channels.
91 * @lli_pool: The pool with two entries pre-allocated.
941b77a3 92 * @lli_len: Number of llis of current descriptor.
25985edc 93 * @lli_current: Number of transferred llis.
698e4732 94 * @lcla_alloc: Number of LCLA entries allocated.
8d318a50
LW		 95 * @txd: DMA engine struct. Used for among other things for communication
96 * during a transfer.
97 * @node: List entry.
8d318a50 98 * @is_in_client_list: true if the client owns this descriptor.
aa182ae2 99 * the previous one.
8d318a50
LW		 100 *
101 * This descriptor is used for both logical and physical transfers.
102 */
8d318a50
LW		 103struct d40_desc {
104 /* LLI physical */
105 struct d40_phy_lli_bidir lli_phy;
106 /* LLI logical */
107 struct d40_log_lli_bidir lli_log;
108
109 struct d40_lli_pool lli_pool;
941b77a3 110 int lli_len;
698e4732
JA		 111 int lli_current;
112 int lcla_alloc;
8d318a50
LW		 113
114 struct dma_async_tx_descriptor txd;
115 struct list_head node;
116
8d318a50 117 bool is_in_client_list;
0c842b55 118 bool cyclic;
8d318a50
LW		 119};
120
121/**
122 * struct d40_lcla_pool - LCLA pool settings and data.
123 *
508849ad
LW		 124 * @base: The virtual address of LCLA. 18 bit aligned.
125 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
126 * This pointer is only there for clean-up on error.
127 * @pages: The number of pages needed for all physical channels.
128 * Only used later for clean-up on error
8d318a50 129 * @lock: Lock to protect the content in this struct.
698e4732 130 * @alloc_map: big map over which LCLA entry is own by which job.
8d318a50
LW		 131 */
132struct d40_lcla_pool {
133 void *base;
026cbc42 134 dma_addr_t dma_addr;
508849ad
LW		 135 void *base_unaligned;
136 int pages;
8d318a50 137 spinlock_t lock;
698e4732 138 struct d40_desc **alloc_map;
8d318a50
LW		 139};
140
141/**
142 * struct d40_phy_res - struct for handling eventlines mapped to physical
143 * channels.
144 *
145 * @lock: A lock protection this entity.
146 * @num: The physical channel number of this entity.
147 * @allocated_src: Bit mapped to show which src event line's are mapped to
148 * this physical channel. Can also be free or physically allocated.
149 * @allocated_dst: Same as for src but is dst.
150 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
767a9675 151 * event line number.
8d318a50
LW		 152 */
153struct d40_phy_res {
154 spinlock_t lock;
155 int num;
156 u32 allocated_src;
157 u32 allocated_dst;
158};
159
160struct d40_base;
161
162/**
163 * struct d40_chan - Struct that describes a channel.
164 *
165 * @lock: A spinlock to protect this struct.
166 * @log_num: The logical number, if any of this channel.
167 * @completed: Starts with 1, after first interrupt it is set to dma engine's
168 * current cookie.
169 * @pending_tx: The number of pending transfers. Used between interrupt handler
170 * and tasklet.
171 * @busy: Set to true when transfer is ongoing on this channel.
2a614340
JA		 172 * @phy_chan: Pointer to physical channel which this instance runs on. If this
173 * point is NULL, then the channel is not allocated.
8d318a50
LW		 174 * @chan: DMA engine handle.
175 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
176 * transfer and call client callback.
177 * @client: Cliented owned descriptor list.
178 * @active: Active descriptor.
179 * @queue: Queued jobs.
8d318a50 180 * @dma_cfg: The client configuration of this dma channel.
ce2ca125 181 * @configured: whether the dma_cfg configuration is valid
8d318a50
LW		 182 * @base: Pointer to the device instance struct.
183 * @src_def_cfg: Default cfg register setting for src.
184 * @dst_def_cfg: Default cfg register setting for dst.
185 * @log_def: Default logical channel settings.
186 * @lcla: Space for one dst src pair for logical channel transfers.
187 * @lcpa: Pointer to dst and src lcpa settings.
ae752bf4 188 * @runtime_addr: runtime configured address.
189 * @runtime_direction: runtime configured direction.
8d318a50
LW		 190 *
191 * This struct can either "be" a logical or a physical channel.
192 */
193struct d40_chan {
194 spinlock_t lock;
195 int log_num;
196 /* ID of the most recent completed transfer */
197 int completed;
198 int pending_tx;
199 bool busy;
200 struct d40_phy_res *phy_chan;
201 struct dma_chan chan;
202 struct tasklet_struct tasklet;
203 struct list_head client;
a8f3067b 204 struct list_head pending_queue;
8d318a50
LW		 205 struct list_head active;
206 struct list_head queue;
8d318a50 207 struct stedma40_chan_cfg dma_cfg;
ce2ca125 208 bool configured;
8d318a50
LW		 209 struct d40_base *base;
210 /* Default register configurations */
211 u32 src_def_cfg;
212 u32 dst_def_cfg;
213 struct d40_def_lcsp log_def;
8d318a50 214 struct d40_log_lli_full *lcpa;
95e1400f
LW		 215 /* Runtime reconfiguration */
216 dma_addr_t runtime_addr;
217 enum dma_data_direction runtime_direction;
8d318a50
LW		 218};
219
220/**
221 * struct d40_base - The big global struct, one for each probe'd instance.
222 *
223 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
224 * @execmd_lock: Lock for execute command usage since several channels share
225 * the same physical register.
226 * @dev: The device structure.
227 * @virtbase: The virtual base address of the DMA's register.
f4185592 228 * @rev: silicon revision detected.
8d318a50
LW		 229 * @clk: Pointer to the DMA clock structure.
230 * @phy_start: Physical memory start of the DMA registers.
231 * @phy_size: Size of the DMA register map.
232 * @irq: The IRQ number.
233 * @num_phy_chans: The number of physical channels. Read from HW. This
234 * is the number of available channels for this driver, not counting "Secure
235 * mode" allocated physical channels.
236 * @num_log_chans: The number of logical channels. Calculated from
237 * num_phy_chans.
238 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
239 * @dma_slave: dma_device channels that can do only do slave transfers.
240 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
8d318a50
LW		 241 * @log_chans: Room for all possible logical channels in system.
242 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
243 * to log_chans entries.
244 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
245 * to phy_chans entries.
246 * @plat_data: Pointer to provided platform_data which is the driver
247 * configuration.
248 * @phy_res: Vector containing all physical channels.
249 * @lcla_pool: lcla pool settings and data.
250 * @lcpa_base: The virtual mapped address of LCPA.
251 * @phy_lcpa: The physical address of the LCPA.
252 * @lcpa_size: The size of the LCPA area.
c675b1b4 253 * @desc_slab: cache for descriptors.
8d318a50
LW		 254 */
255struct d40_base {
256 spinlock_t interrupt_lock;
257 spinlock_t execmd_lock;
258 struct device *dev;
259 void __iomem *virtbase;
f4185592 260 u8 rev:4;
8d318a50
LW		 261 struct clk *clk;
262 phys_addr_t phy_start;
263 resource_size_t phy_size;
264 int irq;
265 int num_phy_chans;
266 int num_log_chans;
267 struct dma_device dma_both;
268 struct dma_device dma_slave;
269 struct dma_device dma_memcpy;
270 struct d40_chan *phy_chans;
271 struct d40_chan *log_chans;
272 struct d40_chan **lookup_log_chans;
273 struct d40_chan **lookup_phy_chans;
274 struct stedma40_platform_data *plat_data;
275 /* Physical half channels */
276 struct d40_phy_res *phy_res;
277 struct d40_lcla_pool lcla_pool;
278 void *lcpa_base;
279 dma_addr_t phy_lcpa;
280 resource_size_t lcpa_size;
c675b1b4 281 struct kmem_cache *desc_slab;
8d318a50
LW		 282};
283
284/**
285 * struct d40_interrupt_lookup - lookup table for interrupt handler
286 *
287 * @src: Interrupt mask register.
288 * @clr: Interrupt clear register.
289 * @is_error: true if this is an error interrupt.
290 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
291 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
292 */
293struct d40_interrupt_lookup {
294 u32 src;
295 u32 clr;
296 bool is_error;
297 int offset;
298};
299
300/**
301 * struct d40_reg_val - simple lookup struct
302 *
303 * @reg: The register.
304 * @val: The value that belongs to the register in reg.
305 */
306struct d40_reg_val {
307 unsigned int reg;
308 unsigned int val;
309};
310
262d2915
RV		 311static struct device *chan2dev(struct d40_chan *d40c)
312{
313 return &d40c->chan.dev->device;
314}
315
724a8577
RV		 316static bool chan_is_physical(struct d40_chan *chan)
317{
318 return chan->log_num == D40_PHY_CHAN;
319}
320
321static bool chan_is_logical(struct d40_chan *chan)
322{
323 return !chan_is_physical(chan);
324}
325
8ca84687
RV		 326static void __iomem *chan_base(struct d40_chan *chan)
327{
328 return chan->base->virtbase + D40_DREG_PCBASE +
329 chan->phy_chan->num * D40_DREG_PCDELTA;
330}
331
6db5a8ba
RV		 332#define d40_err(dev, format, arg...) \
333 dev_err(dev, "[%s] " format, __func__, ## arg)
334
335#define chan_err(d40c, format, arg...) \
336 d40_err(chan2dev(d40c), format, ## arg)
337
b00f938c 338static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
dbd88788 339 int lli_len)
8d318a50 340{
dbd88788 341 bool is_log = chan_is_logical(d40c);
8d318a50
LW		 342 u32 align;
343 void *base;
344
345 if (is_log)
346 align = sizeof(struct d40_log_lli);
347 else
348 align = sizeof(struct d40_phy_lli);
349
350 if (lli_len == 1) {
351 base = d40d->lli_pool.pre_alloc_lli;
352 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
353 d40d->lli_pool.base = NULL;
354 } else {
594ece4d 355 d40d->lli_pool.size = lli_len * 2 * align;
8d318a50
LW		 356
357 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
358 d40d->lli_pool.base = base;
359
360 if (d40d->lli_pool.base == NULL)
361 return -ENOMEM;
362 }
363
364 if (is_log) {
d924abad 365 d40d->lli_log.src = PTR_ALIGN(base, align);
594ece4d 366 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
b00f938c
RV		 367
368 d40d->lli_pool.dma_addr = 0;
8d318a50 369 } else {
d924abad 370 d40d->lli_phy.src = PTR_ALIGN(base, align);
594ece4d 371 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
b00f938c
RV		 372
373 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
374 d40d->lli_phy.src,
375 d40d->lli_pool.size,
376 DMA_TO_DEVICE);
377
378 if (dma_mapping_error(d40c->base->dev,
379 d40d->lli_pool.dma_addr)) {
380 kfree(d40d->lli_pool.base);
381 d40d->lli_pool.base = NULL;
382 d40d->lli_pool.dma_addr = 0;
383 return -ENOMEM;
384 }
8d318a50
LW		 385 }
386
387 return 0;
388}
389
b00f938c 390static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
8d318a50 391{
b00f938c
RV		 392 if (d40d->lli_pool.dma_addr)
393 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
394 d40d->lli_pool.size, DMA_TO_DEVICE);
395
8d318a50
LW		 396 kfree(d40d->lli_pool.base);
397 d40d->lli_pool.base = NULL;
398 d40d->lli_pool.size = 0;
399 d40d->lli_log.src = NULL;
400 d40d->lli_log.dst = NULL;
401 d40d->lli_phy.src = NULL;
402 d40d->lli_phy.dst = NULL;
8d318a50
LW		 403}
404
698e4732
JA		 405static int d40_lcla_alloc_one(struct d40_chan *d40c,
406 struct d40_desc *d40d)
407{
408 unsigned long flags;
409 int i;
410 int ret = -EINVAL;
411 int p;
412
413 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
414
415 p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
416
417 /*
418 * Allocate both src and dst at the same time, therefore the half
419 * start on 1 since 0 can't be used since zero is used as end marker.
420 */
421 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
422 if (!d40c->base->lcla_pool.alloc_map[p + i]) {
423 d40c->base->lcla_pool.alloc_map[p + i] = d40d;
424 d40d->lcla_alloc++;
425 ret = i;
426 break;
427 }
428 }
429
430 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
431
432 return ret;
433}
434
435static int d40_lcla_free_all(struct d40_chan *d40c,
436 struct d40_desc *d40d)
437{
438 unsigned long flags;
439 int i;
440 int ret = -EINVAL;
441
724a8577 442 if (chan_is_physical(d40c))
698e4732
JA		 443 return 0;
444
445 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
446
447 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
448 if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
449 D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
450 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
451 D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
452 d40d->lcla_alloc--;
453 if (d40d->lcla_alloc == 0) {
454 ret = 0;
455 break;
456 }
457 }
458 }
459
460 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
461
462 return ret;
463
464}
465
8d318a50
LW		 466static void d40_desc_remove(struct d40_desc *d40d)
467{
468 list_del(&d40d->node);
469}
470
471static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
472{
a2c15fa4 473 struct d40_desc *desc = NULL;
8d318a50
LW		 474
475 if (!list_empty(&d40c->client)) {
a2c15fa4
RV		 476 struct d40_desc *d;
477 struct d40_desc *_d;
478
8d318a50
LW		 479 list_for_each_entry_safe(d, _d, &d40c->client, node)
480 if (async_tx_test_ack(&d->txd)) {
b00f938c 481 d40_pool_lli_free(d40c, d);
8d318a50 482 d40_desc_remove(d);
a2c15fa4
RV		 483 desc = d;
484 memset(desc, 0, sizeof(*desc));
c675b1b4 485 break;
8d318a50 486 }
8d318a50 487 }
a2c15fa4
RV		 488
489 if (!desc)
490 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
491
492 if (desc)
493 INIT_LIST_HEAD(&desc->node);
494
495 return desc;
8d318a50
LW		 496}
497
498static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
499{
698e4732 500
b00f938c 501 d40_pool_lli_free(d40c, d40d);
698e4732 502 d40_lcla_free_all(d40c, d40d);
c675b1b4 503 kmem_cache_free(d40c->base->desc_slab, d40d);
8d318a50
LW		 504}
505
506static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
507{
508 list_add_tail(&desc->node, &d40c->active);
509}
510
1c4b0927
RV		 511static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
512{
513 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
514 struct d40_phy_lli *lli_src = desc->lli_phy.src;
515 void __iomem *base = chan_base(chan);
516
517 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
518 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
519 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
520 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
521
522 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
523 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
524 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
525 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
526}
527
e65889c7 528static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
698e4732 529{
e65889c7
RV		 530 struct d40_lcla_pool *pool = &chan->base->lcla_pool;
531 struct d40_log_lli_bidir *lli = &desc->lli_log;
532 int lli_current = desc->lli_current;
533 int lli_len = desc->lli_len;
0c842b55 534 bool cyclic = desc->cyclic;
e65889c7 535 int curr_lcla = -EINVAL;
0c842b55
RV		 536 int first_lcla = 0;
537 bool linkback;
e65889c7 538
0c842b55
RV		 539 /*
540 * We may have partially running cyclic transfers, in case we did't get
541 * enough LCLA entries.
542 */
543 linkback = cyclic && lli_current == 0;
544
545 /*
546 * For linkback, we need one LCLA even with only one link, because we
547 * can't link back to the one in LCPA space
548 */
549 if (linkback || (lli_len - lli_current > 1)) {
e65889c7 550 curr_lcla = d40_lcla_alloc_one(chan, desc);
0c842b55
RV		 551 first_lcla = curr_lcla;
552 }
553
554 /*
555 * For linkback, we normally load the LCPA in the loop since we need to
556 * link it to the second LCLA and not the first. However, if we
557 * couldn't even get a first LCLA, then we have to run in LCPA and
558 * reload manually.
559 */
560 if (!linkback || curr_lcla == -EINVAL) {
561 unsigned int flags = 0;
e65889c7 562
0c842b55
RV		 563 if (curr_lcla == -EINVAL)
564 flags |= LLI_TERM_INT;
e65889c7 565
0c842b55
RV		 566 d40_log_lli_lcpa_write(chan->lcpa,
567 &lli->dst[lli_current],
568 &lli->src[lli_current],
569 curr_lcla,
570 flags);
571 lli_current++;
572 }
6045f0bb
RV		 573
574 if (curr_lcla < 0)
575 goto out;
576
e65889c7
RV		 577 for (; lli_current < lli_len; lli_current++) {
578 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
579 8 * curr_lcla * 2;
580 struct d40_log_lli *lcla = pool->base + lcla_offset;
0c842b55 581 unsigned int flags = 0;
e65889c7
RV		 582 int next_lcla;
583
584 if (lli_current + 1 < lli_len)
585 next_lcla = d40_lcla_alloc_one(chan, desc);
586 else
0c842b55
RV		 587 next_lcla = linkback ? first_lcla : -EINVAL;
588
589 if (cyclic || next_lcla == -EINVAL)
590 flags |= LLI_TERM_INT;
e65889c7 591
0c842b55
RV		 592 if (linkback && curr_lcla == first_lcla) {
593 /* First link goes in both LCPA and LCLA */
594 d40_log_lli_lcpa_write(chan->lcpa,
595 &lli->dst[lli_current],
596 &lli->src[lli_current],
597 next_lcla, flags);
598 }
599
600 /*
601 * One unused LCLA in the cyclic case if the very first
602 * next_lcla fails...
603 */
e65889c7
RV		 604 d40_log_lli_lcla_write(lcla,
605 &lli->dst[lli_current],
606 &lli->src[lli_current],
0c842b55 607 next_lcla, flags);
e65889c7
RV		 608
609 dma_sync_single_range_for_device(chan->base->dev,
610 pool->dma_addr, lcla_offset,
611 2 * sizeof(struct d40_log_lli),
612 DMA_TO_DEVICE);
613
614 curr_lcla = next_lcla;
615
0c842b55 616 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
e65889c7
RV		 617 lli_current++;
618 break;
619 }
620 }
621
6045f0bb 622out:
e65889c7
RV		 623 desc->lli_current = lli_current;
624}
698e4732 625
e65889c7
RV		 626static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
627{
724a8577 628 if (chan_is_physical(d40c)) {
1c4b0927 629 d40_phy_lli_load(d40c, d40d);
698e4732 630 d40d->lli_current = d40d->lli_len;
e65889c7
RV		 631 } else
632 d40_log_lli_to_lcxa(d40c, d40d);
698e4732
JA		 633}
634
8d318a50
LW		 635static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
636{
637 struct d40_desc *d;
638
639 if (list_empty(&d40c->active))
640 return NULL;
641
642 d = list_first_entry(&d40c->active,
643 struct d40_desc,
644 node);
645 return d;
646}
647
648static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
649{
a8f3067b
PF		 650 list_add_tail(&desc->node, &d40c->pending_queue);
651}
652
653static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
654{
655 struct d40_desc *d;
656
657 if (list_empty(&d40c->pending_queue))
658 return NULL;
659
660 d = list_first_entry(&d40c->pending_queue,
661 struct d40_desc,
662 node);
663 return d;
8d318a50
LW		 664}
665
666static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
667{
668 struct d40_desc *d;
669
670 if (list_empty(&d40c->queue))
671 return NULL;
672
673 d = list_first_entry(&d40c->queue,
674 struct d40_desc,
675 node);
676 return d;
677}
678
d49278e3
PF		 679static int d40_psize_2_burst_size(bool is_log, int psize)
680{
681 if (is_log) {
682 if (psize == STEDMA40_PSIZE_LOG_1)
683 return 1;
684 } else {
685 if (psize == STEDMA40_PSIZE_PHY_1)
686 return 1;
687 }
688
689 return 2 << psize;
690}
691
692/*
693 * The dma only supports transmitting packages up to
694 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
695 * dma elements required to send the entire sg list
696 */
697static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
698{
699 int dmalen;
700 u32 max_w = max(data_width1, data_width2);
701 u32 min_w = min(data_width1, data_width2);
702 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
703
704 if (seg_max > STEDMA40_MAX_SEG_SIZE)
705 seg_max -= (1 << max_w);
706
707 if (!IS_ALIGNED(size, 1 << max_w))
708 return -EINVAL;
709
710 if (size <= seg_max)
711 dmalen = 1;
712 else {
713 dmalen = size / seg_max;
714 if (dmalen * seg_max < size)
715 dmalen++;
716 }
717 return dmalen;
718}
719
720static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
721 u32 data_width1, u32 data_width2)
722{
723 struct scatterlist *sg;
724 int i;
725 int len = 0;
726 int ret;
727
728 for_each_sg(sgl, sg, sg_len, i) {
729 ret = d40_size_2_dmalen(sg_dma_len(sg),
730 data_width1, data_width2);
731 if (ret < 0)
732 return ret;
733 len += ret;
734 }
735 return len;
736}
8d318a50 737
d49278e3 738/* Support functions for logical channels */
8d318a50
LW		 739
740static int d40_channel_execute_command(struct d40_chan *d40c,
741 enum d40_command command)
742{
767a9675
JA		 743 u32 status;
744 int i;
8d318a50
LW		 745 void __iomem *active_reg;
746 int ret = 0;
747 unsigned long flags;
1d392a7b 748 u32 wmask;
8d318a50
LW		 749
750 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
751
752 if (d40c->phy_chan->num % 2 == 0)
753 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
754 else
755 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
756
757 if (command == D40_DMA_SUSPEND_REQ) {
758 status = (readl(active_reg) &
759 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
760 D40_CHAN_POS(d40c->phy_chan->num);
761
762 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
763 goto done;
764 }
765
1d392a7b
JA		 766 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
767 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
768 active_reg);
8d318a50
LW		 769
770 if (command == D40_DMA_SUSPEND_REQ) {
771
772 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
773 status = (readl(active_reg) &
774 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
775 D40_CHAN_POS(d40c->phy_chan->num);
776
777 cpu_relax();
778 /*
779 * Reduce the number of bus accesses while
780 * waiting for the DMA to suspend.
781 */
782 udelay(3);
783
784 if (status == D40_DMA_STOP ||
785 status == D40_DMA_SUSPENDED)
786 break;
787 }
788
789 if (i == D40_SUSPEND_MAX_IT) {
6db5a8ba
RV		 790 chan_err(d40c,
791 "unable to suspend the chl %d (log: %d) status %x\n",
792 d40c->phy_chan->num, d40c->log_num,
8d318a50
LW		 793 status);
794 dump_stack();
795 ret = -EBUSY;
796 }
797
798 }
799done:
800 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
801 return ret;
802}
803
804static void d40_term_all(struct d40_chan *d40c)
805{
806 struct d40_desc *d40d;
8d318a50
LW		 807
808 /* Release active descriptors */
809 while ((d40d = d40_first_active_get(d40c))) {
810 d40_desc_remove(d40d);
8d318a50
LW		 811 d40_desc_free(d40c, d40d);
812 }
813
814 /* Release queued descriptors waiting for transfer */
815 while ((d40d = d40_first_queued(d40c))) {
816 d40_desc_remove(d40d);
8d318a50
LW		 817 d40_desc_free(d40c, d40d);
818 }
819
a8f3067b
PF		 820 /* Release pending descriptors */
821 while ((d40d = d40_first_pending(d40c))) {
822 d40_desc_remove(d40d);
823 d40_desc_free(d40c, d40d);
824 }
8d318a50
LW		 825
826 d40c->pending_tx = 0;
827 d40c->busy = false;
828}
829
262d2915
RV		 830static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
831 u32 event, int reg)
832{
8ca84687 833 void __iomem *addr = chan_base(d40c) + reg;
262d2915
RV		 834 int tries;
835
836 if (!enable) {
837 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
838 | ~D40_EVENTLINE_MASK(event), addr);
839 return;
840 }
841
842 /*
843 * The hardware sometimes doesn't register the enable when src and dst
844 * event lines are active on the same logical channel. Retry to ensure
845 * it does. Usually only one retry is sufficient.
846 */
847 tries = 100;
848 while (--tries) {
849 writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
850 | ~D40_EVENTLINE_MASK(event), addr);
851
852 if (readl(addr) & D40_EVENTLINE_MASK(event))
853 break;
854 }
855
856 if (tries != 99)
857 dev_dbg(chan2dev(d40c),
858 "[%s] workaround enable S%cLNK (%d tries)\n",
859 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
860 100 - tries);
861
862 WARN_ON(!tries);
863}
864
8d318a50
LW		 865static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
866{
8d318a50
LW		 867 unsigned long flags;
868
8d318a50
LW		 869 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
870
871 /* Enable event line connected to device (or memcpy) */
872 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
873 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
874 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
875
262d2915
RV		 876 __d40_config_set_event(d40c, do_enable, event,
877 D40_CHAN_REG_SSLNK);
8d318a50 878 }
262d2915 879
8d318a50
LW		 880 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
881 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
882
262d2915
RV		 883 __d40_config_set_event(d40c, do_enable, event,
884 D40_CHAN_REG_SDLNK);
8d318a50
LW		 885 }
886
887 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
888}
889
a5ebca47 890static u32 d40_chan_has_events(struct d40_chan *d40c)
8d318a50 891{
8ca84687 892 void __iomem *chanbase = chan_base(d40c);
be8cb7df 893 u32 val;
8d318a50 894
8ca84687
RV		 895 val = readl(chanbase + D40_CHAN_REG_SSLNK);
896 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
be8cb7df 897
a5ebca47 898 return val;
8d318a50
LW		 899}
900
20a5b6d0
RV		 901static u32 d40_get_prmo(struct d40_chan *d40c)
902{
903 static const unsigned int phy_map[] = {
904 [STEDMA40_PCHAN_BASIC_MODE]
905 = D40_DREG_PRMO_PCHAN_BASIC,
906 [STEDMA40_PCHAN_MODULO_MODE]
907 = D40_DREG_PRMO_PCHAN_MODULO,
908 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
909 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
910 };
911 static const unsigned int log_map[] = {
912 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
913 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
914 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
915 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
916 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
917 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
918 };
919
724a8577 920 if (chan_is_physical(d40c))
20a5b6d0
RV		 921 return phy_map[d40c->dma_cfg.mode_opt];
922 else
923 return log_map[d40c->dma_cfg.mode_opt];
924}
925
b55912c6 926static void d40_config_write(struct d40_chan *d40c)
8d318a50
LW		 927{
928 u32 addr_base;
929 u32 var;
8d318a50
LW		 930
931 /* Odd addresses are even addresses + 4 */
932 addr_base = (d40c->phy_chan->num % 2) * 4;
933 /* Setup channel mode to logical or physical */
724a8577 934 var = ((u32)(chan_is_logical(d40c)) + 1) <<
8d318a50
LW		 935 D40_CHAN_POS(d40c->phy_chan->num);
936 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
937
938 /* Setup operational mode option register */
20a5b6d0 939 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
8d318a50
LW		 940
941 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
942
724a8577 943 if (chan_is_logical(d40c)) {
8ca84687
RV		 944 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
945 & D40_SREG_ELEM_LOG_LIDX_MASK;
946 void __iomem *chanbase = chan_base(d40c);
947
8d318a50 948 /* Set default config for CFG reg */
8ca84687
RV		 949 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
950 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
8d318a50 951
b55912c6 952 /* Set LIDX for lcla */
8ca84687
RV		 953 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
954 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
8d318a50 955 }
8d318a50
LW		 956}
957
aa182ae2
JA		 958static u32 d40_residue(struct d40_chan *d40c)
959{
960 u32 num_elt;
961
724a8577 962 if (chan_is_logical(d40c))
aa182ae2
JA		 963 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
964 >> D40_MEM_LCSP2_ECNT_POS;
8ca84687
RV		 965 else {
966 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
967 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
968 >> D40_SREG_ELEM_PHY_ECNT_POS;
969 }
970
aa182ae2
JA		 971 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
972}
973
974static bool d40_tx_is_linked(struct d40_chan *d40c)
975{
976 bool is_link;
977
724a8577 978 if (chan_is_logical(d40c))
aa182ae2
JA		 979 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
980 else
8ca84687
RV		 981 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
982 & D40_SREG_LNK_PHYS_LNK_MASK;
983
aa182ae2
JA		 984 return is_link;
985}
986
86eb5fb6 987static int d40_pause(struct d40_chan *d40c)
aa182ae2 988{
aa182ae2
JA		 989 int res = 0;
990 unsigned long flags;
991
3ac012af
JA		 992 if (!d40c->busy)
993 return 0;
994
aa182ae2
JA		 995 spin_lock_irqsave(&d40c->lock, flags);
996
997 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
998 if (res == 0) {
724a8577 999 if (chan_is_logical(d40c)) {
aa182ae2
JA		 1000 d40_config_set_event(d40c, false);
1001 /* Resume the other logical channels if any */
1002 if (d40_chan_has_events(d40c))
1003 res = d40_channel_execute_command(d40c,
1004 D40_DMA_RUN);
1005 }
1006 }
1007
1008 spin_unlock_irqrestore(&d40c->lock, flags);
1009 return res;
1010}
1011
86eb5fb6 1012static int d40_resume(struct d40_chan *d40c)
aa182ae2 1013{
aa182ae2
JA		 1014 int res = 0;
1015 unsigned long flags;
1016
3ac012af
JA		 1017 if (!d40c->busy)
1018 return 0;
1019
aa182ae2
JA		 1020 spin_lock_irqsave(&d40c->lock, flags);
1021
1022 if (d40c->base->rev == 0)
724a8577 1023 if (chan_is_logical(d40c)) {
aa182ae2
JA		 1024 res = d40_channel_execute_command(d40c,
1025 D40_DMA_SUSPEND_REQ);
1026 goto no_suspend;
1027 }
1028
1029 /* If bytes left to transfer or linked tx resume job */
1030 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
1031
724a8577 1032 if (chan_is_logical(d40c))
aa182ae2
JA		 1033 d40_config_set_event(d40c, true);
1034
1035 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1036 }
1037
1038no_suspend:
1039 spin_unlock_irqrestore(&d40c->lock, flags);
1040 return res;
1041}
1042
86eb5fb6
RV		 1043static int d40_terminate_all(struct d40_chan *chan)
1044{
1045 unsigned long flags;
1046 int ret = 0;
1047
1048 ret = d40_pause(chan);
1049 if (!ret && chan_is_physical(chan))
1050 ret = d40_channel_execute_command(chan, D40_DMA_STOP);
1051
1052 spin_lock_irqsave(&chan->lock, flags);
1053 d40_term_all(chan);
1054 spin_unlock_irqrestore(&chan->lock, flags);
1055
1056 return ret;
1057}
1058
8d318a50
LW		 1059static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1060{
1061 struct d40_chan *d40c = container_of(tx->chan,
1062 struct d40_chan,
1063 chan);
1064 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1065 unsigned long flags;
1066
1067 spin_lock_irqsave(&d40c->lock, flags);
1068
aa182ae2
JA		 1069 d40c->chan.cookie++;
1070
1071 if (d40c->chan.cookie < 0)
1072 d40c->chan.cookie = 1;
1073
1074 d40d->txd.cookie = d40c->chan.cookie;
1075
8d318a50
LW		 1076 d40_desc_queue(d40c, d40d);
1077
1078 spin_unlock_irqrestore(&d40c->lock, flags);
1079
1080 return tx->cookie;
1081}
1082
1083static int d40_start(struct d40_chan *d40c)
1084{
f4185592
LW		 1085 if (d40c->base->rev == 0) {
1086 int err;
1087
724a8577 1088 if (chan_is_logical(d40c)) {
f4185592
LW		 1089 err = d40_channel_execute_command(d40c,
1090 D40_DMA_SUSPEND_REQ);
1091 if (err)
1092 return err;
1093 }
1094 }
1095
724a8577 1096 if (chan_is_logical(d40c))
8d318a50 1097 d40_config_set_event(d40c, true);
8d318a50 1098
0c32269d 1099 return d40_channel_execute_command(d40c, D40_DMA_RUN);
8d318a50
LW		 1100}
1101
1102static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1103{
1104 struct d40_desc *d40d;
1105 int err;
1106
1107 /* Start queued jobs, if any */
1108 d40d = d40_first_queued(d40c);
1109
1110 if (d40d != NULL) {
1111 d40c->busy = true;
1112
1113 /* Remove from queue */
1114 d40_desc_remove(d40d);
1115
1116 /* Add to active queue */
1117 d40_desc_submit(d40c, d40d);
1118
7d83a854
RV		 1119 /* Initiate DMA job */
1120 d40_desc_load(d40c, d40d);
8d318a50 1121
7d83a854
RV		 1122 /* Start dma job */
1123 err = d40_start(d40c);
8d318a50 1124
7d83a854
RV		 1125 if (err)
1126 return NULL;
8d318a50
LW		 1127 }
1128
1129 return d40d;
1130}
1131
1132/* called from interrupt context */
1133static void dma_tc_handle(struct d40_chan *d40c)
1134{
1135 struct d40_desc *d40d;
1136
8d318a50
LW		 1137 /* Get first active entry from list */
1138 d40d = d40_first_active_get(d40c);
1139
1140 if (d40d == NULL)
1141 return;
1142
0c842b55
RV		 1143 if (d40d->cyclic) {
1144 /*
1145 * If this was a paritially loaded list, we need to reloaded
1146 * it, and only when the list is completed. We need to check
1147 * for done because the interrupt will hit for every link, and
1148 * not just the last one.
1149 */
1150 if (d40d->lli_current < d40d->lli_len
1151 && !d40_tx_is_linked(d40c)
1152 && !d40_residue(d40c)) {
1153 d40_lcla_free_all(d40c, d40d);
1154 d40_desc_load(d40c, d40d);
1155 (void) d40_start(d40c);
8d318a50 1156
0c842b55
RV		 1157 if (d40d->lli_current == d40d->lli_len)
1158 d40d->lli_current = 0;
1159 }
1160 } else {
1161 d40_lcla_free_all(d40c, d40d);
8d318a50 1162
0c842b55
RV		 1163 if (d40d->lli_current < d40d->lli_len) {
1164 d40_desc_load(d40c, d40d);
1165 /* Start dma job */
1166 (void) d40_start(d40c);
1167 return;
1168 }
1169
1170 if (d40_queue_start(d40c) == NULL)
1171 d40c->busy = false;
1172 }
8d318a50
LW		 1173
1174 d40c->pending_tx++;
1175 tasklet_schedule(&d40c->tasklet);
1176
1177}
1178
1179static void dma_tasklet(unsigned long data)
1180{
1181 struct d40_chan *d40c = (struct d40_chan *) data;
767a9675 1182 struct d40_desc *d40d;
8d318a50
LW		 1183 unsigned long flags;
1184 dma_async_tx_callback callback;
1185 void *callback_param;
1186
1187 spin_lock_irqsave(&d40c->lock, flags);
1188
1189 /* Get first active entry from list */
767a9675 1190 d40d = d40_first_active_get(d40c);
767a9675 1191 if (d40d == NULL)
8d318a50
LW		 1192 goto err;
1193
0c842b55
RV		 1194 if (!d40d->cyclic)
1195 d40c->completed = d40d->txd.cookie;
8d318a50
LW		 1196
1197 /*
1198 * If terminating a channel pending_tx is set to zero.
1199 * This prevents any finished active jobs to return to the client.
1200 */
1201 if (d40c->pending_tx == 0) {
1202 spin_unlock_irqrestore(&d40c->lock, flags);
1203 return;
1204 }
1205
1206 /* Callback to client */
767a9675
JA		 1207 callback = d40d->txd.callback;
1208 callback_param = d40d->txd.callback_param;
1209
0c842b55
RV		 1210 if (!d40d->cyclic) {
1211 if (async_tx_test_ack(&d40d->txd)) {
1212 d40_pool_lli_free(d40c, d40d);
767a9675 1213 d40_desc_remove(d40d);
0c842b55
RV		 1214 d40_desc_free(d40c, d40d);
1215 } else {
1216 if (!d40d->is_in_client_list) {
1217 d40_desc_remove(d40d);
1218 d40_lcla_free_all(d40c, d40d);
1219 list_add_tail(&d40d->node, &d40c->client);
1220 d40d->is_in_client_list = true;
1221 }
8d318a50
LW		 1222 }
1223 }
1224
1225 d40c->pending_tx--;
1226
1227 if (d40c->pending_tx)
1228 tasklet_schedule(&d40c->tasklet);
1229
1230 spin_unlock_irqrestore(&d40c->lock, flags);
1231
767a9675 1232 if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
8d318a50
LW		 1233 callback(callback_param);
1234
1235 return;
1236
1237 err:
25985edc 1238 /* Rescue manoeuvre if receiving double interrupts */
8d318a50
LW		 1239 if (d40c->pending_tx > 0)
1240 d40c->pending_tx--;
1241 spin_unlock_irqrestore(&d40c->lock, flags);
1242}
1243
1244static irqreturn_t d40_handle_interrupt(int irq, void *data)
1245{
1246 static const struct d40_interrupt_lookup il[] = {
1247 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
1248 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
1249 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
1250 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
1251 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
1252 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
1253 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
1254 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
1255 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
1256 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
1257 };
1258
1259 int i;
1260 u32 regs[ARRAY_SIZE(il)];
8d318a50
LW		 1261 u32 idx;
1262 u32 row;
1263 long chan = -1;
1264 struct d40_chan *d40c;
1265 unsigned long flags;
1266 struct d40_base *base = data;
1267
1268 spin_lock_irqsave(&base->interrupt_lock, flags);
1269
1270 /* Read interrupt status of both logical and physical channels */
1271 for (i = 0; i < ARRAY_SIZE(il); i++)
1272 regs[i] = readl(base->virtbase + il[i].src);
1273
1274 for (;;) {
1275
1276 chan = find_next_bit((unsigned long *)regs,
1277 BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
1278
1279 /* No more set bits found? */
1280 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
1281 break;
1282
1283 row = chan / BITS_PER_LONG;
1284 idx = chan & (BITS_PER_LONG - 1);
1285
1286 /* ACK interrupt */
1b00348d 1287 writel(1 << idx, base->virtbase + il[row].clr);
8d318a50
LW		 1288
1289 if (il[row].offset == D40_PHY_CHAN)
1290 d40c = base->lookup_phy_chans[idx];
1291 else
1292 d40c = base->lookup_log_chans[il[row].offset + idx];
1293 spin_lock(&d40c->lock);
1294
1295 if (!il[row].is_error)
1296 dma_tc_handle(d40c);
1297 else
6db5a8ba
RV		 1298 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1299 chan, il[row].offset, idx);
8d318a50
LW		 1300
1301 spin_unlock(&d40c->lock);
1302 }
1303
1304 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1305
1306 return IRQ_HANDLED;
1307}
1308
8d318a50
LW		 1309static int d40_validate_conf(struct d40_chan *d40c,
1310 struct stedma40_chan_cfg *conf)
1311{
1312 int res = 0;
1313 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1314 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
38bdbf02 1315 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
8d318a50 1316
0747c7ba 1317 if (!conf->dir) {
6db5a8ba 1318 chan_err(d40c, "Invalid direction.\n");
0747c7ba
LW		 1319 res = -EINVAL;
1320 }
1321
1322 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1323 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1324 d40c->runtime_addr == 0) {
1325
6db5a8ba
RV		 1326 chan_err(d40c, "Invalid TX channel address (%d)\n",
1327 conf->dst_dev_type);
0747c7ba
LW		 1328 res = -EINVAL;
1329 }
1330
1331 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1332 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1333 d40c->runtime_addr == 0) {
6db5a8ba
RV		 1334 chan_err(d40c, "Invalid RX channel address (%d)\n",
1335 conf->src_dev_type);
0747c7ba
LW		 1336 res = -EINVAL;
1337 }
1338
1339 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
8d318a50 1340 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
6db5a8ba 1341 chan_err(d40c, "Invalid dst\n");
8d318a50
LW		 1342 res = -EINVAL;
1343 }
1344
0747c7ba 1345 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
8d318a50 1346 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
6db5a8ba 1347 chan_err(d40c, "Invalid src\n");
8d318a50
LW		 1348 res = -EINVAL;
1349 }
1350
1351 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1352 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
6db5a8ba 1353 chan_err(d40c, "No event line\n");
8d318a50
LW		 1354 res = -EINVAL;
1355 }
1356
1357 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1358 (src_event_group != dst_event_group)) {
6db5a8ba 1359 chan_err(d40c, "Invalid event group\n");
8d318a50
LW		 1360 res = -EINVAL;
1361 }
1362
1363 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1364 /*
1365 * DMAC HW supports it. Will be added to this driver,
1366 * in case any dma client requires it.
1367 */
6db5a8ba 1368 chan_err(d40c, "periph to periph not supported\n");
8d318a50
LW		 1369 res = -EINVAL;
1370 }
1371
d49278e3
PF		 1372 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1373 (1 << conf->src_info.data_width) !=
1374 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1375 (1 << conf->dst_info.data_width)) {
1376 /*
1377 * The DMAC hardware only supports
1378 * src (burst x width) == dst (burst x width)
1379 */
1380
6db5a8ba 1381 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
d49278e3
PF		 1382 res = -EINVAL;
1383 }
1384
8d318a50
LW		 1385 return res;
1386}
1387
1388static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
4aed79b2 1389 int log_event_line, bool is_log)
8d318a50
LW		 1390{
1391 unsigned long flags;
1392 spin_lock_irqsave(&phy->lock, flags);
4aed79b2 1393 if (!is_log) {
8d318a50
LW		 1394 /* Physical interrupts are masked per physical full channel */
1395 if (phy->allocated_src == D40_ALLOC_FREE &&
1396 phy->allocated_dst == D40_ALLOC_FREE) {
1397 phy->allocated_dst = D40_ALLOC_PHY;
1398 phy->allocated_src = D40_ALLOC_PHY;
1399 goto found;
1400 } else
1401 goto not_found;
1402 }
1403
1404 /* Logical channel */
1405 if (is_src) {
1406 if (phy->allocated_src == D40_ALLOC_PHY)
1407 goto not_found;
1408
1409 if (phy->allocated_src == D40_ALLOC_FREE)
1410 phy->allocated_src = D40_ALLOC_LOG_FREE;
1411
1412 if (!(phy->allocated_src & (1 << log_event_line))) {
1413 phy->allocated_src |= 1 << log_event_line;
1414 goto found;
1415 } else
1416 goto not_found;
1417 } else {
1418 if (phy->allocated_dst == D40_ALLOC_PHY)
1419 goto not_found;
1420
1421 if (phy->allocated_dst == D40_ALLOC_FREE)
1422 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1423
1424 if (!(phy->allocated_dst & (1 << log_event_line))) {
1425 phy->allocated_dst |= 1 << log_event_line;
1426 goto found;
1427 } else
1428 goto not_found;
1429 }
1430
1431not_found:
1432 spin_unlock_irqrestore(&phy->lock, flags);
1433 return false;
1434found:
1435 spin_unlock_irqrestore(&phy->lock, flags);
1436 return true;
1437}
1438
1439static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1440 int log_event_line)
1441{
1442 unsigned long flags;
1443 bool is_free = false;
1444
1445 spin_lock_irqsave(&phy->lock, flags);
1446 if (!log_event_line) {
8d318a50
LW		 1447 phy->allocated_dst = D40_ALLOC_FREE;
1448 phy->allocated_src = D40_ALLOC_FREE;
1449 is_free = true;
1450 goto out;
1451 }
1452
1453 /* Logical channel */
1454 if (is_src) {
1455 phy->allocated_src &= ~(1 << log_event_line);
1456 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1457 phy->allocated_src = D40_ALLOC_FREE;
1458 } else {
1459 phy->allocated_dst &= ~(1 << log_event_line);
1460 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1461 phy->allocated_dst = D40_ALLOC_FREE;
1462 }
1463
1464 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1465 D40_ALLOC_FREE);
1466
1467out:
1468 spin_unlock_irqrestore(&phy->lock, flags);
1469
1470 return is_free;
1471}
1472
1473static int d40_allocate_channel(struct d40_chan *d40c)
1474{
1475 int dev_type;
1476 int event_group;
1477 int event_line;
1478 struct d40_phy_res *phys;
1479 int i;
1480 int j;
1481 int log_num;
1482 bool is_src;
38bdbf02 1483 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
8d318a50
LW		 1484
1485 phys = d40c->base->phy_res;
1486
1487 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1488 dev_type = d40c->dma_cfg.src_dev_type;
1489 log_num = 2 * dev_type;
1490 is_src = true;
1491 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1492 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1493 /* dst event lines are used for logical memcpy */
1494 dev_type = d40c->dma_cfg.dst_dev_type;
1495 log_num = 2 * dev_type + 1;
1496 is_src = false;
1497 } else
1498 return -EINVAL;
1499
1500 event_group = D40_TYPE_TO_GROUP(dev_type);
1501 event_line = D40_TYPE_TO_EVENT(dev_type);
1502
1503 if (!is_log) {
1504 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1505 /* Find physical half channel */
1506 for (i = 0; i < d40c->base->num_phy_chans; i++) {
1507
4aed79b2
MM		 1508 if (d40_alloc_mask_set(&phys[i], is_src,
1509 0, is_log))
8d318a50
LW		 1510 goto found_phy;
1511 }
1512 } else
1513 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1514 int phy_num = j + event_group * 2;
1515 for (i = phy_num; i < phy_num + 2; i++) {
508849ad
LW		 1516 if (d40_alloc_mask_set(&phys[i],
1517 is_src,
1518 0,
1519 is_log))
8d318a50
LW		 1520 goto found_phy;
1521 }
1522 }
1523 return -EINVAL;
1524found_phy:
1525 d40c->phy_chan = &phys[i];
1526 d40c->log_num = D40_PHY_CHAN;
1527 goto out;
1528 }
1529 if (dev_type == -1)
1530 return -EINVAL;
1531
1532 /* Find logical channel */
1533 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1534 int phy_num = j + event_group * 2;
1535 /*
1536 * Spread logical channels across all available physical rather
1537 * than pack every logical channel at the first available phy
1538 * channels.
1539 */
1540 if (is_src) {
1541 for (i = phy_num; i < phy_num + 2; i++) {
1542 if (d40_alloc_mask_set(&phys[i], is_src,
4aed79b2 1543 event_line, is_log))
8d318a50
LW		 1544 goto found_log;
1545 }
1546 } else {
1547 for (i = phy_num + 1; i >= phy_num; i--) {
1548 if (d40_alloc_mask_set(&phys[i], is_src,
4aed79b2 1549 event_line, is_log))
8d318a50
LW		 1550 goto found_log;
1551 }
1552 }
1553 }
1554 return -EINVAL;
1555
1556found_log:
1557 d40c->phy_chan = &phys[i];
1558 d40c->log_num = log_num;
1559out:
1560
1561 if (is_log)
1562 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1563 else
1564 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1565
1566 return 0;
1567
1568}
1569
8d318a50
LW		 1570static int d40_config_memcpy(struct d40_chan *d40c)
1571{
1572 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1573
1574 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1575 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1576 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1577 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1578 memcpy[d40c->chan.chan_id];
1579
1580 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1581 dma_has_cap(DMA_SLAVE, cap)) {
1582 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1583 } else {
6db5a8ba 1584 chan_err(d40c, "No memcpy\n");
8d318a50
LW		 1585 return -EINVAL;
1586 }
1587
1588 return 0;
1589}
1590
1591
1592static int d40_free_dma(struct d40_chan *d40c)
1593{
1594
1595 int res = 0;
d181b3a8 1596 u32 event;
8d318a50
LW		 1597 struct d40_phy_res *phy = d40c->phy_chan;
1598 bool is_src;
a8be8627
PF		 1599 struct d40_desc *d;
1600 struct d40_desc *_d;
1601
8d318a50
LW		 1602
1603 /* Terminate all queued and active transfers */
1604 d40_term_all(d40c);
1605
a8be8627
PF		 1606 /* Release client owned descriptors */
1607 if (!list_empty(&d40c->client))
1608 list_for_each_entry_safe(d, _d, &d40c->client, node) {
b00f938c 1609 d40_pool_lli_free(d40c, d);
a8be8627 1610 d40_desc_remove(d);
a8be8627
PF		 1611 d40_desc_free(d40c, d);
1612 }
1613
8d318a50 1614 if (phy == NULL) {
6db5a8ba 1615 chan_err(d40c, "phy == null\n");
8d318a50
LW		 1616 return -EINVAL;
1617 }
1618
1619 if (phy->allocated_src == D40_ALLOC_FREE &&
1620 phy->allocated_dst == D40_ALLOC_FREE) {
6db5a8ba 1621 chan_err(d40c, "channel already free\n");
8d318a50
LW		 1622 return -EINVAL;
1623 }
1624
8d318a50
LW		 1625 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1626 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1627 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8d318a50
LW		 1628 is_src = false;
1629 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1630 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8d318a50
LW		 1631 is_src = true;
1632 } else {
6db5a8ba 1633 chan_err(d40c, "Unknown direction\n");
8d318a50
LW		 1634 return -EINVAL;
1635 }
1636
d181b3a8
JA		 1637 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1638 if (res) {
6db5a8ba 1639 chan_err(d40c, "suspend failed\n");
d181b3a8
JA		 1640 return res;
1641 }
1642
724a8577 1643 if (chan_is_logical(d40c)) {
d181b3a8 1644 /* Release logical channel, deactivate the event line */
8d318a50 1645
d181b3a8 1646 d40_config_set_event(d40c, false);
8d318a50
LW		 1647 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1648
1649 /*
1650 * Check if there are more logical allocation
1651 * on this phy channel.
1652 */
1653 if (!d40_alloc_mask_free(phy, is_src, event)) {
1654 /* Resume the other logical channels if any */
1655 if (d40_chan_has_events(d40c)) {
1656 res = d40_channel_execute_command(d40c,
1657 D40_DMA_RUN);
1658 if (res) {
6db5a8ba
RV		 1659 chan_err(d40c,
1660 "Executing RUN command\n");
8d318a50
LW		 1661 return res;
1662 }
1663 }
1664 return 0;
1665 }
d181b3a8
JA		 1666 } else {
1667 (void) d40_alloc_mask_free(phy, is_src, 0);
1668 }
8d318a50
LW		 1669
1670 /* Release physical channel */
1671 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1672 if (res) {
6db5a8ba 1673 chan_err(d40c, "Failed to stop channel\n");
8d318a50
LW		 1674 return res;
1675 }
1676 d40c->phy_chan = NULL;
ce2ca125 1677 d40c->configured = false;
8d318a50
LW		 1678 d40c->base->lookup_phy_chans[phy->num] = NULL;
1679
1680 return 0;
8d318a50
LW		 1681}
1682
a5ebca47
JA		 1683static bool d40_is_paused(struct d40_chan *d40c)
1684{
8ca84687 1685 void __iomem *chanbase = chan_base(d40c);
a5ebca47
JA		 1686 bool is_paused = false;
1687 unsigned long flags;
1688 void __iomem *active_reg;
1689 u32 status;
1690 u32 event;
a5ebca47
JA		 1691
1692 spin_lock_irqsave(&d40c->lock, flags);
1693
724a8577 1694 if (chan_is_physical(d40c)) {
a5ebca47
JA		 1695 if (d40c->phy_chan->num % 2 == 0)
1696 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1697 else
1698 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1699
1700 status = (readl(active_reg) &
1701 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1702 D40_CHAN_POS(d40c->phy_chan->num);
1703 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1704 is_paused = true;
1705
1706 goto _exit;
1707 }
1708
a5ebca47 1709 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
9dbfbd35 1710 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
a5ebca47 1711 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
8ca84687 1712 status = readl(chanbase + D40_CHAN_REG_SDLNK);
9dbfbd35 1713 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
a5ebca47 1714 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
8ca84687 1715 status = readl(chanbase + D40_CHAN_REG_SSLNK);
9dbfbd35 1716 } else {
6db5a8ba 1717 chan_err(d40c, "Unknown direction\n");
a5ebca47
JA		 1718 goto _exit;
1719 }
9dbfbd35 1720
a5ebca47
JA		 1721 status = (status & D40_EVENTLINE_MASK(event)) >>
1722 D40_EVENTLINE_POS(event);
1723
1724 if (status != D40_DMA_RUN)
1725 is_paused = true;
a5ebca47
JA		 1726_exit:
1727 spin_unlock_irqrestore(&d40c->lock, flags);
1728 return is_paused;
1729
1730}
1731
1732
8d318a50
LW		 1733static u32 stedma40_residue(struct dma_chan *chan)
1734{
1735 struct d40_chan *d40c =
1736 container_of(chan, struct d40_chan, chan);
1737 u32 bytes_left;
1738 unsigned long flags;
1739
1740 spin_lock_irqsave(&d40c->lock, flags);
1741 bytes_left = d40_residue(d40c);
1742 spin_unlock_irqrestore(&d40c->lock, flags);
1743
1744 return bytes_left;
1745}
1746
3e3a0763
RV		 1747static int
1748d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
1749 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 1750 unsigned int sg_len, dma_addr_t src_dev_addr,
1751 dma_addr_t dst_dev_addr)
3e3a0763
RV		 1752{
1753 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1754 struct stedma40_half_channel_info *src_info = &cfg->src_info;
1755 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
5ed04b85 1756 int ret;
3e3a0763 1757
5ed04b85
RV		 1758 ret = d40_log_sg_to_lli(sg_src, sg_len,
1759 src_dev_addr,
1760 desc->lli_log.src,
1761 chan->log_def.lcsp1,
1762 src_info->data_width,
1763 dst_info->data_width);
1764
1765 ret = d40_log_sg_to_lli(sg_dst, sg_len,
1766 dst_dev_addr,
1767 desc->lli_log.dst,
1768 chan->log_def.lcsp3,
1769 dst_info->data_width,
1770 src_info->data_width);
1771
1772 return ret < 0 ? ret : 0;
3e3a0763
RV		 1773}
1774
1775static int
1776d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
1777 struct scatterlist *sg_src, struct scatterlist *sg_dst,
822c5676
RV		 1778 unsigned int sg_len, dma_addr_t src_dev_addr,
1779 dma_addr_t dst_dev_addr)
3e3a0763 1780{
3e3a0763
RV		 1781 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1782 struct stedma40_half_channel_info *src_info = &cfg->src_info;
1783 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
0c842b55 1784 unsigned long flags = 0;
3e3a0763
RV		 1785 int ret;
1786
0c842b55
RV		 1787 if (desc->cyclic)
1788 flags |= LLI_CYCLIC | LLI_TERM_INT;
1789
3e3a0763
RV		 1790 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
1791 desc->lli_phy.src,
1792 virt_to_phys(desc->lli_phy.src),
1793 chan->src_def_cfg,
0c842b55 1794 src_info, dst_info, flags);
3e3a0763
RV		 1795
1796 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
1797 desc->lli_phy.dst,
1798 virt_to_phys(desc->lli_phy.dst),
1799 chan->dst_def_cfg,
0c842b55 1800 dst_info, src_info, flags);
3e3a0763
RV		 1801
1802 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
1803 desc->lli_pool.size, DMA_TO_DEVICE);
1804
1805 return ret < 0 ? ret : 0;
1806}
1807
1808
5f81158f
RV		 1809static struct d40_desc *
1810d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
1811 unsigned int sg_len, unsigned long dma_flags)
1812{
1813 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1814 struct d40_desc *desc;
dbd88788 1815 int ret;
5f81158f
RV		 1816
1817 desc = d40_desc_get(chan);
1818 if (!desc)
1819 return NULL;
1820
1821 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
1822 cfg->dst_info.data_width);
1823 if (desc->lli_len < 0) {
1824 chan_err(chan, "Unaligned size\n");
dbd88788
RV		 1825 goto err;
1826 }
5f81158f 1827
dbd88788
RV		 1828 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
1829 if (ret < 0) {
1830 chan_err(chan, "Could not allocate lli\n");
1831 goto err;
5f81158f
RV		 1832 }
1833
dbd88788 1834
5f81158f
RV		 1835 desc->lli_current = 0;
1836 desc->txd.flags = dma_flags;
1837 desc->txd.tx_submit = d40_tx_submit;
1838
1839 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
1840
1841 return desc;
dbd88788
RV		 1842
1843err:
1844 d40_desc_free(chan, desc);
1845 return NULL;
5f81158f
RV		 1846}
1847
cade1d30
RV		 1848static dma_addr_t
1849d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction)
8d318a50 1850{
cade1d30
RV		 1851 struct stedma40_platform_data *plat = chan->base->plat_data;
1852 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
711b9cea 1853 dma_addr_t addr = 0;
cade1d30
RV		 1854
1855 if (chan->runtime_addr)
1856 return chan->runtime_addr;
1857
1858 if (direction == DMA_FROM_DEVICE)
1859 addr = plat->dev_rx[cfg->src_dev_type];
1860 else if (direction == DMA_TO_DEVICE)
1861 addr = plat->dev_tx[cfg->dst_dev_type];
1862
1863 return addr;
1864}
1865
1866static struct dma_async_tx_descriptor *
1867d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
1868 struct scatterlist *sg_dst, unsigned int sg_len,
1869 enum dma_data_direction direction, unsigned long dma_flags)
1870{
1871 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
822c5676
RV		 1872 dma_addr_t src_dev_addr = 0;
1873 dma_addr_t dst_dev_addr = 0;
cade1d30 1874 struct d40_desc *desc;
2a614340 1875 unsigned long flags;
cade1d30 1876 int ret;
8d318a50 1877
cade1d30
RV		 1878 if (!chan->phy_chan) {
1879 chan_err(chan, "Cannot prepare unallocated channel\n");
1880 return NULL;
0d0f6b8b
JA		 1881 }
1882
0c842b55 1883
cade1d30 1884 spin_lock_irqsave(&chan->lock, flags);
8d318a50 1885
cade1d30
RV		 1886 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
1887 if (desc == NULL)
8d318a50
LW		 1888 goto err;
1889
0c842b55
RV		 1890 if (sg_next(&sg_src[sg_len - 1]) == sg_src)
1891 desc->cyclic = true;
1892
822c5676
RV		 1893 if (direction != DMA_NONE) {
1894 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
1895
1896 if (direction == DMA_FROM_DEVICE)
1897 src_dev_addr = dev_addr;
1898 else if (direction == DMA_TO_DEVICE)
1899 dst_dev_addr = dev_addr;
1900 }
cade1d30
RV		 1901
1902 if (chan_is_logical(chan))
1903 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
822c5676 1904 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 1905 else
1906 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
822c5676 1907 sg_len, src_dev_addr, dst_dev_addr);
cade1d30
RV		 1908
1909 if (ret) {
1910 chan_err(chan, "Failed to prepare %s sg job: %d\n",
1911 chan_is_logical(chan) ? "log" : "phy", ret);
1912 goto err;
8d318a50
LW		 1913 }
1914
cade1d30
RV		 1915 spin_unlock_irqrestore(&chan->lock, flags);
1916
1917 return &desc->txd;
8d318a50 1918
8d318a50 1919err:
cade1d30
RV		 1920 if (desc)
1921 d40_desc_free(chan, desc);
1922 spin_unlock_irqrestore(&chan->lock, flags);
8d318a50
LW		 1923 return NULL;
1924}
8d318a50
LW		 1925
1926bool stedma40_filter(struct dma_chan *chan, void *data)
1927{
1928 struct stedma40_chan_cfg *info = data;
1929 struct d40_chan *d40c =
1930 container_of(chan, struct d40_chan, chan);
1931 int err;
1932
1933 if (data) {
1934 err = d40_validate_conf(d40c, info);
1935 if (!err)
1936 d40c->dma_cfg = *info;
1937 } else
1938 err = d40_config_memcpy(d40c);
1939
ce2ca125
RV		 1940 if (!err)
1941 d40c->configured = true;
1942
8d318a50
LW		 1943 return err == 0;
1944}
1945EXPORT_SYMBOL(stedma40_filter);
1946
ac2c0a38
RV		 1947static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
1948{
1949 bool realtime = d40c->dma_cfg.realtime;
1950 bool highprio = d40c->dma_cfg.high_priority;
1951 u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
1952 u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
1953 u32 event = D40_TYPE_TO_EVENT(dev_type);
1954 u32 group = D40_TYPE_TO_GROUP(dev_type);
1955 u32 bit = 1 << event;
1956
1957 /* Destination event lines are stored in the upper halfword */
1958 if (!src)
1959 bit <<= 16;
1960
1961 writel(bit, d40c->base->virtbase + prioreg + group * 4);
1962 writel(bit, d40c->base->virtbase + rtreg + group * 4);
1963}
1964
1965static void d40_set_prio_realtime(struct d40_chan *d40c)
1966{
1967 if (d40c->base->rev < 3)
1968 return;
1969
1970 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
1971 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1972 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
1973
1974 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
1975 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1976 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
1977}
1978
8d318a50
LW		 1979/* DMA ENGINE functions */
1980static int d40_alloc_chan_resources(struct dma_chan *chan)
1981{
1982 int err;
1983 unsigned long flags;
1984 struct d40_chan *d40c =
1985 container_of(chan, struct d40_chan, chan);
ef1872ec 1986 bool is_free_phy;
8d318a50
LW		 1987 spin_lock_irqsave(&d40c->lock, flags);
1988
1989 d40c->completed = chan->cookie = 1;
1990
ce2ca125
RV		 1991 /* If no dma configuration is set use default configuration (memcpy) */
1992 if (!d40c->configured) {
8d318a50 1993 err = d40_config_memcpy(d40c);
ff0b12ba 1994 if (err) {
6db5a8ba 1995 chan_err(d40c, "Failed to configure memcpy channel\n");
ff0b12ba
JA		 1996 goto fail;
1997 }
8d318a50 1998 }
ef1872ec 1999 is_free_phy = (d40c->phy_chan == NULL);
8d318a50
LW		 2000
2001 err = d40_allocate_channel(d40c);
2002 if (err) {
6db5a8ba 2003 chan_err(d40c, "Failed to allocate channel\n");
ff0b12ba 2004 goto fail;
8d318a50
LW		 2005 }
2006
ef1872ec
LW		 2007 /* Fill in basic CFG register values */
2008 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
724a8577 2009 &d40c->dst_def_cfg, chan_is_logical(d40c));
ef1872ec 2010
ac2c0a38
RV		 2011 d40_set_prio_realtime(d40c);
2012
724a8577 2013 if (chan_is_logical(d40c)) {
ef1872ec
LW		 2014 d40_log_cfg(&d40c->dma_cfg,
2015 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2016
2017 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
2018 d40c->lcpa = d40c->base->lcpa_base +
2019 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
2020 else
2021 d40c->lcpa = d40c->base->lcpa_base +
2022 d40c->dma_cfg.dst_dev_type *
2023 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
2024 }
2025
2026 /*
2027 * Only write channel configuration to the DMA if the physical
2028 * resource is free. In case of multiple logical channels
2029 * on the same physical resource, only the first write is necessary.
2030 */
b55912c6
JA		 2031 if (is_free_phy)
2032 d40_config_write(d40c);
ff0b12ba 2033fail:
8d318a50 2034 spin_unlock_irqrestore(&d40c->lock, flags);
ff0b12ba 2035 return err;
8d318a50
LW		 2036}
2037
2038static void d40_free_chan_resources(struct dma_chan *chan)
2039{
2040 struct d40_chan *d40c =
2041 container_of(chan, struct d40_chan, chan);
2042 int err;
2043 unsigned long flags;
2044
0d0f6b8b 2045 if (d40c->phy_chan == NULL) {
6db5a8ba 2046 chan_err(d40c, "Cannot free unallocated channel\n");
0d0f6b8b
JA		 2047 return;
2048 }
2049
2050
8d318a50
LW		 2051 spin_lock_irqsave(&d40c->lock, flags);
2052
2053 err = d40_free_dma(d40c);
2054
2055 if (err)
6db5a8ba 2056 chan_err(d40c, "Failed to free channel\n");
8d318a50
LW		 2057 spin_unlock_irqrestore(&d40c->lock, flags);
2058}
2059
2060static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2061 dma_addr_t dst,
2062 dma_addr_t src,
2063 size_t size,
2a614340 2064 unsigned long dma_flags)
8d318a50 2065{
95944c6e
RV		 2066 struct scatterlist dst_sg;
2067 struct scatterlist src_sg;
8d318a50 2068
95944c6e
RV		 2069 sg_init_table(&dst_sg, 1);
2070 sg_init_table(&src_sg, 1);
8d318a50 2071
95944c6e
RV		 2072 sg_dma_address(&dst_sg) = dst;
2073 sg_dma_address(&src_sg) = src;
8d318a50 2074
95944c6e
RV		 2075 sg_dma_len(&dst_sg) = size;
2076 sg_dma_len(&src_sg) = size;
8d318a50 2077
cade1d30 2078 return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
8d318a50
LW		 2079}
2080
0d688662 2081static struct dma_async_tx_descriptor *
cade1d30
RV		 2082d40_prep_memcpy_sg(struct dma_chan *chan,
2083 struct scatterlist *dst_sg, unsigned int dst_nents,
2084 struct scatterlist *src_sg, unsigned int src_nents,
2085 unsigned long dma_flags)
0d688662
IS		 2086{
2087 if (dst_nents != src_nents)
2088 return NULL;
2089
cade1d30 2090 return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
00ac0341
RV		 2091}
2092
8d318a50
LW		 2093static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2094 struct scatterlist *sgl,
2095 unsigned int sg_len,
2096 enum dma_data_direction direction,
2a614340 2097 unsigned long dma_flags)
8d318a50 2098{
00ac0341
RV		 2099 if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE)
2100 return NULL;
2101
cade1d30 2102 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
8d318a50
LW		 2103}
2104
0c842b55
RV		 2105static struct dma_async_tx_descriptor *
2106dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2107 size_t buf_len, size_t period_len,
2108 enum dma_data_direction direction)
2109{
2110 unsigned int periods = buf_len / period_len;
2111 struct dma_async_tx_descriptor *txd;
2112 struct scatterlist *sg;
2113 int i;
2114
2115 sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_KERNEL);
2116 for (i = 0; i < periods; i++) {
2117 sg_dma_address(&sg[i]) = dma_addr;
2118 sg_dma_len(&sg[i]) = period_len;
2119 dma_addr += period_len;
2120 }
2121
2122 sg[periods].offset = 0;
2123 sg[periods].length = 0;
2124 sg[periods].page_link =
2125 ((unsigned long)sg | 0x01) & ~0x02;
2126
2127 txd = d40_prep_sg(chan, sg, sg, periods, direction,
2128 DMA_PREP_INTERRUPT);
2129
2130 kfree(sg);
2131
2132 return txd;
2133}
2134
8d318a50
LW		 2135static enum dma_status d40_tx_status(struct dma_chan *chan,
2136 dma_cookie_t cookie,
2137 struct dma_tx_state *txstate)
2138{
2139 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2140 dma_cookie_t last_used;
2141 dma_cookie_t last_complete;
2142 int ret;
2143
0d0f6b8b 2144 if (d40c->phy_chan == NULL) {
6db5a8ba 2145 chan_err(d40c, "Cannot read status of unallocated channel\n");
0d0f6b8b
JA		 2146 return -EINVAL;
2147 }
2148
8d318a50
LW		 2149 last_complete = d40c->completed;
2150 last_used = chan->cookie;
2151
a5ebca47
JA		 2152 if (d40_is_paused(d40c))
2153 ret = DMA_PAUSED;
2154 else
2155 ret = dma_async_is_complete(cookie, last_complete, last_used);
8d318a50 2156
a5ebca47
JA		 2157 dma_set_tx_state(txstate, last_complete, last_used,
2158 stedma40_residue(chan));
8d318a50
LW		 2159
2160 return ret;
2161}
2162
2163static void d40_issue_pending(struct dma_chan *chan)
2164{
2165 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2166 unsigned long flags;
2167
0d0f6b8b 2168 if (d40c->phy_chan == NULL) {
6db5a8ba 2169 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2170 return;
2171 }
2172
8d318a50
LW		 2173 spin_lock_irqsave(&d40c->lock, flags);
2174
a8f3067b
PF		 2175 list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2176
2177 /* Busy means that queued jobs are already being processed */
8d318a50
LW		 2178 if (!d40c->busy)
2179 (void) d40_queue_start(d40c);
2180
2181 spin_unlock_irqrestore(&d40c->lock, flags);
2182}
2183
95e1400f
LW		 2184/* Runtime reconfiguration extension */
2185static void d40_set_runtime_config(struct dma_chan *chan,
2186 struct dma_slave_config *config)
2187{
2188 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2189 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2190 enum dma_slave_buswidth config_addr_width;
2191 dma_addr_t config_addr;
2192 u32 config_maxburst;
2193 enum stedma40_periph_data_width addr_width;
2194 int psize;
2195
2196 if (config->direction == DMA_FROM_DEVICE) {
2197 dma_addr_t dev_addr_rx =
2198 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2199
2200 config_addr = config->src_addr;
2201 if (dev_addr_rx)
2202 dev_dbg(d40c->base->dev,
2203 "channel has a pre-wired RX address %08x "
2204 "overriding with %08x\n",
2205 dev_addr_rx, config_addr);
2206 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2207 dev_dbg(d40c->base->dev,
2208 "channel was not configured for peripheral "
2209 "to memory transfer (%d) overriding\n",
2210 cfg->dir);
2211 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2212
2213 config_addr_width = config->src_addr_width;
2214 config_maxburst = config->src_maxburst;
2215
2216 } else if (config->direction == DMA_TO_DEVICE) {
2217 dma_addr_t dev_addr_tx =
2218 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2219
2220 config_addr = config->dst_addr;
2221 if (dev_addr_tx)
2222 dev_dbg(d40c->base->dev,
2223 "channel has a pre-wired TX address %08x "
2224 "overriding with %08x\n",
2225 dev_addr_tx, config_addr);
2226 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2227 dev_dbg(d40c->base->dev,
2228 "channel was not configured for memory "
2229 "to peripheral transfer (%d) overriding\n",
2230 cfg->dir);
2231 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2232
2233 config_addr_width = config->dst_addr_width;
2234 config_maxburst = config->dst_maxburst;
2235
2236 } else {
2237 dev_err(d40c->base->dev,
2238 "unrecognized channel direction %d\n",
2239 config->direction);
2240 return;
2241 }
2242
2243 switch (config_addr_width) {
2244 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2245 addr_width = STEDMA40_BYTE_WIDTH;
2246 break;
2247 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2248 addr_width = STEDMA40_HALFWORD_WIDTH;
2249 break;
2250 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2251 addr_width = STEDMA40_WORD_WIDTH;
2252 break;
2253 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2254 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2255 break;
2256 default:
2257 dev_err(d40c->base->dev,
2258 "illegal peripheral address width "
2259 "requested (%d)\n",
2260 config->src_addr_width);
2261 return;
2262 }
2263
724a8577 2264 if (chan_is_logical(d40c)) {
a59670a4
PF		 2265 if (config_maxburst >= 16)
2266 psize = STEDMA40_PSIZE_LOG_16;
2267 else if (config_maxburst >= 8)
2268 psize = STEDMA40_PSIZE_LOG_8;
2269 else if (config_maxburst >= 4)
2270 psize = STEDMA40_PSIZE_LOG_4;
2271 else
2272 psize = STEDMA40_PSIZE_LOG_1;
2273 } else {
2274 if (config_maxburst >= 16)
2275 psize = STEDMA40_PSIZE_PHY_16;
2276 else if (config_maxburst >= 8)
2277 psize = STEDMA40_PSIZE_PHY_8;
2278 else if (config_maxburst >= 4)
2279 psize = STEDMA40_PSIZE_PHY_4;
d49278e3
PF		 2280 else if (config_maxburst >= 2)
2281 psize = STEDMA40_PSIZE_PHY_2;
a59670a4
PF		 2282 else
2283 psize = STEDMA40_PSIZE_PHY_1;
2284 }
95e1400f
LW		 2285
2286 /* Set up all the endpoint configs */
2287 cfg->src_info.data_width = addr_width;
2288 cfg->src_info.psize = psize;
51f5d744 2289 cfg->src_info.big_endian = false;
95e1400f
LW		 2290 cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2291 cfg->dst_info.data_width = addr_width;
2292 cfg->dst_info.psize = psize;
51f5d744 2293 cfg->dst_info.big_endian = false;
95e1400f
LW		 2294 cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2295
a59670a4 2296 /* Fill in register values */
724a8577 2297 if (chan_is_logical(d40c))
a59670a4
PF		 2298 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2299 else
2300 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2301 &d40c->dst_def_cfg, false);
2302
95e1400f
LW		 2303 /* These settings will take precedence later */
2304 d40c->runtime_addr = config_addr;
2305 d40c->runtime_direction = config->direction;
2306 dev_dbg(d40c->base->dev,
2307 "configured channel %s for %s, data width %d, "
2308 "maxburst %d bytes, LE, no flow control\n",
2309 dma_chan_name(chan),
2310 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
2311 config_addr_width,
2312 config_maxburst);
2313}
2314
05827630
LW		 2315static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2316 unsigned long arg)
8d318a50 2317{
8d318a50
LW		 2318 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2319
0d0f6b8b 2320 if (d40c->phy_chan == NULL) {
6db5a8ba 2321 chan_err(d40c, "Channel is not allocated!\n");
0d0f6b8b
JA		 2322 return -EINVAL;
2323 }
2324
8d318a50
LW		 2325 switch (cmd) {
2326 case DMA_TERMINATE_ALL:
86eb5fb6 2327 return d40_terminate_all(d40c);
8d318a50 2328 case DMA_PAUSE:
86eb5fb6 2329 return d40_pause(d40c);
8d318a50 2330 case DMA_RESUME:
86eb5fb6 2331 return d40_resume(d40c);
95e1400f
LW		 2332 case DMA_SLAVE_CONFIG:
2333 d40_set_runtime_config(chan,
2334 (struct dma_slave_config *) arg);
2335 return 0;
2336 default:
2337 break;
8d318a50
LW		 2338 }
2339
2340 /* Other commands are unimplemented */
2341 return -ENXIO;
2342}
2343
2344/* Initialization functions */
2345
2346static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2347 struct d40_chan *chans, int offset,
2348 int num_chans)
2349{
2350 int i = 0;
2351 struct d40_chan *d40c;
2352
2353 INIT_LIST_HEAD(&dma->channels);
2354
2355 for (i = offset; i < offset + num_chans; i++) {
2356 d40c = &chans[i];
2357 d40c->base = base;
2358 d40c->chan.device = dma;
2359
8d318a50
LW		 2360 spin_lock_init(&d40c->lock);
2361
2362 d40c->log_num = D40_PHY_CHAN;
2363
8d318a50
LW		 2364 INIT_LIST_HEAD(&d40c->active);
2365 INIT_LIST_HEAD(&d40c->queue);
a8f3067b 2366 INIT_LIST_HEAD(&d40c->pending_queue);
8d318a50
LW		 2367 INIT_LIST_HEAD(&d40c->client);
2368
8d318a50
LW		 2369 tasklet_init(&d40c->tasklet, dma_tasklet,
2370 (unsigned long) d40c);
2371
2372 list_add_tail(&d40c->chan.device_node,
2373 &dma->channels);
2374 }
2375}
2376
7ad74a7c
RV		 2377static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2378{
2379 if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2380 dev->device_prep_slave_sg = d40_prep_slave_sg;
2381
2382 if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2383 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2384
2385 /*
2386 * This controller can only access address at even
2387 * 32bit boundaries, i.e. 2^2
2388 */
2389 dev->copy_align = 2;
2390 }
2391
2392 if (dma_has_cap(DMA_SG, dev->cap_mask))
2393 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2394
0c842b55
RV		 2395 if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2396 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2397
7ad74a7c
RV		 2398 dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2399 dev->device_free_chan_resources = d40_free_chan_resources;
2400 dev->device_issue_pending = d40_issue_pending;
2401 dev->device_tx_status = d40_tx_status;
2402 dev->device_control = d40_control;
2403 dev->dev = base->dev;
2404}
2405
8d318a50
LW		 2406static int __init d40_dmaengine_init(struct d40_base *base,
2407 int num_reserved_chans)
2408{
2409 int err ;
2410
2411 d40_chan_init(base, &base->dma_slave, base->log_chans,
2412 0, base->num_log_chans);
2413
2414 dma_cap_zero(base->dma_slave.cap_mask);
2415 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
0c842b55 2416 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
8d318a50 2417
7ad74a7c 2418 d40_ops_init(base, &base->dma_slave);
8d318a50
LW		 2419
2420 err = dma_async_device_register(&base->dma_slave);
2421
2422 if (err) {
6db5a8ba 2423 d40_err(base->dev, "Failed to register slave channels\n");
8d318a50
LW		 2424 goto failure1;
2425 }
2426
2427 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2428 base->num_log_chans, base->plat_data->memcpy_len);
2429
2430 dma_cap_zero(base->dma_memcpy.cap_mask);
2431 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
7ad74a7c
RV		 2432 dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
2433
2434 d40_ops_init(base, &base->dma_memcpy);
8d318a50
LW		 2435
2436 err = dma_async_device_register(&base->dma_memcpy);
2437
2438 if (err) {
6db5a8ba
RV		 2439 d40_err(base->dev,
2440 "Failed to regsiter memcpy only channels\n");
8d318a50
LW		 2441 goto failure2;
2442 }
2443
2444 d40_chan_init(base, &base->dma_both, base->phy_chans,
2445 0, num_reserved_chans);
2446
2447 dma_cap_zero(base->dma_both.cap_mask);
2448 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2449 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
7ad74a7c 2450 dma_cap_set(DMA_SG, base->dma_both.cap_mask);
0c842b55 2451 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
7ad74a7c
RV		 2452
2453 d40_ops_init(base, &base->dma_both);
8d318a50
LW		 2454 err = dma_async_device_register(&base->dma_both);
2455
2456 if (err) {
6db5a8ba
RV		 2457 d40_err(base->dev,
2458 "Failed to register logical and physical capable channels\n");
8d318a50
LW		 2459 goto failure3;
2460 }
2461 return 0;
2462failure3:
2463 dma_async_device_unregister(&base->dma_memcpy);
2464failure2:
2465 dma_async_device_unregister(&base->dma_slave);
2466failure1:
2467 return err;
2468}
2469
2470/* Initialization functions. */
2471
2472static int __init d40_phy_res_init(struct d40_base *base)
2473{
2474 int i;
2475 int num_phy_chans_avail = 0;
2476 u32 val[2];
2477 int odd_even_bit = -2;
2478
2479 val[0] = readl(base->virtbase + D40_DREG_PRSME);
2480 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2481
2482 for (i = 0; i < base->num_phy_chans; i++) {
2483 base->phy_res[i].num = i;
2484 odd_even_bit += 2 * ((i % 2) == 0);
2485 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2486 /* Mark security only channels as occupied */
2487 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2488 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2489 } else {
2490 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2491 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2492 num_phy_chans_avail++;
2493 }
2494 spin_lock_init(&base->phy_res[i].lock);
2495 }
6b7acd84
JA		 2496
2497 /* Mark disabled channels as occupied */
2498 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
f57b407c
RV		 2499 int chan = base->plat_data->disabled_channels[i];
2500
2501 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
2502 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
2503 num_phy_chans_avail--;
6b7acd84
JA		 2504 }
2505
8d318a50
LW		 2506 dev_info(base->dev, "%d of %d physical DMA channels available\n",
2507 num_phy_chans_avail, base->num_phy_chans);
2508
2509 /* Verify settings extended vs standard */
2510 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2511
2512 for (i = 0; i < base->num_phy_chans; i++) {
2513
2514 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2515 (val[0] & 0x3) != 1)
2516 dev_info(base->dev,
2517 "[%s] INFO: channel %d is misconfigured (%d)\n",
2518 __func__, i, val[0] & 0x3);
2519
2520 val[0] = val[0] >> 2;
2521 }
2522
2523 return num_phy_chans_avail;
2524}
2525
2526static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2527{
2528 static const struct d40_reg_val dma_id_regs[] = {
2529 /* Peripheral Id */
2530 { .reg = D40_DREG_PERIPHID0, .val = 0x0040},
2531 { .reg = D40_DREG_PERIPHID1, .val = 0x0000},
2532 /*
2533 * D40_DREG_PERIPHID2 Depends on HW revision:
4d594900 2534 * DB8500ed has 0x0008,
8d318a50 2535 * ? has 0x0018,
4d594900
RV		 2536 * DB8500v1 has 0x0028
2537 * DB8500v2 has 0x0038
8d318a50
LW		 2538 */
2539 { .reg = D40_DREG_PERIPHID3, .val = 0x0000},
2540
2541 /* PCell Id */
2542 { .reg = D40_DREG_CELLID0, .val = 0x000d},
2543 { .reg = D40_DREG_CELLID1, .val = 0x00f0},
2544 { .reg = D40_DREG_CELLID2, .val = 0x0005},
2545 { .reg = D40_DREG_CELLID3, .val = 0x00b1}
2546 };
2547 struct stedma40_platform_data *plat_data;
2548 struct clk *clk = NULL;
2549 void __iomem *virtbase = NULL;
2550 struct resource *res = NULL;
2551 struct d40_base *base = NULL;
2552 int num_log_chans = 0;
2553 int num_phy_chans;
2554 int i;
f4185592 2555 u32 val;
3ae0267f 2556 u32 rev;
8d318a50
LW		 2557
2558 clk = clk_get(&pdev->dev, NULL);
2559
2560 if (IS_ERR(clk)) {
6db5a8ba 2561 d40_err(&pdev->dev, "No matching clock found\n");
8d318a50
LW		 2562 goto failure;
2563 }
2564
2565 clk_enable(clk);
2566
2567 /* Get IO for DMAC base address */
2568 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2569 if (!res)
2570 goto failure;
2571
2572 if (request_mem_region(res->start, resource_size(res),
2573 D40_NAME " I/O base") == NULL)
2574 goto failure;
2575
2576 virtbase = ioremap(res->start, resource_size(res));
2577 if (!virtbase)
2578 goto failure;
2579
2580 /* HW version check */
2581 for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {
2582 if (dma_id_regs[i].val !=
2583 readl(virtbase + dma_id_regs[i].reg)) {
6db5a8ba
RV		 2584 d40_err(&pdev->dev,
2585 "Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
8d318a50
LW		 2586 dma_id_regs[i].val,
2587 dma_id_regs[i].reg,
2588 readl(virtbase + dma_id_regs[i].reg));
2589 goto failure;
2590 }
2591 }
2592
3ae0267f 2593 /* Get silicon revision and designer */
f4185592 2594 val = readl(virtbase + D40_DREG_PERIPHID2);
8d318a50 2595
3ae0267f
JA		 2596 if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) !=
2597 D40_HW_DESIGNER) {
6db5a8ba
RV		 2598 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
2599 val & D40_DREG_PERIPHID2_DESIGNER_MASK,
3ae0267f 2600 D40_HW_DESIGNER);
8d318a50
LW		 2601 goto failure;
2602 }
2603
3ae0267f
JA		 2604 rev = (val & D40_DREG_PERIPHID2_REV_MASK) >>
2605 D40_DREG_PERIPHID2_REV_POS;
2606
8d318a50
LW		 2607 /* The number of physical channels on this HW */
2608 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2609
2610 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
3ae0267f 2611 rev, res->start);
8d318a50
LW		 2612
2613 plat_data = pdev->dev.platform_data;
2614
2615 /* Count the number of logical channels in use */
2616 for (i = 0; i < plat_data->dev_len; i++)
2617 if (plat_data->dev_rx[i] != 0)
2618 num_log_chans++;
2619
2620 for (i = 0; i < plat_data->dev_len; i++)
2621 if (plat_data->dev_tx[i] != 0)
2622 num_log_chans++;
2623
2624 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2625 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2626 sizeof(struct d40_chan), GFP_KERNEL);
2627
2628 if (base == NULL) {
6db5a8ba 2629 d40_err(&pdev->dev, "Out of memory\n");
8d318a50
LW		 2630 goto failure;
2631 }
2632
3ae0267f 2633 base->rev = rev;
8d318a50
LW		 2634 base->clk = clk;
2635 base->num_phy_chans = num_phy_chans;
2636 base->num_log_chans = num_log_chans;
2637 base->phy_start = res->start;
2638 base->phy_size = resource_size(res);
2639 base->virtbase = virtbase;
2640 base->plat_data = plat_data;
2641 base->dev = &pdev->dev;
2642 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2643 base->log_chans = &base->phy_chans[num_phy_chans];
2644
2645 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2646 GFP_KERNEL);
2647 if (!base->phy_res)
2648 goto failure;
2649
2650 base->lookup_phy_chans = kzalloc(num_phy_chans *
2651 sizeof(struct d40_chan *),
2652 GFP_KERNEL);
2653 if (!base->lookup_phy_chans)
2654 goto failure;
2655
2656 if (num_log_chans + plat_data->memcpy_len) {
2657 /*
2658 * The max number of logical channels are event lines for all
2659 * src devices and dst devices
2660 */
2661 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2662 sizeof(struct d40_chan *),
2663 GFP_KERNEL);
2664 if (!base->lookup_log_chans)
2665 goto failure;
2666 }
698e4732
JA		 2667
2668 base->lcla_pool.alloc_map = kzalloc(num_phy_chans *
2669 sizeof(struct d40_desc *) *
2670 D40_LCLA_LINK_PER_EVENT_GRP,
8d318a50
LW		 2671 GFP_KERNEL);
2672 if (!base->lcla_pool.alloc_map)
2673 goto failure;
2674
c675b1b4
JA		 2675 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2676 0, SLAB_HWCACHE_ALIGN,
2677 NULL);
2678 if (base->desc_slab == NULL)
2679 goto failure;
2680
8d318a50
LW		 2681 return base;
2682
2683failure:
c6134c96 2684 if (!IS_ERR(clk)) {
8d318a50
LW		 2685 clk_disable(clk);
2686 clk_put(clk);
2687 }
2688 if (virtbase)
2689 iounmap(virtbase);
2690 if (res)
2691 release_mem_region(res->start,
2692 resource_size(res));
2693 if (virtbase)
2694 iounmap(virtbase);
2695
2696 if (base) {
2697 kfree(base->lcla_pool.alloc_map);
2698 kfree(base->lookup_log_chans);
2699 kfree(base->lookup_phy_chans);
2700 kfree(base->phy_res);
2701 kfree(base);
2702 }
2703
2704 return NULL;
2705}
2706
2707static void __init d40_hw_init(struct d40_base *base)
2708{
2709
2710 static const struct d40_reg_val dma_init_reg[] = {
2711 /* Clock every part of the DMA block from start */
2712 { .reg = D40_DREG_GCC, .val = 0x0000ff01},
2713
2714 /* Interrupts on all logical channels */
2715 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
2716 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
2717 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
2718 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
2719 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
2720 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
2721 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
2722 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
2723 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
2724 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
2725 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
2726 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
2727 };
2728 int i;
2729 u32 prmseo[2] = {0, 0};
2730 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2731 u32 pcmis = 0;
2732 u32 pcicr = 0;
2733
2734 for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
2735 writel(dma_init_reg[i].val,
2736 base->virtbase + dma_init_reg[i].reg);
2737
2738 /* Configure all our dma channels to default settings */
2739 for (i = 0; i < base->num_phy_chans; i++) {
2740
2741 activeo[i % 2] = activeo[i % 2] << 2;
2742
2743 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
2744 == D40_ALLOC_PHY) {
2745 activeo[i % 2] |= 3;
2746 continue;
2747 }
2748
2749 /* Enable interrupt # */
2750 pcmis = (pcmis << 1) | 1;
2751
2752 /* Clear interrupt # */
2753 pcicr = (pcicr << 1) | 1;
2754
2755 /* Set channel to physical mode */
2756 prmseo[i % 2] = prmseo[i % 2] << 2;
2757 prmseo[i % 2] |= 1;
2758
2759 }
2760
2761 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
2762 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
2763 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
2764 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
2765
2766 /* Write which interrupt to enable */
2767 writel(pcmis, base->virtbase + D40_DREG_PCMIS);
2768
2769 /* Write which interrupt to clear */
2770 writel(pcicr, base->virtbase + D40_DREG_PCICR);
2771
2772}
2773
508849ad
LW		 2774static int __init d40_lcla_allocate(struct d40_base *base)
2775{
026cbc42 2776 struct d40_lcla_pool *pool = &base->lcla_pool;
508849ad
LW		 2777 unsigned long *page_list;
2778 int i, j;
2779 int ret = 0;
2780
2781 /*
2782 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2783 * To full fill this hardware requirement without wasting 256 kb
2784 * we allocate pages until we get an aligned one.
2785 */
2786 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
2787 GFP_KERNEL);
2788
2789 if (!page_list) {
2790 ret = -ENOMEM;
2791 goto failure;
2792 }
2793
2794 /* Calculating how many pages that are required */
2795 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
2796
2797 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
2798 page_list[i] = __get_free_pages(GFP_KERNEL,
2799 base->lcla_pool.pages);
2800 if (!page_list[i]) {
2801
6db5a8ba
RV		 2802 d40_err(base->dev, "Failed to allocate %d pages.\n",
2803 base->lcla_pool.pages);
508849ad
LW		 2804
2805 for (j = 0; j < i; j++)
2806 free_pages(page_list[j], base->lcla_pool.pages);
2807 goto failure;
2808 }
2809
2810 if ((virt_to_phys((void *)page_list[i]) &
2811 (LCLA_ALIGNMENT - 1)) == 0)
2812 break;
2813 }
2814
2815 for (j = 0; j < i; j++)
2816 free_pages(page_list[j], base->lcla_pool.pages);
2817
2818 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
2819 base->lcla_pool.base = (void *)page_list[i];
2820 } else {
767a9675
JA		 2821 /*
2822 * After many attempts and no succees with finding the correct
2823 * alignment, try with allocating a big buffer.
2824 */
508849ad
LW		 2825 dev_warn(base->dev,
2826 "[%s] Failed to get %d pages @ 18 bit align.\n",
2827 __func__, base->lcla_pool.pages);
2828 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
2829 base->num_phy_chans +
2830 LCLA_ALIGNMENT,
2831 GFP_KERNEL);
2832 if (!base->lcla_pool.base_unaligned) {
2833 ret = -ENOMEM;
2834 goto failure;
2835 }
2836
2837 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
2838 LCLA_ALIGNMENT);
2839 }
2840
026cbc42
RV		 2841 pool->dma_addr = dma_map_single(base->dev, pool->base,
2842 SZ_1K * base->num_phy_chans,
2843 DMA_TO_DEVICE);
2844 if (dma_mapping_error(base->dev, pool->dma_addr)) {
2845 pool->dma_addr = 0;
2846 ret = -ENOMEM;
2847 goto failure;
2848 }
2849
508849ad
LW		 2850 writel(virt_to_phys(base->lcla_pool.base),
2851 base->virtbase + D40_DREG_LCLA);
2852failure:
2853 kfree(page_list);
2854 return ret;
2855}
2856
8d318a50
LW		 2857static int __init d40_probe(struct platform_device *pdev)
2858{
2859 int err;
2860 int ret = -ENOENT;
2861 struct d40_base *base;
2862 struct resource *res = NULL;
2863 int num_reserved_chans;
2864 u32 val;
2865
2866 base = d40_hw_detect_init(pdev);
2867
2868 if (!base)
2869 goto failure;
2870
2871 num_reserved_chans = d40_phy_res_init(base);
2872
2873 platform_set_drvdata(pdev, base);
2874
2875 spin_lock_init(&base->interrupt_lock);
2876 spin_lock_init(&base->execmd_lock);
2877
2878 /* Get IO for logical channel parameter address */
2879 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
2880 if (!res) {
2881 ret = -ENOENT;
6db5a8ba 2882 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
8d318a50
LW		 2883 goto failure;
2884 }
2885 base->lcpa_size = resource_size(res);
2886 base->phy_lcpa = res->start;
2887
2888 if (request_mem_region(res->start, resource_size(res),
2889 D40_NAME " I/O lcpa") == NULL) {
2890 ret = -EBUSY;
6db5a8ba
RV		 2891 d40_err(&pdev->dev,
2892 "Failed to request LCPA region 0x%x-0x%x\n",
2893 res->start, res->end);
8d318a50
LW		 2894 goto failure;
2895 }
2896
2897 /* We make use of ESRAM memory for this. */
2898 val = readl(base->virtbase + D40_DREG_LCPA);
2899 if (res->start != val && val != 0) {
2900 dev_warn(&pdev->dev,
2901 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2902 __func__, val, res->start);
2903 } else
2904 writel(res->start, base->virtbase + D40_DREG_LCPA);
2905
2906 base->lcpa_base = ioremap(res->start, resource_size(res));
2907 if (!base->lcpa_base) {
2908 ret = -ENOMEM;
6db5a8ba 2909 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
8d318a50
LW		 2910 goto failure;
2911 }
8d318a50 2912
508849ad
LW		 2913 ret = d40_lcla_allocate(base);
2914 if (ret) {
6db5a8ba 2915 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
8d318a50
LW		 2916 goto failure;
2917 }
2918
2919 spin_lock_init(&base->lcla_pool.lock);
2920
8d318a50
LW		 2921 base->irq = platform_get_irq(pdev, 0);
2922
2923 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
8d318a50 2924 if (ret) {
6db5a8ba 2925 d40_err(&pdev->dev, "No IRQ defined\n");
8d318a50
LW		 2926 goto failure;
2927 }
2928
2929 err = d40_dmaengine_init(base, num_reserved_chans);
2930 if (err)
2931 goto failure;
2932
2933 d40_hw_init(base);
2934
2935 dev_info(base->dev, "initialized\n");
2936 return 0;
2937
2938failure:
2939 if (base) {
c675b1b4
JA		 2940 if (base->desc_slab)
2941 kmem_cache_destroy(base->desc_slab);
8d318a50
LW		 2942 if (base->virtbase)
2943 iounmap(base->virtbase);
026cbc42
RV		 2944
2945 if (base->lcla_pool.dma_addr)
2946 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
2947 SZ_1K * base->num_phy_chans,
2948 DMA_TO_DEVICE);
2949
508849ad
LW		 2950 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
2951 free_pages((unsigned long)base->lcla_pool.base,
2952 base->lcla_pool.pages);
767a9675
JA		 2953
2954 kfree(base->lcla_pool.base_unaligned);
2955
8d318a50
LW		 2956 if (base->phy_lcpa)
2957 release_mem_region(base->phy_lcpa,
2958 base->lcpa_size);
2959 if (base->phy_start)
2960 release_mem_region(base->phy_start,
2961 base->phy_size);
2962 if (base->clk) {
2963 clk_disable(base->clk);
2964 clk_put(base->clk);
2965 }
2966
2967 kfree(base->lcla_pool.alloc_map);
2968 kfree(base->lookup_log_chans);
2969 kfree(base->lookup_phy_chans);
2970 kfree(base->phy_res);
2971 kfree(base);
2972 }
2973
6db5a8ba 2974 d40_err(&pdev->dev, "probe failed\n");
8d318a50
LW		 2975 return ret;
2976}
2977
2978static struct platform_driver d40_driver = {
2979 .driver = {
2980 .owner = THIS_MODULE,
2981 .name = D40_NAME,
2982 },
2983};
2984
cb9ab2d8 2985static int __init stedma40_init(void)
8d318a50
LW		 2986{
2987 return platform_driver_probe(&d40_driver, d40_probe);
2988}
a0eb221a 2989subsys_initcall(stedma40_init);
Linux kernel - Deliverables
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