[deliverable/linux.git] / drivers / dma / ste_dma40_ll.c

/*
 * Copyright (C) ST-Ericsson SA 2007-2010
 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
 * License terms: GNU General Public License (GPL) version 2
 */

#include <linux/kernel.h>
#include <plat/ste_dma40.h>

#include "ste_dma40_ll.h"

/* Sets up proper LCSP1 and LCSP3 register for a logical channel */
void d40_log_cfg(struct stedma40_chan_cfg *cfg,
		 u32 *lcsp1, u32 *lcsp3)
{
	u32 l3 = 0; /* dst */
	u32 l1 = 0; /* src */

	/* src is mem? -> increase address pos */
	if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
	    cfg->dir ==  STEDMA40_MEM_TO_MEM)
		l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;

	/* dst is mem? -> increase address pos */
	if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
	    cfg->dir ==  STEDMA40_MEM_TO_MEM)
		l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;

	/* src is hw? -> master port 1 */
	if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
	    cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
		l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;

	/* dst is hw? -> master port 1 */
	if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
	    cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
		l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;

	l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
	l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
	l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;

	l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
	l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
	l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;

	*lcsp1 = l1;
	*lcsp3 = l3;

}

/* Sets up SRC and DST CFG register for both logical and physical channels */
void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
		 u32 *src_cfg, u32 *dst_cfg, bool is_log)
{
	u32 src = 0;
	u32 dst = 0;

	if (!is_log) {
		/* Physical channel */
		if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
			/* Set master port to 1 */
			src |= 1 << D40_SREG_CFG_MST_POS;
			src |= D40_TYPE_TO_EVENT(cfg->src_dev_type);

			if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
				src |= 1 << D40_SREG_CFG_PHY_TM_POS;
			else
				src |= 3 << D40_SREG_CFG_PHY_TM_POS;
		}
		if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
			/* Set master port to 1 */
			dst |= 1 << D40_SREG_CFG_MST_POS;
			dst |= D40_TYPE_TO_EVENT(cfg->dst_dev_type);

			if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
				dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
			else
				dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
		}
		/* Interrupt on end of transfer for destination */
		dst |= 1 << D40_SREG_CFG_TIM_POS;

		/* Generate interrupt on error */
		src |= 1 << D40_SREG_CFG_EIM_POS;
		dst |= 1 << D40_SREG_CFG_EIM_POS;

		/* PSIZE */
		if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
			src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
			src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
		}
		if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
			dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
			dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
		}

		/* Element size */
		src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
		dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;

	} else {
		/* Logical channel */
		dst |= 1 << D40_SREG_CFG_LOG_GIM_POS;
		src |= 1 << D40_SREG_CFG_LOG_GIM_POS;
	}

	if (cfg->high_priority) {
		src |= 1 << D40_SREG_CFG_PRI_POS;
		dst |= 1 << D40_SREG_CFG_PRI_POS;
	}

	if (cfg->src_info.big_endian)
		src |= 1 << D40_SREG_CFG_LBE_POS;
	if (cfg->dst_info.big_endian)
		dst |= 1 << D40_SREG_CFG_LBE_POS;

	*src_cfg = src;
	*dst_cfg = dst;
}

static int d40_phy_fill_lli(struct d40_phy_lli *lli,
			    dma_addr_t data,
			    u32 data_size,
			    int psize,
			    dma_addr_t next_lli,
			    u32 reg_cfg,
			    bool term_int,
			    u32 data_width,
			    bool is_device)
{
	int num_elems;

	if (psize == STEDMA40_PSIZE_PHY_1)
		num_elems = 1;
	else
		num_elems = 2 << psize;

	/* Must be aligned */
	if (!IS_ALIGNED(data, 0x1 << data_width))
		return -EINVAL;

	/* Transfer size can't be smaller than (num_elms * elem_size) */
	if (data_size < num_elems * (0x1 << data_width))
		return -EINVAL;

	/* The number of elements. IE now many chunks */
	lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;

	/*
	 * Distance to next element sized entry.
	 * Usually the size of the element unless you want gaps.
	 */
	if (!is_device)
		lli->reg_elt |= (0x1 << data_width) <<
			D40_SREG_ELEM_PHY_EIDX_POS;

	/* Where the data is */
	lli->reg_ptr = data;
	lli->reg_cfg = reg_cfg;

	/* If this scatter list entry is the last one, no next link */
	if (next_lli == 0)
		lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
	else
		lli->reg_lnk = next_lli;

	/* Set/clear interrupt generation on this link item.*/
	if (term_int)
		lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
	else
		lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);

	/* Post link */
	lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;

	return 0;
}

static int d40_seg_size(int size, int data_width1, int data_width2)
{
	u32 max_w = max(data_width1, data_width2);
	u32 min_w = min(data_width1, data_width2);
	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);

	if (seg_max > STEDMA40_MAX_SEG_SIZE)
		seg_max -= (1 << max_w);

	if (size <= seg_max)
		return size;

	if (size <= 2 * seg_max)
		return ALIGN(size / 2, 1 << max_w);

	return seg_max;
}

struct d40_phy_lli *d40_phy_buf_to_lli(struct d40_phy_lli *lli,
				       dma_addr_t addr,
				       u32 size,
				       int psize,
				       dma_addr_t lli_phys,
				       u32 reg_cfg,
				       bool term_int,
				       u32 data_width1,
				       u32 data_width2,
				       bool is_device)
{
	int err;
	dma_addr_t next = lli_phys;
	int size_rest = size;
	int size_seg = 0;

	do {
		size_seg = d40_seg_size(size_rest, data_width1, data_width2);
		size_rest -= size_seg;

		if (term_int && size_rest == 0)
			next = 0;
		else
			next = ALIGN(next + sizeof(struct d40_phy_lli),
				     D40_LLI_ALIGN);

		err = d40_phy_fill_lli(lli,
				       addr,
				       size_seg,
				       psize,
				       next,
				       reg_cfg,
				       !next,
				       data_width1,
				       is_device);

		if (err)
			goto err;

		lli++;
		if (!is_device)
			addr += size_seg;
	} while (size_rest);

	return lli;

 err:
	return NULL;
}

int d40_phy_sg_to_lli(struct scatterlist *sg,
		      int sg_len,
		      dma_addr_t target,
		      struct d40_phy_lli *lli_sg,
		      dma_addr_t lli_phys,
		      u32 reg_cfg,
		      u32 data_width1,
		      u32 data_width2,
		      int psize)
{
	int total_size = 0;
	int i;
	struct scatterlist *current_sg = sg;
	dma_addr_t dst;
	struct d40_phy_lli *lli = lli_sg;
	dma_addr_t l_phys = lli_phys;

	for_each_sg(sg, current_sg, sg_len, i) {

		total_size += sg_dma_len(current_sg);

		if (target)
			dst = target;
		else
			dst = sg_phys(current_sg);

		l_phys = ALIGN(lli_phys + (lli - lli_sg) *
			       sizeof(struct d40_phy_lli), D40_LLI_ALIGN);

		lli = d40_phy_buf_to_lli(lli,
					 dst,
					 sg_dma_len(current_sg),
					 psize,
					 l_phys,
					 reg_cfg,
					 sg_len - 1 == i,
					 data_width1,
					 data_width2,
					 target == dst);
		if (lli == NULL)
			return -EINVAL;
	}

	return total_size;
}


void d40_phy_lli_write(void __iomem *virtbase,
		       u32 phy_chan_num,
		       struct d40_phy_lli *lli_dst,
		       struct d40_phy_lli *lli_src)
{

	writel(lli_src->reg_cfg, virtbase + D40_DREG_PCBASE +
	       phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSCFG);
	writel(lli_src->reg_elt, virtbase + D40_DREG_PCBASE +
	       phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSELT);
	writel(lli_src->reg_ptr, virtbase + D40_DREG_PCBASE +
	       phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSPTR);
	writel(lli_src->reg_lnk, virtbase + D40_DREG_PCBASE +
	       phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSLNK);

	writel(lli_dst->reg_cfg, virtbase + D40_DREG_PCBASE +
	       phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDCFG);
	writel(lli_dst->reg_elt, virtbase + D40_DREG_PCBASE +
	       phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDELT);
	writel(lli_dst->reg_ptr, virtbase + D40_DREG_PCBASE +
	       phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDPTR);
	writel(lli_dst->reg_lnk, virtbase + D40_DREG_PCBASE +
	       phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDLNK);

}

/* DMA logical lli operations */

static void d40_log_lli_link(struct d40_log_lli *lli_dst,
			     struct d40_log_lli *lli_src,
			     int next)
{
	u32 slos = 0;
	u32 dlos = 0;

	if (next != -EINVAL) {
		slos = next * 2;
		dlos = next * 2 + 1;
	} else {
		lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
		lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
	}

	lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
		(slos << D40_MEM_LCSP1_SLOS_POS);

	lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
		(dlos << D40_MEM_LCSP1_SLOS_POS);
}

void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
			   struct d40_log_lli *lli_dst,
			   struct d40_log_lli *lli_src,
			   int next)
{
	d40_log_lli_link(lli_dst, lli_src, next);

	writel(lli_src->lcsp02, &lcpa[0].lcsp0);
	writel(lli_src->lcsp13, &lcpa[0].lcsp1);
	writel(lli_dst->lcsp02, &lcpa[0].lcsp2);
	writel(lli_dst->lcsp13, &lcpa[0].lcsp3);
}

void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
			   struct d40_log_lli *lli_dst,
			   struct d40_log_lli *lli_src,
			   int next)
{
	d40_log_lli_link(lli_dst, lli_src, next);

	writel(lli_src->lcsp02, &lcla[0].lcsp02);
	writel(lli_src->lcsp13, &lcla[0].lcsp13);
	writel(lli_dst->lcsp02, &lcla[1].lcsp02);
	writel(lli_dst->lcsp13, &lcla[1].lcsp13);
}

static void d40_log_fill_lli(struct d40_log_lli *lli,
			     dma_addr_t data, u32 data_size,
			     u32 reg_cfg,
			     u32 data_width,
			     bool addr_inc)
{
	lli->lcsp13 = reg_cfg;

	/* The number of elements to transfer */
	lli->lcsp02 = ((data_size >> data_width) <<
		       D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;

	BUG_ON((data_size >> data_width) > STEDMA40_MAX_SEG_SIZE);

	/* 16 LSBs address of the current element */
	lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
	/* 16 MSBs address of the current element */
	lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;

	if (addr_inc)
		lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;

}

int d40_log_sg_to_dev(struct scatterlist *sg,
		      int sg_len,
		      struct d40_log_lli_bidir *lli,
		      struct d40_def_lcsp *lcsp,
		      u32 src_data_width,
		      u32 dst_data_width,
		      enum dma_data_direction direction,
		      dma_addr_t dev_addr)
{
	int total_size = 0;
	struct scatterlist *current_sg = sg;
	int i;
	struct d40_log_lli *lli_src = lli->src;
	struct d40_log_lli *lli_dst = lli->dst;

	for_each_sg(sg, current_sg, sg_len, i) {
		total_size += sg_dma_len(current_sg);

		if (direction == DMA_TO_DEVICE) {
			lli_src =
				d40_log_buf_to_lli(lli_src,
						   sg_phys(current_sg),
						   sg_dma_len(current_sg),
						   lcsp->lcsp1, src_data_width,
						   dst_data_width,
						   true);
			lli_dst =
				d40_log_buf_to_lli(lli_dst,
						   dev_addr,
						   sg_dma_len(current_sg),
						   lcsp->lcsp3, dst_data_width,
						   src_data_width,
						   false);
		} else {
			lli_dst =
				d40_log_buf_to_lli(lli_dst,
						   sg_phys(current_sg),
						   sg_dma_len(current_sg),
						   lcsp->lcsp3, dst_data_width,
						   src_data_width,
						   true);
			lli_src =
				d40_log_buf_to_lli(lli_src,
						   dev_addr,
						   sg_dma_len(current_sg),
						   lcsp->lcsp1, src_data_width,
						   dst_data_width,
						   false);
		}
	}
	return total_size;
}

struct d40_log_lli *d40_log_buf_to_lli(struct d40_log_lli *lli_sg,
				       dma_addr_t addr,
				       int size,
				       u32 lcsp13, /* src or dst*/
				       u32 data_width1,
				       u32 data_width2,
				       bool addr_inc)
{
	struct d40_log_lli *lli = lli_sg;
	int size_rest = size;
	int size_seg = 0;

	do {
		size_seg = d40_seg_size(size_rest, data_width1, data_width2);
		size_rest -= size_seg;

		d40_log_fill_lli(lli,
				 addr,
				 size_seg,
				 lcsp13, data_width1,
				 addr_inc);
		if (addr_inc)
			addr += size_seg;
		lli++;
	} while (size_rest);

	return lli;
}

int d40_log_sg_to_lli(struct scatterlist *sg,
		      int sg_len,
		      struct d40_log_lli *lli_sg,
		      u32 lcsp13, /* src or dst*/
		      u32 data_width1, u32 data_width2)
{
	int total_size = 0;
	struct scatterlist *current_sg = sg;
	int i;
	struct d40_log_lli *lli = lli_sg;

	for_each_sg(sg, current_sg, sg_len, i) {
		total_size += sg_dma_len(current_sg);
		lli = d40_log_buf_to_lli(lli,
					 sg_phys(current_sg),
					 sg_dma_len(current_sg),
					 lcsp13,
					 data_width1, data_width2, true);
	}
	return total_size;
}
Commit	Line	Data
8d318a50	1	/*
767a9675	2	* Copyright (C) ST-Ericsson SA 2007-2010
d49278e3	3	* Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675	4	* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50	5	* License terms: GNU General Public License (GPL) version 2
8d318a50 LW	6	*/
	7
	8	#include <linux/kernel.h>
	9	#include <plat/ste_dma40.h>
	10
	11	#include "ste_dma40_ll.h"
	12
	13	/* Sets up proper LCSP1 and LCSP3 register for a logical channel */
	14	void d40_log_cfg(struct stedma40_chan_cfg *cfg,
	15	u32 lcsp1, u32 lcsp3)
	16	{
	17	u32 l3 = 0; /* dst */
	18	u32 l1 = 0; /* src */
	19
	20	/* src is mem? -> increase address pos */
	21	if (cfg->dir == STEDMA40_MEM_TO_PERIPH \|\|
	22	cfg->dir == STEDMA40_MEM_TO_MEM)
	23	l1 \|= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
	24
	25	/* dst is mem? -> increase address pos */
	26	if (cfg->dir == STEDMA40_PERIPH_TO_MEM \|\|
	27	cfg->dir == STEDMA40_MEM_TO_MEM)
	28	l3 \|= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
	29
	30	/* src is hw? -> master port 1 */
	31	if (cfg->dir == STEDMA40_PERIPH_TO_MEM \|\|
	32	cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
	33	l1 \|= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
	34
	35	/* dst is hw? -> master port 1 */
	36	if (cfg->dir == STEDMA40_MEM_TO_PERIPH \|\|
	37	cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
	38	l3 \|= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
	39
8d318a50 LW	40	l3 \|= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
	41	l3 \|= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
	42	l3 \|= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
8d318a50 LW	43
	44	l1 \|= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
	45	l1 \|= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
	46	l1 \|= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
8d318a50 LW	47
	48	*lcsp1 = l1;
	49	*lcsp3 = l3;
	50
	51	}
	52
	53	/* Sets up SRC and DST CFG register for both logical and physical channels */
	54	void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
	55	u32 src_cfg, u32 dst_cfg, bool is_log)
	56	{
	57	u32 src = 0;
	58	u32 dst = 0;
	59
	60	if (!is_log) {
	61	/* Physical channel */
	62	if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) \|\|
	63	(cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
	64	/* Set master port to 1 */
	65	src \|= 1 << D40_SREG_CFG_MST_POS;
	66	src \|= D40_TYPE_TO_EVENT(cfg->src_dev_type);
	67
	68	if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
	69	src \|= 1 << D40_SREG_CFG_PHY_TM_POS;
	70	else
	71	src \|= 3 << D40_SREG_CFG_PHY_TM_POS;
	72	}
	73	if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) \|\|
	74	(cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
	75	/* Set master port to 1 */
	76	dst \|= 1 << D40_SREG_CFG_MST_POS;
	77	dst \|= D40_TYPE_TO_EVENT(cfg->dst_dev_type);
	78
	79	if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
	80	dst \|= 1 << D40_SREG_CFG_PHY_TM_POS;
	81	else
	82	dst \|= 3 << D40_SREG_CFG_PHY_TM_POS;
	83	}
	84	/* Interrupt on end of transfer for destination */
	85	dst \|= 1 << D40_SREG_CFG_TIM_POS;
	86
	87	/* Generate interrupt on error */
	88	src \|= 1 << D40_SREG_CFG_EIM_POS;
	89	dst \|= 1 << D40_SREG_CFG_EIM_POS;
	90
	91	/* PSIZE */
	92	if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
	93	src \|= 1 << D40_SREG_CFG_PHY_PEN_POS;
	94	src \|= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
	95	}
	96	if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
	97	dst \|= 1 << D40_SREG_CFG_PHY_PEN_POS;
	98	dst \|= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
	99	}
	100
	101	/* Element size */
	102	src \|= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
	103	dst \|= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
	104
	105	} else {
	106	/* Logical channel */
	107	dst \|= 1 << D40_SREG_CFG_LOG_GIM_POS;
	108	src \|= 1 << D40_SREG_CFG_LOG_GIM_POS;
	109	}
	110
730c1871	111	if (cfg->high_priority) {
8d318a50 LW	112	src \|= 1 << D40_SREG_CFG_PRI_POS;
	113	dst \|= 1 << D40_SREG_CFG_PRI_POS;
	114	}
	115
51f5d744 RV	116	if (cfg->src_info.big_endian)
	117	src \|= 1 << D40_SREG_CFG_LBE_POS;
	118	if (cfg->dst_info.big_endian)
	119	dst \|= 1 << D40_SREG_CFG_LBE_POS;
8d318a50 LW	120
	121	*src_cfg = src;
	122	*dst_cfg = dst;
	123	}
	124
d49278e3 PF	125	static int d40_phy_fill_lli(struct d40_phy_lli *lli,
	126	dma_addr_t data,
	127	u32 data_size,
	128	int psize,
	129	dma_addr_t next_lli,
	130	u32 reg_cfg,
	131	bool term_int,
	132	u32 data_width,
	133	bool is_device)
8d318a50 LW	134	{
	135	int num_elems;
	136
	137	if (psize == STEDMA40_PSIZE_PHY_1)
	138	num_elems = 1;
	139	else
	140	num_elems = 2 << psize;
	141
8d318a50 LW	142	/* Must be aligned */
	143	if (!IS_ALIGNED(data, 0x1 << data_width))
	144	return -EINVAL;
	145
	146	/* Transfer size can't be smaller than (num_elms * elem_size) */
	147	if (data_size < num_elems * (0x1 << data_width))
	148	return -EINVAL;
	149
	150	/* The number of elements. IE now many chunks */
	151	lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
	152
	153	/*
	154	* Distance to next element sized entry.
	155	* Usually the size of the element unless you want gaps.
	156	*/
	157	if (!is_device)
	158	lli->reg_elt \|= (0x1 << data_width) <<
	159	D40_SREG_ELEM_PHY_EIDX_POS;
	160
	161	/* Where the data is */
	162	lli->reg_ptr = data;
	163	lli->reg_cfg = reg_cfg;
	164
	165	/* If this scatter list entry is the last one, no next link */
	166	if (next_lli == 0)
	167	lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
	168	else
	169	lli->reg_lnk = next_lli;
	170
	171	/* Set/clear interrupt generation on this link item.*/
	172	if (term_int)
	173	lli->reg_cfg \|= 0x1 << D40_SREG_CFG_TIM_POS;
	174	else
	175	lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
	176
	177	/* Post link */
	178	lli->reg_lnk \|= 0 << D40_SREG_LNK_PHY_PRE_POS;
	179
	180	return 0;
	181	}
	182
d49278e3 PF	183	static int d40_seg_size(int size, int data_width1, int data_width2)
	184	{
	185	u32 max_w = max(data_width1, data_width2);
	186	u32 min_w = min(data_width1, data_width2);
	187	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
	188
	189	if (seg_max > STEDMA40_MAX_SEG_SIZE)
	190	seg_max -= (1 << max_w);
	191
	192	if (size <= seg_max)
	193	return size;
	194
	195	if (size <= 2 * seg_max)
	196	return ALIGN(size / 2, 1 << max_w);
	197
	198	return seg_max;
	199	}
	200
	201	struct d40_phy_lli d40_phy_buf_to_lli(struct d40_phy_lli lli,
	202	dma_addr_t addr,
	203	u32 size,
	204	int psize,
	205	dma_addr_t lli_phys,
	206	u32 reg_cfg,
	207	bool term_int,
	208	u32 data_width1,
	209	u32 data_width2,
	210	bool is_device)
	211	{
	212	int err;
	213	dma_addr_t next = lli_phys;
	214	int size_rest = size;
	215	int size_seg = 0;
	216
	217	do {
	218	size_seg = d40_seg_size(size_rest, data_width1, data_width2);
	219	size_rest -= size_seg;
	220
	221	if (term_int && size_rest == 0)
	222	next = 0;
	223	else
	224	next = ALIGN(next + sizeof(struct d40_phy_lli),
	225	D40_LLI_ALIGN);
	226
	227	err = d40_phy_fill_lli(lli,
	228	addr,
	229	size_seg,
	230	psize,
	231	next,
	232	reg_cfg,
	233	!next,
	234	data_width1,
	235	is_device);
	236
	237	if (err)
	238	goto err;
	239
	240	lli++;
	241	if (!is_device)
	242	addr += size_seg;
	243	} while (size_rest);
	244
	245	return lli;
	246
247	err:
248	return NULL;
249	}
250
8d318a50 LW	251	int d40_phy_sg_to_lli(struct scatterlist *sg,
	252	int sg_len,
	253	dma_addr_t target,
d49278e3	254	struct d40_phy_lli *lli_sg,
8d318a50 LW	255	dma_addr_t lli_phys,
8d318a50 LW	256	u32 reg_cfg,
d49278e3 PF	257	u32 data_width1,
d49278e3 PF	258	u32 data_width2,
0246e77b	259	int psize)
8d318a50 LW	260	{
	261	int total_size = 0;
	262	int i;
	263	struct scatterlist *current_sg = sg;
8d318a50	264	dma_addr_t dst;
d49278e3 PF	265	struct d40_phy_lli *lli = lli_sg;
d49278e3 PF	266	dma_addr_t l_phys = lli_phys;
8d318a50 LW	267
	268	for_each_sg(sg, current_sg, sg_len, i) {
	269
	270	total_size += sg_dma_len(current_sg);
	271
8d318a50 LW	272	if (target)
	273	dst = target;
	274	else
	275	dst = sg_phys(current_sg);
	276
d49278e3 PF	277	l_phys = ALIGN(lli_phys + (lli - lli_sg) *
	278	sizeof(struct d40_phy_lli), D40_LLI_ALIGN);
	279
	280	lli = d40_phy_buf_to_lli(lli,
	281	dst,
	282	sg_dma_len(current_sg),
	283	psize,
	284	l_phys,
	285	reg_cfg,
	286	sg_len - 1 == i,
	287	data_width1,
	288	data_width2,
	289	target == dst);
	290	if (lli == NULL)
	291	return -EINVAL;
8d318a50 LW	292	}
	293
	294	return total_size;
8d318a50 LW	295	}
	296
	297
	298	void d40_phy_lli_write(void __iomem *virtbase,
	299	u32 phy_chan_num,
	300	struct d40_phy_lli *lli_dst,
	301	struct d40_phy_lli *lli_src)
	302	{
	303
	304	writel(lli_src->reg_cfg, virtbase + D40_DREG_PCBASE +
	305	phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSCFG);
	306	writel(lli_src->reg_elt, virtbase + D40_DREG_PCBASE +
	307	phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSELT);
	308	writel(lli_src->reg_ptr, virtbase + D40_DREG_PCBASE +
	309	phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSPTR);
	310	writel(lli_src->reg_lnk, virtbase + D40_DREG_PCBASE +
	311	phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SSLNK);
	312
	313	writel(lli_dst->reg_cfg, virtbase + D40_DREG_PCBASE +
	314	phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDCFG);
	315	writel(lli_dst->reg_elt, virtbase + D40_DREG_PCBASE +
	316	phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDELT);
	317	writel(lli_dst->reg_ptr, virtbase + D40_DREG_PCBASE +
	318	phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDPTR);
	319	writel(lli_dst->reg_lnk, virtbase + D40_DREG_PCBASE +
	320	phy_chan_num * D40_DREG_PCDELTA + D40_CHAN_REG_SDLNK);
	321
	322	}
	323
	324	/* DMA logical lli operations */
	325
698e4732 JA	326	static void d40_log_lli_link(struct d40_log_lli *lli_dst,
	327	struct d40_log_lli *lli_src,
	328	int next)
	329	{
	330	u32 slos = 0;
	331	u32 dlos = 0;
	332
	333	if (next != -EINVAL) {
	334	slos = next * 2;
	335	dlos = next * 2 + 1;
	336	} else {
	337	lli_dst->lcsp13 \|= D40_MEM_LCSP1_SCFG_TIM_MASK;
	338	lli_dst->lcsp13 \|= D40_MEM_LCSP3_DTCP_MASK;
	339	}
	340
	341	lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) \|
	342	(slos << D40_MEM_LCSP1_SLOS_POS);
	343
	344	lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) \|
	345	(dlos << D40_MEM_LCSP1_SLOS_POS);
	346	}
	347
	348	void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
	349	struct d40_log_lli *lli_dst,
	350	struct d40_log_lli *lli_src,
	351	int next)
	352	{
	353	d40_log_lli_link(lli_dst, lli_src, next);
	354
	355	writel(lli_src->lcsp02, &lcpa[0].lcsp0);
	356	writel(lli_src->lcsp13, &lcpa[0].lcsp1);
	357	writel(lli_dst->lcsp02, &lcpa[0].lcsp2);
	358	writel(lli_dst->lcsp13, &lcpa[0].lcsp3);
	359	}
	360
	361	void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
	362	struct d40_log_lli *lli_dst,
	363	struct d40_log_lli *lli_src,
	364	int next)
	365	{
	366	d40_log_lli_link(lli_dst, lli_src, next);
	367
	368	writel(lli_src->lcsp02, &lcla[0].lcsp02);
	369	writel(lli_src->lcsp13, &lcla[0].lcsp13);
	370	writel(lli_dst->lcsp02, &lcla[1].lcsp02);
	371	writel(lli_dst->lcsp13, &lcla[1].lcsp13);
	372	}
	373
d49278e3 PF	374	static void d40_log_fill_lli(struct d40_log_lli *lli,
	375	dma_addr_t data, u32 data_size,
	376	u32 reg_cfg,
	377	u32 data_width,
	378	bool addr_inc)
8d318a50 LW	379	{
	380	lli->lcsp13 = reg_cfg;
	381
	382	/* The number of elements to transfer */
	383	lli->lcsp02 = ((data_size >> data_width) <<
	384	D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
d49278e3 PF	385
	386	BUG_ON((data_size >> data_width) > STEDMA40_MAX_SEG_SIZE);
	387
8d318a50 LW	388	/* 16 LSBs address of the current element */
	389	lli->lcsp02 \|= data & D40_MEM_LCSP0_SPTR_MASK;
	390	/* 16 MSBs address of the current element */
	391	lli->lcsp13 \|= data & D40_MEM_LCSP1_SPTR_MASK;
	392
	393	if (addr_inc)
	394	lli->lcsp13 \|= D40_MEM_LCSP1_SCFG_INCR_MASK;
	395
8d318a50 LW	396	}
8d318a50 LW	397
698e4732	398	int d40_log_sg_to_dev(struct scatterlist *sg,
8d318a50 LW	399	int sg_len,
	400	struct d40_log_lli_bidir *lli,
	401	struct d40_def_lcsp *lcsp,
	402	u32 src_data_width,
	403	u32 dst_data_width,
	404	enum dma_data_direction direction,
698e4732	405	dma_addr_t dev_addr)
8d318a50 LW	406	{
	407	int total_size = 0;
	408	struct scatterlist *current_sg = sg;
	409	int i;
d49278e3 PF	410	struct d40_log_lli *lli_src = lli->src;
d49278e3 PF	411	struct d40_log_lli *lli_dst = lli->dst;
8d318a50 LW	412
	413	for_each_sg(sg, current_sg, sg_len, i) {
	414	total_size += sg_dma_len(current_sg);
	415
8d318a50	416	if (direction == DMA_TO_DEVICE) {
d49278e3 PF	417	lli_src =
	418	d40_log_buf_to_lli(lli_src,
	419	sg_phys(current_sg),
	420	sg_dma_len(current_sg),
	421	lcsp->lcsp1, src_data_width,
	422	dst_data_width,
	423	true);
	424	lli_dst =
	425	d40_log_buf_to_lli(lli_dst,
	426	dev_addr,
	427	sg_dma_len(current_sg),
	428	lcsp->lcsp3, dst_data_width,
	429	src_data_width,
	430	false);
8d318a50	431	} else {
d49278e3 PF	432	lli_dst =
	433	d40_log_buf_to_lli(lli_dst,
	434	sg_phys(current_sg),
	435	sg_dma_len(current_sg),
	436	lcsp->lcsp3, dst_data_width,
	437	src_data_width,
	438	true);
	439	lli_src =
	440	d40_log_buf_to_lli(lli_src,
	441	dev_addr,
	442	sg_dma_len(current_sg),
	443	lcsp->lcsp1, src_data_width,
	444	dst_data_width,
	445	false);
8d318a50 LW	446	}
	447	}
	448	return total_size;
	449	}
	450
d49278e3 PF	451	struct d40_log_lli d40_log_buf_to_lli(struct d40_log_lli lli_sg,
	452	dma_addr_t addr,
	453	int size,
	454	u32 lcsp13, /* src or dst*/
	455	u32 data_width1,
	456	u32 data_width2,
	457	bool addr_inc)
	458	{
	459	struct d40_log_lli *lli = lli_sg;
	460	int size_rest = size;
	461	int size_seg = 0;
	462
	463	do {
	464	size_seg = d40_seg_size(size_rest, data_width1, data_width2);
	465	size_rest -= size_seg;
	466
	467	d40_log_fill_lli(lli,
	468	addr,
	469	size_seg,
	470	lcsp13, data_width1,
	471	addr_inc);
	472	if (addr_inc)
	473	addr += size_seg;
	474	lli++;
	475	} while (size_rest);
	476
	477	return lli;
	478	}
	479
698e4732	480	int d40_log_sg_to_lli(struct scatterlist *sg,
8d318a50 LW	481	int sg_len,
	482	struct d40_log_lli *lli_sg,
	483	u32 lcsp13, /* src or dst*/
d49278e3	484	u32 data_width1, u32 data_width2)
8d318a50 LW	485	{
	486	int total_size = 0;
	487	struct scatterlist *current_sg = sg;
	488	int i;
d49278e3	489	struct d40_log_lli *lli = lli_sg;
8d318a50 LW	490
	491	for_each_sg(sg, current_sg, sg_len, i) {
	492	total_size += sg_dma_len(current_sg);
d49278e3 PF	493	lli = d40_log_buf_to_lli(lli,
	494	sg_phys(current_sg),
	495	sg_dma_len(current_sg),
	496	lcsp13,
	497	data_width1, data_width2, true);
8d318a50 LW	498	}
	499	return total_size;
	500	}