[deliverable/linux.git] / drivers / dma / ste_dma40_ll.c

/*
 * Copyright (C) ST-Ericsson SA 2007-2010
 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
 * License terms: GNU General Public License (GPL) version 2
 */

#include <linux/kernel.h>
#include <linux/platform_data/dma-ste-dma40.h>

#include "ste_dma40_ll.h"

/* Sets up proper LCSP1 and LCSP3 register for a logical channel */
void d40_log_cfg(struct stedma40_chan_cfg *cfg,
		 u32 *lcsp1, u32 *lcsp3)
{
	u32 l3 = 0; /* dst */
	u32 l1 = 0; /* src */

	/* src is mem? -> increase address pos */
	if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
	    cfg->dir ==  STEDMA40_MEM_TO_MEM)
		l1 |= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;

	/* dst is mem? -> increase address pos */
	if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
	    cfg->dir ==  STEDMA40_MEM_TO_MEM)
		l3 |= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;

	/* src is hw? -> master port 1 */
	if (cfg->dir ==  STEDMA40_PERIPH_TO_MEM ||
	    cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
		l1 |= 1 << D40_MEM_LCSP1_SCFG_MST_POS;

	/* dst is hw? -> master port 1 */
	if (cfg->dir ==  STEDMA40_MEM_TO_PERIPH ||
	    cfg->dir ==  STEDMA40_PERIPH_TO_PERIPH)
		l3 |= 1 << D40_MEM_LCSP3_DCFG_MST_POS;

	l3 |= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
	l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
	l3 |= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;

	l1 |= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
	l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
	l1 |= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;

	*lcsp1 = l1;
	*lcsp3 = l3;

}

/* Sets up SRC and DST CFG register for both logical and physical channels */
void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
		 u32 *src_cfg, u32 *dst_cfg, bool is_log)
{
	u32 src = 0;
	u32 dst = 0;

	if (!is_log) {
		/* Physical channel */
		if ((cfg->dir ==  STEDMA40_PERIPH_TO_MEM) ||
		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
			/* Set master port to 1 */
			src |= 1 << D40_SREG_CFG_MST_POS;
			src |= D40_TYPE_TO_EVENT(cfg->dev_type);

			if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
				src |= 1 << D40_SREG_CFG_PHY_TM_POS;
			else
				src |= 3 << D40_SREG_CFG_PHY_TM_POS;
		}
		if ((cfg->dir ==  STEDMA40_MEM_TO_PERIPH) ||
		    (cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
			/* Set master port to 1 */
			dst |= 1 << D40_SREG_CFG_MST_POS;
			dst |= D40_TYPE_TO_EVENT(cfg->dev_type);

			if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
				dst |= 1 << D40_SREG_CFG_PHY_TM_POS;
			else
				dst |= 3 << D40_SREG_CFG_PHY_TM_POS;
		}
		/* Interrupt on end of transfer for destination */
		dst |= 1 << D40_SREG_CFG_TIM_POS;

		/* Generate interrupt on error */
		src |= 1 << D40_SREG_CFG_EIM_POS;
		dst |= 1 << D40_SREG_CFG_EIM_POS;

		/* PSIZE */
		if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
			src |= 1 << D40_SREG_CFG_PHY_PEN_POS;
			src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
		}
		if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
			dst |= 1 << D40_SREG_CFG_PHY_PEN_POS;
			dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
		}

		/* Element size */
		src |= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
		dst |= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;

		/* Set the priority bit to high for the physical channel */
		if (cfg->high_priority) {
			src |= 1 << D40_SREG_CFG_PRI_POS;
			dst |= 1 << D40_SREG_CFG_PRI_POS;
		}
	}

	if (cfg->src_info.big_endian)
		src |= 1 << D40_SREG_CFG_LBE_POS;
	if (cfg->dst_info.big_endian)
		dst |= 1 << D40_SREG_CFG_LBE_POS;

	*src_cfg = src;
	*dst_cfg = dst;
}

static int d40_phy_fill_lli(struct d40_phy_lli *lli,
			    dma_addr_t data,
			    u32 data_size,
			    dma_addr_t next_lli,
			    u32 reg_cfg,
			    struct stedma40_half_channel_info *info,
			    unsigned int flags)
{
	bool addr_inc = flags & LLI_ADDR_INC;
	bool term_int = flags & LLI_TERM_INT;
	unsigned int data_width = info->data_width;
	int psize = info->psize;
	int num_elems;

	if (psize == STEDMA40_PSIZE_PHY_1)
		num_elems = 1;
	else
		num_elems = 2 << psize;

	/* Must be aligned */
	if (!IS_ALIGNED(data, 0x1 << data_width))
		return -EINVAL;

	/* Transfer size can't be smaller than (num_elms * elem_size) */
	if (data_size < num_elems * (0x1 << data_width))
		return -EINVAL;

	/* The number of elements. IE now many chunks */
	lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;

	/*
	 * Distance to next element sized entry.
	 * Usually the size of the element unless you want gaps.
	 */
	if (addr_inc)
		lli->reg_elt |= (0x1 << data_width) <<
			D40_SREG_ELEM_PHY_EIDX_POS;

	/* Where the data is */
	lli->reg_ptr = data;
	lli->reg_cfg = reg_cfg;

	/* If this scatter list entry is the last one, no next link */
	if (next_lli == 0)
		lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
	else
		lli->reg_lnk = next_lli;

	/* Set/clear interrupt generation on this link item.*/
	if (term_int)
		lli->reg_cfg |= 0x1 << D40_SREG_CFG_TIM_POS;
	else
		lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);

	/* Post link */
	lli->reg_lnk |= 0 << D40_SREG_LNK_PHY_PRE_POS;

	return 0;
}

static int d40_seg_size(int size, int data_width1, int data_width2)
{
	u32 max_w = max(data_width1, data_width2);
	u32 min_w = min(data_width1, data_width2);
	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);

	if (seg_max > STEDMA40_MAX_SEG_SIZE)
		seg_max -= (1 << max_w);

	if (size <= seg_max)
		return size;

	if (size <= 2 * seg_max)
		return ALIGN(size / 2, 1 << max_w);

	return seg_max;
}

static struct d40_phy_lli *
d40_phy_buf_to_lli(struct d40_phy_lli *lli, dma_addr_t addr, u32 size,
		   dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,
		   struct stedma40_half_channel_info *info,
		   struct stedma40_half_channel_info *otherinfo,
		   unsigned long flags)
{
	bool lastlink = flags & LLI_LAST_LINK;
	bool addr_inc = flags & LLI_ADDR_INC;
	bool term_int = flags & LLI_TERM_INT;
	bool cyclic = flags & LLI_CYCLIC;
	int err;
	dma_addr_t next = lli_phys;
	int size_rest = size;
	int size_seg = 0;

	/*
	 * This piece may be split up based on d40_seg_size(); we only want the
	 * term int on the last part.
	 */
	if (term_int)
		flags &= ~LLI_TERM_INT;

	do {
		size_seg = d40_seg_size(size_rest, info->data_width,
					otherinfo->data_width);
		size_rest -= size_seg;

		if (size_rest == 0 && term_int)
			flags |= LLI_TERM_INT;

		if (size_rest == 0 && lastlink)
			next = cyclic ? first_phys : 0;
		else
			next = ALIGN(next + sizeof(struct d40_phy_lli),
				     D40_LLI_ALIGN);

		err = d40_phy_fill_lli(lli, addr, size_seg, next,
				       reg_cfg, info, flags);

		if (err)
			goto err;

		lli++;
		if (addr_inc)
			addr += size_seg;
	} while (size_rest);

	return lli;

err:
	return NULL;
}

int d40_phy_sg_to_lli(struct scatterlist *sg,
		      int sg_len,
		      dma_addr_t target,
		      struct d40_phy_lli *lli_sg,
		      dma_addr_t lli_phys,
		      u32 reg_cfg,
		      struct stedma40_half_channel_info *info,
		      struct stedma40_half_channel_info *otherinfo,
		      unsigned long flags)
{
	int total_size = 0;
	int i;
	struct scatterlist *current_sg = sg;
	struct d40_phy_lli *lli = lli_sg;
	dma_addr_t l_phys = lli_phys;

	if (!target)
		flags |= LLI_ADDR_INC;

	for_each_sg(sg, current_sg, sg_len, i) {
		dma_addr_t sg_addr = sg_dma_address(current_sg);
		unsigned int len = sg_dma_len(current_sg);
		dma_addr_t dst = target ?: sg_addr;

		total_size += sg_dma_len(current_sg);

		if (i == sg_len - 1)
			flags |= LLI_TERM_INT | LLI_LAST_LINK;

		l_phys = ALIGN(lli_phys + (lli - lli_sg) *
			       sizeof(struct d40_phy_lli), D40_LLI_ALIGN);

		lli = d40_phy_buf_to_lli(lli, dst, len, l_phys, lli_phys,
					 reg_cfg, info, otherinfo, flags);

		if (lli == NULL)
			return -EINVAL;
	}

	return total_size;
}


/* DMA logical lli operations */

static void d40_log_lli_link(struct d40_log_lli *lli_dst,
			     struct d40_log_lli *lli_src,
			     int next, unsigned int flags)
{
	bool interrupt = flags & LLI_TERM_INT;
	u32 slos = 0;
	u32 dlos = 0;

	if (next != -EINVAL) {
		slos = next * 2;
		dlos = next * 2 + 1;
	}

	if (interrupt) {
		lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;
		lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;
	}

	lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
		(slos << D40_MEM_LCSP1_SLOS_POS);

	lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |
		(dlos << D40_MEM_LCSP1_SLOS_POS);
}

void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
			   struct d40_log_lli *lli_dst,
			   struct d40_log_lli *lli_src,
			   int next, unsigned int flags)
{
	d40_log_lli_link(lli_dst, lli_src, next, flags);

	writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0);
	writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1);
	writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2);
	writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3);
}

void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
			   struct d40_log_lli *lli_dst,
			   struct d40_log_lli *lli_src,
			   int next, unsigned int flags)
{
	d40_log_lli_link(lli_dst, lli_src, next, flags);

	writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02);
	writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13);
	writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02);
	writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13);
}

static void d40_log_fill_lli(struct d40_log_lli *lli,
			     dma_addr_t data, u32 data_size,
			     u32 reg_cfg,
			     u32 data_width,
			     unsigned int flags)
{
	bool addr_inc = flags & LLI_ADDR_INC;

	lli->lcsp13 = reg_cfg;

	/* The number of elements to transfer */
	lli->lcsp02 = ((data_size >> data_width) <<
		       D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;

	BUG_ON((data_size >> data_width) > STEDMA40_MAX_SEG_SIZE);

	/* 16 LSBs address of the current element */
	lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;
	/* 16 MSBs address of the current element */
	lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;

	if (addr_inc)
		lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;

}

static struct d40_log_lli *d40_log_buf_to_lli(struct d40_log_lli *lli_sg,
				       dma_addr_t addr,
				       int size,
				       u32 lcsp13, /* src or dst*/
				       u32 data_width1,
				       u32 data_width2,
				       unsigned int flags)
{
	bool addr_inc = flags & LLI_ADDR_INC;
	struct d40_log_lli *lli = lli_sg;
	int size_rest = size;
	int size_seg = 0;

	do {
		size_seg = d40_seg_size(size_rest, data_width1, data_width2);
		size_rest -= size_seg;

		d40_log_fill_lli(lli,
				 addr,
				 size_seg,
				 lcsp13, data_width1,
				 flags);
		if (addr_inc)
			addr += size_seg;
		lli++;
	} while (size_rest);

	return lli;
}

int d40_log_sg_to_lli(struct scatterlist *sg,
		      int sg_len,
		      dma_addr_t dev_addr,
		      struct d40_log_lli *lli_sg,
		      u32 lcsp13, /* src or dst*/
		      u32 data_width1, u32 data_width2)
{
	int total_size = 0;
	struct scatterlist *current_sg = sg;
	int i;
	struct d40_log_lli *lli = lli_sg;
	unsigned long flags = 0;

	if (!dev_addr)
		flags |= LLI_ADDR_INC;

	for_each_sg(sg, current_sg, sg_len, i) {
		dma_addr_t sg_addr = sg_dma_address(current_sg);
		unsigned int len = sg_dma_len(current_sg);
		dma_addr_t addr = dev_addr ?: sg_addr;

		total_size += sg_dma_len(current_sg);

		lli = d40_log_buf_to_lli(lli, addr, len,
					 lcsp13,
					 data_width1,
					 data_width2,
					 flags);
	}

	return total_size;
}
Commit	Line	Data
8d318a50	1	/*
767a9675	2	* Copyright (C) ST-Ericsson SA 2007-2010
d49278e3	3	* Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675	4	* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50	5	* License terms: GNU General Public License (GPL) version 2
8d318a50 LW	6	*/
	7
	8	#include <linux/kernel.h>
865fab60	9	#include <linux/platform_data/dma-ste-dma40.h>
8d318a50 LW	10
	11	#include "ste_dma40_ll.h"
	12
	13	/* Sets up proper LCSP1 and LCSP3 register for a logical channel */
	14	void d40_log_cfg(struct stedma40_chan_cfg *cfg,
	15	u32 lcsp1, u32 lcsp3)
	16	{
	17	u32 l3 = 0; /* dst */
	18	u32 l1 = 0; /* src */
	19
	20	/* src is mem? -> increase address pos */
	21	if (cfg->dir == STEDMA40_MEM_TO_PERIPH \|\|
	22	cfg->dir == STEDMA40_MEM_TO_MEM)
	23	l1 \|= 1 << D40_MEM_LCSP1_SCFG_INCR_POS;
	24
	25	/* dst is mem? -> increase address pos */
	26	if (cfg->dir == STEDMA40_PERIPH_TO_MEM \|\|
	27	cfg->dir == STEDMA40_MEM_TO_MEM)
	28	l3 \|= 1 << D40_MEM_LCSP3_DCFG_INCR_POS;
	29
	30	/* src is hw? -> master port 1 */
	31	if (cfg->dir == STEDMA40_PERIPH_TO_MEM \|\|
	32	cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
	33	l1 \|= 1 << D40_MEM_LCSP1_SCFG_MST_POS;
	34
	35	/* dst is hw? -> master port 1 */
	36	if (cfg->dir == STEDMA40_MEM_TO_PERIPH \|\|
	37	cfg->dir == STEDMA40_PERIPH_TO_PERIPH)
	38	l3 \|= 1 << D40_MEM_LCSP3_DCFG_MST_POS;
	39
8d318a50 LW	40	l3 \|= 1 << D40_MEM_LCSP3_DCFG_EIM_POS;
	41	l3 \|= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;
	42	l3 \|= cfg->dst_info.data_width << D40_MEM_LCSP3_DCFG_ESIZE_POS;
8d318a50 LW	43
	44	l1 \|= 1 << D40_MEM_LCSP1_SCFG_EIM_POS;
	45	l1 \|= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;
	46	l1 \|= cfg->src_info.data_width << D40_MEM_LCSP1_SCFG_ESIZE_POS;
8d318a50 LW	47
	48	*lcsp1 = l1;
	49	*lcsp3 = l3;
	50
	51	}
	52
	53	/* Sets up SRC and DST CFG register for both logical and physical channels */
	54	void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
	55	u32 src_cfg, u32 dst_cfg, bool is_log)
	56	{
	57	u32 src = 0;
	58	u32 dst = 0;
	59
	60	if (!is_log) {
	61	/* Physical channel */
	62	if ((cfg->dir == STEDMA40_PERIPH_TO_MEM) \|\|
	63	(cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
	64	/* Set master port to 1 */
	65	src \|= 1 << D40_SREG_CFG_MST_POS;
26955c07	66	src \|= D40_TYPE_TO_EVENT(cfg->dev_type);
8d318a50 LW	67
	68	if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
	69	src \|= 1 << D40_SREG_CFG_PHY_TM_POS;
	70	else
	71	src \|= 3 << D40_SREG_CFG_PHY_TM_POS;
	72	}
	73	if ((cfg->dir == STEDMA40_MEM_TO_PERIPH) \|\|
	74	(cfg->dir == STEDMA40_PERIPH_TO_PERIPH)) {
	75	/* Set master port to 1 */
	76	dst \|= 1 << D40_SREG_CFG_MST_POS;
26955c07	77	dst \|= D40_TYPE_TO_EVENT(cfg->dev_type);
8d318a50 LW	78
	79	if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)
	80	dst \|= 1 << D40_SREG_CFG_PHY_TM_POS;
	81	else
	82	dst \|= 3 << D40_SREG_CFG_PHY_TM_POS;
	83	}
	84	/* Interrupt on end of transfer for destination */
	85	dst \|= 1 << D40_SREG_CFG_TIM_POS;
	86
	87	/* Generate interrupt on error */
	88	src \|= 1 << D40_SREG_CFG_EIM_POS;
	89	dst \|= 1 << D40_SREG_CFG_EIM_POS;
	90
	91	/* PSIZE */
	92	if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {
	93	src \|= 1 << D40_SREG_CFG_PHY_PEN_POS;
	94	src \|= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;
	95	}
	96	if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {
	97	dst \|= 1 << D40_SREG_CFG_PHY_PEN_POS;
	98	dst \|= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;
	99	}
	100
	101	/* Element size */
	102	src \|= cfg->src_info.data_width << D40_SREG_CFG_ESIZE_POS;
	103	dst \|= cfg->dst_info.data_width << D40_SREG_CFG_ESIZE_POS;
	104
0fd60223 N	105	/* Set the priority bit to high for the physical channel */
	106	if (cfg->high_priority) {
	107	src \|= 1 << D40_SREG_CFG_PRI_POS;
	108	dst \|= 1 << D40_SREG_CFG_PRI_POS;
	109	}
8d318a50 LW	110	}
8d318a50 LW	111
51f5d744 RV	112	if (cfg->src_info.big_endian)
	113	src \|= 1 << D40_SREG_CFG_LBE_POS;
	114	if (cfg->dst_info.big_endian)
	115	dst \|= 1 << D40_SREG_CFG_LBE_POS;
8d318a50 LW	116
	117	*src_cfg = src;
	118	*dst_cfg = dst;
	119	}
	120
d49278e3 PF	121	static int d40_phy_fill_lli(struct d40_phy_lli *lli,
	122	dma_addr_t data,
	123	u32 data_size,
d49278e3 PF	124	dma_addr_t next_lli,
d49278e3 PF	125	u32 reg_cfg,
7f933bed RV	126	struct stedma40_half_channel_info *info,
7f933bed RV	127	unsigned int flags)
8d318a50	128	{
7f933bed RV	129	bool addr_inc = flags & LLI_ADDR_INC;
7f933bed RV	130	bool term_int = flags & LLI_TERM_INT;
cc31b6f7 RV	131	unsigned int data_width = info->data_width;
cc31b6f7 RV	132	int psize = info->psize;
8d318a50 LW	133	int num_elems;
	134
	135	if (psize == STEDMA40_PSIZE_PHY_1)
	136	num_elems = 1;
	137	else
	138	num_elems = 2 << psize;
	139
8d318a50 LW	140	/* Must be aligned */
	141	if (!IS_ALIGNED(data, 0x1 << data_width))
	142	return -EINVAL;
	143
	144	/* Transfer size can't be smaller than (num_elms * elem_size) */
	145	if (data_size < num_elems * (0x1 << data_width))
	146	return -EINVAL;
	147
	148	/* The number of elements. IE now many chunks */
	149	lli->reg_elt = (data_size >> data_width) << D40_SREG_ELEM_PHY_ECNT_POS;
	150
	151	/*
	152	* Distance to next element sized entry.
	153	* Usually the size of the element unless you want gaps.
	154	*/
7f933bed	155	if (addr_inc)
8d318a50 LW	156	lli->reg_elt \|= (0x1 << data_width) <<
	157	D40_SREG_ELEM_PHY_EIDX_POS;
	158
	159	/* Where the data is */
	160	lli->reg_ptr = data;
	161	lli->reg_cfg = reg_cfg;
	162
	163	/* If this scatter list entry is the last one, no next link */
	164	if (next_lli == 0)
	165	lli->reg_lnk = 0x1 << D40_SREG_LNK_PHY_TCP_POS;
	166	else
	167	lli->reg_lnk = next_lli;
	168
	169	/* Set/clear interrupt generation on this link item.*/
	170	if (term_int)
	171	lli->reg_cfg \|= 0x1 << D40_SREG_CFG_TIM_POS;
	172	else
	173	lli->reg_cfg &= ~(0x1 << D40_SREG_CFG_TIM_POS);
	174
	175	/* Post link */
	176	lli->reg_lnk \|= 0 << D40_SREG_LNK_PHY_PRE_POS;
	177
	178	return 0;
	179	}
	180
d49278e3 PF	181	static int d40_seg_size(int size, int data_width1, int data_width2)
	182	{
	183	u32 max_w = max(data_width1, data_width2);
	184	u32 min_w = min(data_width1, data_width2);
	185	u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
	186
	187	if (seg_max > STEDMA40_MAX_SEG_SIZE)
	188	seg_max -= (1 << max_w);
	189
	190	if (size <= seg_max)
	191	return size;
	192
	193	if (size <= 2 * seg_max)
	194	return ALIGN(size / 2, 1 << max_w);
	195
	196	return seg_max;
	197	}
	198
cc31b6f7 RV	199	static struct d40_phy_lli *
cc31b6f7 RV	200	d40_phy_buf_to_lli(struct d40_phy_lli *lli, dma_addr_t addr, u32 size,
0c842b55	201	dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg,
7f933bed RV	202	struct stedma40_half_channel_info *info,
	203	struct stedma40_half_channel_info *otherinfo,
	204	unsigned long flags)
d49278e3	205	{
0c842b55	206	bool lastlink = flags & LLI_LAST_LINK;
7f933bed RV	207	bool addr_inc = flags & LLI_ADDR_INC;
7f933bed RV	208	bool term_int = flags & LLI_TERM_INT;
0c842b55	209	bool cyclic = flags & LLI_CYCLIC;
d49278e3 PF	210	int err;
	211	dma_addr_t next = lli_phys;
	212	int size_rest = size;
	213	int size_seg = 0;
	214
7f933bed RV	215	/*
	216	* This piece may be split up based on d40_seg_size(); we only want the
	217	* term int on the last part.
	218	*/
	219	if (term_int)
	220	flags &= ~LLI_TERM_INT;
	221
d49278e3	222	do {
cc31b6f7 RV	223	size_seg = d40_seg_size(size_rest, info->data_width,
cc31b6f7 RV	224	otherinfo->data_width);
d49278e3 PF	225	size_rest -= size_seg;
d49278e3 PF	226
0c842b55	227	if (size_rest == 0 && term_int)
7f933bed	228	flags \|= LLI_TERM_INT;
0c842b55 RV	229
	230	if (size_rest == 0 && lastlink)
	231	next = cyclic ? first_phys : 0;
	232	else
d49278e3 PF	233	next = ALIGN(next + sizeof(struct d40_phy_lli),
	234	D40_LLI_ALIGN);
	235
7f933bed RV	236	err = d40_phy_fill_lli(lli, addr, size_seg, next,
7f933bed RV	237	reg_cfg, info, flags);
d49278e3 PF	238
	239	if (err)
	240	goto err;
	241
	242	lli++;
7f933bed	243	if (addr_inc)
d49278e3 PF	244	addr += size_seg;
	245	} while (size_rest);
	246
	247	return lli;
	248
f26e03ad	249	err:
d49278e3 PF	250	return NULL;
	251	}
	252
8d318a50 LW	253	int d40_phy_sg_to_lli(struct scatterlist *sg,
	254	int sg_len,
	255	dma_addr_t target,
d49278e3	256	struct d40_phy_lli *lli_sg,
8d318a50 LW	257	dma_addr_t lli_phys,
8d318a50 LW	258	u32 reg_cfg,
cc31b6f7	259	struct stedma40_half_channel_info *info,
0c842b55 RV	260	struct stedma40_half_channel_info *otherinfo,
0c842b55 RV	261	unsigned long flags)
8d318a50 LW	262	{
	263	int total_size = 0;
	264	int i;
	265	struct scatterlist *current_sg = sg;
d49278e3 PF	266	struct d40_phy_lli *lli = lli_sg;
d49278e3 PF	267	dma_addr_t l_phys = lli_phys;
7f933bed RV	268
	269	if (!target)
	270	flags \|= LLI_ADDR_INC;
8d318a50 LW	271
8d318a50 LW	272	for_each_sg(sg, current_sg, sg_len, i) {
7f933bed RV	273	dma_addr_t sg_addr = sg_dma_address(current_sg);
	274	unsigned int len = sg_dma_len(current_sg);
	275	dma_addr_t dst = target ?: sg_addr;
8d318a50 LW	276
	277	total_size += sg_dma_len(current_sg);
	278
7f933bed	279	if (i == sg_len - 1)
0c842b55	280	flags \|= LLI_TERM_INT \| LLI_LAST_LINK;
8d318a50	281
d49278e3 PF	282	l_phys = ALIGN(lli_phys + (lli - lli_sg) *
	283	sizeof(struct d40_phy_lli), D40_LLI_ALIGN);
	284
0c842b55	285	lli = d40_phy_buf_to_lli(lli, dst, len, l_phys, lli_phys,
7f933bed RV	286	reg_cfg, info, otherinfo, flags);
7f933bed RV	287
d49278e3 PF	288	if (lli == NULL)
d49278e3 PF	289	return -EINVAL;
8d318a50 LW	290	}
	291
	292	return total_size;
8d318a50 LW	293	}
	294
	295
8d318a50 LW	296	/* DMA logical lli operations */
8d318a50 LW	297
698e4732 JA	298	static void d40_log_lli_link(struct d40_log_lli *lli_dst,
698e4732 JA	299	struct d40_log_lli *lli_src,
0c842b55	300	int next, unsigned int flags)
698e4732	301	{
0c842b55	302	bool interrupt = flags & LLI_TERM_INT;
698e4732 JA	303	u32 slos = 0;
	304	u32 dlos = 0;
	305
	306	if (next != -EINVAL) {
	307	slos = next * 2;
	308	dlos = next * 2 + 1;
0c842b55 RV	309	}
	310
	311	if (interrupt) {
698e4732 JA	312	lli_dst->lcsp13 \|= D40_MEM_LCSP1_SCFG_TIM_MASK;
	313	lli_dst->lcsp13 \|= D40_MEM_LCSP3_DTCP_MASK;
	314	}
	315
	316	lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) \|
	317	(slos << D40_MEM_LCSP1_SLOS_POS);
	318
	319	lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) \|
	320	(dlos << D40_MEM_LCSP1_SLOS_POS);
	321	}
	322
	323	void d40_log_lli_lcpa_write(struct d40_log_lli_full *lcpa,
	324	struct d40_log_lli *lli_dst,
	325	struct d40_log_lli *lli_src,
0c842b55	326	int next, unsigned int flags)
698e4732	327	{
0c842b55	328	d40_log_lli_link(lli_dst, lli_src, next, flags);
698e4732	329
8a5d2039 PF	330	writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0);
	331	writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1);
	332	writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2);
	333	writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3);
698e4732 JA	334	}
	335
	336	void d40_log_lli_lcla_write(struct d40_log_lli *lcla,
	337	struct d40_log_lli *lli_dst,
	338	struct d40_log_lli *lli_src,
0c842b55	339	int next, unsigned int flags)
698e4732	340	{
0c842b55	341	d40_log_lli_link(lli_dst, lli_src, next, flags);
698e4732	342
8a5d2039 PF	343	writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02);
	344	writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13);
	345	writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02);
	346	writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13);
698e4732 JA	347	}
698e4732 JA	348
d49278e3 PF	349	static void d40_log_fill_lli(struct d40_log_lli *lli,
	350	dma_addr_t data, u32 data_size,
	351	u32 reg_cfg,
	352	u32 data_width,
7f933bed	353	unsigned int flags)
8d318a50	354	{
7f933bed RV	355	bool addr_inc = flags & LLI_ADDR_INC;
7f933bed RV	356
8d318a50 LW	357	lli->lcsp13 = reg_cfg;
	358
	359	/* The number of elements to transfer */
	360	lli->lcsp02 = ((data_size >> data_width) <<
	361	D40_MEM_LCSP0_ECNT_POS) & D40_MEM_LCSP0_ECNT_MASK;
d49278e3 PF	362
	363	BUG_ON((data_size >> data_width) > STEDMA40_MAX_SEG_SIZE);
	364
8d318a50 LW	365	/* 16 LSBs address of the current element */
	366	lli->lcsp02 \|= data & D40_MEM_LCSP0_SPTR_MASK;
	367	/* 16 MSBs address of the current element */
	368	lli->lcsp13 \|= data & D40_MEM_LCSP1_SPTR_MASK;
	369
	370	if (addr_inc)
	371	lli->lcsp13 \|= D40_MEM_LCSP1_SCFG_INCR_MASK;
	372
8d318a50 LW	373	}
8d318a50 LW	374
1f7622ca	375	static struct d40_log_lli d40_log_buf_to_lli(struct d40_log_lli lli_sg,
d49278e3 PF	376	dma_addr_t addr,
	377	int size,
	378	u32 lcsp13, /* src or dst*/
	379	u32 data_width1,
	380	u32 data_width2,
7f933bed	381	unsigned int flags)
d49278e3	382	{
7f933bed	383	bool addr_inc = flags & LLI_ADDR_INC;
d49278e3 PF	384	struct d40_log_lli *lli = lli_sg;
	385	int size_rest = size;
	386	int size_seg = 0;
	387
	388	do {
	389	size_seg = d40_seg_size(size_rest, data_width1, data_width2);
	390	size_rest -= size_seg;
	391
	392	d40_log_fill_lli(lli,
	393	addr,
	394	size_seg,
	395	lcsp13, data_width1,
7f933bed	396	flags);
d49278e3 PF	397	if (addr_inc)
	398	addr += size_seg;
	399	lli++;
	400	} while (size_rest);
	401
	402	return lli;
	403	}
	404
698e4732	405	int d40_log_sg_to_lli(struct scatterlist *sg,
8d318a50	406	int sg_len,
5ed04b85	407	dma_addr_t dev_addr,
8d318a50 LW	408	struct d40_log_lli *lli_sg,
8d318a50 LW	409	u32 lcsp13, /* src or dst*/
d49278e3	410	u32 data_width1, u32 data_width2)
8d318a50 LW	411	{
	412	int total_size = 0;
	413	struct scatterlist *current_sg = sg;
	414	int i;
d49278e3	415	struct d40_log_lli *lli = lli_sg;
7f933bed RV	416	unsigned long flags = 0;
	417
	418	if (!dev_addr)
	419	flags \|= LLI_ADDR_INC;
8d318a50 LW	420
8d318a50 LW	421	for_each_sg(sg, current_sg, sg_len, i) {
5ed04b85 RV	422	dma_addr_t sg_addr = sg_dma_address(current_sg);
	423	unsigned int len = sg_dma_len(current_sg);
	424	dma_addr_t addr = dev_addr ?: sg_addr;
	425
8d318a50	426	total_size += sg_dma_len(current_sg);
5ed04b85 RV	427
5ed04b85 RV	428	lli = d40_log_buf_to_lli(lli, addr, len,
d49278e3	429	lcsp13,
5ed04b85 RV	430	data_width1,
5ed04b85 RV	431	data_width2,
7f933bed	432	flags);
8d318a50	433	}
5ed04b85	434
8d318a50 LW	435	return total_size;
8d318a50 LW	436	}