[deliverable/linux.git] / drivers / dma / ste_dma40_ll.h

/*
 * driver/dma/ste_dma40_ll.h
 *
 * Copyright (C) ST-Ericsson 2007-2010
 * License terms: GNU General Public License (GPL) version 2
 * Author: Per Friden <per.friden@stericsson.com>
 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
 */
#ifndef STE_DMA40_LL_H
#define STE_DMA40_LL_H

#define D40_DREG_PCBASE		0x400
#define D40_DREG_PCDELTA	(8 * 4)
#define D40_LLI_ALIGN		16 /* LLI alignment must be 16 bytes. */

#define D40_LCPA_CHAN_SIZE 32
#define D40_LCPA_CHAN_DST_DELTA 16

#define D40_TYPE_TO_GROUP(type) (type / 16)
#define D40_TYPE_TO_EVENT(type) (type % 16)

/* Most bits of the CFG register are the same in log as in phy mode */
#define D40_SREG_CFG_MST_POS		15
#define D40_SREG_CFG_TIM_POS		14
#define D40_SREG_CFG_EIM_POS		13
#define D40_SREG_CFG_LOG_INCR_POS	12
#define D40_SREG_CFG_PHY_PEN_POS	12
#define D40_SREG_CFG_PSIZE_POS		10
#define D40_SREG_CFG_ESIZE_POS		 8
#define D40_SREG_CFG_PRI_POS		 7
#define D40_SREG_CFG_LBE_POS		 6
#define D40_SREG_CFG_LOG_GIM_POS	 5
#define D40_SREG_CFG_LOG_MFU_POS	 4
#define D40_SREG_CFG_PHY_TM_POS		 4
#define D40_SREG_CFG_PHY_EVTL_POS	 0


/* Standard channel parameters - basic mode (element register) */
#define D40_SREG_ELEM_PHY_ECNT_POS	16
#define D40_SREG_ELEM_PHY_EIDX_POS	 0

#define D40_SREG_ELEM_PHY_ECNT_MASK	(0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)

/* Standard channel parameters - basic mode (Link register) */
#define D40_SREG_LNK_PHY_TCP_POS	0
#define D40_SREG_LNK_PHY_LMP_POS	1
#define D40_SREG_LNK_PHY_PRE_POS	2
/*
 * Source  destination link address. Contains the
 * 29-bit byte word aligned address of the reload area.
 */
#define D40_SREG_LNK_PHYS_LNK_MASK	0xFFFFFFF8UL

/* Standard basic channel logical mode */

/* Element register */
#define D40_SREG_ELEM_LOG_ECNT_POS	16
#define D40_SREG_ELEM_LOG_LIDX_POS	 8
#define D40_SREG_ELEM_LOG_LOS_POS	 1
#define D40_SREG_ELEM_LOG_TCP_POS	 0

#define D40_SREG_ELEM_LOG_LIDX_MASK	(0xFF << D40_SREG_ELEM_LOG_LIDX_POS)

/* Link register */
#define D40_DEACTIVATE_EVENTLINE	0x0
#define D40_ACTIVATE_EVENTLINE		0x1
#define D40_EVENTLINE_POS(i)		(2 * i)
#define D40_EVENTLINE_MASK(i)		(0x3 << D40_EVENTLINE_POS(i))

/* Standard basic channel logical params in memory */

/* LCSP0 */
#define D40_MEM_LCSP0_ECNT_POS		16
#define D40_MEM_LCSP0_SPTR_POS		 0

#define D40_MEM_LCSP0_ECNT_MASK		(0xFFFF << D40_MEM_LCSP0_ECNT_POS)
#define D40_MEM_LCSP0_SPTR_MASK		(0xFFFF << D40_MEM_LCSP0_SPTR_POS)

/* LCSP1 */
#define D40_MEM_LCSP1_SPTR_POS		16
#define D40_MEM_LCSP1_SCFG_MST_POS	15
#define D40_MEM_LCSP1_SCFG_TIM_POS	14
#define D40_MEM_LCSP1_SCFG_EIM_POS	13
#define D40_MEM_LCSP1_SCFG_INCR_POS	12
#define D40_MEM_LCSP1_SCFG_PSIZE_POS	10
#define D40_MEM_LCSP1_SCFG_ESIZE_POS	 8
#define D40_MEM_LCSP1_SLOS_POS		 1
#define D40_MEM_LCSP1_STCP_POS		 0

#define D40_MEM_LCSP1_SPTR_MASK		(0xFFFF << D40_MEM_LCSP1_SPTR_POS)
#define D40_MEM_LCSP1_SCFG_TIM_MASK	(0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)
#define D40_MEM_LCSP1_SCFG_INCR_MASK	(0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)
#define D40_MEM_LCSP1_SCFG_PSIZE_MASK	(0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)
#define D40_MEM_LCSP1_SLOS_MASK		(0x7F << D40_MEM_LCSP1_SLOS_POS)
#define D40_MEM_LCSP1_STCP_MASK		(0x1 << D40_MEM_LCSP1_STCP_POS)

/* LCSP2 */
#define D40_MEM_LCSP2_ECNT_POS		16

#define D40_MEM_LCSP2_ECNT_MASK		(0xFFFF << D40_MEM_LCSP2_ECNT_POS)

/* LCSP3 */
#define D40_MEM_LCSP3_DCFG_MST_POS	15
#define D40_MEM_LCSP3_DCFG_TIM_POS	14
#define D40_MEM_LCSP3_DCFG_EIM_POS	13
#define D40_MEM_LCSP3_DCFG_INCR_POS	12
#define D40_MEM_LCSP3_DCFG_PSIZE_POS	10
#define D40_MEM_LCSP3_DCFG_ESIZE_POS	 8
#define D40_MEM_LCSP3_DLOS_POS		 1
#define D40_MEM_LCSP3_DTCP_POS		 0

#define D40_MEM_LCSP3_DLOS_MASK		(0x7F << D40_MEM_LCSP3_DLOS_POS)
#define D40_MEM_LCSP3_DTCP_MASK		(0x1 << D40_MEM_LCSP3_DTCP_POS)


/* Standard channel parameter register offsets */
#define D40_CHAN_REG_SSCFG	0x00
#define D40_CHAN_REG_SSELT	0x04
#define D40_CHAN_REG_SSPTR	0x08
#define D40_CHAN_REG_SSLNK	0x0C
#define D40_CHAN_REG_SDCFG	0x10
#define D40_CHAN_REG_SDELT	0x14
#define D40_CHAN_REG_SDPTR	0x18
#define D40_CHAN_REG_SDLNK	0x1C

/* DMA Register Offsets */
#define D40_DREG_GCC		0x000
#define D40_DREG_PRTYP		0x004
#define D40_DREG_PRSME		0x008
#define D40_DREG_PRSMO		0x00C
#define D40_DREG_PRMSE		0x010
#define D40_DREG_PRMSO		0x014
#define D40_DREG_PRMOE		0x018
#define D40_DREG_PRMOO		0x01C
#define D40_DREG_LCPA		0x020
#define D40_DREG_LCLA		0x024
#define D40_DREG_ACTIVE		0x050
#define D40_DREG_ACTIVO		0x054
#define D40_DREG_FSEB1		0x058
#define D40_DREG_FSEB2		0x05C
#define D40_DREG_PCMIS		0x060
#define D40_DREG_PCICR		0x064
#define D40_DREG_PCTIS		0x068
#define D40_DREG_PCEIS		0x06C
#define D40_DREG_LCMIS0		0x080
#define D40_DREG_LCMIS1		0x084
#define D40_DREG_LCMIS2		0x088
#define D40_DREG_LCMIS3		0x08C
#define D40_DREG_LCICR0		0x090
#define D40_DREG_LCICR1		0x094
#define D40_DREG_LCICR2		0x098
#define D40_DREG_LCICR3		0x09C
#define D40_DREG_LCTIS0		0x0A0
#define D40_DREG_LCTIS1		0x0A4
#define D40_DREG_LCTIS2		0x0A8
#define D40_DREG_LCTIS3		0x0AC
#define D40_DREG_LCEIS0		0x0B0
#define D40_DREG_LCEIS1		0x0B4
#define D40_DREG_LCEIS2		0x0B8
#define D40_DREG_LCEIS3		0x0BC
#define D40_DREG_STFU		0xFC8
#define D40_DREG_ICFG		0xFCC
#define D40_DREG_PERIPHID0	0xFE0
#define D40_DREG_PERIPHID1	0xFE4
#define D40_DREG_PERIPHID2	0xFE8
#define D40_DREG_PERIPHID3	0xFEC
#define D40_DREG_CELLID0	0xFF0
#define D40_DREG_CELLID1	0xFF4
#define D40_DREG_CELLID2	0xFF8
#define D40_DREG_CELLID3	0xFFC

/* LLI related structures */

/**
 * struct d40_phy_lli - The basic configration register for each physical
 * channel.
 *
 * @reg_cfg: The configuration register.
 * @reg_elt: The element register.
 * @reg_ptr: The pointer register.
 * @reg_lnk: The link register.
 *
 * These registers are set up for both physical and logical transfers
 * Note that the bit in each register means differently in logical and
 * physical(standard) mode.
 *
 * This struct must be 16 bytes aligned, and only contain physical registers
 * since it will be directly accessed by the DMA.
 */
struct d40_phy_lli {
	u32 reg_cfg;
	u32 reg_elt;
	u32 reg_ptr;
	u32 reg_lnk;
};

/**
 * struct d40_phy_lli_bidir - struct for a transfer.
 *
 * @src: Register settings for src channel.
 * @dst: Register settings for dst channel.
 * @dst_addr: Physical destination address.
 * @src_addr: Physical source address.
 *
 * All DMA transfers have a source and a destination.
 */

struct d40_phy_lli_bidir {
	struct d40_phy_lli	*src;
	struct d40_phy_lli	*dst;
	dma_addr_t		 dst_addr;
	dma_addr_t		 src_addr;
};


/**
 * struct d40_log_lli - logical lli configuration
 *
 * @lcsp02: Either maps to register lcsp0 if src or lcsp2 if dst.
 * @lcsp13: Either maps to register lcsp1 if src or lcsp3 if dst.
 *
 * This struct must be 8 bytes aligned since it will be accessed directy by
 * the DMA. Never add any none hw mapped registers to this struct.
 */

struct d40_log_lli {
	u32 lcsp02;
	u32 lcsp13;
};

/**
 * struct d40_log_lli_bidir - For both src and dst
 *
 * @src: pointer to src lli configuration.
 * @dst: pointer to dst lli configuration.
 *
 * You always have a src and a dst when doing DMA transfers.
 */

struct d40_log_lli_bidir {
	struct d40_log_lli *src;
	struct d40_log_lli *dst;
};

/**
 * struct d40_log_lli_full - LCPA layout
 *
 * @lcsp0: Logical Channel Standard Param 0 - Src.
 * @lcsp1: Logical Channel Standard Param 1 - Src.
 * @lcsp2: Logical Channel Standard Param 2 - Dst.
 * @lcsp3: Logical Channel Standard Param 3 - Dst.
 *
 * This struct maps to LCPA physical memory layout. Must map to
 * the hw.
 */
struct d40_log_lli_full {
	u32 lcsp0;
	u32 lcsp1;
	u32 lcsp2;
	u32 lcsp3;
};

/**
 * struct d40_def_lcsp - Default LCSP1 and LCSP3 settings
 *
 * @lcsp3: The default configuration for dst.
 * @lcsp1: The default configuration for src.
 */
struct d40_def_lcsp {
	u32 lcsp3;
	u32 lcsp1;
};

/**
 * struct d40_lcla_elem - Info for one LCA element.
 *
 * @src_id: logical channel src id
 * @dst_id: logical channel dst id
 * @src: LCPA formated src parameters
 * @dst: LCPA formated dst parameters
 *
 */
struct d40_lcla_elem {
	int			src_id;
	int			dst_id;
	struct d40_log_lli     *src;
	struct d40_log_lli     *dst;
};

/* Physical channels */

void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
		 u32 *src_cfg, u32 *dst_cfg, bool is_log);

void d40_log_cfg(struct stedma40_chan_cfg *cfg,
		 u32 *lcsp1, u32 *lcsp2);

int d40_phy_sg_to_lli(struct scatterlist *sg,
		      int sg_len,
		      dma_addr_t target,
		      struct d40_phy_lli *lli,
		      dma_addr_t lli_phys,
		      u32 reg_cfg,
		      u32 data_width,
		      int psize,
		      bool term_int);

int d40_phy_fill_lli(struct d40_phy_lli *lli,
		     dma_addr_t data,
		     u32 data_size,
		     int psize,
		     dma_addr_t next_lli,
		     u32 reg_cfg,
		     bool term_int,
		     u32 data_width,
		     bool is_device);

void d40_phy_lli_write(void __iomem *virtbase,
		       u32 phy_chan_num,
		       struct d40_phy_lli *lli_dst,
		       struct d40_phy_lli *lli_src);

/* Logical channels */

void d40_log_fill_lli(struct d40_log_lli *lli,
		      dma_addr_t data, u32 data_size,
		      u32 lli_next_off, u32 reg_cfg,
		      u32 data_width,
		      bool term_int, bool addr_inc);

int d40_log_sg_to_dev(struct d40_lcla_elem *lcla,
		      struct scatterlist *sg,
		      int sg_len,
		      struct d40_log_lli_bidir *lli,
		      struct d40_def_lcsp *lcsp,
		      u32 src_data_width,
		      u32 dst_data_width,
		      enum dma_data_direction direction,
		      bool term_int, dma_addr_t dev_addr, int max_len,
		      int llis_per_log);

int d40_log_lli_write(struct d40_log_lli_full *lcpa,
		      struct d40_log_lli *lcla_src,
		      struct d40_log_lli *lcla_dst,
		      struct d40_log_lli *lli_dst,
		      struct d40_log_lli *lli_src,
		      int llis_per_log);

int d40_log_sg_to_lli(int lcla_id,
		      struct scatterlist *sg,
		      int sg_len,
		      struct d40_log_lli *lli_sg,
		      u32 lcsp13, /* src or dst*/
		      u32 data_width,
		      bool term_int, int max_len, int llis_per_log);

#endif /* STE_DMA40_LLI_H */
Commit	Line	Data
8d318a50 LW	1	/*
	2	* driver/dma/ste_dma40_ll.h
	3	*
	4	* Copyright (C) ST-Ericsson 2007-2010
	5	* License terms: GNU General Public License (GPL) version 2
	6	* Author: Per Friden <per.friden@stericsson.com>
	7	* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
	8	*/
	9	#ifndef STE_DMA40_LL_H
	10	#define STE_DMA40_LL_H
	11
	12	#define D40_DREG_PCBASE 0x400
	13	#define D40_DREG_PCDELTA (8 * 4)
	14	#define D40_LLI_ALIGN 16 /* LLI alignment must be 16 bytes. */
	15
ef1872ec LW	16	#define D40_LCPA_CHAN_SIZE 32
	17	#define D40_LCPA_CHAN_DST_DELTA 16
	18
8d318a50 LW	19	#define D40_TYPE_TO_GROUP(type) (type / 16)
	20	#define D40_TYPE_TO_EVENT(type) (type % 16)
	21
	22	/* Most bits of the CFG register are the same in log as in phy mode */
	23	#define D40_SREG_CFG_MST_POS 15
	24	#define D40_SREG_CFG_TIM_POS 14
	25	#define D40_SREG_CFG_EIM_POS 13
	26	#define D40_SREG_CFG_LOG_INCR_POS 12
	27	#define D40_SREG_CFG_PHY_PEN_POS 12
	28	#define D40_SREG_CFG_PSIZE_POS 10
	29	#define D40_SREG_CFG_ESIZE_POS 8
	30	#define D40_SREG_CFG_PRI_POS 7
	31	#define D40_SREG_CFG_LBE_POS 6
	32	#define D40_SREG_CFG_LOG_GIM_POS 5
	33	#define D40_SREG_CFG_LOG_MFU_POS 4
	34	#define D40_SREG_CFG_PHY_TM_POS 4
	35	#define D40_SREG_CFG_PHY_EVTL_POS 0
	36
	37
	38	/* Standard channel parameters - basic mode (element register) */
	39	#define D40_SREG_ELEM_PHY_ECNT_POS 16
	40	#define D40_SREG_ELEM_PHY_EIDX_POS 0
	41
	42	#define D40_SREG_ELEM_PHY_ECNT_MASK (0xFFFF << D40_SREG_ELEM_PHY_ECNT_POS)
	43
	44	/* Standard channel parameters - basic mode (Link register) */
	45	#define D40_SREG_LNK_PHY_TCP_POS 0
	46	#define D40_SREG_LNK_PHY_LMP_POS 1
	47	#define D40_SREG_LNK_PHY_PRE_POS 2
	48	/*
	49	* Source destination link address. Contains the
	50	* 29-bit byte word aligned address of the reload area.
	51	*/
	52	#define D40_SREG_LNK_PHYS_LNK_MASK 0xFFFFFFF8UL
	53
	54	/* Standard basic channel logical mode */
	55
	56	/* Element register */
	57	#define D40_SREG_ELEM_LOG_ECNT_POS 16
	58	#define D40_SREG_ELEM_LOG_LIDX_POS 8
	59	#define D40_SREG_ELEM_LOG_LOS_POS 1
	60	#define D40_SREG_ELEM_LOG_TCP_POS 0
	61
	62	#define D40_SREG_ELEM_LOG_LIDX_MASK (0xFF << D40_SREG_ELEM_LOG_LIDX_POS)
	63
	64	/* Link register */
	65	#define D40_DEACTIVATE_EVENTLINE 0x0
	66	#define D40_ACTIVATE_EVENTLINE 0x1
	67	#define D40_EVENTLINE_POS(i) (2 * i)
	68	#define D40_EVENTLINE_MASK(i) (0x3 << D40_EVENTLINE_POS(i))
	69
	70	/* Standard basic channel logical params in memory */
	71
	72	/* LCSP0 */
	73	#define D40_MEM_LCSP0_ECNT_POS 16
	74	#define D40_MEM_LCSP0_SPTR_POS 0
	75
	76	#define D40_MEM_LCSP0_ECNT_MASK (0xFFFF << D40_MEM_LCSP0_ECNT_POS)
	77	#define D40_MEM_LCSP0_SPTR_MASK (0xFFFF << D40_MEM_LCSP0_SPTR_POS)
	78
	79	/* LCSP1 */
	80	#define D40_MEM_LCSP1_SPTR_POS 16
	81	#define D40_MEM_LCSP1_SCFG_MST_POS 15
	82	#define D40_MEM_LCSP1_SCFG_TIM_POS 14
83	#define D40_MEM_LCSP1_SCFG_EIM_POS 13
84	#define D40_MEM_LCSP1_SCFG_INCR_POS 12
85	#define D40_MEM_LCSP1_SCFG_PSIZE_POS 10
86	#define D40_MEM_LCSP1_SCFG_ESIZE_POS 8
87	#define D40_MEM_LCSP1_SLOS_POS 1
88	#define D40_MEM_LCSP1_STCP_POS 0
89
90	#define D40_MEM_LCSP1_SPTR_MASK (0xFFFF << D40_MEM_LCSP1_SPTR_POS)
91	#define D40_MEM_LCSP1_SCFG_TIM_MASK (0x1 << D40_MEM_LCSP1_SCFG_TIM_POS)
92	#define D40_MEM_LCSP1_SCFG_INCR_MASK (0x1 << D40_MEM_LCSP1_SCFG_INCR_POS)
93	#define D40_MEM_LCSP1_SCFG_PSIZE_MASK (0x3 << D40_MEM_LCSP1_SCFG_PSIZE_POS)
94	#define D40_MEM_LCSP1_SLOS_MASK (0x7F << D40_MEM_LCSP1_SLOS_POS)
95	#define D40_MEM_LCSP1_STCP_MASK (0x1 << D40_MEM_LCSP1_STCP_POS)
96
97	/* LCSP2 */
98	#define D40_MEM_LCSP2_ECNT_POS 16
99
100	#define D40_MEM_LCSP2_ECNT_MASK (0xFFFF << D40_MEM_LCSP2_ECNT_POS)
101
102	/* LCSP3 */
103	#define D40_MEM_LCSP3_DCFG_MST_POS 15
104	#define D40_MEM_LCSP3_DCFG_TIM_POS 14
105	#define D40_MEM_LCSP3_DCFG_EIM_POS 13
106	#define D40_MEM_LCSP3_DCFG_INCR_POS 12
107	#define D40_MEM_LCSP3_DCFG_PSIZE_POS 10
108	#define D40_MEM_LCSP3_DCFG_ESIZE_POS 8
109	#define D40_MEM_LCSP3_DLOS_POS 1
110	#define D40_MEM_LCSP3_DTCP_POS 0
111
112	#define D40_MEM_LCSP3_DLOS_MASK (0x7F << D40_MEM_LCSP3_DLOS_POS)
113	#define D40_MEM_LCSP3_DTCP_MASK (0x1 << D40_MEM_LCSP3_DTCP_POS)
114
115
116	/* Standard channel parameter register offsets */
117	#define D40_CHAN_REG_SSCFG 0x00
118	#define D40_CHAN_REG_SSELT 0x04
119	#define D40_CHAN_REG_SSPTR 0x08
120	#define D40_CHAN_REG_SSLNK 0x0C
121	#define D40_CHAN_REG_SDCFG 0x10
122	#define D40_CHAN_REG_SDELT 0x14
123	#define D40_CHAN_REG_SDPTR 0x18
124	#define D40_CHAN_REG_SDLNK 0x1C
125
126	/* DMA Register Offsets */
127	#define D40_DREG_GCC 0x000
128	#define D40_DREG_PRTYP 0x004
129	#define D40_DREG_PRSME 0x008
130	#define D40_DREG_PRSMO 0x00C
131	#define D40_DREG_PRMSE 0x010
132	#define D40_DREG_PRMSO 0x014
133	#define D40_DREG_PRMOE 0x018
134	#define D40_DREG_PRMOO 0x01C
135	#define D40_DREG_LCPA 0x020
136	#define D40_DREG_LCLA 0x024
137	#define D40_DREG_ACTIVE 0x050
138	#define D40_DREG_ACTIVO 0x054
139	#define D40_DREG_FSEB1 0x058
140	#define D40_DREG_FSEB2 0x05C
141	#define D40_DREG_PCMIS 0x060
142	#define D40_DREG_PCICR 0x064
143	#define D40_DREG_PCTIS 0x068
144	#define D40_DREG_PCEIS 0x06C
145	#define D40_DREG_LCMIS0 0x080
146	#define D40_DREG_LCMIS1 0x084
147	#define D40_DREG_LCMIS2 0x088
148	#define D40_DREG_LCMIS3 0x08C
149	#define D40_DREG_LCICR0 0x090
150	#define D40_DREG_LCICR1 0x094
151	#define D40_DREG_LCICR2 0x098
152	#define D40_DREG_LCICR3 0x09C
153	#define D40_DREG_LCTIS0 0x0A0
154	#define D40_DREG_LCTIS1 0x0A4
155	#define D40_DREG_LCTIS2 0x0A8
156	#define D40_DREG_LCTIS3 0x0AC
157	#define D40_DREG_LCEIS0 0x0B0
158	#define D40_DREG_LCEIS1 0x0B4
159	#define D40_DREG_LCEIS2 0x0B8
160	#define D40_DREG_LCEIS3 0x0BC
161	#define D40_DREG_STFU 0xFC8
162	#define D40_DREG_ICFG 0xFCC
163	#define D40_DREG_PERIPHID0 0xFE0
164	#define D40_DREG_PERIPHID1 0xFE4
165	#define D40_DREG_PERIPHID2 0xFE8
166	#define D40_DREG_PERIPHID3 0xFEC
167	#define D40_DREG_CELLID0 0xFF0
168	#define D40_DREG_CELLID1 0xFF4
169	#define D40_DREG_CELLID2 0xFF8
170	#define D40_DREG_CELLID3 0xFFC
171
172	/* LLI related structures */
173
174	/**
175	* struct d40_phy_lli - The basic configration register for each physical
176	* channel.
177	*
178	* @reg_cfg: The configuration register.
179	* @reg_elt: The element register.
180	* @reg_ptr: The pointer register.
181	* @reg_lnk: The link register.
182	*
183	* These registers are set up for both physical and logical transfers
184	* Note that the bit in each register means differently in logical and
185	* physical(standard) mode.
186	*
187	* This struct must be 16 bytes aligned, and only contain physical registers
188	* since it will be directly accessed by the DMA.
189	*/
190	struct d40_phy_lli {
191	u32 reg_cfg;
192	u32 reg_elt;
193	u32 reg_ptr;
194	u32 reg_lnk;
195	};
196
197	/**
198	* struct d40_phy_lli_bidir - struct for a transfer.
199	*
200	* @src: Register settings for src channel.
201	* @dst: Register settings for dst channel.
202	* @dst_addr: Physical destination address.
203	* @src_addr: Physical source address.
204	*
205	* All DMA transfers have a source and a destination.
206	*/
207
208	struct d40_phy_lli_bidir {
209	struct d40_phy_lli *src;
210	struct d40_phy_lli *dst;
211	dma_addr_t dst_addr;
212	dma_addr_t src_addr;
213	};
214
215
216	/**
217	* struct d40_log_lli - logical lli configuration
218	*
219	* @lcsp02: Either maps to register lcsp0 if src or lcsp2 if dst.
220	* @lcsp13: Either maps to register lcsp1 if src or lcsp3 if dst.
221	*
222	* This struct must be 8 bytes aligned since it will be accessed directy by
223	* the DMA. Never add any none hw mapped registers to this struct.
224	*/
225
226	struct d40_log_lli {
227	u32 lcsp02;
228	u32 lcsp13;
229	};
230
231	/**
232	* struct d40_log_lli_bidir - For both src and dst
233	*
234	* @src: pointer to src lli configuration.
235	* @dst: pointer to dst lli configuration.
236	*
237	* You always have a src and a dst when doing DMA transfers.
238	*/
239
240	struct d40_log_lli_bidir {
241	struct d40_log_lli *src;
242	struct d40_log_lli *dst;
243	};
244
245	/**
246	* struct d40_log_lli_full - LCPA layout
247	*
248	* @lcsp0: Logical Channel Standard Param 0 - Src.
249	* @lcsp1: Logical Channel Standard Param 1 - Src.
250	* @lcsp2: Logical Channel Standard Param 2 - Dst.
251	* @lcsp3: Logical Channel Standard Param 3 - Dst.
252	*
253	* This struct maps to LCPA physical memory layout. Must map to
254	* the hw.
255	*/
256	struct d40_log_lli_full {
257	u32 lcsp0;
258	u32 lcsp1;
259	u32 lcsp2;
260	u32 lcsp3;
261	};
262
263	/**
264	* struct d40_def_lcsp - Default LCSP1 and LCSP3 settings
265	*
266	* @lcsp3: The default configuration for dst.
267	* @lcsp1: The default configuration for src.
268	*/
269	struct d40_def_lcsp {
270	u32 lcsp3;
271	u32 lcsp1;
272	};
273
274	/**
275	* struct d40_lcla_elem - Info for one LCA element.
276	*
277	* @src_id: logical channel src id
278	* @dst_id: logical channel dst id
279	* @src: LCPA formated src parameters
280	* @dst: LCPA formated dst parameters
281	*
282	*/
283	struct d40_lcla_elem {
284	int src_id;
285	int dst_id;
286	struct d40_log_lli *src;
287	struct d40_log_lli *dst;
288	};
289
290	/* Physical channels */
291
292	void d40_phy_cfg(struct stedma40_chan_cfg *cfg,
293	u32 src_cfg, u32 dst_cfg, bool is_log);
294
295	void d40_log_cfg(struct stedma40_chan_cfg *cfg,
296	u32 lcsp1, u32 lcsp2);
297
298	int d40_phy_sg_to_lli(struct scatterlist *sg,
299	int sg_len,
300	dma_addr_t target,
301	struct d40_phy_lli *lli,
302	dma_addr_t lli_phys,
303	u32 reg_cfg,
304	u32 data_width,
305	int psize,
306	bool term_int);
307
308	int d40_phy_fill_lli(struct d40_phy_lli *lli,
309	dma_addr_t data,
310	u32 data_size,
311	int psize,
312	dma_addr_t next_lli,
313	u32 reg_cfg,
314	bool term_int,
315	u32 data_width,
316	bool is_device);
317
318	void d40_phy_lli_write(void __iomem *virtbase,
319	u32 phy_chan_num,
320	struct d40_phy_lli *lli_dst,
321	struct d40_phy_lli *lli_src);
322
323	/* Logical channels */
324
325	void d40_log_fill_lli(struct d40_log_lli *lli,
326	dma_addr_t data, u32 data_size,
327	u32 lli_next_off, u32 reg_cfg,
328	u32 data_width,
329	bool term_int, bool addr_inc);
330
331	int d40_log_sg_to_dev(struct d40_lcla_elem *lcla,
332	struct scatterlist *sg,
333	int sg_len,
334	struct d40_log_lli_bidir *lli,
335	struct d40_def_lcsp *lcsp,
336	u32 src_data_width,
337	u32 dst_data_width,
338	enum dma_data_direction direction,
339	bool term_int, dma_addr_t dev_addr, int max_len,
340	int llis_per_log);
341
508849ad LW	342	int d40_log_lli_write(struct d40_log_lli_full *lcpa,
	343	struct d40_log_lli *lcla_src,
	344	struct d40_log_lli *lcla_dst,
	345	struct d40_log_lli *lli_dst,
	346	struct d40_log_lli *lli_src,
	347	int llis_per_log);
8d318a50 LW	348
	349	int d40_log_sg_to_lli(int lcla_id,
	350	struct scatterlist *sg,
	351	int sg_len,
	352	struct d40_log_lli *lli_sg,
	353	u32 lcsp13, /* src or dst*/
	354	u32 data_width,
	355	bool term_int, int max_len, int llis_per_log);
	356
	357	#endif /* STE_DMA40_LLI_H */