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FIRMWARE: bcm47xx_nvram: Fix module license.
[deliverable/linux.git] / drivers / dma / xgene-dma.c
CommitLineData
9f2fd0df
RPS		 1/*
2 * Applied Micro X-Gene SoC DMA engine Driver
3 *
4 * Copyright (c) 2015, Applied Micro Circuits Corporation
5 * Authors: Rameshwar Prasad Sahu <rsahu@apm.com>
6 * Loc Ho <lho@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 *
21 * NOTE: PM support is currently not available.
22 */
23
24#include <linux/clk.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/dmaengine.h>
28#include <linux/dmapool.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/module.h>
32#include <linux/of_device.h>
33
34#include "dmaengine.h"
35
36/* X-Gene DMA ring csr registers and bit definations */
37#define XGENE_DMA_RING_CONFIG 0x04
38#define XGENE_DMA_RING_ENABLE BIT(31)
39#define XGENE_DMA_RING_ID 0x08
40#define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31))
41#define XGENE_DMA_RING_ID_BUF 0x0C
42#define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21))
43#define XGENE_DMA_RING_THRESLD0_SET1 0x30
44#define XGENE_DMA_RING_THRESLD0_SET1_VAL 0X64
45#define XGENE_DMA_RING_THRESLD1_SET1 0x34
46#define XGENE_DMA_RING_THRESLD1_SET1_VAL 0xC8
47#define XGENE_DMA_RING_HYSTERESIS 0x68
48#define XGENE_DMA_RING_HYSTERESIS_VAL 0xFFFFFFFF
49#define XGENE_DMA_RING_STATE 0x6C
50#define XGENE_DMA_RING_STATE_WR_BASE 0x70
51#define XGENE_DMA_RING_NE_INT_MODE 0x017C
52#define XGENE_DMA_RING_NE_INT_MODE_SET(m, v) \
53 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
54#define XGENE_DMA_RING_NE_INT_MODE_RESET(m, v) \
55 ((m) &= (~BIT(31 - (v))))
56#define XGENE_DMA_RING_CLKEN 0xC208
57#define XGENE_DMA_RING_SRST 0xC200
58#define XGENE_DMA_RING_MEM_RAM_SHUTDOWN 0xD070
59#define XGENE_DMA_RING_BLK_MEM_RDY 0xD074
60#define XGENE_DMA_RING_BLK_MEM_RDY_VAL 0xFFFFFFFF
61#define XGENE_DMA_RING_DESC_CNT(v) (((v) & 0x0001FFFE) >> 1)
62#define XGENE_DMA_RING_ID_GET(owner, num) (((owner) << 6) | (num))
63#define XGENE_DMA_RING_DST_ID(v) ((1 << 10) | (v))
64#define XGENE_DMA_RING_CMD_OFFSET 0x2C
65#define XGENE_DMA_RING_CMD_BASE_OFFSET(v) ((v) << 6)
66#define XGENE_DMA_RING_COHERENT_SET(m) \
67 (((u32 *)(m))[2] |= BIT(4))
68#define XGENE_DMA_RING_ADDRL_SET(m, v) \
69 (((u32 *)(m))[2] |= (((v) >> 8) << 5))
70#define XGENE_DMA_RING_ADDRH_SET(m, v) \
71 (((u32 *)(m))[3] |= ((v) >> 35))
72#define XGENE_DMA_RING_ACCEPTLERR_SET(m) \
73 (((u32 *)(m))[3] |= BIT(19))
74#define XGENE_DMA_RING_SIZE_SET(m, v) \
75 (((u32 *)(m))[3] |= ((v) << 23))
76#define XGENE_DMA_RING_RECOMBBUF_SET(m) \
77 (((u32 *)(m))[3] |= BIT(27))
78#define XGENE_DMA_RING_RECOMTIMEOUTL_SET(m) \
79 (((u32 *)(m))[3] |= (0x7 << 28))
80#define XGENE_DMA_RING_RECOMTIMEOUTH_SET(m) \
81 (((u32 *)(m))[4] |= 0x3)
82#define XGENE_DMA_RING_SELTHRSH_SET(m) \
83 (((u32 *)(m))[4] |= BIT(3))
84#define XGENE_DMA_RING_TYPE_SET(m, v) \
85 (((u32 *)(m))[4] |= ((v) << 19))
86
87/* X-Gene DMA device csr registers and bit definitions */
88#define XGENE_DMA_IPBRR 0x0
89#define XGENE_DMA_DEV_ID_RD(v) ((v) & 0x00000FFF)
90#define XGENE_DMA_BUS_ID_RD(v) (((v) >> 12) & 3)
91#define XGENE_DMA_REV_NO_RD(v) (((v) >> 14) & 3)
92#define XGENE_DMA_GCR 0x10
93#define XGENE_DMA_CH_SETUP(v) \
94 ((v) = ((v) & ~0x000FFFFF) | 0x000AAFFF)
95#define XGENE_DMA_ENABLE(v) ((v) |= BIT(31))
96#define XGENE_DMA_DISABLE(v) ((v) &= ~BIT(31))
97#define XGENE_DMA_RAID6_CONT 0x14
98#define XGENE_DMA_RAID6_MULTI_CTRL(v) ((v) << 24)
99#define XGENE_DMA_INT 0x70
100#define XGENE_DMA_INT_MASK 0x74
101#define XGENE_DMA_INT_ALL_MASK 0xFFFFFFFF
102#define XGENE_DMA_INT_ALL_UNMASK 0x0
103#define XGENE_DMA_INT_MASK_SHIFT 0x14
104#define XGENE_DMA_RING_INT0_MASK 0x90A0
105#define XGENE_DMA_RING_INT1_MASK 0x90A8
106#define XGENE_DMA_RING_INT2_MASK 0x90B0
107#define XGENE_DMA_RING_INT3_MASK 0x90B8
108#define XGENE_DMA_RING_INT4_MASK 0x90C0
109#define XGENE_DMA_CFG_RING_WQ_ASSOC 0x90E0
110#define XGENE_DMA_ASSOC_RING_MNGR1 0xFFFFFFFF
111#define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070
112#define XGENE_DMA_BLK_MEM_RDY 0xD074
113#define XGENE_DMA_BLK_MEM_RDY_VAL 0xFFFFFFFF
cda8e937 114#define XGENE_DMA_RING_CMD_SM_OFFSET 0x8000
9f2fd0df
RPS		 115
116/* X-Gene SoC EFUSE csr register and bit defination */
117#define XGENE_SOC_JTAG1_SHADOW 0x18
118#define XGENE_DMA_PQ_DISABLE_MASK BIT(13)
119
120/* X-Gene DMA Descriptor format */
121#define XGENE_DMA_DESC_NV_BIT BIT_ULL(50)
122#define XGENE_DMA_DESC_IN_BIT BIT_ULL(55)
123#define XGENE_DMA_DESC_C_BIT BIT_ULL(63)
124#define XGENE_DMA_DESC_DR_BIT BIT_ULL(61)
125#define XGENE_DMA_DESC_ELERR_POS 46
126#define XGENE_DMA_DESC_RTYPE_POS 56
127#define XGENE_DMA_DESC_LERR_POS 60
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RPS		 128#define XGENE_DMA_DESC_BUFLEN_POS 48
129#define XGENE_DMA_DESC_HOENQ_NUM_POS 48
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RPS		 130#define XGENE_DMA_DESC_ELERR_RD(m) \
131 (((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
132#define XGENE_DMA_DESC_LERR_RD(m) \
133 (((m) >> XGENE_DMA_DESC_LERR_POS) & 0x7)
134#define XGENE_DMA_DESC_STATUS(elerr, lerr) \
135 (((elerr) << 4) | (lerr))
136
137/* X-Gene DMA descriptor empty s/w signature */
9f2fd0df 138#define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL
9f2fd0df
RPS		 139
140/* X-Gene DMA configurable parameters defines */
141#define XGENE_DMA_RING_NUM 512
142#define XGENE_DMA_BUFNUM 0x0
143#define XGENE_DMA_CPU_BUFNUM 0x18
144#define XGENE_DMA_RING_OWNER_DMA 0x03
145#define XGENE_DMA_RING_OWNER_CPU 0x0F
146#define XGENE_DMA_RING_TYPE_REGULAR 0x01
147#define XGENE_DMA_RING_WQ_DESC_SIZE 32 /* 32 Bytes */
148#define XGENE_DMA_RING_NUM_CONFIG 5
149#define XGENE_DMA_MAX_CHANNEL 4
150#define XGENE_DMA_XOR_CHANNEL 0
151#define XGENE_DMA_PQ_CHANNEL 1
152#define XGENE_DMA_MAX_BYTE_CNT 0x4000 /* 16 KB */
153#define XGENE_DMA_MAX_64B_DESC_BYTE_CNT 0x14000 /* 80 KB */
154#define XGENE_DMA_XOR_ALIGNMENT 6 /* 64 Bytes */
155#define XGENE_DMA_MAX_XOR_SRC 5
156#define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0
6d0767c1 157#define XGENE_DMA_INVALID_LEN_CODE 0x7800000000000000ULL
9f2fd0df
RPS		 158
159/* X-Gene DMA descriptor error codes */
160#define ERR_DESC_AXI 0x01
161#define ERR_BAD_DESC 0x02
162#define ERR_READ_DATA_AXI 0x03
163#define ERR_WRITE_DATA_AXI 0x04
164#define ERR_FBP_TIMEOUT 0x05
165#define ERR_ECC 0x06
166#define ERR_DIFF_SIZE 0x08
167#define ERR_SCT_GAT_LEN 0x09
168#define ERR_CRC_ERR 0x11
169#define ERR_CHKSUM 0x12
170#define ERR_DIF 0x13
171
172/* X-Gene DMA error interrupt codes */
173#define ERR_DIF_SIZE_INT 0x0
174#define ERR_GS_ERR_INT 0x1
175#define ERR_FPB_TIMEO_INT 0x2
176#define ERR_WFIFO_OVF_INT 0x3
177#define ERR_RFIFO_OVF_INT 0x4
178#define ERR_WR_TIMEO_INT 0x5
179#define ERR_RD_TIMEO_INT 0x6
180#define ERR_WR_ERR_INT 0x7
181#define ERR_RD_ERR_INT 0x8
182#define ERR_BAD_DESC_INT 0x9
183#define ERR_DESC_DST_INT 0xA
184#define ERR_DESC_SRC_INT 0xB
185
186/* X-Gene DMA flyby operation code */
6d0767c1
RPS		 187#define FLYBY_2SRC_XOR 0x80
188#define FLYBY_3SRC_XOR 0x90
189#define FLYBY_4SRC_XOR 0xA0
190#define FLYBY_5SRC_XOR 0xB0
9f2fd0df
RPS		 191
192/* X-Gene DMA SW descriptor flags */
193#define XGENE_DMA_FLAG_64B_DESC BIT(0)
194
195/* Define to dump X-Gene DMA descriptor */
196#define XGENE_DMA_DESC_DUMP(desc, m) \
197 print_hex_dump(KERN_ERR, (m), \
198 DUMP_PREFIX_ADDRESS, 16, 8, (desc), 32, 0)
199
200#define to_dma_desc_sw(tx) \
201 container_of(tx, struct xgene_dma_desc_sw, tx)
202#define to_dma_chan(dchan) \
203 container_of(dchan, struct xgene_dma_chan, dma_chan)
204
205#define chan_dbg(chan, fmt, arg...) \
206 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
207#define chan_err(chan, fmt, arg...) \
208 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
209
210struct xgene_dma_desc_hw {
6d0767c1
RPS		 211 __le64 m0;
212 __le64 m1;
213 __le64 m2;
214 __le64 m3;
9f2fd0df
RPS		 215};
216
217enum xgene_dma_ring_cfgsize {
218 XGENE_DMA_RING_CFG_SIZE_512B,
219 XGENE_DMA_RING_CFG_SIZE_2KB,
220 XGENE_DMA_RING_CFG_SIZE_16KB,
221 XGENE_DMA_RING_CFG_SIZE_64KB,
222 XGENE_DMA_RING_CFG_SIZE_512KB,
223 XGENE_DMA_RING_CFG_SIZE_INVALID
224};
225
226struct xgene_dma_ring {
227 struct xgene_dma *pdma;
228 u8 buf_num;
229 u16 id;
230 u16 num;
231 u16 head;
232 u16 owner;
233 u16 slots;
234 u16 dst_ring_num;
235 u32 size;
236 void __iomem *cmd;
237 void __iomem *cmd_base;
238 dma_addr_t desc_paddr;
239 u32 state[XGENE_DMA_RING_NUM_CONFIG];
240 enum xgene_dma_ring_cfgsize cfgsize;
241 union {
242 void *desc_vaddr;
243 struct xgene_dma_desc_hw *desc_hw;
244 };
245};
246
247struct xgene_dma_desc_sw {
248 struct xgene_dma_desc_hw desc1;
249 struct xgene_dma_desc_hw desc2;
250 u32 flags;
251 struct list_head node;
252 struct list_head tx_list;
253 struct dma_async_tx_descriptor tx;
254};
255
256/**
257 * struct xgene_dma_chan - internal representation of an X-Gene DMA channel
258 * @dma_chan: dmaengine channel object member
259 * @pdma: X-Gene DMA device structure reference
260 * @dev: struct device reference for dma mapping api
261 * @id: raw id of this channel
262 * @rx_irq: channel IRQ
263 * @name: name of X-Gene DMA channel
264 * @lock: serializes enqueue/dequeue operations to the descriptor pool
265 * @pending: number of transaction request pushed to DMA controller for
266 * execution, but still waiting for completion,
267 * @max_outstanding: max number of outstanding request we can push to channel
268 * @ld_pending: descriptors which are queued to run, but have not yet been
269 * submitted to the hardware for execution
270 * @ld_running: descriptors which are currently being executing by the hardware
271 * @ld_completed: descriptors which have finished execution by the hardware.
272 * These descriptors have already had their cleanup actions run. They
273 * are waiting for the ACK bit to be set by the async tx API.
274 * @desc_pool: descriptor pool for DMA operations
275 * @tasklet: bottom half where all completed descriptors cleans
276 * @tx_ring: transmit ring descriptor that we use to prepare actual
277 * descriptors for further executions
278 * @rx_ring: receive ring descriptor that we use to get completed DMA
279 * descriptors during cleanup time
280 */
281struct xgene_dma_chan {
282 struct dma_chan dma_chan;
283 struct xgene_dma *pdma;
284 struct device *dev;
285 int id;
286 int rx_irq;
ed1f0418 287 char name[10];
9f2fd0df
RPS		 288 spinlock_t lock;
289 int pending;
290 int max_outstanding;
291 struct list_head ld_pending;
292 struct list_head ld_running;
293 struct list_head ld_completed;
294 struct dma_pool *desc_pool;
295 struct tasklet_struct tasklet;
296 struct xgene_dma_ring tx_ring;
297 struct xgene_dma_ring rx_ring;
298};
299
300/**
301 * struct xgene_dma - internal representation of an X-Gene DMA device
302 * @err_irq: DMA error irq number
303 * @ring_num: start id number for DMA ring
304 * @csr_dma: base for DMA register access
305 * @csr_ring: base for DMA ring register access
306 * @csr_ring_cmd: base for DMA ring command register access
307 * @csr_efuse: base for efuse register access
308 * @dma_dev: embedded struct dma_device
309 * @chan: reference to X-Gene DMA channels
310 */
311struct xgene_dma {
312 struct device *dev;
313 struct clk *clk;
314 int err_irq;
315 int ring_num;
316 void __iomem *csr_dma;
317 void __iomem *csr_ring;
318 void __iomem *csr_ring_cmd;
319 void __iomem *csr_efuse;
320 struct dma_device dma_dev[XGENE_DMA_MAX_CHANNEL];
321 struct xgene_dma_chan chan[XGENE_DMA_MAX_CHANNEL];
322};
323
324static const char * const xgene_dma_desc_err[] = {
325 [ERR_DESC_AXI] = "AXI error when reading src/dst link list",
326 [ERR_BAD_DESC] = "ERR or El_ERR fields not set to zero in desc",
327 [ERR_READ_DATA_AXI] = "AXI error when reading data",
328 [ERR_WRITE_DATA_AXI] = "AXI error when writing data",
329 [ERR_FBP_TIMEOUT] = "Timeout on bufpool fetch",
330 [ERR_ECC] = "ECC double bit error",
331 [ERR_DIFF_SIZE] = "Bufpool too small to hold all the DIF result",
332 [ERR_SCT_GAT_LEN] = "Gather and scatter data length not same",
333 [ERR_CRC_ERR] = "CRC error",
334 [ERR_CHKSUM] = "Checksum error",
335 [ERR_DIF] = "DIF error",
336};
337
338static const char * const xgene_dma_err[] = {
339 [ERR_DIF_SIZE_INT] = "DIF size error",
340 [ERR_GS_ERR_INT] = "Gather scatter not same size error",
341 [ERR_FPB_TIMEO_INT] = "Free pool time out error",
342 [ERR_WFIFO_OVF_INT] = "Write FIFO over flow error",
343 [ERR_RFIFO_OVF_INT] = "Read FIFO over flow error",
344 [ERR_WR_TIMEO_INT] = "Write time out error",
345 [ERR_RD_TIMEO_INT] = "Read time out error",
346 [ERR_WR_ERR_INT] = "HBF bus write error",
347 [ERR_RD_ERR_INT] = "HBF bus read error",
348 [ERR_BAD_DESC_INT] = "Ring descriptor HE0 not set error",
349 [ERR_DESC_DST_INT] = "HFB reading dst link address error",
350 [ERR_DESC_SRC_INT] = "HFB reading src link address error",
351};
352
353static bool is_pq_enabled(struct xgene_dma *pdma)
354{
355 u32 val;
356
357 val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW);
358 return !(val & XGENE_DMA_PQ_DISABLE_MASK);
359}
360
6d0767c1 361static u64 xgene_dma_encode_len(size_t len)
9f2fd0df
RPS		 362{
363 return (len < XGENE_DMA_MAX_BYTE_CNT) ?
6d0767c1
RPS		 364 ((u64)len << XGENE_DMA_DESC_BUFLEN_POS) :
365 XGENE_DMA_16K_BUFFER_LEN_CODE;
9f2fd0df
RPS		 366}
367
368static u8 xgene_dma_encode_xor_flyby(u32 src_cnt)
369{
370 static u8 flyby_type[] = {
371 FLYBY_2SRC_XOR, /* Dummy */
372 FLYBY_2SRC_XOR, /* Dummy */
373 FLYBY_2SRC_XOR,
374 FLYBY_3SRC_XOR,
375 FLYBY_4SRC_XOR,
376 FLYBY_5SRC_XOR
377 };
378
379 return flyby_type[src_cnt];
380}
381
382static u32 xgene_dma_ring_desc_cnt(struct xgene_dma_ring *ring)
383{
384 u32 __iomem *cmd_base = ring->cmd_base;
385 u32 ring_state = ioread32(&cmd_base[1]);
386
387 return XGENE_DMA_RING_DESC_CNT(ring_state);
388}
389
6d0767c1 390static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len,
9f2fd0df
RPS		 391 dma_addr_t *paddr)
392{
393 size_t nbytes = (*len < XGENE_DMA_MAX_BYTE_CNT) ?
394 *len : XGENE_DMA_MAX_BYTE_CNT;
395
6d0767c1
RPS		 396 *ext8 |= cpu_to_le64(*paddr);
397 *ext8 |= cpu_to_le64(xgene_dma_encode_len(nbytes));
9f2fd0df
RPS		 398 *len -= nbytes;
399 *paddr += nbytes;
400}
401
6d0767c1 402static void xgene_dma_invalidate_buffer(__le64 *ext8)
9f2fd0df 403{
6d0767c1 404 *ext8 |= cpu_to_le64(XGENE_DMA_INVALID_LEN_CODE);
9f2fd0df
RPS		 405}
406
6d0767c1 407static __le64 *xgene_dma_lookup_ext8(struct xgene_dma_desc_hw *desc, int idx)
9f2fd0df 408{
6d0767c1
RPS		 409 switch (idx) {
410 case 0:
411 return &desc->m1;
412 case 1:
413 return &desc->m0;
414 case 2:
415 return &desc->m3;
416 case 3:
417 return &desc->m2;
418 default:
419 pr_err("Invalid dma descriptor index\n");
420 }
421
422 return NULL;
9f2fd0df
RPS		 423}
424
6d0767c1
RPS		 425static void xgene_dma_init_desc(struct xgene_dma_desc_hw *desc,
426 u16 dst_ring_num)
9f2fd0df 427{
6d0767c1
RPS		 428 desc->m0 |= cpu_to_le64(XGENE_DMA_DESC_IN_BIT);
429 desc->m0 |= cpu_to_le64((u64)XGENE_DMA_RING_OWNER_DMA <<
430 XGENE_DMA_DESC_RTYPE_POS);
431 desc->m1 |= cpu_to_le64(XGENE_DMA_DESC_C_BIT);
432 desc->m3 |= cpu_to_le64((u64)dst_ring_num <<
433 XGENE_DMA_DESC_HOENQ_NUM_POS);
9f2fd0df
RPS		 434}
435
436static void xgene_dma_prep_cpy_desc(struct xgene_dma_chan *chan,
437 struct xgene_dma_desc_sw *desc_sw,
438 dma_addr_t dst, dma_addr_t src,
439 size_t len)
440{
6d0767c1 441 struct xgene_dma_desc_hw *desc1, *desc2;
9f2fd0df
RPS		 442 int i;
443
444 /* Get 1st descriptor */
445 desc1 = &desc_sw->desc1;
446 xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num);
447
448 /* Set destination address */
6d0767c1
RPS		 449 desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT);
450 desc1->m3 |= cpu_to_le64(dst);
9f2fd0df
RPS		 451
452 /* Set 1st source address */
6d0767c1 453 xgene_dma_set_src_buffer(&desc1->m1, &len, &src);
9f2fd0df 454
6d0767c1
RPS		 455 if (!len)
456 return;
9f2fd0df
RPS		 457
458 /*
459 * We need to split this source buffer,
460 * and need to use 2nd descriptor
461 */
462 desc2 = &desc_sw->desc2;
6d0767c1 463 desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT);
9f2fd0df
RPS		 464
465 /* Set 2nd to 5th source address */
466 for (i = 0; i < 4 && len; i++)
467 xgene_dma_set_src_buffer(xgene_dma_lookup_ext8(desc2, i),
468 &len, &src);
469
470 /* Invalidate unused source address field */
471 for (; i < 4; i++)
472 xgene_dma_invalidate_buffer(xgene_dma_lookup_ext8(desc2, i));
473
474 /* Updated flag that we have prepared 64B descriptor */
475 desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC;
9f2fd0df
RPS		 476}
477
478static void xgene_dma_prep_xor_desc(struct xgene_dma_chan *chan,
479 struct xgene_dma_desc_sw *desc_sw,
480 dma_addr_t *dst, dma_addr_t *src,
481 u32 src_cnt, size_t *nbytes,
482 const u8 *scf)
483{
6d0767c1 484 struct xgene_dma_desc_hw *desc1, *desc2;
9f2fd0df
RPS		 485 size_t len = *nbytes;
486 int i;
487
488 desc1 = &desc_sw->desc1;
489 desc2 = &desc_sw->desc2;
490
491 /* Initialize DMA descriptor */
492 xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num);
493
494 /* Set destination address */
6d0767c1
RPS		 495 desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT);
496 desc1->m3 |= cpu_to_le64(*dst);
9f2fd0df
RPS		 497
498 /* We have multiple source addresses, so need to set NV bit*/
6d0767c1 499 desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT);
9f2fd0df
RPS		 500
501 /* Set flyby opcode */
6d0767c1 502 desc1->m2 |= cpu_to_le64(xgene_dma_encode_xor_flyby(src_cnt));
9f2fd0df
RPS		 503
504 /* Set 1st to 5th source addresses */
505 for (i = 0; i < src_cnt; i++) {
506 len = *nbytes;
6d0767c1 507 xgene_dma_set_src_buffer((i == 0) ? &desc1->m1 :
9f2fd0df
RPS		 508 xgene_dma_lookup_ext8(desc2, i - 1),
509 &len, &src[i]);
6d0767c1 510 desc1->m2 |= cpu_to_le64((scf[i] << ((i + 1) * 8)));
9f2fd0df
RPS		 511 }
512
9f2fd0df
RPS		 513 /* Update meta data */
514 *nbytes = len;
515 *dst += XGENE_DMA_MAX_BYTE_CNT;
516
517 /* We need always 64B descriptor to perform xor or pq operations */
518 desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC;
519}
520
521static dma_cookie_t xgene_dma_tx_submit(struct dma_async_tx_descriptor *tx)
522{
523 struct xgene_dma_desc_sw *desc;
524 struct xgene_dma_chan *chan;
525 dma_cookie_t cookie;
526
527 if (unlikely(!tx))
528 return -EINVAL;
529
530 chan = to_dma_chan(tx->chan);
531 desc = to_dma_desc_sw(tx);
532
533 spin_lock_bh(&chan->lock);
534
535 cookie = dma_cookie_assign(tx);
536
537 /* Add this transaction list onto the tail of the pending queue */
538 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
539
540 spin_unlock_bh(&chan->lock);
541
542 return cookie;
543}
544
545static void xgene_dma_clean_descriptor(struct xgene_dma_chan *chan,
546 struct xgene_dma_desc_sw *desc)
547{
548 list_del(&desc->node);
549 chan_dbg(chan, "LD %p free\n", desc);
550 dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
551}
552
553static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor(
554 struct xgene_dma_chan *chan)
555{
556 struct xgene_dma_desc_sw *desc;
557 dma_addr_t phys;
558
559 desc = dma_pool_alloc(chan->desc_pool, GFP_NOWAIT, &phys);
560 if (!desc) {
561 chan_err(chan, "Failed to allocate LDs\n");
562 return NULL;
563 }
564
565 memset(desc, 0, sizeof(*desc));
566
567 INIT_LIST_HEAD(&desc->tx_list);
568 desc->tx.phys = phys;
569 desc->tx.tx_submit = xgene_dma_tx_submit;
570 dma_async_tx_descriptor_init(&desc->tx, &chan->dma_chan);
571
572 chan_dbg(chan, "LD %p allocated\n", desc);
573
574 return desc;
575}
576
577/**
578 * xgene_dma_clean_completed_descriptor - free all descriptors which
579 * has been completed and acked
580 * @chan: X-Gene DMA channel
581 *
582 * This function is used on all completed and acked descriptors.
583 */
584static void xgene_dma_clean_completed_descriptor(struct xgene_dma_chan *chan)
585{
586 struct xgene_dma_desc_sw *desc, *_desc;
587
588 /* Run the callback for each descriptor, in order */
589 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) {
590 if (async_tx_test_ack(&desc->tx))
591 xgene_dma_clean_descriptor(chan, desc);
592 }
593}
594
595/**
596 * xgene_dma_run_tx_complete_actions - cleanup a single link descriptor
597 * @chan: X-Gene DMA channel
598 * @desc: descriptor to cleanup and free
599 *
600 * This function is used on a descriptor which has been executed by the DMA
601 * controller. It will run any callbacks, submit any dependencies.
602 */
603static void xgene_dma_run_tx_complete_actions(struct xgene_dma_chan *chan,
604 struct xgene_dma_desc_sw *desc)
605{
606 struct dma_async_tx_descriptor *tx = &desc->tx;
607
608 /*
609 * If this is not the last transaction in the group,
610 * then no need to complete cookie and run any callback as
611 * this is not the tx_descriptor which had been sent to caller
612 * of this DMA request
613 */
614
615 if (tx->cookie == 0)
616 return;
617
618 dma_cookie_complete(tx);
619
620 /* Run the link descriptor callback function */
621 if (tx->callback)
622 tx->callback(tx->callback_param);
623
624 dma_descriptor_unmap(tx);
625
626 /* Run any dependencies */
627 dma_run_dependencies(tx);
628}
629
630/**
631 * xgene_dma_clean_running_descriptor - move the completed descriptor from
632 * ld_running to ld_completed
633 * @chan: X-Gene DMA channel
634 * @desc: the descriptor which is completed
635 *
636 * Free the descriptor directly if acked by async_tx api,
637 * else move it to queue ld_completed.
638 */
639static void xgene_dma_clean_running_descriptor(struct xgene_dma_chan *chan,
640 struct xgene_dma_desc_sw *desc)
641{
642 /* Remove from the list of running transactions */
643 list_del(&desc->node);
644
645 /*
646 * the client is allowed to attach dependent operations
647 * until 'ack' is set
648 */
649 if (!async_tx_test_ack(&desc->tx)) {
650 /*
651 * Move this descriptor to the list of descriptors which is
652 * completed, but still awaiting the 'ack' bit to be set.
653 */
654 list_add_tail(&desc->node, &chan->ld_completed);
655 return;
656 }
657
658 chan_dbg(chan, "LD %p free\n", desc);
659 dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
660}
661
662static int xgene_chan_xfer_request(struct xgene_dma_ring *ring,
663 struct xgene_dma_desc_sw *desc_sw)
664{
665 struct xgene_dma_desc_hw *desc_hw;
666
667 /* Check if can push more descriptor to hw for execution */
668 if (xgene_dma_ring_desc_cnt(ring) > (ring->slots - 2))
669 return -EBUSY;
670
671 /* Get hw descriptor from DMA tx ring */
672 desc_hw = &ring->desc_hw[ring->head];
673
674 /*
675 * Increment the head count to point next
676 * descriptor for next time
677 */
678 if (++ring->head == ring->slots)
679 ring->head = 0;
680
681 /* Copy prepared sw descriptor data to hw descriptor */
682 memcpy(desc_hw, &desc_sw->desc1, sizeof(*desc_hw));
683
684 /*
685 * Check if we have prepared 64B descriptor,
686 * in this case we need one more hw descriptor
687 */
688 if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) {
689 desc_hw = &ring->desc_hw[ring->head];
690
691 if (++ring->head == ring->slots)
692 ring->head = 0;
693
694 memcpy(desc_hw, &desc_sw->desc2, sizeof(*desc_hw));
695 }
696
697 /* Notify the hw that we have descriptor ready for execution */
698 iowrite32((desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) ?
699 2 : 1, ring->cmd);
700
701 return 0;
702}
703
704/**
705 * xgene_chan_xfer_ld_pending - push any pending transactions to hw
706 * @chan : X-Gene DMA channel
707 *
6d0767c1 708 * LOCKING: must hold chan->lock
9f2fd0df
RPS		 709 */
710static void xgene_chan_xfer_ld_pending(struct xgene_dma_chan *chan)
711{
712 struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
713 int ret;
714
715 /*
716 * If the list of pending descriptors is empty, then we
717 * don't need to do any work at all
718 */
719 if (list_empty(&chan->ld_pending)) {
720 chan_dbg(chan, "No pending LDs\n");
721 return;
722 }
723
724 /*
725 * Move elements from the queue of pending transactions onto the list
726 * of running transactions and push it to hw for further executions
727 */
728 list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_pending, node) {
729 /*
730 * Check if have pushed max number of transactions to hw
731 * as capable, so let's stop here and will push remaining
732 * elements from pening ld queue after completing some
733 * descriptors that we have already pushed
734 */
735 if (chan->pending >= chan->max_outstanding)
736 return;
737
738 ret = xgene_chan_xfer_request(&chan->tx_ring, desc_sw);
739 if (ret)
740 return;
741
742 /*
743 * Delete this element from ld pending queue and append it to
744 * ld running queue
745 */
746 list_move_tail(&desc_sw->node, &chan->ld_running);
747
748 /* Increment the pending transaction count */
749 chan->pending++;
750 }
751}
752
753/**
754 * xgene_dma_cleanup_descriptors - cleanup link descriptors which are completed
755 * and move them to ld_completed to free until flag 'ack' is set
756 * @chan: X-Gene DMA channel
757 *
758 * This function is used on descriptors which have been executed by the DMA
759 * controller. It will run any callbacks, submit any dependencies, then
760 * free these descriptors if flag 'ack' is set.
761 */
762static void xgene_dma_cleanup_descriptors(struct xgene_dma_chan *chan)
763{
764 struct xgene_dma_ring *ring = &chan->rx_ring;
765 struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
766 struct xgene_dma_desc_hw *desc_hw;
767 u8 status;
768
769 /* Clean already completed and acked descriptors */
770 xgene_dma_clean_completed_descriptor(chan);
771
772 /* Run the callback for each descriptor, in order */
773 list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_running, node) {
774 /* Get subsequent hw descriptor from DMA rx ring */
775 desc_hw = &ring->desc_hw[ring->head];
776
777 /* Check if this descriptor has been completed */
6d0767c1
RPS		 778 if (unlikely(le64_to_cpu(desc_hw->m0) ==
779 XGENE_DMA_DESC_EMPTY_SIGNATURE))
9f2fd0df
RPS		 780 break;
781
782 if (++ring->head == ring->slots)
783 ring->head = 0;
784
785 /* Check if we have any error with DMA transactions */
786 status = XGENE_DMA_DESC_STATUS(
787 XGENE_DMA_DESC_ELERR_RD(le64_to_cpu(
788 desc_hw->m0)),
789 XGENE_DMA_DESC_LERR_RD(le64_to_cpu(
790 desc_hw->m0)));
791 if (status) {
792 /* Print the DMA error type */
793 chan_err(chan, "%s\n", xgene_dma_desc_err[status]);
794
795 /*
796 * We have DMA transactions error here. Dump DMA Tx
797 * and Rx descriptors for this request */
798 XGENE_DMA_DESC_DUMP(&desc_sw->desc1,
799 "X-Gene DMA TX DESC1: ");
800
801 if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC)
802 XGENE_DMA_DESC_DUMP(&desc_sw->desc2,
803 "X-Gene DMA TX DESC2: ");
804
805 XGENE_DMA_DESC_DUMP(desc_hw,
806 "X-Gene DMA RX ERR DESC: ");
807 }
808
809 /* Notify the hw about this completed descriptor */
810 iowrite32(-1, ring->cmd);
811
812 /* Mark this hw descriptor as processed */
6d0767c1 813 desc_hw->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
9f2fd0df
RPS		 814
815 xgene_dma_run_tx_complete_actions(chan, desc_sw);
816
817 xgene_dma_clean_running_descriptor(chan, desc_sw);
818
819 /*
820 * Decrement the pending transaction count
821 * as we have processed one
822 */
823 chan->pending--;
824 }
825
826 /*
827 * Start any pending transactions automatically
828 * In the ideal case, we keep the DMA controller busy while we go
829 * ahead and free the descriptors below.
830 */
831 xgene_chan_xfer_ld_pending(chan);
832}
833
834static int xgene_dma_alloc_chan_resources(struct dma_chan *dchan)
835{
836 struct xgene_dma_chan *chan = to_dma_chan(dchan);
837
838 /* Has this channel already been allocated? */
839 if (chan->desc_pool)
840 return 1;
841
842 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
843 sizeof(struct xgene_dma_desc_sw),
844 0, 0);
845 if (!chan->desc_pool) {
846 chan_err(chan, "Failed to allocate descriptor pool\n");
847 return -ENOMEM;
848 }
849
850 chan_dbg(chan, "Allocate descripto pool\n");
851
852 return 1;
853}
854
855/**
856 * xgene_dma_free_desc_list - Free all descriptors in a queue
857 * @chan: X-Gene DMA channel
858 * @list: the list to free
859 *
6d0767c1 860 * LOCKING: must hold chan->lock
9f2fd0df
RPS		 861 */
862static void xgene_dma_free_desc_list(struct xgene_dma_chan *chan,
863 struct list_head *list)
864{
865 struct xgene_dma_desc_sw *desc, *_desc;
866
867 list_for_each_entry_safe(desc, _desc, list, node)
868 xgene_dma_clean_descriptor(chan, desc);
869}
870
9f2fd0df
RPS		 871static void xgene_dma_free_chan_resources(struct dma_chan *dchan)
872{
873 struct xgene_dma_chan *chan = to_dma_chan(dchan);
874
875 chan_dbg(chan, "Free all resources\n");
876
877 if (!chan->desc_pool)
878 return;
879
880 spin_lock_bh(&chan->lock);
881
882 /* Process all running descriptor */
883 xgene_dma_cleanup_descriptors(chan);
884
885 /* Clean all link descriptor queues */
886 xgene_dma_free_desc_list(chan, &chan->ld_pending);
887 xgene_dma_free_desc_list(chan, &chan->ld_running);
888 xgene_dma_free_desc_list(chan, &chan->ld_completed);
889
890 spin_unlock_bh(&chan->lock);
891
892 /* Delete this channel DMA pool */
893 dma_pool_destroy(chan->desc_pool);
894 chan->desc_pool = NULL;
895}
896
897static struct dma_async_tx_descriptor *xgene_dma_prep_memcpy(
898 struct dma_chan *dchan, dma_addr_t dst, dma_addr_t src,
899 size_t len, unsigned long flags)
900{
901 struct xgene_dma_desc_sw *first = NULL, *new;
902 struct xgene_dma_chan *chan;
903 size_t copy;
904
905 if (unlikely(!dchan || !len))
906 return NULL;
907
908 chan = to_dma_chan(dchan);
909
910 do {
911 /* Allocate the link descriptor from DMA pool */
912 new = xgene_dma_alloc_descriptor(chan);
913 if (!new)
914 goto fail;
915
916 /* Create the largest transaction possible */
917 copy = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT);
918
919 /* Prepare DMA descriptor */
920 xgene_dma_prep_cpy_desc(chan, new, dst, src, copy);
921
922 if (!first)
923 first = new;
924
925 new->tx.cookie = 0;
926 async_tx_ack(&new->tx);
927
928 /* Update metadata */
929 len -= copy;
930 dst += copy;
931 src += copy;
932
933 /* Insert the link descriptor to the LD ring */
934 list_add_tail(&new->node, &first->tx_list);
935 } while (len);
936
937 new->tx.flags = flags; /* client is in control of this ack */
938 new->tx.cookie = -EBUSY;
939 list_splice(&first->tx_list, &new->tx_list);
940
941 return &new->tx;
942
943fail:
944 if (!first)
945 return NULL;
946
6d0767c1 947 xgene_dma_free_desc_list(chan, &first->tx_list);
9f2fd0df
RPS		 948 return NULL;
949}
950
951static struct dma_async_tx_descriptor *xgene_dma_prep_sg(
952 struct dma_chan *dchan, struct scatterlist *dst_sg,
953 u32 dst_nents, struct scatterlist *src_sg,
954 u32 src_nents, unsigned long flags)
955{
956 struct xgene_dma_desc_sw *first = NULL, *new = NULL;
957 struct xgene_dma_chan *chan;
958 size_t dst_avail, src_avail;
959 dma_addr_t dst, src;
960 size_t len;
961
962 if (unlikely(!dchan))
963 return NULL;
964
965 if (unlikely(!dst_nents || !src_nents))
966 return NULL;
967
968 if (unlikely(!dst_sg || !src_sg))
969 return NULL;
970
971 chan = to_dma_chan(dchan);
972
973 /* Get prepared for the loop */
974 dst_avail = sg_dma_len(dst_sg);
975 src_avail = sg_dma_len(src_sg);
976 dst_nents--;
977 src_nents--;
978
979 /* Run until we are out of scatterlist entries */
980 while (true) {
981 /* Create the largest transaction possible */
982 len = min_t(size_t, src_avail, dst_avail);
983 len = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT);
984 if (len == 0)
985 goto fetch;
986
987 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
988 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
989
990 /* Allocate the link descriptor from DMA pool */
991 new = xgene_dma_alloc_descriptor(chan);
992 if (!new)
993 goto fail;
994
995 /* Prepare DMA descriptor */
996 xgene_dma_prep_cpy_desc(chan, new, dst, src, len);
997
998 if (!first)
999 first = new;
1000
1001 new->tx.cookie = 0;
1002 async_tx_ack(&new->tx);
1003
1004 /* update metadata */
1005 dst_avail -= len;
1006 src_avail -= len;
1007
1008 /* Insert the link descriptor to the LD ring */
1009 list_add_tail(&new->node, &first->tx_list);
1010
1011fetch:
1012 /* fetch the next dst scatterlist entry */
1013 if (dst_avail == 0) {
1014 /* no more entries: we're done */
1015 if (dst_nents == 0)
1016 break;
1017
1018 /* fetch the next entry: if there are no more: done */
1019 dst_sg = sg_next(dst_sg);
1020 if (!dst_sg)
1021 break;
1022
1023 dst_nents--;
1024 dst_avail = sg_dma_len(dst_sg);
1025 }
1026
1027 /* fetch the next src scatterlist entry */
1028 if (src_avail == 0) {
1029 /* no more entries: we're done */
1030 if (src_nents == 0)
1031 break;
1032
1033 /* fetch the next entry: if there are no more: done */
1034 src_sg = sg_next(src_sg);
1035 if (!src_sg)
1036 break;
1037
1038 src_nents--;
1039 src_avail = sg_dma_len(src_sg);
1040 }
1041 }
1042
1043 if (!new)
1044 return NULL;
1045
1046 new->tx.flags = flags; /* client is in control of this ack */
1047 new->tx.cookie = -EBUSY;
1048 list_splice(&first->tx_list, &new->tx_list);
1049
1050 return &new->tx;
1051fail:
1052 if (!first)
1053 return NULL;
1054
6d0767c1 1055 xgene_dma_free_desc_list(chan, &first->tx_list);
9f2fd0df
RPS		 1056 return NULL;
1057}
1058
1059static struct dma_async_tx_descriptor *xgene_dma_prep_xor(
1060 struct dma_chan *dchan, dma_addr_t dst, dma_addr_t *src,
1061 u32 src_cnt, size_t len, unsigned long flags)
1062{
1063 struct xgene_dma_desc_sw *first = NULL, *new;
1064 struct xgene_dma_chan *chan;
1065 static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {
1066 0x01, 0x01, 0x01, 0x01, 0x01};
1067
1068 if (unlikely(!dchan || !len))
1069 return NULL;
1070
1071 chan = to_dma_chan(dchan);
1072
1073 do {
1074 /* Allocate the link descriptor from DMA pool */
1075 new = xgene_dma_alloc_descriptor(chan);
1076 if (!new)
1077 goto fail;
1078
1079 /* Prepare xor DMA descriptor */
1080 xgene_dma_prep_xor_desc(chan, new, &dst, src,
1081 src_cnt, &len, multi);
1082
1083 if (!first)
1084 first = new;
1085
1086 new->tx.cookie = 0;
1087 async_tx_ack(&new->tx);
1088
1089 /* Insert the link descriptor to the LD ring */
1090 list_add_tail(&new->node, &first->tx_list);
1091 } while (len);
1092
1093 new->tx.flags = flags; /* client is in control of this ack */
1094 new->tx.cookie = -EBUSY;
1095 list_splice(&first->tx_list, &new->tx_list);
1096
1097 return &new->tx;
1098
1099fail:
1100 if (!first)
1101 return NULL;
1102
6d0767c1 1103 xgene_dma_free_desc_list(chan, &first->tx_list);
9f2fd0df
RPS		 1104 return NULL;
1105}
1106
1107static struct dma_async_tx_descriptor *xgene_dma_prep_pq(
1108 struct dma_chan *dchan, dma_addr_t *dst, dma_addr_t *src,
1109 u32 src_cnt, const u8 *scf, size_t len, unsigned long flags)
1110{
1111 struct xgene_dma_desc_sw *first = NULL, *new;
1112 struct xgene_dma_chan *chan;
1113 size_t _len = len;
1114 dma_addr_t _src[XGENE_DMA_MAX_XOR_SRC];
1115 static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {0x01, 0x01, 0x01, 0x01, 0x01};
1116
1117 if (unlikely(!dchan || !len))
1118 return NULL;
1119
1120 chan = to_dma_chan(dchan);
1121
1122 /*
1123 * Save source addresses on local variable, may be we have to
1124 * prepare two descriptor to generate P and Q if both enabled
1125 * in the flags by client
1126 */
1127 memcpy(_src, src, sizeof(*src) * src_cnt);
1128
1129 if (flags & DMA_PREP_PQ_DISABLE_P)
1130 len = 0;
1131
1132 if (flags & DMA_PREP_PQ_DISABLE_Q)
1133 _len = 0;
1134
1135 do {
1136 /* Allocate the link descriptor from DMA pool */
1137 new = xgene_dma_alloc_descriptor(chan);
1138 if (!new)
1139 goto fail;
1140
1141 if (!first)
1142 first = new;
1143
1144 new->tx.cookie = 0;
1145 async_tx_ack(&new->tx);
1146
1147 /* Insert the link descriptor to the LD ring */
1148 list_add_tail(&new->node, &first->tx_list);
1149
1150 /*
1151 * Prepare DMA descriptor to generate P,
1152 * if DMA_PREP_PQ_DISABLE_P flag is not set
1153 */
1154 if (len) {
1155 xgene_dma_prep_xor_desc(chan, new, &dst[0], src,
1156 src_cnt, &len, multi);
1157 continue;
1158 }
1159
1160 /*
1161 * Prepare DMA descriptor to generate Q,
1162 * if DMA_PREP_PQ_DISABLE_Q flag is not set
1163 */
1164 if (_len) {
1165 xgene_dma_prep_xor_desc(chan, new, &dst[1], _src,
1166 src_cnt, &_len, scf);
1167 }
1168 } while (len || _len);
1169
1170 new->tx.flags = flags; /* client is in control of this ack */
1171 new->tx.cookie = -EBUSY;
1172 list_splice(&first->tx_list, &new->tx_list);
1173
1174 return &new->tx;
1175
1176fail:
1177 if (!first)
1178 return NULL;
1179
6d0767c1 1180 xgene_dma_free_desc_list(chan, &first->tx_list);
9f2fd0df
RPS		 1181 return NULL;
1182}
1183
1184static void xgene_dma_issue_pending(struct dma_chan *dchan)
1185{
1186 struct xgene_dma_chan *chan = to_dma_chan(dchan);
1187
1188 spin_lock_bh(&chan->lock);
1189 xgene_chan_xfer_ld_pending(chan);
1190 spin_unlock_bh(&chan->lock);
1191}
1192
1193static enum dma_status xgene_dma_tx_status(struct dma_chan *dchan,
1194 dma_cookie_t cookie,
1195 struct dma_tx_state *txstate)
1196{
1197 return dma_cookie_status(dchan, cookie, txstate);
1198}
1199
1200static void xgene_dma_tasklet_cb(unsigned long data)
1201{
1202 struct xgene_dma_chan *chan = (struct xgene_dma_chan *)data;
1203
1204 spin_lock_bh(&chan->lock);
1205
1206 /* Run all cleanup for descriptors which have been completed */
1207 xgene_dma_cleanup_descriptors(chan);
1208
1209 /* Re-enable DMA channel IRQ */
1210 enable_irq(chan->rx_irq);
1211
1212 spin_unlock_bh(&chan->lock);
1213}
1214
1215static irqreturn_t xgene_dma_chan_ring_isr(int irq, void *id)
1216{
1217 struct xgene_dma_chan *chan = (struct xgene_dma_chan *)id;
1218
1219 BUG_ON(!chan);
1220
1221 /*
1222 * Disable DMA channel IRQ until we process completed
1223 * descriptors
1224 */
1225 disable_irq_nosync(chan->rx_irq);
1226
1227 /*
1228 * Schedule the tasklet to handle all cleanup of the current
1229 * transaction. It will start a new transaction if there is
1230 * one pending.
1231 */
1232 tasklet_schedule(&chan->tasklet);
1233
1234 return IRQ_HANDLED;
1235}
1236
1237static irqreturn_t xgene_dma_err_isr(int irq, void *id)
1238{
1239 struct xgene_dma *pdma = (struct xgene_dma *)id;
1240 unsigned long int_mask;
1241 u32 val, i;
1242
1243 val = ioread32(pdma->csr_dma + XGENE_DMA_INT);
1244
1245 /* Clear DMA interrupts */
1246 iowrite32(val, pdma->csr_dma + XGENE_DMA_INT);
1247
1248 /* Print DMA error info */
1249 int_mask = val >> XGENE_DMA_INT_MASK_SHIFT;
1250 for_each_set_bit(i, &int_mask, ARRAY_SIZE(xgene_dma_err))
1251 dev_err(pdma->dev,
1252 "Interrupt status 0x%08X %s\n", val, xgene_dma_err[i]);
1253
1254 return IRQ_HANDLED;
1255}
1256
1257static void xgene_dma_wr_ring_state(struct xgene_dma_ring *ring)
1258{
1259 int i;
1260
1261 iowrite32(ring->num, ring->pdma->csr_ring + XGENE_DMA_RING_STATE);
1262
1263 for (i = 0; i < XGENE_DMA_RING_NUM_CONFIG; i++)
1264 iowrite32(ring->state[i], ring->pdma->csr_ring +
1265 XGENE_DMA_RING_STATE_WR_BASE + (i * 4));
1266}
1267
1268static void xgene_dma_clr_ring_state(struct xgene_dma_ring *ring)
1269{
1270 memset(ring->state, 0, sizeof(u32) * XGENE_DMA_RING_NUM_CONFIG);
1271 xgene_dma_wr_ring_state(ring);
1272}
1273
1274static void xgene_dma_setup_ring(struct xgene_dma_ring *ring)
1275{
1276 void *ring_cfg = ring->state;
1277 u64 addr = ring->desc_paddr;
9f2fd0df
RPS		 1278 u32 i, val;
1279
1280 ring->slots = ring->size / XGENE_DMA_RING_WQ_DESC_SIZE;
1281
1282 /* Clear DMA ring state */
1283 xgene_dma_clr_ring_state(ring);
1284
1285 /* Set DMA ring type */
1286 XGENE_DMA_RING_TYPE_SET(ring_cfg, XGENE_DMA_RING_TYPE_REGULAR);
1287
1288 if (ring->owner == XGENE_DMA_RING_OWNER_DMA) {
1289 /* Set recombination buffer and timeout */
1290 XGENE_DMA_RING_RECOMBBUF_SET(ring_cfg);
1291 XGENE_DMA_RING_RECOMTIMEOUTL_SET(ring_cfg);
1292 XGENE_DMA_RING_RECOMTIMEOUTH_SET(ring_cfg);
1293 }
1294
1295 /* Initialize DMA ring state */
1296 XGENE_DMA_RING_SELTHRSH_SET(ring_cfg);
1297 XGENE_DMA_RING_ACCEPTLERR_SET(ring_cfg);
1298 XGENE_DMA_RING_COHERENT_SET(ring_cfg);
1299 XGENE_DMA_RING_ADDRL_SET(ring_cfg, addr);
1300 XGENE_DMA_RING_ADDRH_SET(ring_cfg, addr);
1301 XGENE_DMA_RING_SIZE_SET(ring_cfg, ring->cfgsize);
1302
1303 /* Write DMA ring configurations */
1304 xgene_dma_wr_ring_state(ring);
1305
1306 /* Set DMA ring id */
1307 iowrite32(XGENE_DMA_RING_ID_SETUP(ring->id),
1308 ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1309
1310 /* Set DMA ring buffer */
1311 iowrite32(XGENE_DMA_RING_ID_BUF_SETUP(ring->num),
1312 ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1313
1314 if (ring->owner != XGENE_DMA_RING_OWNER_CPU)
1315 return;
1316
1317 /* Set empty signature to DMA Rx ring descriptors */
1318 for (i = 0; i < ring->slots; i++) {
6d0767c1
RPS		 1319 struct xgene_dma_desc_hw *desc;
1320
9f2fd0df 1321 desc = &ring->desc_hw[i];
6d0767c1 1322 desc->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
9f2fd0df
RPS		 1323 }
1324
1325 /* Enable DMA Rx ring interrupt */
1326 val = ioread32(ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1327 XGENE_DMA_RING_NE_INT_MODE_SET(val, ring->buf_num);
1328 iowrite32(val, ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1329}
1330
1331static void xgene_dma_clear_ring(struct xgene_dma_ring *ring)
1332{
1333 u32 ring_id, val;
1334
1335 if (ring->owner == XGENE_DMA_RING_OWNER_CPU) {
1336 /* Disable DMA Rx ring interrupt */
1337 val = ioread32(ring->pdma->csr_ring +
1338 XGENE_DMA_RING_NE_INT_MODE);
1339 XGENE_DMA_RING_NE_INT_MODE_RESET(val, ring->buf_num);
1340 iowrite32(val, ring->pdma->csr_ring +
1341 XGENE_DMA_RING_NE_INT_MODE);
1342 }
1343
1344 /* Clear DMA ring state */
1345 ring_id = XGENE_DMA_RING_ID_SETUP(ring->id);
1346 iowrite32(ring_id, ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1347
1348 iowrite32(0, ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1349 xgene_dma_clr_ring_state(ring);
1350}
1351
1352static void xgene_dma_set_ring_cmd(struct xgene_dma_ring *ring)
1353{
1354 ring->cmd_base = ring->pdma->csr_ring_cmd +
1355 XGENE_DMA_RING_CMD_BASE_OFFSET((ring->num -
1356 XGENE_DMA_RING_NUM));
1357
1358 ring->cmd = ring->cmd_base + XGENE_DMA_RING_CMD_OFFSET;
1359}
1360
1361static int xgene_dma_get_ring_size(struct xgene_dma_chan *chan,
1362 enum xgene_dma_ring_cfgsize cfgsize)
1363{
1364 int size;
1365
1366 switch (cfgsize) {
1367 case XGENE_DMA_RING_CFG_SIZE_512B:
1368 size = 0x200;
1369 break;
1370 case XGENE_DMA_RING_CFG_SIZE_2KB:
1371 size = 0x800;
1372 break;
1373 case XGENE_DMA_RING_CFG_SIZE_16KB:
1374 size = 0x4000;
1375 break;
1376 case XGENE_DMA_RING_CFG_SIZE_64KB:
1377 size = 0x10000;
1378 break;
1379 case XGENE_DMA_RING_CFG_SIZE_512KB:
1380 size = 0x80000;
1381 break;
1382 default:
1383 chan_err(chan, "Unsupported cfg ring size %d\n", cfgsize);
1384 return -EINVAL;
1385 }
1386
1387 return size;
1388}
1389
1390static void xgene_dma_delete_ring_one(struct xgene_dma_ring *ring)
1391{
1392 /* Clear DMA ring configurations */
1393 xgene_dma_clear_ring(ring);
1394
1395 /* De-allocate DMA ring descriptor */
1396 if (ring->desc_vaddr) {
1397 dma_free_coherent(ring->pdma->dev, ring->size,
1398 ring->desc_vaddr, ring->desc_paddr);
1399 ring->desc_vaddr = NULL;
1400 }
1401}
1402
1403static void xgene_dma_delete_chan_rings(struct xgene_dma_chan *chan)
1404{
1405 xgene_dma_delete_ring_one(&chan->rx_ring);
1406 xgene_dma_delete_ring_one(&chan->tx_ring);
1407}
1408
1409static int xgene_dma_create_ring_one(struct xgene_dma_chan *chan,
1410 struct xgene_dma_ring *ring,
1411 enum xgene_dma_ring_cfgsize cfgsize)
1412{
1413 /* Setup DMA ring descriptor variables */
1414 ring->pdma = chan->pdma;
1415 ring->cfgsize = cfgsize;
1416 ring->num = chan->pdma->ring_num++;
1417 ring->id = XGENE_DMA_RING_ID_GET(ring->owner, ring->buf_num);
1418
1419 ring->size = xgene_dma_get_ring_size(chan, cfgsize);
1420 if (ring->size <= 0)
1421 return ring->size;
1422
1423 /* Allocate memory for DMA ring descriptor */
1424 ring->desc_vaddr = dma_zalloc_coherent(chan->dev, ring->size,
1425 &ring->desc_paddr, GFP_KERNEL);
1426 if (!ring->desc_vaddr) {
1427 chan_err(chan, "Failed to allocate ring desc\n");
1428 return -ENOMEM;
1429 }
1430
1431 /* Configure and enable DMA ring */
1432 xgene_dma_set_ring_cmd(ring);
1433 xgene_dma_setup_ring(ring);
1434
1435 return 0;
1436}
1437
1438static int xgene_dma_create_chan_rings(struct xgene_dma_chan *chan)
1439{
1440 struct xgene_dma_ring *rx_ring = &chan->rx_ring;
1441 struct xgene_dma_ring *tx_ring = &chan->tx_ring;
1442 int ret;
1443
1444 /* Create DMA Rx ring descriptor */
1445 rx_ring->owner = XGENE_DMA_RING_OWNER_CPU;
1446 rx_ring->buf_num = XGENE_DMA_CPU_BUFNUM + chan->id;
1447
1448 ret = xgene_dma_create_ring_one(chan, rx_ring,
1449 XGENE_DMA_RING_CFG_SIZE_64KB);
1450 if (ret)
1451 return ret;
1452
1453 chan_dbg(chan, "Rx ring id 0x%X num %d desc 0x%p\n",
1454 rx_ring->id, rx_ring->num, rx_ring->desc_vaddr);
1455
1456 /* Create DMA Tx ring descriptor */
1457 tx_ring->owner = XGENE_DMA_RING_OWNER_DMA;
1458 tx_ring->buf_num = XGENE_DMA_BUFNUM + chan->id;
1459
1460 ret = xgene_dma_create_ring_one(chan, tx_ring,
1461 XGENE_DMA_RING_CFG_SIZE_64KB);
1462 if (ret) {
1463 xgene_dma_delete_ring_one(rx_ring);
1464 return ret;
1465 }
1466
1467 tx_ring->dst_ring_num = XGENE_DMA_RING_DST_ID(rx_ring->num);
1468
1469 chan_dbg(chan,
1470 "Tx ring id 0x%X num %d desc 0x%p\n",
1471 tx_ring->id, tx_ring->num, tx_ring->desc_vaddr);
1472
1473 /* Set the max outstanding request possible to this channel */
1474 chan->max_outstanding = rx_ring->slots;
1475
1476 return ret;
1477}
1478
1479static int xgene_dma_init_rings(struct xgene_dma *pdma)
1480{
1481 int ret, i, j;
1482
1483 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1484 ret = xgene_dma_create_chan_rings(&pdma->chan[i]);
1485 if (ret) {
1486 for (j = 0; j < i; j++)
1487 xgene_dma_delete_chan_rings(&pdma->chan[j]);
1488 return ret;
1489 }
1490 }
1491
1492 return ret;
1493}
1494
1495static void xgene_dma_enable(struct xgene_dma *pdma)
1496{
1497 u32 val;
1498
1499 /* Configure and enable DMA engine */
1500 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1501 XGENE_DMA_CH_SETUP(val);
1502 XGENE_DMA_ENABLE(val);
1503 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1504}
1505
1506static void xgene_dma_disable(struct xgene_dma *pdma)
1507{
1508 u32 val;
1509
1510 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1511 XGENE_DMA_DISABLE(val);
1512 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1513}
1514
1515static void xgene_dma_mask_interrupts(struct xgene_dma *pdma)
1516{
1517 /*
1518 * Mask DMA ring overflow, underflow and
1519 * AXI write/read error interrupts
1520 */
1521 iowrite32(XGENE_DMA_INT_ALL_MASK,
1522 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1523 iowrite32(XGENE_DMA_INT_ALL_MASK,
1524 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1525 iowrite32(XGENE_DMA_INT_ALL_MASK,
1526 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1527 iowrite32(XGENE_DMA_INT_ALL_MASK,
1528 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1529 iowrite32(XGENE_DMA_INT_ALL_MASK,
1530 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1531
1532 /* Mask DMA error interrupts */
1533 iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK);
1534}
1535
1536static void xgene_dma_unmask_interrupts(struct xgene_dma *pdma)
1537{
1538 /*
1539 * Unmask DMA ring overflow, underflow and
1540 * AXI write/read error interrupts
1541 */
1542 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1543 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1544 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1545 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1546 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1547 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1548 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1549 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1550 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1551 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1552
1553 /* Unmask DMA error interrupts */
1554 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1555 pdma->csr_dma + XGENE_DMA_INT_MASK);
1556}
1557
1558static void xgene_dma_init_hw(struct xgene_dma *pdma)
1559{
1560 u32 val;
1561
1562 /* Associate DMA ring to corresponding ring HW */
1563 iowrite32(XGENE_DMA_ASSOC_RING_MNGR1,
1564 pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC);
1565
1566 /* Configure RAID6 polynomial control setting */
1567 if (is_pq_enabled(pdma))
1568 iowrite32(XGENE_DMA_RAID6_MULTI_CTRL(0x1D),
1569 pdma->csr_dma + XGENE_DMA_RAID6_CONT);
1570 else
1571 dev_info(pdma->dev, "PQ is disabled in HW\n");
1572
1573 xgene_dma_enable(pdma);
1574 xgene_dma_unmask_interrupts(pdma);
1575
1576 /* Get DMA id and version info */
1577 val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR);
1578
1579 /* DMA device info */
1580 dev_info(pdma->dev,
1581 "X-Gene DMA v%d.%02d.%02d driver registered %d channels",
1582 XGENE_DMA_REV_NO_RD(val), XGENE_DMA_BUS_ID_RD(val),
1583 XGENE_DMA_DEV_ID_RD(val), XGENE_DMA_MAX_CHANNEL);
1584}
1585
a3f92e8e 1586static int xgene_dma_init_ring_mngr(struct xgene_dma *pdma)
9f2fd0df
RPS		 1587{
1588 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_CLKEN) &&
1589 (!ioread32(pdma->csr_ring + XGENE_DMA_RING_SRST)))
1590 return 0;
1591
1592 iowrite32(0x3, pdma->csr_ring + XGENE_DMA_RING_CLKEN);
1593 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_SRST);
1594
1595 /* Bring up memory */
1596 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1597
1598 /* Force a barrier */
1599 ioread32(pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1600
1601 /* reset may take up to 1ms */
1602 usleep_range(1000, 1100);
1603
1604 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_BLK_MEM_RDY)
1605 != XGENE_DMA_RING_BLK_MEM_RDY_VAL) {
1606 dev_err(pdma->dev,
1607 "Failed to release ring mngr memory from shutdown\n");
1608 return -ENODEV;
1609 }
1610
1611 /* program threshold set 1 and all hysteresis */
1612 iowrite32(XGENE_DMA_RING_THRESLD0_SET1_VAL,
1613 pdma->csr_ring + XGENE_DMA_RING_THRESLD0_SET1);
1614 iowrite32(XGENE_DMA_RING_THRESLD1_SET1_VAL,
1615 pdma->csr_ring + XGENE_DMA_RING_THRESLD1_SET1);
1616 iowrite32(XGENE_DMA_RING_HYSTERESIS_VAL,
1617 pdma->csr_ring + XGENE_DMA_RING_HYSTERESIS);
1618
1619 /* Enable QPcore and assign error queue */
1620 iowrite32(XGENE_DMA_RING_ENABLE,
1621 pdma->csr_ring + XGENE_DMA_RING_CONFIG);
1622
1623 return 0;
1624}
1625
1626static int xgene_dma_init_mem(struct xgene_dma *pdma)
1627{
1628 int ret;
1629
1630 ret = xgene_dma_init_ring_mngr(pdma);
1631 if (ret)
1632 return ret;
1633
1634 /* Bring up memory */
1635 iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1636
1637 /* Force a barrier */
1638 ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1639
1640 /* reset may take up to 1ms */
1641 usleep_range(1000, 1100);
1642
1643 if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY)
1644 != XGENE_DMA_BLK_MEM_RDY_VAL) {
1645 dev_err(pdma->dev,
1646 "Failed to release DMA memory from shutdown\n");
1647 return -ENODEV;
1648 }
1649
1650 return 0;
1651}
1652
1653static int xgene_dma_request_irqs(struct xgene_dma *pdma)
1654{
1655 struct xgene_dma_chan *chan;
1656 int ret, i, j;
1657
1658 /* Register DMA error irq */
1659 ret = devm_request_irq(pdma->dev, pdma->err_irq, xgene_dma_err_isr,
1660 0, "dma_error", pdma);
1661 if (ret) {
1662 dev_err(pdma->dev,
1663 "Failed to register error IRQ %d\n", pdma->err_irq);
1664 return ret;
1665 }
1666
1667 /* Register DMA channel rx irq */
1668 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1669 chan = &pdma->chan[i];
1670 ret = devm_request_irq(chan->dev, chan->rx_irq,
1671 xgene_dma_chan_ring_isr,
1672 0, chan->name, chan);
1673 if (ret) {
1674 chan_err(chan, "Failed to register Rx IRQ %d\n",
1675 chan->rx_irq);
1676 devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1677
1678 for (j = 0; j < i; j++) {
1679 chan = &pdma->chan[i];
1680 devm_free_irq(chan->dev, chan->rx_irq, chan);
1681 }
1682
1683 return ret;
1684 }
1685 }
1686
1687 return 0;
1688}
1689
1690static void xgene_dma_free_irqs(struct xgene_dma *pdma)
1691{
1692 struct xgene_dma_chan *chan;
1693 int i;
1694
1695 /* Free DMA device error irq */
1696 devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1697
1698 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1699 chan = &pdma->chan[i];
1700 devm_free_irq(chan->dev, chan->rx_irq, chan);
1701 }
1702}
1703
1704static void xgene_dma_set_caps(struct xgene_dma_chan *chan,
1705 struct dma_device *dma_dev)
1706{
1707 /* Initialize DMA device capability mask */
1708 dma_cap_zero(dma_dev->cap_mask);
1709
1710 /* Set DMA device capability */
1711 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
1712 dma_cap_set(DMA_SG, dma_dev->cap_mask);
1713
1714 /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR
1715 * and channel 1 supports XOR, PQ both. First thing here is we have
1716 * mechanism in hw to enable/disable PQ/XOR supports on channel 1,
1717 * we can make sure this by reading SoC Efuse register.
1718 * Second thing, we have hw errata that if we run channel 0 and
1719 * channel 1 simultaneously with executing XOR and PQ request,
1720 * suddenly DMA engine hangs, So here we enable XOR on channel 0 only
1721 * if XOR and PQ supports on channel 1 is disabled.
1722 */
1723 if ((chan->id == XGENE_DMA_PQ_CHANNEL) &&
1724 is_pq_enabled(chan->pdma)) {
1725 dma_cap_set(DMA_PQ, dma_dev->cap_mask);
1726 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1727 } else if ((chan->id == XGENE_DMA_XOR_CHANNEL) &&
1728 !is_pq_enabled(chan->pdma)) {
1729 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1730 }
1731
1732 /* Set base and prep routines */
1733 dma_dev->dev = chan->dev;
1734 dma_dev->device_alloc_chan_resources = xgene_dma_alloc_chan_resources;
1735 dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources;
1736 dma_dev->device_issue_pending = xgene_dma_issue_pending;
1737 dma_dev->device_tx_status = xgene_dma_tx_status;
1738 dma_dev->device_prep_dma_memcpy = xgene_dma_prep_memcpy;
1739 dma_dev->device_prep_dma_sg = xgene_dma_prep_sg;
1740
1741 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1742 dma_dev->device_prep_dma_xor = xgene_dma_prep_xor;
1743 dma_dev->max_xor = XGENE_DMA_MAX_XOR_SRC;
1744 dma_dev->xor_align = XGENE_DMA_XOR_ALIGNMENT;
1745 }
1746
1747 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1748 dma_dev->device_prep_dma_pq = xgene_dma_prep_pq;
1749 dma_dev->max_pq = XGENE_DMA_MAX_XOR_SRC;
1750 dma_dev->pq_align = XGENE_DMA_XOR_ALIGNMENT;
1751 }
1752}
1753
1754static int xgene_dma_async_register(struct xgene_dma *pdma, int id)
1755{
1756 struct xgene_dma_chan *chan = &pdma->chan[id];
1757 struct dma_device *dma_dev = &pdma->dma_dev[id];
1758 int ret;
1759
1760 chan->dma_chan.device = dma_dev;
1761
1762 spin_lock_init(&chan->lock);
1763 INIT_LIST_HEAD(&chan->ld_pending);
1764 INIT_LIST_HEAD(&chan->ld_running);
1765 INIT_LIST_HEAD(&chan->ld_completed);
1766 tasklet_init(&chan->tasklet, xgene_dma_tasklet_cb,
1767 (unsigned long)chan);
1768
1769 chan->pending = 0;
1770 chan->desc_pool = NULL;
1771 dma_cookie_init(&chan->dma_chan);
1772
1773 /* Setup dma device capabilities and prep routines */
1774 xgene_dma_set_caps(chan, dma_dev);
1775
1776 /* Initialize DMA device list head */
1777 INIT_LIST_HEAD(&dma_dev->channels);
1778 list_add_tail(&chan->dma_chan.device_node, &dma_dev->channels);
1779
1780 /* Register with Linux async DMA framework*/
1781 ret = dma_async_device_register(dma_dev);
1782 if (ret) {
1783 chan_err(chan, "Failed to register async device %d", ret);
1784 tasklet_kill(&chan->tasklet);
1785
1786 return ret;
1787 }
1788
1789 /* DMA capability info */
1790 dev_info(pdma->dev,
1791 "%s: CAPABILITY ( %s%s%s%s)\n", dma_chan_name(&chan->dma_chan),
1792 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "MEMCPY " : "",
1793 dma_has_cap(DMA_SG, dma_dev->cap_mask) ? "SGCPY " : "",
1794 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "",
1795 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : "");
1796
1797 return 0;
1798}
1799
1800static int xgene_dma_init_async(struct xgene_dma *pdma)
1801{
1802 int ret, i, j;
1803
1804 for (i = 0; i < XGENE_DMA_MAX_CHANNEL ; i++) {
1805 ret = xgene_dma_async_register(pdma, i);
1806 if (ret) {
1807 for (j = 0; j < i; j++) {
1808 dma_async_device_unregister(&pdma->dma_dev[j]);
1809 tasklet_kill(&pdma->chan[j].tasklet);
1810 }
1811
1812 return ret;
1813 }
1814 }
1815
1816 return ret;
1817}
1818
1819static void xgene_dma_async_unregister(struct xgene_dma *pdma)
1820{
1821 int i;
1822
1823 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
1824 dma_async_device_unregister(&pdma->dma_dev[i]);
1825}
1826
1827static void xgene_dma_init_channels(struct xgene_dma *pdma)
1828{
1829 struct xgene_dma_chan *chan;
1830 int i;
1831
1832 pdma->ring_num = XGENE_DMA_RING_NUM;
1833
1834 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1835 chan = &pdma->chan[i];
1836 chan->dev = pdma->dev;
1837 chan->pdma = pdma;
1838 chan->id = i;
ed1f0418 1839 snprintf(chan->name, sizeof(chan->name), "dmachan%d", chan->id);
9f2fd0df
RPS		 1840 }
1841}
1842
1843static int xgene_dma_get_resources(struct platform_device *pdev,
1844 struct xgene_dma *pdma)
1845{
1846 struct resource *res;
1847 int irq, i;
1848
1849 /* Get DMA csr region */
1850 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1851 if (!res) {
1852 dev_err(&pdev->dev, "Failed to get csr region\n");
1853 return -ENXIO;
1854 }
1855
1856 pdma->csr_dma = devm_ioremap(&pdev->dev, res->start,
1857 resource_size(res));
9c361b1a 1858 if (!pdma->csr_dma) {
9f2fd0df 1859 dev_err(&pdev->dev, "Failed to ioremap csr region");
9c361b1a 1860 return -ENOMEM;
9f2fd0df
RPS		 1861 }
1862
1863 /* Get DMA ring csr region */
1864 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1865 if (!res) {
1866 dev_err(&pdev->dev, "Failed to get ring csr region\n");
1867 return -ENXIO;
1868 }
1869
1870 pdma->csr_ring = devm_ioremap(&pdev->dev, res->start,
1871 resource_size(res));
9c361b1a 1872 if (!pdma->csr_ring) {
9f2fd0df 1873 dev_err(&pdev->dev, "Failed to ioremap ring csr region");
9c361b1a 1874 return -ENOMEM;
9f2fd0df
RPS		 1875 }
1876
1877 /* Get DMA ring cmd csr region */
1878 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1879 if (!res) {
1880 dev_err(&pdev->dev, "Failed to get ring cmd csr region\n");
1881 return -ENXIO;
1882 }
1883
1884 pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start,
1885 resource_size(res));
9c361b1a 1886 if (!pdma->csr_ring_cmd) {
9f2fd0df 1887 dev_err(&pdev->dev, "Failed to ioremap ring cmd csr region");
9c361b1a 1888 return -ENOMEM;
9f2fd0df
RPS		 1889 }
1890
cda8e937
RPS		 1891 pdma->csr_ring_cmd += XGENE_DMA_RING_CMD_SM_OFFSET;
1892
9f2fd0df
RPS		 1893 /* Get efuse csr region */
1894 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1895 if (!res) {
1896 dev_err(&pdev->dev, "Failed to get efuse csr region\n");
1897 return -ENXIO;
1898 }
1899
1900 pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start,
1901 resource_size(res));
9c361b1a 1902 if (!pdma->csr_efuse) {
9f2fd0df 1903 dev_err(&pdev->dev, "Failed to ioremap efuse csr region");
9c361b1a 1904 return -ENOMEM;
9f2fd0df
RPS		 1905 }
1906
1907 /* Get DMA error interrupt */
1908 irq = platform_get_irq(pdev, 0);
1909 if (irq <= 0) {
1910 dev_err(&pdev->dev, "Failed to get Error IRQ\n");
1911 return -ENXIO;
1912 }
1913
1914 pdma->err_irq = irq;
1915
1916 /* Get DMA Rx ring descriptor interrupts for all DMA channels */
1917 for (i = 1; i <= XGENE_DMA_MAX_CHANNEL; i++) {
1918 irq = platform_get_irq(pdev, i);
1919 if (irq <= 0) {
1920 dev_err(&pdev->dev, "Failed to get Rx IRQ\n");
1921 return -ENXIO;
1922 }
1923
1924 pdma->chan[i - 1].rx_irq = irq;
1925 }
1926
1927 return 0;
1928}
1929
1930static int xgene_dma_probe(struct platform_device *pdev)
1931{
1932 struct xgene_dma *pdma;
1933 int ret, i;
1934
1935 pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL);
1936 if (!pdma)
1937 return -ENOMEM;
1938
1939 pdma->dev = &pdev->dev;
1940 platform_set_drvdata(pdev, pdma);
1941
1942 ret = xgene_dma_get_resources(pdev, pdma);
1943 if (ret)
1944 return ret;
1945
1946 pdma->clk = devm_clk_get(&pdev->dev, NULL);
1947 if (IS_ERR(pdma->clk)) {
1948 dev_err(&pdev->dev, "Failed to get clk\n");
1949 return PTR_ERR(pdma->clk);
1950 }
1951
1952 /* Enable clk before accessing registers */
1953 ret = clk_prepare_enable(pdma->clk);
1954 if (ret) {
1955 dev_err(&pdev->dev, "Failed to enable clk %d\n", ret);
1956 return ret;
1957 }
1958
1959 /* Remove DMA RAM out of shutdown */
1960 ret = xgene_dma_init_mem(pdma);
1961 if (ret)
1962 goto err_clk_enable;
1963
1964 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(42));
1965 if (ret) {
1966 dev_err(&pdev->dev, "No usable DMA configuration\n");
1967 goto err_dma_mask;
1968 }
1969
1970 /* Initialize DMA channels software state */
1971 xgene_dma_init_channels(pdma);
1972
1973 /* Configue DMA rings */
1974 ret = xgene_dma_init_rings(pdma);
1975 if (ret)
1976 goto err_clk_enable;
1977
1978 ret = xgene_dma_request_irqs(pdma);
1979 if (ret)
1980 goto err_request_irq;
1981
1982 /* Configure and enable DMA engine */
1983 xgene_dma_init_hw(pdma);
1984
1985 /* Register DMA device with linux async framework */
1986 ret = xgene_dma_init_async(pdma);
1987 if (ret)
1988 goto err_async_init;
1989
1990 return 0;
1991
1992err_async_init:
1993 xgene_dma_free_irqs(pdma);
1994
1995err_request_irq:
1996 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
1997 xgene_dma_delete_chan_rings(&pdma->chan[i]);
1998
1999err_dma_mask:
2000err_clk_enable:
2001 clk_disable_unprepare(pdma->clk);
2002
2003 return ret;
2004}
2005
2006static int xgene_dma_remove(struct platform_device *pdev)
2007{
2008 struct xgene_dma *pdma = platform_get_drvdata(pdev);
2009 struct xgene_dma_chan *chan;
2010 int i;
2011
2012 xgene_dma_async_unregister(pdma);
2013
2014 /* Mask interrupts and disable DMA engine */
2015 xgene_dma_mask_interrupts(pdma);
2016 xgene_dma_disable(pdma);
2017 xgene_dma_free_irqs(pdma);
2018
2019 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
2020 chan = &pdma->chan[i];
2021 tasklet_kill(&chan->tasklet);
2022 xgene_dma_delete_chan_rings(chan);
2023 }
2024
2025 clk_disable_unprepare(pdma->clk);
2026
2027 return 0;
2028}
2029
2030static const struct of_device_id xgene_dma_of_match_ptr[] = {
2031 {.compatible = "apm,xgene-storm-dma",},
2032 {},
2033};
2034MODULE_DEVICE_TABLE(of, xgene_dma_of_match_ptr);
2035
2036static struct platform_driver xgene_dma_driver = {
2037 .probe = xgene_dma_probe,
2038 .remove = xgene_dma_remove,
2039 .driver = {
2040 .name = "X-Gene-DMA",
9f2fd0df
RPS		 2041 .of_match_table = xgene_dma_of_match_ptr,
2042 },
2043};
2044
2045module_platform_driver(xgene_dma_driver);
2046
2047MODULE_DESCRIPTION("APM X-Gene SoC DMA driver");
2048MODULE_AUTHOR("Rameshwar Prasad Sahu <rsahu@apm.com>");
2049MODULE_AUTHOR("Loc Ho <lho@apm.com>");
2050MODULE_LICENSE("GPL");
2051MODULE_VERSION("1.0");
Linux kernel - Deliverables
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