Commit | Line | Data |
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71bcada8 | 1 | /* |
c3eea194 | 2 | * Copyright Altera Corporation (C) 2014-2016. All rights reserved. |
71bcada8 TT |
3 | * Copyright 2011-2012 Calxeda, Inc. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | * | |
17 | * Adapted from the highbank_mc_edac driver. | |
18 | */ | |
19 | ||
c3eea194 | 20 | #include <asm/cacheflush.h> |
71bcada8 TT |
21 | #include <linux/ctype.h> |
22 | #include <linux/edac.h> | |
c3eea194 | 23 | #include <linux/genalloc.h> |
71bcada8 TT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/kernel.h> | |
26 | #include <linux/mfd/syscon.h> | |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/regmap.h> | |
30 | #include <linux/types.h> | |
31 | #include <linux/uaccess.h> | |
32 | ||
143f4a5a | 33 | #include "altera_edac.h" |
71bcada8 TT |
34 | #include "edac_core.h" |
35 | #include "edac_module.h" | |
36 | ||
37 | #define EDAC_MOD_STR "altera_edac" | |
38 | #define EDAC_VERSION "1" | |
c3eea194 | 39 | #define EDAC_DEVICE "Altera" |
71bcada8 | 40 | |
143f4a5a TT |
41 | static const struct altr_sdram_prv_data c5_data = { |
42 | .ecc_ctrl_offset = CV_CTLCFG_OFST, | |
43 | .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN, | |
44 | .ecc_stat_offset = CV_DRAMSTS_OFST, | |
45 | .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR, | |
46 | .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR, | |
47 | .ecc_saddr_offset = CV_ERRADDR_OFST, | |
73bcc942 | 48 | .ecc_daddr_offset = CV_ERRADDR_OFST, |
143f4a5a TT |
49 | .ecc_cecnt_offset = CV_SBECOUNT_OFST, |
50 | .ecc_uecnt_offset = CV_DBECOUNT_OFST, | |
51 | .ecc_irq_en_offset = CV_DRAMINTR_OFST, | |
52 | .ecc_irq_en_mask = CV_DRAMINTR_INTREN, | |
53 | .ecc_irq_clr_offset = CV_DRAMINTR_OFST, | |
54 | .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN), | |
55 | .ecc_cnt_rst_offset = CV_DRAMINTR_OFST, | |
56 | .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR, | |
143f4a5a TT |
57 | .ce_ue_trgr_offset = CV_CTLCFG_OFST, |
58 | .ce_set_mask = CV_CTLCFG_GEN_SB_ERR, | |
59 | .ue_set_mask = CV_CTLCFG_GEN_DB_ERR, | |
71bcada8 TT |
60 | }; |
61 | ||
73bcc942 TT |
62 | static const struct altr_sdram_prv_data a10_data = { |
63 | .ecc_ctrl_offset = A10_ECCCTRL1_OFST, | |
64 | .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN, | |
65 | .ecc_stat_offset = A10_INTSTAT_OFST, | |
66 | .ecc_stat_ce_mask = A10_INTSTAT_SBEERR, | |
67 | .ecc_stat_ue_mask = A10_INTSTAT_DBEERR, | |
68 | .ecc_saddr_offset = A10_SERRADDR_OFST, | |
69 | .ecc_daddr_offset = A10_DERRADDR_OFST, | |
70 | .ecc_irq_en_offset = A10_ERRINTEN_OFST, | |
71 | .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK, | |
72 | .ecc_irq_clr_offset = A10_INTSTAT_OFST, | |
73 | .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR), | |
74 | .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST, | |
75 | .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK, | |
73bcc942 TT |
76 | .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST, |
77 | .ce_set_mask = A10_DIAGINT_TSERRA_MASK, | |
78 | .ue_set_mask = A10_DIAGINT_TDERRA_MASK, | |
73bcc942 TT |
79 | }; |
80 | ||
c3eea194 TT |
81 | /*********************** EDAC Memory Controller Functions ****************/ |
82 | ||
83 | /* The SDRAM controller uses the EDAC Memory Controller framework. */ | |
84 | ||
71bcada8 TT |
85 | static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) |
86 | { | |
87 | struct mem_ctl_info *mci = dev_id; | |
88 | struct altr_sdram_mc_data *drvdata = mci->pvt_info; | |
143f4a5a | 89 | const struct altr_sdram_prv_data *priv = drvdata->data; |
73bcc942 | 90 | u32 status, err_count = 1, err_addr; |
71bcada8 | 91 | |
143f4a5a | 92 | regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); |
71bcada8 | 93 | |
143f4a5a | 94 | if (status & priv->ecc_stat_ue_mask) { |
73bcc942 TT |
95 | regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset, |
96 | &err_addr); | |
97 | if (priv->ecc_uecnt_offset) | |
98 | regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset, | |
99 | &err_count); | |
71bcada8 TT |
100 | panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n", |
101 | err_count, err_addr); | |
102 | } | |
143f4a5a | 103 | if (status & priv->ecc_stat_ce_mask) { |
73bcc942 TT |
104 | regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, |
105 | &err_addr); | |
106 | if (priv->ecc_uecnt_offset) | |
107 | regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset, | |
108 | &err_count); | |
71bcada8 TT |
109 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, |
110 | err_addr >> PAGE_SHIFT, | |
111 | err_addr & ~PAGE_MASK, 0, | |
112 | 0, 0, -1, mci->ctl_name, ""); | |
73bcc942 TT |
113 | /* Clear IRQ to resume */ |
114 | regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset, | |
115 | priv->ecc_irq_clr_mask); | |
71bcada8 | 116 | |
73bcc942 TT |
117 | return IRQ_HANDLED; |
118 | } | |
119 | return IRQ_NONE; | |
71bcada8 TT |
120 | } |
121 | ||
71bcada8 TT |
122 | static ssize_t altr_sdr_mc_err_inject_write(struct file *file, |
123 | const char __user *data, | |
124 | size_t count, loff_t *ppos) | |
125 | { | |
126 | struct mem_ctl_info *mci = file->private_data; | |
127 | struct altr_sdram_mc_data *drvdata = mci->pvt_info; | |
143f4a5a | 128 | const struct altr_sdram_prv_data *priv = drvdata->data; |
71bcada8 TT |
129 | u32 *ptemp; |
130 | dma_addr_t dma_handle; | |
131 | u32 reg, read_reg; | |
132 | ||
133 | ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL); | |
134 | if (!ptemp) { | |
135 | dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); | |
136 | edac_printk(KERN_ERR, EDAC_MC, | |
137 | "Inject: Buffer Allocation error\n"); | |
138 | return -ENOMEM; | |
139 | } | |
140 | ||
143f4a5a TT |
141 | regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
142 | &read_reg); | |
143 | read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask); | |
71bcada8 TT |
144 | |
145 | /* Error are injected by writing a word while the SBE or DBE | |
146 | * bit in the CTLCFG register is set. Reading the word will | |
147 | * trigger the SBE or DBE error and the corresponding IRQ. | |
148 | */ | |
149 | if (count == 3) { | |
150 | edac_printk(KERN_ALERT, EDAC_MC, | |
151 | "Inject Double bit error\n"); | |
143f4a5a TT |
152 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
153 | (read_reg | priv->ue_set_mask)); | |
71bcada8 TT |
154 | } else { |
155 | edac_printk(KERN_ALERT, EDAC_MC, | |
156 | "Inject Single bit error\n"); | |
143f4a5a TT |
157 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, |
158 | (read_reg | priv->ce_set_mask)); | |
71bcada8 TT |
159 | } |
160 | ||
161 | ptemp[0] = 0x5A5A5A5A; | |
162 | ptemp[1] = 0xA5A5A5A5; | |
163 | ||
164 | /* Clear the error injection bits */ | |
143f4a5a | 165 | regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg); |
71bcada8 TT |
166 | /* Ensure it has been written out */ |
167 | wmb(); | |
168 | ||
169 | /* | |
170 | * To trigger the error, we need to read the data back | |
171 | * (the data was written with errors above). | |
172 | * The ACCESS_ONCE macros and printk are used to prevent the | |
173 | * the compiler optimizing these reads out. | |
174 | */ | |
175 | reg = ACCESS_ONCE(ptemp[0]); | |
176 | read_reg = ACCESS_ONCE(ptemp[1]); | |
177 | /* Force Read */ | |
178 | rmb(); | |
179 | ||
180 | edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n", | |
181 | reg, read_reg); | |
182 | ||
183 | dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); | |
184 | ||
185 | return count; | |
186 | } | |
187 | ||
188 | static const struct file_operations altr_sdr_mc_debug_inject_fops = { | |
189 | .open = simple_open, | |
190 | .write = altr_sdr_mc_err_inject_write, | |
191 | .llseek = generic_file_llseek, | |
192 | }; | |
193 | ||
194 | static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci) | |
195 | { | |
bba3b31e BP |
196 | if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) |
197 | return; | |
198 | ||
199 | if (!mci->debugfs) | |
200 | return; | |
201 | ||
202 | edac_debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci, | |
203 | &altr_sdr_mc_debug_inject_fops); | |
71bcada8 | 204 | } |
71bcada8 | 205 | |
f9ae487e TT |
206 | /* Get total memory size from Open Firmware DTB */ |
207 | static unsigned long get_total_mem(void) | |
71bcada8 | 208 | { |
f9ae487e TT |
209 | struct device_node *np = NULL; |
210 | const unsigned int *reg, *reg_end; | |
211 | int len, sw, aw; | |
212 | unsigned long start, size, total_mem = 0; | |
213 | ||
214 | for_each_node_by_type(np, "memory") { | |
215 | aw = of_n_addr_cells(np); | |
216 | sw = of_n_size_cells(np); | |
217 | reg = (const unsigned int *)of_get_property(np, "reg", &len); | |
218 | reg_end = reg + (len / sizeof(u32)); | |
219 | ||
220 | total_mem = 0; | |
221 | do { | |
222 | start = of_read_number(reg, aw); | |
223 | reg += aw; | |
224 | size = of_read_number(reg, sw); | |
225 | reg += sw; | |
226 | total_mem += size; | |
227 | } while (reg < reg_end); | |
228 | } | |
229 | edac_dbg(0, "total_mem 0x%lx\n", total_mem); | |
230 | return total_mem; | |
71bcada8 TT |
231 | } |
232 | ||
143f4a5a TT |
233 | static const struct of_device_id altr_sdram_ctrl_of_match[] = { |
234 | { .compatible = "altr,sdram-edac", .data = (void *)&c5_data}, | |
73bcc942 | 235 | { .compatible = "altr,sdram-edac-a10", .data = (void *)&a10_data}, |
143f4a5a TT |
236 | {}, |
237 | }; | |
238 | MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match); | |
239 | ||
73bcc942 TT |
240 | static int a10_init(struct regmap *mc_vbase) |
241 | { | |
242 | if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST, | |
243 | A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) { | |
244 | edac_printk(KERN_ERR, EDAC_MC, | |
245 | "Error setting SB IRQ mode\n"); | |
246 | return -ENODEV; | |
247 | } | |
248 | ||
249 | if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) { | |
250 | edac_printk(KERN_ERR, EDAC_MC, | |
251 | "Error setting trigger count\n"); | |
252 | return -ENODEV; | |
253 | } | |
254 | ||
255 | return 0; | |
256 | } | |
257 | ||
258 | static int a10_unmask_irq(struct platform_device *pdev, u32 mask) | |
259 | { | |
260 | void __iomem *sm_base; | |
261 | int ret = 0; | |
262 | ||
263 | if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32), | |
264 | dev_name(&pdev->dev))) { | |
265 | edac_printk(KERN_ERR, EDAC_MC, | |
266 | "Unable to request mem region\n"); | |
267 | return -EBUSY; | |
268 | } | |
269 | ||
270 | sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32)); | |
271 | if (!sm_base) { | |
272 | edac_printk(KERN_ERR, EDAC_MC, | |
273 | "Unable to ioremap device\n"); | |
274 | ||
275 | ret = -ENOMEM; | |
276 | goto release; | |
277 | } | |
278 | ||
279 | iowrite32(mask, sm_base); | |
280 | ||
281 | iounmap(sm_base); | |
282 | ||
283 | release: | |
284 | release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32)); | |
285 | ||
286 | return ret; | |
287 | } | |
288 | ||
71bcada8 TT |
289 | static int altr_sdram_probe(struct platform_device *pdev) |
290 | { | |
143f4a5a | 291 | const struct of_device_id *id; |
71bcada8 TT |
292 | struct edac_mc_layer layers[2]; |
293 | struct mem_ctl_info *mci; | |
294 | struct altr_sdram_mc_data *drvdata; | |
143f4a5a | 295 | const struct altr_sdram_prv_data *priv; |
71bcada8 TT |
296 | struct regmap *mc_vbase; |
297 | struct dimm_info *dimm; | |
143f4a5a | 298 | u32 read_reg; |
73bcc942 TT |
299 | int irq, irq2, res = 0; |
300 | unsigned long mem_size, irqflags = 0; | |
143f4a5a TT |
301 | |
302 | id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev); | |
303 | if (!id) | |
304 | return -ENODEV; | |
71bcada8 | 305 | |
71bcada8 TT |
306 | /* Grab the register range from the sdr controller in device tree */ |
307 | mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, | |
308 | "altr,sdr-syscon"); | |
309 | if (IS_ERR(mc_vbase)) { | |
310 | edac_printk(KERN_ERR, EDAC_MC, | |
311 | "regmap for altr,sdr-syscon lookup failed.\n"); | |
312 | return -ENODEV; | |
313 | } | |
314 | ||
143f4a5a TT |
315 | /* Check specific dependencies for the module */ |
316 | priv = of_match_node(altr_sdram_ctrl_of_match, | |
317 | pdev->dev.of_node)->data; | |
318 | ||
319 | /* Validate the SDRAM controller has ECC enabled */ | |
320 | if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) || | |
321 | ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) { | |
71bcada8 TT |
322 | edac_printk(KERN_ERR, EDAC_MC, |
323 | "No ECC/ECC disabled [0x%08X]\n", read_reg); | |
324 | return -ENODEV; | |
325 | } | |
326 | ||
327 | /* Grab memory size from device tree. */ | |
f9ae487e | 328 | mem_size = get_total_mem(); |
71bcada8 | 329 | if (!mem_size) { |
f9ae487e | 330 | edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n"); |
71bcada8 TT |
331 | return -ENODEV; |
332 | } | |
333 | ||
143f4a5a TT |
334 | /* Ensure the SDRAM Interrupt is disabled */ |
335 | if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset, | |
336 | priv->ecc_irq_en_mask, 0)) { | |
337 | edac_printk(KERN_ERR, EDAC_MC, | |
338 | "Error disabling SDRAM ECC IRQ\n"); | |
339 | return -ENODEV; | |
340 | } | |
341 | ||
342 | /* Toggle to clear the SDRAM Error count */ | |
343 | if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, | |
344 | priv->ecc_cnt_rst_mask, | |
345 | priv->ecc_cnt_rst_mask)) { | |
346 | edac_printk(KERN_ERR, EDAC_MC, | |
347 | "Error clearing SDRAM ECC count\n"); | |
348 | return -ENODEV; | |
349 | } | |
350 | ||
351 | if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, | |
352 | priv->ecc_cnt_rst_mask, 0)) { | |
71bcada8 | 353 | edac_printk(KERN_ERR, EDAC_MC, |
143f4a5a | 354 | "Error clearing SDRAM ECC count\n"); |
71bcada8 TT |
355 | return -ENODEV; |
356 | } | |
357 | ||
358 | irq = platform_get_irq(pdev, 0); | |
359 | if (irq < 0) { | |
360 | edac_printk(KERN_ERR, EDAC_MC, | |
361 | "No irq %d in DT\n", irq); | |
362 | return -ENODEV; | |
363 | } | |
364 | ||
73bcc942 TT |
365 | /* Arria10 has a 2nd IRQ */ |
366 | irq2 = platform_get_irq(pdev, 1); | |
367 | ||
71bcada8 TT |
368 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
369 | layers[0].size = 1; | |
370 | layers[0].is_virt_csrow = true; | |
371 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
372 | layers[1].size = 1; | |
373 | layers[1].is_virt_csrow = false; | |
374 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, | |
375 | sizeof(struct altr_sdram_mc_data)); | |
376 | if (!mci) | |
377 | return -ENOMEM; | |
378 | ||
379 | mci->pdev = &pdev->dev; | |
380 | drvdata = mci->pvt_info; | |
381 | drvdata->mc_vbase = mc_vbase; | |
143f4a5a | 382 | drvdata->data = priv; |
71bcada8 TT |
383 | platform_set_drvdata(pdev, mci); |
384 | ||
385 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { | |
143f4a5a TT |
386 | edac_printk(KERN_ERR, EDAC_MC, |
387 | "Unable to get managed device resource\n"); | |
71bcada8 TT |
388 | res = -ENOMEM; |
389 | goto free; | |
390 | } | |
391 | ||
392 | mci->mtype_cap = MEM_FLAG_DDR3; | |
393 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
394 | mci->edac_cap = EDAC_FLAG_SECDED; | |
395 | mci->mod_name = EDAC_MOD_STR; | |
396 | mci->mod_ver = EDAC_VERSION; | |
397 | mci->ctl_name = dev_name(&pdev->dev); | |
398 | mci->scrub_mode = SCRUB_SW_SRC; | |
399 | mci->dev_name = dev_name(&pdev->dev); | |
400 | ||
401 | dimm = *mci->dimms; | |
402 | dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1; | |
403 | dimm->grain = 8; | |
404 | dimm->dtype = DEV_X8; | |
405 | dimm->mtype = MEM_DDR3; | |
406 | dimm->edac_mode = EDAC_SECDED; | |
407 | ||
408 | res = edac_mc_add_mc(mci); | |
409 | if (res < 0) | |
410 | goto err; | |
411 | ||
73bcc942 TT |
412 | /* Only the Arria10 has separate IRQs */ |
413 | if (irq2 > 0) { | |
414 | /* Arria10 specific initialization */ | |
415 | res = a10_init(mc_vbase); | |
416 | if (res < 0) | |
417 | goto err2; | |
418 | ||
419 | res = devm_request_irq(&pdev->dev, irq2, | |
420 | altr_sdram_mc_err_handler, | |
421 | IRQF_SHARED, dev_name(&pdev->dev), mci); | |
422 | if (res < 0) { | |
423 | edac_mc_printk(mci, KERN_ERR, | |
424 | "Unable to request irq %d\n", irq2); | |
425 | res = -ENODEV; | |
426 | goto err2; | |
427 | } | |
428 | ||
429 | res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK); | |
430 | if (res < 0) | |
431 | goto err2; | |
432 | ||
433 | irqflags = IRQF_SHARED; | |
434 | } | |
435 | ||
71bcada8 | 436 | res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler, |
73bcc942 | 437 | irqflags, dev_name(&pdev->dev), mci); |
71bcada8 TT |
438 | if (res < 0) { |
439 | edac_mc_printk(mci, KERN_ERR, | |
440 | "Unable to request irq %d\n", irq); | |
441 | res = -ENODEV; | |
442 | goto err2; | |
443 | } | |
444 | ||
143f4a5a TT |
445 | /* Infrastructure ready - enable the IRQ */ |
446 | if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset, | |
447 | priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) { | |
71bcada8 TT |
448 | edac_mc_printk(mci, KERN_ERR, |
449 | "Error enabling SDRAM ECC IRQ\n"); | |
450 | res = -ENODEV; | |
451 | goto err2; | |
452 | } | |
453 | ||
454 | altr_sdr_mc_create_debugfs_nodes(mci); | |
455 | ||
456 | devres_close_group(&pdev->dev, NULL); | |
457 | ||
458 | return 0; | |
459 | ||
460 | err2: | |
461 | edac_mc_del_mc(&pdev->dev); | |
462 | err: | |
463 | devres_release_group(&pdev->dev, NULL); | |
464 | free: | |
465 | edac_mc_free(mci); | |
466 | edac_printk(KERN_ERR, EDAC_MC, | |
467 | "EDAC Probe Failed; Error %d\n", res); | |
468 | ||
469 | return res; | |
470 | } | |
471 | ||
472 | static int altr_sdram_remove(struct platform_device *pdev) | |
473 | { | |
474 | struct mem_ctl_info *mci = platform_get_drvdata(pdev); | |
475 | ||
476 | edac_mc_del_mc(&pdev->dev); | |
477 | edac_mc_free(mci); | |
478 | platform_set_drvdata(pdev, NULL); | |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
6f2b6422 AT |
483 | /* |
484 | * If you want to suspend, need to disable EDAC by removing it | |
485 | * from the device tree or defconfig. | |
486 | */ | |
487 | #ifdef CONFIG_PM | |
488 | static int altr_sdram_prepare(struct device *dev) | |
489 | { | |
490 | pr_err("Suspend not allowed when EDAC is enabled.\n"); | |
491 | ||
492 | return -EPERM; | |
493 | } | |
494 | ||
495 | static const struct dev_pm_ops altr_sdram_pm_ops = { | |
496 | .prepare = altr_sdram_prepare, | |
497 | }; | |
498 | #endif | |
499 | ||
71bcada8 TT |
500 | static struct platform_driver altr_sdram_edac_driver = { |
501 | .probe = altr_sdram_probe, | |
502 | .remove = altr_sdram_remove, | |
503 | .driver = { | |
504 | .name = "altr_sdram_edac", | |
6f2b6422 AT |
505 | #ifdef CONFIG_PM |
506 | .pm = &altr_sdram_pm_ops, | |
507 | #endif | |
71bcada8 TT |
508 | .of_match_table = altr_sdram_ctrl_of_match, |
509 | }, | |
510 | }; | |
511 | ||
512 | module_platform_driver(altr_sdram_edac_driver); | |
513 | ||
c3eea194 TT |
514 | /************************* EDAC Parent Probe *************************/ |
515 | ||
516 | static const struct of_device_id altr_edac_device_of_match[]; | |
517 | ||
518 | static const struct of_device_id altr_edac_of_match[] = { | |
519 | { .compatible = "altr,socfpga-ecc-manager" }, | |
520 | {}, | |
521 | }; | |
522 | MODULE_DEVICE_TABLE(of, altr_edac_of_match); | |
523 | ||
524 | static int altr_edac_probe(struct platform_device *pdev) | |
525 | { | |
526 | of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match, | |
527 | NULL, &pdev->dev); | |
528 | return 0; | |
529 | } | |
530 | ||
531 | static struct platform_driver altr_edac_driver = { | |
532 | .probe = altr_edac_probe, | |
533 | .driver = { | |
534 | .name = "socfpga_ecc_manager", | |
535 | .of_match_table = altr_edac_of_match, | |
536 | }, | |
537 | }; | |
538 | module_platform_driver(altr_edac_driver); | |
539 | ||
540 | /************************* EDAC Device Functions *************************/ | |
541 | ||
542 | /* | |
543 | * EDAC Device Functions (shared between various IPs). | |
544 | * The discrete memories use the EDAC Device framework. The probe | |
545 | * and error handling functions are very similar between memories | |
546 | * so they are shared. The memory allocation and freeing for EDAC | |
547 | * trigger testing are different for each memory. | |
548 | */ | |
549 | ||
550 | const struct edac_device_prv_data ocramecc_data; | |
551 | const struct edac_device_prv_data l2ecc_data; | |
552 | ||
c3eea194 TT |
553 | static irqreturn_t altr_edac_device_handler(int irq, void *dev_id) |
554 | { | |
555 | irqreturn_t ret_value = IRQ_NONE; | |
556 | struct edac_device_ctl_info *dci = dev_id; | |
557 | struct altr_edac_device_dev *drvdata = dci->pvt_info; | |
558 | const struct edac_device_prv_data *priv = drvdata->data; | |
559 | ||
560 | if (irq == drvdata->sb_irq) { | |
561 | if (priv->ce_clear_mask) | |
562 | writel(priv->ce_clear_mask, drvdata->base); | |
563 | edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name); | |
564 | ret_value = IRQ_HANDLED; | |
565 | } else if (irq == drvdata->db_irq) { | |
566 | if (priv->ue_clear_mask) | |
567 | writel(priv->ue_clear_mask, drvdata->base); | |
568 | edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name); | |
569 | panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); | |
570 | ret_value = IRQ_HANDLED; | |
571 | } else { | |
572 | WARN_ON(1); | |
573 | } | |
574 | ||
575 | return ret_value; | |
576 | } | |
577 | ||
578 | static ssize_t altr_edac_device_trig(struct file *file, | |
579 | const char __user *user_buf, | |
580 | size_t count, loff_t *ppos) | |
581 | ||
582 | { | |
583 | u32 *ptemp, i, error_mask; | |
584 | int result = 0; | |
585 | u8 trig_type; | |
586 | unsigned long flags; | |
587 | struct edac_device_ctl_info *edac_dci = file->private_data; | |
588 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
589 | const struct edac_device_prv_data *priv = drvdata->data; | |
590 | void *generic_ptr = edac_dci->dev; | |
591 | ||
592 | if (!user_buf || get_user(trig_type, user_buf)) | |
593 | return -EFAULT; | |
594 | ||
595 | if (!priv->alloc_mem) | |
596 | return -ENOMEM; | |
597 | ||
598 | /* | |
599 | * Note that generic_ptr is initialized to the device * but in | |
600 | * some alloc_functions, this is overridden and returns data. | |
601 | */ | |
602 | ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr); | |
603 | if (!ptemp) { | |
604 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
605 | "Inject: Buffer Allocation error\n"); | |
606 | return -ENOMEM; | |
607 | } | |
608 | ||
609 | if (trig_type == ALTR_UE_TRIGGER_CHAR) | |
610 | error_mask = priv->ue_set_mask; | |
611 | else | |
612 | error_mask = priv->ce_set_mask; | |
613 | ||
614 | edac_printk(KERN_ALERT, EDAC_DEVICE, | |
615 | "Trigger Error Mask (0x%X)\n", error_mask); | |
616 | ||
617 | local_irq_save(flags); | |
618 | /* write ECC corrupted data out. */ | |
619 | for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) { | |
620 | /* Read data so we're in the correct state */ | |
621 | rmb(); | |
622 | if (ACCESS_ONCE(ptemp[i])) | |
623 | result = -1; | |
624 | /* Toggle Error bit (it is latched), leave ECC enabled */ | |
811fce4f TT |
625 | writel(error_mask, (drvdata->base + priv->set_err_ofst)); |
626 | writel(priv->ecc_enable_mask, (drvdata->base + | |
627 | priv->set_err_ofst)); | |
c3eea194 TT |
628 | ptemp[i] = i; |
629 | } | |
630 | /* Ensure it has been written out */ | |
631 | wmb(); | |
632 | local_irq_restore(flags); | |
633 | ||
634 | if (result) | |
635 | edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n"); | |
636 | ||
637 | /* Read out written data. ECC error caused here */ | |
638 | for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++) | |
639 | if (ACCESS_ONCE(ptemp[i]) != i) | |
640 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
641 | "Read doesn't match written data\n"); | |
642 | ||
643 | if (priv->free_mem) | |
644 | priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr); | |
645 | ||
646 | return count; | |
647 | } | |
648 | ||
649 | static const struct file_operations altr_edac_device_inject_fops = { | |
650 | .open = simple_open, | |
651 | .write = altr_edac_device_trig, | |
652 | .llseek = generic_file_llseek, | |
653 | }; | |
654 | ||
655 | static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci, | |
656 | const struct edac_device_prv_data *priv) | |
657 | { | |
658 | struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; | |
659 | ||
660 | if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) | |
661 | return; | |
662 | ||
663 | drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name); | |
664 | if (!drvdata->debugfs_dir) | |
665 | return; | |
666 | ||
667 | if (!edac_debugfs_create_file(priv->dbgfs_name, S_IWUSR, | |
668 | drvdata->debugfs_dir, edac_dci, | |
669 | &altr_edac_device_inject_fops)) | |
670 | debugfs_remove_recursive(drvdata->debugfs_dir); | |
671 | } | |
672 | ||
673 | static const struct of_device_id altr_edac_device_of_match[] = { | |
674 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
675 | { .compatible = "altr,socfpga-l2-ecc", .data = (void *)&l2ecc_data }, | |
676 | #endif | |
677 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
678 | { .compatible = "altr,socfpga-ocram-ecc", | |
679 | .data = (void *)&ocramecc_data }, | |
680 | #endif | |
681 | {}, | |
682 | }; | |
683 | MODULE_DEVICE_TABLE(of, altr_edac_device_of_match); | |
684 | ||
685 | /* | |
686 | * altr_edac_device_probe() | |
687 | * This is a generic EDAC device driver that will support | |
688 | * various Altera memory devices such as the L2 cache ECC and | |
689 | * OCRAM ECC as well as the memories for other peripherals. | |
690 | * Module specific initialization is done by passing the | |
691 | * function index in the device tree. | |
692 | */ | |
693 | static int altr_edac_device_probe(struct platform_device *pdev) | |
694 | { | |
695 | struct edac_device_ctl_info *dci; | |
696 | struct altr_edac_device_dev *drvdata; | |
697 | struct resource *r; | |
698 | int res = 0; | |
699 | struct device_node *np = pdev->dev.of_node; | |
700 | char *ecc_name = (char *)np->name; | |
701 | static int dev_instance; | |
702 | ||
703 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { | |
704 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
705 | "Unable to open devm\n"); | |
706 | return -ENOMEM; | |
707 | } | |
708 | ||
709 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
710 | if (!r) { | |
711 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
712 | "Unable to get mem resource\n"); | |
713 | res = -ENODEV; | |
714 | goto fail; | |
715 | } | |
716 | ||
717 | if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r), | |
718 | dev_name(&pdev->dev))) { | |
719 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
720 | "%s:Error requesting mem region\n", ecc_name); | |
721 | res = -EBUSY; | |
722 | goto fail; | |
723 | } | |
724 | ||
725 | dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name, | |
726 | 1, ecc_name, 1, 0, NULL, 0, | |
727 | dev_instance++); | |
728 | ||
729 | if (!dci) { | |
730 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
731 | "%s: Unable to allocate EDAC device\n", ecc_name); | |
732 | res = -ENOMEM; | |
733 | goto fail; | |
734 | } | |
735 | ||
736 | drvdata = dci->pvt_info; | |
737 | dci->dev = &pdev->dev; | |
738 | platform_set_drvdata(pdev, dci); | |
739 | drvdata->edac_dev_name = ecc_name; | |
740 | ||
741 | drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); | |
742 | if (!drvdata->base) | |
743 | goto fail1; | |
744 | ||
745 | /* Get driver specific data for this EDAC device */ | |
746 | drvdata->data = of_match_node(altr_edac_device_of_match, np)->data; | |
747 | ||
748 | /* Check specific dependencies for the module */ | |
749 | if (drvdata->data->setup) { | |
328ca7ae | 750 | res = drvdata->data->setup(drvdata); |
c3eea194 TT |
751 | if (res) |
752 | goto fail1; | |
753 | } | |
754 | ||
755 | drvdata->sb_irq = platform_get_irq(pdev, 0); | |
756 | res = devm_request_irq(&pdev->dev, drvdata->sb_irq, | |
757 | altr_edac_device_handler, | |
758 | 0, dev_name(&pdev->dev), dci); | |
759 | if (res) | |
760 | goto fail1; | |
761 | ||
762 | drvdata->db_irq = platform_get_irq(pdev, 1); | |
763 | res = devm_request_irq(&pdev->dev, drvdata->db_irq, | |
764 | altr_edac_device_handler, | |
765 | 0, dev_name(&pdev->dev), dci); | |
766 | if (res) | |
767 | goto fail1; | |
768 | ||
769 | dci->mod_name = "Altera ECC Manager"; | |
770 | dci->dev_name = drvdata->edac_dev_name; | |
771 | ||
772 | res = edac_device_add_device(dci); | |
773 | if (res) | |
774 | goto fail1; | |
775 | ||
776 | altr_create_edacdev_dbgfs(dci, drvdata->data); | |
777 | ||
778 | devres_close_group(&pdev->dev, NULL); | |
779 | ||
780 | return 0; | |
781 | ||
782 | fail1: | |
783 | edac_device_free_ctl_info(dci); | |
784 | fail: | |
785 | devres_release_group(&pdev->dev, NULL); | |
786 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
787 | "%s:Error setting up EDAC device: %d\n", ecc_name, res); | |
788 | ||
789 | return res; | |
790 | } | |
791 | ||
792 | static int altr_edac_device_remove(struct platform_device *pdev) | |
793 | { | |
794 | struct edac_device_ctl_info *dci = platform_get_drvdata(pdev); | |
795 | struct altr_edac_device_dev *drvdata = dci->pvt_info; | |
796 | ||
797 | debugfs_remove_recursive(drvdata->debugfs_dir); | |
798 | edac_device_del_device(&pdev->dev); | |
799 | edac_device_free_ctl_info(dci); | |
800 | ||
801 | return 0; | |
802 | } | |
803 | ||
804 | static struct platform_driver altr_edac_device_driver = { | |
805 | .probe = altr_edac_device_probe, | |
806 | .remove = altr_edac_device_remove, | |
807 | .driver = { | |
808 | .name = "altr_edac_device", | |
809 | .of_match_table = altr_edac_device_of_match, | |
810 | }, | |
811 | }; | |
812 | module_platform_driver(altr_edac_device_driver); | |
813 | ||
814 | /*********************** OCRAM EDAC Device Functions *********************/ | |
815 | ||
816 | #ifdef CONFIG_EDAC_ALTERA_OCRAM | |
817 | ||
818 | static void *ocram_alloc_mem(size_t size, void **other) | |
819 | { | |
820 | struct device_node *np; | |
821 | struct gen_pool *gp; | |
822 | void *sram_addr; | |
823 | ||
824 | np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); | |
825 | if (!np) | |
826 | return NULL; | |
827 | ||
828 | gp = of_gen_pool_get(np, "iram", 0); | |
829 | of_node_put(np); | |
830 | if (!gp) | |
831 | return NULL; | |
832 | ||
833 | sram_addr = (void *)gen_pool_alloc(gp, size); | |
834 | if (!sram_addr) | |
835 | return NULL; | |
836 | ||
837 | memset(sram_addr, 0, size); | |
838 | /* Ensure data is written out */ | |
839 | wmb(); | |
840 | ||
841 | /* Remember this handle for freeing later */ | |
842 | *other = gp; | |
843 | ||
844 | return sram_addr; | |
845 | } | |
846 | ||
847 | static void ocram_free_mem(void *p, size_t size, void *other) | |
848 | { | |
849 | gen_pool_free((struct gen_pool *)other, (u32)p, size); | |
850 | } | |
851 | ||
852 | /* | |
853 | * altr_ocram_check_deps() | |
854 | * Test for OCRAM cache ECC dependencies upon entry because | |
855 | * platform specific startup should have initialized the | |
856 | * On-Chip RAM memory and enabled the ECC. | |
857 | * Can't turn on ECC here because accessing un-initialized | |
858 | * memory will cause CE/UE errors possibly causing an ABORT. | |
859 | */ | |
328ca7ae | 860 | static int altr_ocram_check_deps(struct altr_edac_device_dev *device) |
c3eea194 | 861 | { |
328ca7ae | 862 | void __iomem *base = device->base; |
27439a1a TT |
863 | const struct edac_device_prv_data *prv = device->data; |
864 | ||
865 | if (readl(base) & prv->ecc_enable_mask) | |
c3eea194 TT |
866 | return 0; |
867 | ||
868 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
869 | "OCRAM: No ECC present or ECC disabled.\n"); | |
870 | return -ENODEV; | |
871 | } | |
872 | ||
873 | const struct edac_device_prv_data ocramecc_data = { | |
874 | .setup = altr_ocram_check_deps, | |
875 | .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR), | |
876 | .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR), | |
877 | .dbgfs_name = "altr_ocram_trigger", | |
878 | .alloc_mem = ocram_alloc_mem, | |
879 | .free_mem = ocram_free_mem, | |
880 | .ecc_enable_mask = ALTR_OCR_ECC_EN, | |
881 | .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS), | |
882 | .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD), | |
811fce4f | 883 | .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET, |
c3eea194 TT |
884 | .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE, |
885 | }; | |
886 | ||
887 | #endif /* CONFIG_EDAC_ALTERA_OCRAM */ | |
888 | ||
889 | /********************* L2 Cache EDAC Device Functions ********************/ | |
890 | ||
891 | #ifdef CONFIG_EDAC_ALTERA_L2C | |
892 | ||
893 | static void *l2_alloc_mem(size_t size, void **other) | |
894 | { | |
895 | struct device *dev = *other; | |
896 | void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL); | |
897 | ||
898 | if (!ptemp) | |
899 | return NULL; | |
900 | ||
901 | /* Make sure everything is written out */ | |
902 | wmb(); | |
903 | ||
904 | /* | |
905 | * Clean all cache levels up to LoC (includes L2) | |
906 | * This ensures the corrupted data is written into | |
907 | * L2 cache for readback test (which causes ECC error). | |
908 | */ | |
909 | flush_cache_all(); | |
910 | ||
911 | return ptemp; | |
912 | } | |
913 | ||
914 | static void l2_free_mem(void *p, size_t size, void *other) | |
915 | { | |
916 | struct device *dev = other; | |
917 | ||
918 | if (dev && p) | |
919 | devm_kfree(dev, p); | |
920 | } | |
921 | ||
922 | /* | |
923 | * altr_l2_check_deps() | |
924 | * Test for L2 cache ECC dependencies upon entry because | |
925 | * platform specific startup should have initialized the L2 | |
926 | * memory and enabled the ECC. | |
927 | * Bail if ECC is not enabled. | |
928 | * Note that L2 Cache Enable is forced at build time. | |
929 | */ | |
328ca7ae | 930 | static int altr_l2_check_deps(struct altr_edac_device_dev *device) |
c3eea194 | 931 | { |
328ca7ae | 932 | void __iomem *base = device->base; |
27439a1a TT |
933 | const struct edac_device_prv_data *prv = device->data; |
934 | ||
935 | if ((readl(base) & prv->ecc_enable_mask) == | |
936 | prv->ecc_enable_mask) | |
c3eea194 TT |
937 | return 0; |
938 | ||
939 | edac_printk(KERN_ERR, EDAC_DEVICE, | |
940 | "L2: No ECC present, or ECC disabled\n"); | |
941 | return -ENODEV; | |
942 | } | |
943 | ||
944 | const struct edac_device_prv_data l2ecc_data = { | |
945 | .setup = altr_l2_check_deps, | |
946 | .ce_clear_mask = 0, | |
947 | .ue_clear_mask = 0, | |
948 | .dbgfs_name = "altr_l2_trigger", | |
949 | .alloc_mem = l2_alloc_mem, | |
950 | .free_mem = l2_free_mem, | |
951 | .ecc_enable_mask = ALTR_L2_ECC_EN, | |
952 | .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS), | |
953 | .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD), | |
811fce4f | 954 | .set_err_ofst = ALTR_L2_ECC_REG_OFFSET, |
c3eea194 TT |
955 | .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, |
956 | }; | |
957 | ||
958 | #endif /* CONFIG_EDAC_ALTERA_L2C */ | |
959 | ||
71bcada8 TT |
960 | MODULE_LICENSE("GPL v2"); |
961 | MODULE_AUTHOR("Thor Thayer"); | |
c3eea194 | 962 | MODULE_DESCRIPTION("EDAC Driver for Altera Memories"); |