[deliverable/linux.git] / drivers / edac / altera_edac.c

/*
 *  Copyright Altera Corporation (C) 2014. All rights reserved.
 *  Copyright 2011-2012 Calxeda, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 * Adapted from the highbank_mc_edac driver.
 */

#include <linux/ctype.h>
#include <linux/edac.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/types.h>
#include <linux/uaccess.h>

#include "edac_core.h"
#include "edac_module.h"

#define EDAC_MOD_STR		"altera_edac"
#define EDAC_VERSION		"1"

/* SDRAM Controller CtrlCfg Register */
#define CTLCFG_OFST             0x00

/* SDRAM Controller CtrlCfg Register Bit Masks */
#define CTLCFG_ECC_EN           0x400
#define CTLCFG_ECC_CORR_EN      0x800
#define CTLCFG_GEN_SB_ERR       0x2000
#define CTLCFG_GEN_DB_ERR       0x4000

#define CTLCFG_ECC_AUTO_EN	(CTLCFG_ECC_EN | \
				 CTLCFG_ECC_CORR_EN)

/* SDRAM Controller Address Width Register */
#define DRAMADDRW_OFST          0x2C

/* SDRAM Controller Address Widths Field Register */
#define DRAMADDRW_COLBIT_MASK   0x001F
#define DRAMADDRW_COLBIT_SHIFT  0
#define DRAMADDRW_ROWBIT_MASK   0x03E0
#define DRAMADDRW_ROWBIT_SHIFT  5
#define DRAMADDRW_BANKBIT_MASK	0x1C00
#define DRAMADDRW_BANKBIT_SHIFT 10
#define DRAMADDRW_CSBIT_MASK	0xE000
#define DRAMADDRW_CSBIT_SHIFT   13

/* SDRAM Controller Interface Data Width Register */
#define DRAMIFWIDTH_OFST        0x30

/* SDRAM Controller Interface Data Width Defines */
#define DRAMIFWIDTH_16B_ECC     24
#define DRAMIFWIDTH_32B_ECC     40

/* SDRAM Controller DRAM Status Register */
#define DRAMSTS_OFST            0x38

/* SDRAM Controller DRAM Status Register Bit Masks */
#define DRAMSTS_SBEERR          0x04
#define DRAMSTS_DBEERR          0x08
#define DRAMSTS_CORR_DROP       0x10

/* SDRAM Controller DRAM IRQ Register */
#define DRAMINTR_OFST           0x3C

/* SDRAM Controller DRAM IRQ Register Bit Masks */
#define DRAMINTR_INTREN         0x01
#define DRAMINTR_SBEMASK        0x02
#define DRAMINTR_DBEMASK        0x04
#define DRAMINTR_CORRDROPMASK   0x08
#define DRAMINTR_INTRCLR        0x10

/* SDRAM Controller Single Bit Error Count Register */
#define SBECOUNT_OFST           0x40

/* SDRAM Controller Single Bit Error Count Register Bit Masks */
#define SBECOUNT_MASK           0x0F

/* SDRAM Controller Double Bit Error Count Register */
#define DBECOUNT_OFST           0x44

/* SDRAM Controller Double Bit Error Count Register Bit Masks */
#define DBECOUNT_MASK           0x0F

/* SDRAM Controller ECC Error Address Register */
#define ERRADDR_OFST            0x48

/* SDRAM Controller ECC Error Address Register Bit Masks */
#define ERRADDR_MASK            0xFFFFFFFF

/* Altera SDRAM Memory Controller data */
struct altr_sdram_mc_data {
	struct regmap *mc_vbase;
};

static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
{
	struct mem_ctl_info *mci = dev_id;
	struct altr_sdram_mc_data *drvdata = mci->pvt_info;
	u32 status, err_count, err_addr;

	/* Error Address is shared by both SBE & DBE */
	regmap_read(drvdata->mc_vbase, ERRADDR_OFST, &err_addr);

	regmap_read(drvdata->mc_vbase, DRAMSTS_OFST, &status);

	if (status & DRAMSTS_DBEERR) {
		regmap_read(drvdata->mc_vbase, DBECOUNT_OFST, &err_count);
		panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
		      err_count, err_addr);
	}
	if (status & DRAMSTS_SBEERR) {
		regmap_read(drvdata->mc_vbase, SBECOUNT_OFST, &err_count);
		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
				     err_addr >> PAGE_SHIFT,
				     err_addr & ~PAGE_MASK, 0,
				     0, 0, -1, mci->ctl_name, "");
	}

	regmap_write(drvdata->mc_vbase,	DRAMINTR_OFST,
		     (DRAMINTR_INTRCLR | DRAMINTR_INTREN));

	return IRQ_HANDLED;
}

#ifdef CONFIG_EDAC_DEBUG
static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
					    const char __user *data,
					    size_t count, loff_t *ppos)
{
	struct mem_ctl_info *mci = file->private_data;
	struct altr_sdram_mc_data *drvdata = mci->pvt_info;
	u32 *ptemp;
	dma_addr_t dma_handle;
	u32 reg, read_reg;

	ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
	if (!ptemp) {
		dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
		edac_printk(KERN_ERR, EDAC_MC,
			    "Inject: Buffer Allocation error\n");
		return -ENOMEM;
	}

	regmap_read(drvdata->mc_vbase, CTLCFG_OFST, &read_reg);
	read_reg &= ~(CTLCFG_GEN_SB_ERR | CTLCFG_GEN_DB_ERR);

	/* Error are injected by writing a word while the SBE or DBE
	 * bit in the CTLCFG register is set. Reading the word will
	 * trigger the SBE or DBE error and the corresponding IRQ.
	 */
	if (count == 3) {
		edac_printk(KERN_ALERT, EDAC_MC,
			    "Inject Double bit error\n");
		regmap_write(drvdata->mc_vbase, CTLCFG_OFST,
			     (read_reg | CTLCFG_GEN_DB_ERR));
	} else {
		edac_printk(KERN_ALERT, EDAC_MC,
			    "Inject Single bit error\n");
		regmap_write(drvdata->mc_vbase,	CTLCFG_OFST,
			     (read_reg | CTLCFG_GEN_SB_ERR));
	}

	ptemp[0] = 0x5A5A5A5A;
	ptemp[1] = 0xA5A5A5A5;

	/* Clear the error injection bits */
	regmap_write(drvdata->mc_vbase,	CTLCFG_OFST, read_reg);
	/* Ensure it has been written out */
	wmb();

	/*
	 * To trigger the error, we need to read the data back
	 * (the data was written with errors above).
	 * The ACCESS_ONCE macros and printk are used to prevent the
	 * the compiler optimizing these reads out.
	 */
	reg = ACCESS_ONCE(ptemp[0]);
	read_reg = ACCESS_ONCE(ptemp[1]);
	/* Force Read */
	rmb();

	edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
		    reg, read_reg);

	dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);

	return count;
}

static const struct file_operations altr_sdr_mc_debug_inject_fops = {
	.open = simple_open,
	.write = altr_sdr_mc_err_inject_write,
	.llseek = generic_file_llseek,
};

static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
{
	if (mci->debugfs)
		debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
				    &altr_sdr_mc_debug_inject_fops);
}
#else
static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
{}
#endif

/* Get total memory size from Open Firmware DTB */
static unsigned long get_total_mem(void)
{
	struct device_node *np = NULL;
	const unsigned int *reg, *reg_end;
	int len, sw, aw;
	unsigned long start, size, total_mem = 0;

	for_each_node_by_type(np, "memory") {
		aw = of_n_addr_cells(np);
		sw = of_n_size_cells(np);
		reg = (const unsigned int *)of_get_property(np, "reg", &len);
		reg_end = reg + (len / sizeof(u32));

		total_mem = 0;
		do {
			start = of_read_number(reg, aw);
			reg += aw;
			size = of_read_number(reg, sw);
			reg += sw;
			total_mem += size;
		} while (reg < reg_end);
	}
	edac_dbg(0, "total_mem 0x%lx\n", total_mem);
	return total_mem;
}

static int altr_sdram_probe(struct platform_device *pdev)
{
	struct edac_mc_layer layers[2];
	struct mem_ctl_info *mci;
	struct altr_sdram_mc_data *drvdata;
	struct regmap *mc_vbase;
	struct dimm_info *dimm;
	u32 read_reg, mem_size;
	int irq;
	int res = 0;

	/* Validate the SDRAM controller has ECC enabled */
	/* Grab the register range from the sdr controller in device tree */
	mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
						   "altr,sdr-syscon");
	if (IS_ERR(mc_vbase)) {
		edac_printk(KERN_ERR, EDAC_MC,
			    "regmap for altr,sdr-syscon lookup failed.\n");
		return -ENODEV;
	}

	if (regmap_read(mc_vbase, CTLCFG_OFST, &read_reg) ||
	    ((read_reg & CTLCFG_ECC_AUTO_EN) !=	CTLCFG_ECC_AUTO_EN)) {
		edac_printk(KERN_ERR, EDAC_MC,
			    "No ECC/ECC disabled [0x%08X]\n", read_reg);
		return -ENODEV;
	}

	/* Grab memory size from device tree. */
	mem_size = get_total_mem();
	if (!mem_size) {
		edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
		return -ENODEV;
	}

	/* Ensure the SDRAM Interrupt is disabled and cleared */
	if (regmap_write(mc_vbase, DRAMINTR_OFST, DRAMINTR_INTRCLR)) {
		edac_printk(KERN_ERR, EDAC_MC,
			    "Error clearing SDRAM ECC IRQ\n");
		return -ENODEV;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		edac_printk(KERN_ERR, EDAC_MC,
			    "No irq %d in DT\n", irq);
		return -ENODEV;
	}

	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = 1;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = 1;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
			    sizeof(struct altr_sdram_mc_data));
	if (!mci)
		return -ENOMEM;

	mci->pdev = &pdev->dev;
	drvdata = mci->pvt_info;
	drvdata->mc_vbase = mc_vbase;
	platform_set_drvdata(pdev, mci);

	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
		res = -ENOMEM;
		goto free;
	}

	mci->mtype_cap = MEM_FLAG_DDR3;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
	mci->edac_cap = EDAC_FLAG_SECDED;
	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = EDAC_VERSION;
	mci->ctl_name = dev_name(&pdev->dev);
	mci->scrub_mode = SCRUB_SW_SRC;
	mci->dev_name = dev_name(&pdev->dev);

	dimm = *mci->dimms;
	dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
	dimm->grain = 8;
	dimm->dtype = DEV_X8;
	dimm->mtype = MEM_DDR3;
	dimm->edac_mode = EDAC_SECDED;

	res = edac_mc_add_mc(mci);
	if (res < 0)
		goto err;

	res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
			       0, dev_name(&pdev->dev), mci);
	if (res < 0) {
		edac_mc_printk(mci, KERN_ERR,
			       "Unable to request irq %d\n", irq);
		res = -ENODEV;
		goto err2;
	}

	if (regmap_write(drvdata->mc_vbase, DRAMINTR_OFST,
			 (DRAMINTR_INTRCLR | DRAMINTR_INTREN))) {
		edac_mc_printk(mci, KERN_ERR,
			       "Error enabling SDRAM ECC IRQ\n");
		res = -ENODEV;
		goto err2;
	}

	altr_sdr_mc_create_debugfs_nodes(mci);

	devres_close_group(&pdev->dev, NULL);

	return 0;

err2:
	edac_mc_del_mc(&pdev->dev);
err:
	devres_release_group(&pdev->dev, NULL);
free:
	edac_mc_free(mci);
	edac_printk(KERN_ERR, EDAC_MC,
		    "EDAC Probe Failed; Error %d\n", res);

	return res;
}

static int altr_sdram_remove(struct platform_device *pdev)
{
	struct mem_ctl_info *mci = platform_get_drvdata(pdev);

	edac_mc_del_mc(&pdev->dev);
	edac_mc_free(mci);
	platform_set_drvdata(pdev, NULL);

	return 0;
}

static const struct of_device_id altr_sdram_ctrl_of_match[] = {
	{ .compatible = "altr,sdram-edac", },
	{},
};
MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);

static struct platform_driver altr_sdram_edac_driver = {
	.probe = altr_sdram_probe,
	.remove = altr_sdram_remove,
	.driver = {
		.name = "altr_sdram_edac",
		.of_match_table = altr_sdram_ctrl_of_match,
	},
};

module_platform_driver(altr_sdram_edac_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Thor Thayer");
MODULE_DESCRIPTION("EDAC Driver for Altera SDRAM Controller");
Commit	Line	Data
71bcada8 TT	1	/*
	2	* Copyright Altera Corporation (C) 2014. All rights reserved.
	3	* Copyright 2011-2012 Calxeda, Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*
	17	* Adapted from the highbank_mc_edac driver.
	18	*/
	19
	20	#include <linux/ctype.h>
	21	#include <linux/edac.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/kernel.h>
	24	#include <linux/mfd/syscon.h>
	25	#include <linux/of_platform.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/regmap.h>
	28	#include <linux/types.h>
	29	#include <linux/uaccess.h>
	30
	31	#include "edac_core.h"
	32	#include "edac_module.h"
	33
	34	#define EDAC_MOD_STR "altera_edac"
	35	#define EDAC_VERSION "1"
	36
	37	/* SDRAM Controller CtrlCfg Register */
	38	#define CTLCFG_OFST 0x00
	39
	40	/* SDRAM Controller CtrlCfg Register Bit Masks */
	41	#define CTLCFG_ECC_EN 0x400
	42	#define CTLCFG_ECC_CORR_EN 0x800
	43	#define CTLCFG_GEN_SB_ERR 0x2000
	44	#define CTLCFG_GEN_DB_ERR 0x4000
	45
	46	#define CTLCFG_ECC_AUTO_EN (CTLCFG_ECC_EN \| \
	47	CTLCFG_ECC_CORR_EN)
	48
	49	/* SDRAM Controller Address Width Register */
	50	#define DRAMADDRW_OFST 0x2C
	51
	52	/* SDRAM Controller Address Widths Field Register */
	53	#define DRAMADDRW_COLBIT_MASK 0x001F
	54	#define DRAMADDRW_COLBIT_SHIFT 0
	55	#define DRAMADDRW_ROWBIT_MASK 0x03E0
	56	#define DRAMADDRW_ROWBIT_SHIFT 5
	57	#define DRAMADDRW_BANKBIT_MASK 0x1C00
	58	#define DRAMADDRW_BANKBIT_SHIFT 10
	59	#define DRAMADDRW_CSBIT_MASK 0xE000
	60	#define DRAMADDRW_CSBIT_SHIFT 13
	61
	62	/* SDRAM Controller Interface Data Width Register */
	63	#define DRAMIFWIDTH_OFST 0x30
	64
65	/* SDRAM Controller Interface Data Width Defines */
66	#define DRAMIFWIDTH_16B_ECC 24
67	#define DRAMIFWIDTH_32B_ECC 40
68
69	/* SDRAM Controller DRAM Status Register */
70	#define DRAMSTS_OFST 0x38
71
72	/* SDRAM Controller DRAM Status Register Bit Masks */
73	#define DRAMSTS_SBEERR 0x04
74	#define DRAMSTS_DBEERR 0x08
75	#define DRAMSTS_CORR_DROP 0x10
76
77	/* SDRAM Controller DRAM IRQ Register */
78	#define DRAMINTR_OFST 0x3C
79
80	/* SDRAM Controller DRAM IRQ Register Bit Masks */
81	#define DRAMINTR_INTREN 0x01
82	#define DRAMINTR_SBEMASK 0x02
83	#define DRAMINTR_DBEMASK 0x04
84	#define DRAMINTR_CORRDROPMASK 0x08
85	#define DRAMINTR_INTRCLR 0x10
86
87	/* SDRAM Controller Single Bit Error Count Register */
88	#define SBECOUNT_OFST 0x40
89
90	/* SDRAM Controller Single Bit Error Count Register Bit Masks */
91	#define SBECOUNT_MASK 0x0F
92
93	/* SDRAM Controller Double Bit Error Count Register */
94	#define DBECOUNT_OFST 0x44
95
96	/* SDRAM Controller Double Bit Error Count Register Bit Masks */
97	#define DBECOUNT_MASK 0x0F
98
99	/* SDRAM Controller ECC Error Address Register */
100	#define ERRADDR_OFST 0x48
101
102	/* SDRAM Controller ECC Error Address Register Bit Masks */
103	#define ERRADDR_MASK 0xFFFFFFFF
104
105	/* Altera SDRAM Memory Controller data */
106	struct altr_sdram_mc_data {
107	struct regmap *mc_vbase;
108	};
109
110	static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
111	{
112	struct mem_ctl_info *mci = dev_id;
113	struct altr_sdram_mc_data *drvdata = mci->pvt_info;
114	u32 status, err_count, err_addr;
115
116	/* Error Address is shared by both SBE & DBE */
117	regmap_read(drvdata->mc_vbase, ERRADDR_OFST, &err_addr);
118
119	regmap_read(drvdata->mc_vbase, DRAMSTS_OFST, &status);
120
121	if (status & DRAMSTS_DBEERR) {
122	regmap_read(drvdata->mc_vbase, DBECOUNT_OFST, &err_count);
123	panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
124	err_count, err_addr);
125	}
126	if (status & DRAMSTS_SBEERR) {
127	regmap_read(drvdata->mc_vbase, SBECOUNT_OFST, &err_count);
128	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
129	err_addr >> PAGE_SHIFT,
130	err_addr & ~PAGE_MASK, 0,
131	0, 0, -1, mci->ctl_name, "");
132	}
133
134	regmap_write(drvdata->mc_vbase, DRAMINTR_OFST,
135	(DRAMINTR_INTRCLR \| DRAMINTR_INTREN));
136
137	return IRQ_HANDLED;
138	}
139
140	#ifdef CONFIG_EDAC_DEBUG
141	static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
142	const char __user *data,
143	size_t count, loff_t *ppos)
144	{
145	struct mem_ctl_info *mci = file->private_data;
146	struct altr_sdram_mc_data *drvdata = mci->pvt_info;
147	u32 *ptemp;
148	dma_addr_t dma_handle;
149	u32 reg, read_reg;
150
151	ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
152	if (!ptemp) {
153	dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
154	edac_printk(KERN_ERR, EDAC_MC,
155	"Inject: Buffer Allocation error\n");
156	return -ENOMEM;
157	}
158
159	regmap_read(drvdata->mc_vbase, CTLCFG_OFST, &read_reg);
160	read_reg &= ~(CTLCFG_GEN_SB_ERR \| CTLCFG_GEN_DB_ERR);
161
162	/* Error are injected by writing a word while the SBE or DBE
163	* bit in the CTLCFG register is set. Reading the word will
164	* trigger the SBE or DBE error and the corresponding IRQ.
165	*/
166	if (count == 3) {
167	edac_printk(KERN_ALERT, EDAC_MC,
168	"Inject Double bit error\n");
169	regmap_write(drvdata->mc_vbase, CTLCFG_OFST,
170	(read_reg \| CTLCFG_GEN_DB_ERR));
171	} else {
172	edac_printk(KERN_ALERT, EDAC_MC,
173	"Inject Single bit error\n");
174	regmap_write(drvdata->mc_vbase, CTLCFG_OFST,
175	(read_reg \| CTLCFG_GEN_SB_ERR));
176	}
177
178	ptemp[0] = 0x5A5A5A5A;
179	ptemp[1] = 0xA5A5A5A5;
180
181	/* Clear the error injection bits */
182	regmap_write(drvdata->mc_vbase, CTLCFG_OFST, read_reg);
183	/* Ensure it has been written out */
184	wmb();
185
186	/*
187	* To trigger the error, we need to read the data back
188	* (the data was written with errors above).
189	* The ACCESS_ONCE macros and printk are used to prevent the
190	* the compiler optimizing these reads out.
191	*/
192	reg = ACCESS_ONCE(ptemp[0]);
193	read_reg = ACCESS_ONCE(ptemp[1]);
194	/* Force Read */
195	rmb();
196
197	edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
198	reg, read_reg);
199
200	dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
201
202	return count;
203	}
204
205	static const struct file_operations altr_sdr_mc_debug_inject_fops = {
206	.open = simple_open,
207	.write = altr_sdr_mc_err_inject_write,
208	.llseek = generic_file_llseek,
209	};
210
211	static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
212	{
213	if (mci->debugfs)
214	debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
215	&altr_sdr_mc_debug_inject_fops);
216	}
217	#else
218	static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
219	{}
220	#endif
221
f9ae487e TT	222	/* Get total memory size from Open Firmware DTB */
f9ae487e TT	223	static unsigned long get_total_mem(void)
71bcada8	224	{
f9ae487e TT	225	struct device_node *np = NULL;
	226	const unsigned int reg, reg_end;
	227	int len, sw, aw;
	228	unsigned long start, size, total_mem = 0;
	229
	230	for_each_node_by_type(np, "memory") {
	231	aw = of_n_addr_cells(np);
	232	sw = of_n_size_cells(np);
	233	reg = (const unsigned int *)of_get_property(np, "reg", &len);
	234	reg_end = reg + (len / sizeof(u32));
	235
	236	total_mem = 0;
	237	do {
	238	start = of_read_number(reg, aw);
	239	reg += aw;
	240	size = of_read_number(reg, sw);
	241	reg += sw;
	242	total_mem += size;
	243	} while (reg < reg_end);
	244	}
	245	edac_dbg(0, "total_mem 0x%lx\n", total_mem);
	246	return total_mem;
71bcada8 TT	247	}
	248
	249	static int altr_sdram_probe(struct platform_device *pdev)
	250	{
	251	struct edac_mc_layer layers[2];
	252	struct mem_ctl_info *mci;
	253	struct altr_sdram_mc_data *drvdata;
	254	struct regmap *mc_vbase;
	255	struct dimm_info *dimm;
	256	u32 read_reg, mem_size;
	257	int irq;
	258	int res = 0;
	259
	260	/* Validate the SDRAM controller has ECC enabled */
	261	/* Grab the register range from the sdr controller in device tree */
	262	mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
	263	"altr,sdr-syscon");
	264	if (IS_ERR(mc_vbase)) {
	265	edac_printk(KERN_ERR, EDAC_MC,
	266	"regmap for altr,sdr-syscon lookup failed.\n");
	267	return -ENODEV;
	268	}
	269
	270	if (regmap_read(mc_vbase, CTLCFG_OFST, &read_reg) \|\|
	271	((read_reg & CTLCFG_ECC_AUTO_EN) != CTLCFG_ECC_AUTO_EN)) {
	272	edac_printk(KERN_ERR, EDAC_MC,
	273	"No ECC/ECC disabled [0x%08X]\n", read_reg);
	274	return -ENODEV;
	275	}
	276
	277	/* Grab memory size from device tree. */
f9ae487e	278	mem_size = get_total_mem();
71bcada8	279	if (!mem_size) {
f9ae487e	280	edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
71bcada8 TT	281	return -ENODEV;
	282	}
	283
	284	/* Ensure the SDRAM Interrupt is disabled and cleared */
	285	if (regmap_write(mc_vbase, DRAMINTR_OFST, DRAMINTR_INTRCLR)) {
	286	edac_printk(KERN_ERR, EDAC_MC,
	287	"Error clearing SDRAM ECC IRQ\n");
	288	return -ENODEV;
	289	}
	290
	291	irq = platform_get_irq(pdev, 0);
	292	if (irq < 0) {
	293	edac_printk(KERN_ERR, EDAC_MC,
	294	"No irq %d in DT\n", irq);
	295	return -ENODEV;
	296	}
	297
	298	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	299	layers[0].size = 1;
	300	layers[0].is_virt_csrow = true;
	301	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	302	layers[1].size = 1;
	303	layers[1].is_virt_csrow = false;
	304	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
	305	sizeof(struct altr_sdram_mc_data));
	306	if (!mci)
	307	return -ENOMEM;
	308
	309	mci->pdev = &pdev->dev;
	310	drvdata = mci->pvt_info;
	311	drvdata->mc_vbase = mc_vbase;
	312	platform_set_drvdata(pdev, mci);
	313
	314	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
	315	res = -ENOMEM;
	316	goto free;
	317	}
	318
	319	mci->mtype_cap = MEM_FLAG_DDR3;
	320	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
	321	mci->edac_cap = EDAC_FLAG_SECDED;
	322	mci->mod_name = EDAC_MOD_STR;
	323	mci->mod_ver = EDAC_VERSION;
	324	mci->ctl_name = dev_name(&pdev->dev);
	325	mci->scrub_mode = SCRUB_SW_SRC;
	326	mci->dev_name = dev_name(&pdev->dev);
	327
	328	dimm = *mci->dimms;
	329	dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
	330	dimm->grain = 8;
	331	dimm->dtype = DEV_X8;
	332	dimm->mtype = MEM_DDR3;
	333	dimm->edac_mode = EDAC_SECDED;
	334
	335	res = edac_mc_add_mc(mci);
	336	if (res < 0)
	337	goto err;
	338
	339	res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
	340	0, dev_name(&pdev->dev), mci);
	341	if (res < 0) {
	342	edac_mc_printk(mci, KERN_ERR,
	343	"Unable to request irq %d\n", irq);
	344	res = -ENODEV;
345	goto err2;
346	}
347
348	if (regmap_write(drvdata->mc_vbase, DRAMINTR_OFST,
349	(DRAMINTR_INTRCLR \| DRAMINTR_INTREN))) {
350	edac_mc_printk(mci, KERN_ERR,
351	"Error enabling SDRAM ECC IRQ\n");
352	res = -ENODEV;
353	goto err2;
354	}
355
356	altr_sdr_mc_create_debugfs_nodes(mci);
357
358	devres_close_group(&pdev->dev, NULL);
359
360	return 0;
361
362	err2:
363	edac_mc_del_mc(&pdev->dev);
364	err:
365	devres_release_group(&pdev->dev, NULL);
366	free:
367	edac_mc_free(mci);
368	edac_printk(KERN_ERR, EDAC_MC,
369	"EDAC Probe Failed; Error %d\n", res);
370
371	return res;
372	}
373
374	static int altr_sdram_remove(struct platform_device *pdev)
375	{
376	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
377
378	edac_mc_del_mc(&pdev->dev);
379	edac_mc_free(mci);
380	platform_set_drvdata(pdev, NULL);
381
382	return 0;
383	}
384
385	static const struct of_device_id altr_sdram_ctrl_of_match[] = {
386	{ .compatible = "altr,sdram-edac", },
387	{},
388	};
389	MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
390
391	static struct platform_driver altr_sdram_edac_driver = {
392	.probe = altr_sdram_probe,
393	.remove = altr_sdram_remove,
394	.driver = {
395	.name = "altr_sdram_edac",
396	.of_match_table = altr_sdram_ctrl_of_match,
397	},
398	};
399
400	module_platform_driver(altr_sdram_edac_driver);
401
402	MODULE_LICENSE("GPL v2");
403	MODULE_AUTHOR("Thor Thayer");
404	MODULE_DESCRIPTION("EDAC Driver for Altera SDRAM Controller");