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143f4a5a TT |
1 | /* |
2 | * | |
3 | * Copyright (C) 2015 Altera Corporation | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef _ALTERA_EDAC_H | |
19 | #define _ALTERA_EDAC_H | |
20 | ||
21 | #include <linux/edac.h> | |
22 | #include <linux/types.h> | |
23 | ||
24 | /* SDRAM Controller CtrlCfg Register */ | |
25 | #define CV_CTLCFG_OFST 0x00 | |
26 | ||
27 | /* SDRAM Controller CtrlCfg Register Bit Masks */ | |
28 | #define CV_CTLCFG_ECC_EN 0x400 | |
29 | #define CV_CTLCFG_ECC_CORR_EN 0x800 | |
30 | #define CV_CTLCFG_GEN_SB_ERR 0x2000 | |
31 | #define CV_CTLCFG_GEN_DB_ERR 0x4000 | |
32 | ||
33 | #define CV_CTLCFG_ECC_AUTO_EN (CV_CTLCFG_ECC_EN | \ | |
34 | CV_CTLCFG_ECC_CORR_EN) | |
35 | ||
36 | /* SDRAM Controller Address Width Register */ | |
37 | #define CV_DRAMADDRW_OFST 0x2C | |
38 | ||
39 | /* SDRAM Controller Address Widths Field Register */ | |
40 | #define DRAMADDRW_COLBIT_MASK 0x001F | |
41 | #define DRAMADDRW_COLBIT_SHIFT 0 | |
42 | #define DRAMADDRW_ROWBIT_MASK 0x03E0 | |
43 | #define DRAMADDRW_ROWBIT_SHIFT 5 | |
44 | #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00 | |
45 | #define CV_DRAMADDRW_BANKBIT_SHIFT 10 | |
46 | #define CV_DRAMADDRW_CSBIT_MASK 0xE000 | |
47 | #define CV_DRAMADDRW_CSBIT_SHIFT 13 | |
48 | ||
49 | /* SDRAM Controller Interface Data Width Register */ | |
50 | #define CV_DRAMIFWIDTH_OFST 0x30 | |
51 | ||
52 | /* SDRAM Controller Interface Data Width Defines */ | |
53 | #define CV_DRAMIFWIDTH_16B_ECC 24 | |
54 | #define CV_DRAMIFWIDTH_32B_ECC 40 | |
55 | ||
56 | /* SDRAM Controller DRAM Status Register */ | |
57 | #define CV_DRAMSTS_OFST 0x38 | |
58 | ||
59 | /* SDRAM Controller DRAM Status Register Bit Masks */ | |
60 | #define CV_DRAMSTS_SBEERR 0x04 | |
61 | #define CV_DRAMSTS_DBEERR 0x08 | |
62 | #define CV_DRAMSTS_CORR_DROP 0x10 | |
63 | ||
64 | /* SDRAM Controller DRAM IRQ Register */ | |
65 | #define CV_DRAMINTR_OFST 0x3C | |
66 | ||
67 | /* SDRAM Controller DRAM IRQ Register Bit Masks */ | |
68 | #define CV_DRAMINTR_INTREN 0x01 | |
69 | #define CV_DRAMINTR_SBEMASK 0x02 | |
70 | #define CV_DRAMINTR_DBEMASK 0x04 | |
71 | #define CV_DRAMINTR_CORRDROPMASK 0x08 | |
72 | #define CV_DRAMINTR_INTRCLR 0x10 | |
73 | ||
74 | /* SDRAM Controller Single Bit Error Count Register */ | |
75 | #define CV_SBECOUNT_OFST 0x40 | |
76 | ||
77 | /* SDRAM Controller Double Bit Error Count Register */ | |
78 | #define CV_DBECOUNT_OFST 0x44 | |
79 | ||
80 | /* SDRAM Controller ECC Error Address Register */ | |
81 | #define CV_ERRADDR_OFST 0x48 | |
82 | ||
73bcc942 TT |
83 | /*-----------------------------------------*/ |
84 | ||
85 | /* SDRAM Controller EccCtrl Register */ | |
86 | #define A10_ECCCTRL1_OFST 0x00 | |
87 | ||
88 | /* SDRAM Controller EccCtrl Register Bit Masks */ | |
89 | #define A10_ECCCTRL1_ECC_EN 0x001 | |
90 | #define A10_ECCCTRL1_CNT_RST 0x010 | |
91 | #define A10_ECCCTRL1_AWB_CNT_RST 0x100 | |
92 | #define A10_ECC_CNT_RESET_MASK (A10_ECCCTRL1_CNT_RST | \ | |
93 | A10_ECCCTRL1_AWB_CNT_RST) | |
94 | ||
95 | /* SDRAM Controller Address Width Register */ | |
96 | #define CV_DRAMADDRW 0xFFC2502C | |
97 | #define A10_DRAMADDRW 0xFFCFA0A8 | |
98 | ||
99 | /* SDRAM Controller Address Widths Field Register */ | |
100 | #define DRAMADDRW_COLBIT_MASK 0x001F | |
101 | #define DRAMADDRW_COLBIT_SHIFT 0 | |
102 | #define DRAMADDRW_ROWBIT_MASK 0x03E0 | |
103 | #define DRAMADDRW_ROWBIT_SHIFT 5 | |
104 | #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00 | |
105 | #define CV_DRAMADDRW_BANKBIT_SHIFT 10 | |
106 | #define CV_DRAMADDRW_CSBIT_MASK 0xE000 | |
107 | #define CV_DRAMADDRW_CSBIT_SHIFT 13 | |
108 | ||
109 | #define A10_DRAMADDRW_BANKBIT_MASK 0x3C00 | |
110 | #define A10_DRAMADDRW_BANKBIT_SHIFT 10 | |
111 | #define A10_DRAMADDRW_GRPBIT_MASK 0xC000 | |
112 | #define A10_DRAMADDRW_GRPBIT_SHIFT 14 | |
113 | #define A10_DRAMADDRW_CSBIT_MASK 0x70000 | |
114 | #define A10_DRAMADDRW_CSBIT_SHIFT 16 | |
115 | ||
116 | /* SDRAM Controller Interface Data Width Register */ | |
117 | #define CV_DRAMIFWIDTH 0xFFC25030 | |
118 | #define A10_DRAMIFWIDTH 0xFFCFB008 | |
119 | ||
120 | /* SDRAM Controller Interface Data Width Defines */ | |
121 | #define CV_DRAMIFWIDTH_16B_ECC 24 | |
122 | #define CV_DRAMIFWIDTH_32B_ECC 40 | |
123 | ||
124 | #define A10_DRAMIFWIDTH_16B 0x0 | |
125 | #define A10_DRAMIFWIDTH_32B 0x1 | |
126 | #define A10_DRAMIFWIDTH_64B 0x2 | |
127 | ||
128 | /* SDRAM Controller DRAM IRQ Register */ | |
129 | #define A10_ERRINTEN_OFST 0x10 | |
130 | ||
131 | /* SDRAM Controller DRAM IRQ Register Bit Masks */ | |
132 | #define A10_ERRINTEN_SERRINTEN 0x01 | |
133 | #define A10_ERRINTEN_DERRINTEN 0x02 | |
134 | #define A10_ECC_IRQ_EN_MASK (A10_ERRINTEN_SERRINTEN | \ | |
135 | A10_ERRINTEN_DERRINTEN) | |
136 | ||
137 | /* SDRAM Interrupt Mode Register */ | |
138 | #define A10_INTMODE_OFST 0x1C | |
139 | #define A10_INTMODE_SB_INT 1 | |
140 | ||
141 | /* SDRAM Controller Error Status Register */ | |
142 | #define A10_INTSTAT_OFST 0x20 | |
143 | ||
144 | /* SDRAM Controller Error Status Register Bit Masks */ | |
145 | #define A10_INTSTAT_SBEERR 0x01 | |
146 | #define A10_INTSTAT_DBEERR 0x02 | |
147 | ||
148 | /* SDRAM Controller ECC Error Address Register */ | |
149 | #define A10_DERRADDR_OFST 0x2C | |
150 | #define A10_SERRADDR_OFST 0x30 | |
151 | ||
152 | /* SDRAM Controller ECC Diagnostic Register */ | |
153 | #define A10_DIAGINTTEST_OFST 0x24 | |
154 | ||
155 | #define A10_DIAGINT_TSERRA_MASK 0x0001 | |
156 | #define A10_DIAGINT_TDERRA_MASK 0x0100 | |
157 | ||
158 | #define A10_SBERR_IRQ 34 | |
159 | #define A10_DBERR_IRQ 32 | |
160 | ||
161 | /* SDRAM Single Bit Error Count Compare Set Register */ | |
162 | #define A10_SERRCNTREG_OFST 0x3C | |
163 | ||
164 | #define A10_SYMAN_INTMASK_CLR 0xFFD06098 | |
165 | #define A10_INTMASK_CLR_OFST 0x10 | |
166 | #define A10_DDR0_IRQ_MASK BIT(17) | |
167 | ||
143f4a5a TT |
168 | struct altr_sdram_prv_data { |
169 | int ecc_ctrl_offset; | |
170 | int ecc_ctl_en_mask; | |
171 | int ecc_cecnt_offset; | |
172 | int ecc_uecnt_offset; | |
173 | int ecc_stat_offset; | |
174 | int ecc_stat_ce_mask; | |
175 | int ecc_stat_ue_mask; | |
176 | int ecc_saddr_offset; | |
177 | int ecc_daddr_offset; | |
178 | int ecc_irq_en_offset; | |
179 | int ecc_irq_en_mask; | |
180 | int ecc_irq_clr_offset; | |
181 | int ecc_irq_clr_mask; | |
182 | int ecc_cnt_rst_offset; | |
183 | int ecc_cnt_rst_mask; | |
184 | #ifdef CONFIG_EDAC_DEBUG | |
185 | struct edac_dev_sysfs_attribute *eccmgr_sysfs_attr; | |
186 | int ecc_enable_mask; | |
187 | int ce_set_mask; | |
188 | int ue_set_mask; | |
189 | int ce_ue_trgr_offset; | |
190 | #endif | |
191 | }; | |
192 | ||
193 | /* Altera SDRAM Memory Controller data */ | |
194 | struct altr_sdram_mc_data { | |
195 | struct regmap *mc_vbase; | |
196 | int sb_irq; | |
197 | int db_irq; | |
198 | const struct altr_sdram_prv_data *data; | |
199 | }; | |
200 | ||
201 | #endif /* #ifndef _ALTERA_EDAC_H */ |