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[PATCH] EDAC: reorder EXPORT_SYMBOL macros
[deliverable/linux.git] / drivers / edac / e752x_edac.c
CommitLineData
806c35f5
AC		 1/*
2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e752x_chips" below for supported chipsets
8 *
9 * Written by Tom Zimmerman
10 *
11 * Contributors:
12 * Thayne Harbaugh at realmsys.com (?)
13 * Wang Zhenyu at intel.com
14 * Dave Jiang at mvista.com
15 *
da9bb1d2 16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
806c35f5
AC		 17 *
18 */
19
20
21#include <linux/config.h>
22#include <linux/module.h>
23#include <linux/init.h>
24
25#include <linux/pci.h>
26#include <linux/pci_ids.h>
27
28#include <linux/slab.h>
29
30#include "edac_mc.h"
31
32
537fba28
DP		 33#define e752x_printk(level, fmt, arg...) \
34 edac_printk(level, "e752x", fmt, ##arg)
35
36
37#define e752x_mc_printk(mci, level, fmt, arg...) \
38 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
39
40
806c35f5
AC		 41#ifndef PCI_DEVICE_ID_INTEL_7520_0
42#define PCI_DEVICE_ID_INTEL_7520_0 0x3590
43#endif /* PCI_DEVICE_ID_INTEL_7520_0 */
44
45#ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
46#define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591
47#endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */
48
49#ifndef PCI_DEVICE_ID_INTEL_7525_0
50#define PCI_DEVICE_ID_INTEL_7525_0 0x359E
51#endif /* PCI_DEVICE_ID_INTEL_7525_0 */
52
53#ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
54#define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593
55#endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */
56
57#ifndef PCI_DEVICE_ID_INTEL_7320_0
58#define PCI_DEVICE_ID_INTEL_7320_0 0x3592
59#endif /* PCI_DEVICE_ID_INTEL_7320_0 */
60
61#ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
62#define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593
63#endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */
64
65#define E752X_NR_CSROWS 8 /* number of csrows */
66
67
68/* E752X register addresses - device 0 function 0 */
69#define E752X_DRB 0x60 /* DRAM row boundary register (8b) */
70#define E752X_DRA 0x70 /* DRAM row attribute register (8b) */
71 /*
72 * 31:30 Device width row 7
73 * 01=x8 10=x4 11=x8 DDR2
74 * 27:26 Device width row 6
75 * 23:22 Device width row 5
76 * 19:20 Device width row 4
77 * 15:14 Device width row 3
78 * 11:10 Device width row 2
79 * 7:6 Device width row 1
80 * 3:2 Device width row 0
81 */
82#define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */
83 /* FIXME:IS THIS RIGHT? */
84 /*
85 * 22 Number channels 0=1,1=2
86 * 19:18 DRB Granularity 32/64MB
87 */
88#define E752X_DRM 0x80 /* Dimm mapping register */
89#define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */
90 /*
91 * 14:12 1 single A, 2 single B, 3 dual
92 */
93#define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
94#define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
95#define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
96#define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */
97
98/* E752X register addresses - device 0 function 1 */
99#define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */
100#define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */
101#define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */
102#define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */
103#define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */
104#define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */
105#define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */
106#define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */
107#define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */
108#define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */
109#define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */
110#define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */
111#define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */
112#define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */
113#define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */
114#define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */
115#define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */
116#define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */
117#define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */
118#define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */
119 /* error address register (32b) */
120 /*
121 * 31 Reserved
122 * 30:2 CE address (64 byte block 34:6)
123 * 1 Reserved
124 * 0 HiLoCS
125 */
126#define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */
127 /* error address register (32b) */
128 /*
129 * 31 Reserved
130 * 30:2 CE address (64 byte block 34:6)
131 * 1 Reserved
132 * 0 HiLoCS
133 */
134#define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */
135 /* error address register (32b) */
136 /*
137 * 31 Reserved
138 * 30:2 CE address (64 byte block 34:6)
139 * 1 Reserved
140 * 0 HiLoCS
141 */
142#define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */
143 /* error address register (32b) */
144 /*
145 * 31 Reserved
146 * 30:2 CE address (64 byte block 34:6)
147 * 1 Reserved
148 * 0 HiLoCS
149 */
150#define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */
151 /* error syndrome register (16b) */
152#define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */
153 /* error syndrome register (16b) */
154#define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */
155
156/* ICH5R register addresses - device 30 function 0 */
157#define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */
158#define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */
159#define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */
160
161enum e752x_chips {
162 E7520 = 0,
163 E7525 = 1,
164 E7320 = 2
165};
166
167
168struct e752x_pvt {
169 struct pci_dev *bridge_ck;
170 struct pci_dev *dev_d0f0;
171 struct pci_dev *dev_d0f1;
172 u32 tolm;
173 u32 remapbase;
174 u32 remaplimit;
175 int mc_symmetric;
176 u8 map[8];
177 int map_type;
178 const struct e752x_dev_info *dev_info;
179};
180
181
182struct e752x_dev_info {
183 u16 err_dev;
3847bccc 184 u16 ctl_dev;
806c35f5
AC		 185 const char *ctl_name;
186};
187
188struct e752x_error_info {
189 u32 ferr_global;
190 u32 nerr_global;
191 u8 hi_ferr;
192 u8 hi_nerr;
193 u16 sysbus_ferr;
194 u16 sysbus_nerr;
195 u8 buf_ferr;
196 u8 buf_nerr;
197 u16 dram_ferr;
198 u16 dram_nerr;
199 u32 dram_sec1_add;
200 u32 dram_sec2_add;
201 u16 dram_sec1_syndrome;
202 u16 dram_sec2_syndrome;
203 u32 dram_ded_add;
204 u32 dram_scrb_add;
205 u32 dram_retr_add;
206};
207
208static const struct e752x_dev_info e752x_devs[] = {
209 [E7520] = {
210 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
3847bccc 211 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
806c35f5
AC		 212 .ctl_name = "E7520"},
213 [E7525] = {
214 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
3847bccc 215 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
806c35f5
AC		 216 .ctl_name = "E7525"},
217 [E7320] = {
218 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
3847bccc 219 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
806c35f5
AC		 220 .ctl_name = "E7320"},
221};
222
223
224static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
225 unsigned long page)
226{
227 u32 remap;
228 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
229
537fba28 230 debugf3("%s()\n", __func__);
806c35f5
AC		 231
232 if (page < pvt->tolm)
233 return page;
234 if ((page >= 0x100000) && (page < pvt->remapbase))
235 return page;
236 remap = (page - pvt->tolm) + pvt->remapbase;
237 if (remap < pvt->remaplimit)
238 return remap;
537fba28 239 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
806c35f5
AC		 240 return pvt->tolm - 1;
241}
242
243static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
244 u32 sec1_add, u16 sec1_syndrome)
245{
246 u32 page;
247 int row;
248 int channel;
249 int i;
250 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
251
537fba28 252 debugf3("%s()\n", __func__);
806c35f5
AC		 253
254 /* convert the addr to 4k page */
255 page = sec1_add >> (PAGE_SHIFT - 4);
256
257 /* FIXME - check for -1 */
258 if (pvt->mc_symmetric) {
259 /* chip select are bits 14 & 13 */
260 row = ((page >> 1) & 3);
537fba28
DP		 261 e752x_printk(KERN_WARNING,
262 "Test row %d Table %d %d %d %d %d %d %d %d\n",
263 row, pvt->map[0], pvt->map[1], pvt->map[2],
264 pvt->map[3], pvt->map[4], pvt->map[5],
265 pvt->map[6], pvt->map[7]);
806c35f5
AC		 266
267 /* test for channel remapping */
268 for (i = 0; i < 8; i++) {
269 if (pvt->map[i] == row)
270 break;
271 }
537fba28 272 e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
806c35f5
AC		 273 if (i < 8)
274 row = i;
275 else
537fba28
DP		 276 e752x_mc_printk(mci, KERN_WARNING,
277 "row %d not found in remap table\n", row);
806c35f5
AC		 278 } else
279 row = edac_mc_find_csrow_by_page(mci, page);
280 /* 0 = channel A, 1 = channel B */
281 channel = !(error_one & 1);
282
283 if (!pvt->map_type)
284 row = 7 - row;
285 edac_mc_handle_ce(mci, page, 0, sec1_syndrome, row, channel,
286 "e752x CE");
287}
288
289
290static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
291 u32 sec1_add, u16 sec1_syndrome, int *error_found,
292 int handle_error)
293{
294 *error_found = 1;
295
296 if (handle_error)
297 do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
298}
299
300static void do_process_ue(struct mem_ctl_info *mci, u16 error_one, u32 ded_add,
301 u32 scrb_add)
302{
303 u32 error_2b, block_page;
304 int row;
305 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
306
537fba28 307 debugf3("%s()\n", __func__);
806c35f5
AC		 308
309 if (error_one & 0x0202) {
310 error_2b = ded_add;
311 /* convert to 4k address */
312 block_page = error_2b >> (PAGE_SHIFT - 4);
313 row = pvt->mc_symmetric ?
314 /* chip select are bits 14 & 13 */
315 ((block_page >> 1) & 3) :
316 edac_mc_find_csrow_by_page(mci, block_page);
317 edac_mc_handle_ue(mci, block_page, 0, row,
318 "e752x UE from Read");
319 }
320 if (error_one & 0x0404) {
321 error_2b = scrb_add;
322 /* convert to 4k address */
323 block_page = error_2b >> (PAGE_SHIFT - 4);
324 row = pvt->mc_symmetric ?
325 /* chip select are bits 14 & 13 */
326 ((block_page >> 1) & 3) :
327 edac_mc_find_csrow_by_page(mci, block_page);
328 edac_mc_handle_ue(mci, block_page, 0, row,
329 "e752x UE from Scruber");
330 }
331}
332
333static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
334 u32 ded_add, u32 scrb_add, int *error_found, int handle_error)
335{
336 *error_found = 1;
337
338 if (handle_error)
339 do_process_ue(mci, error_one, ded_add, scrb_add);
340}
341
342static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
343 int *error_found, int handle_error)
344{
345 *error_found = 1;
346
347 if (!handle_error)
348 return;
349
537fba28 350 debugf3("%s()\n", __func__);
806c35f5
AC		 351 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
352}
353
354static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
355 u32 retry_add)
356{
357 u32 error_1b, page;
358 int row;
359 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
360
361 error_1b = retry_add;
362 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */
363 row = pvt->mc_symmetric ?
364 ((page >> 1) & 3) : /* chip select are bits 14 & 13 */
365 edac_mc_find_csrow_by_page(mci, page);
537fba28
DP		 366 e752x_mc_printk(mci, KERN_WARNING,
367 "CE page 0x%lx, row %d : Memory read retry\n",
368 (long unsigned int) page, row);
806c35f5
AC		 369}
370
371static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
372 u32 retry_add, int *error_found, int handle_error)
373{
374 *error_found = 1;
375
376 if (handle_error)
377 do_process_ded_retry(mci, error, retry_add);
378}
379
380static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
381 int *error_found, int handle_error)
382{
383 *error_found = 1;
384
385 if (handle_error)
537fba28 386 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
806c35f5
AC		 387}
388
da9bb1d2 389static char *global_message[11] = {
806c35f5
AC		 390 "PCI Express C1", "PCI Express C", "PCI Express B1",
391 "PCI Express B", "PCI Express A1", "PCI Express A",
392 "DMA Controler", "HUB Interface", "System Bus",
393 "DRAM Controler", "Internal Buffer"
394};
395
da9bb1d2 396static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
806c35f5
AC		 397
398static void do_global_error(int fatal, u32 errors)
399{
400 int i;
401
402 for (i = 0; i < 11; i++) {
403 if (errors & (1 << i))
537fba28 404 e752x_printk(KERN_WARNING, "%sError %s\n",
806c35f5
AC		 405 fatal_message[fatal], global_message[i]);
406 }
407}
408
409static inline void global_error(int fatal, u32 errors, int *error_found,
410 int handle_error)
411{
412 *error_found = 1;
413
414 if (handle_error)
415 do_global_error(fatal, errors);
416}
417
da9bb1d2 418static char *hub_message[7] = {
806c35f5
AC		 419 "HI Address or Command Parity", "HI Illegal Access",
420 "HI Internal Parity", "Out of Range Access",
421 "HI Data Parity", "Enhanced Config Access",
422 "Hub Interface Target Abort"
423};
424
425static void do_hub_error(int fatal, u8 errors)
426{
427 int i;
428
429 for (i = 0; i < 7; i++) {
430 if (errors & (1 << i))
537fba28 431 e752x_printk(KERN_WARNING, "%sError %s\n",
806c35f5
AC		 432 fatal_message[fatal], hub_message[i]);
433 }
434}
435
436static inline void hub_error(int fatal, u8 errors, int *error_found,
437 int handle_error)
438{
439 *error_found = 1;
440
441 if (handle_error)
442 do_hub_error(fatal, errors);
443}
444
da9bb1d2 445static char *membuf_message[4] = {
806c35f5
AC		 446 "Internal PMWB to DRAM parity",
447 "Internal PMWB to System Bus Parity",
448 "Internal System Bus or IO to PMWB Parity",
449 "Internal DRAM to PMWB Parity"
450};
451
452static void do_membuf_error(u8 errors)
453{
454 int i;
455
456 for (i = 0; i < 4; i++) {
457 if (errors & (1 << i))
537fba28 458 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
806c35f5
AC		 459 membuf_message[i]);
460 }
461}
462
463static inline void membuf_error(u8 errors, int *error_found, int handle_error)
464{
465 *error_found = 1;
466
467 if (handle_error)
468 do_membuf_error(errors);
469}
470
da9bb1d2 471#if 0
806c35f5
AC		 472char *sysbus_message[10] = {
473 "Addr or Request Parity",
474 "Data Strobe Glitch",
475 "Addr Strobe Glitch",
476 "Data Parity",
477 "Addr Above TOM",
478 "Non DRAM Lock Error",
479 "MCERR", "BINIT",
480 "Memory Parity",
481 "IO Subsystem Parity"
482};
da9bb1d2 483#endif /* 0 */
806c35f5
AC		 484
485static void do_sysbus_error(int fatal, u32 errors)
486{
487 int i;
488
489 for (i = 0; i < 10; i++) {
490 if (errors & (1 << i))
537fba28 491 e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
806c35f5
AC		 492 fatal_message[fatal], global_message[i]);
493 }
494}
495
496static inline void sysbus_error(int fatal, u32 errors, int *error_found,
497 int handle_error)
498{
499 *error_found = 1;
500
501 if (handle_error)
502 do_sysbus_error(fatal, errors);
503}
504
505static void e752x_check_hub_interface (struct e752x_error_info *info,
506 int *error_found, int handle_error)
507{
508 u8 stat8;
509
510 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
511 stat8 = info->hi_ferr;
512 if(stat8 & 0x7f) { /* Error, so process */
513 stat8 &= 0x7f;
514 if(stat8 & 0x2b)
515 hub_error(1, stat8 & 0x2b, error_found, handle_error);
516 if(stat8 & 0x54)
517 hub_error(0, stat8 & 0x54, error_found, handle_error);
518 }
519 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
520 stat8 = info->hi_nerr;
521 if(stat8 & 0x7f) { /* Error, so process */
522 stat8 &= 0x7f;
523 if (stat8 & 0x2b)
524 hub_error(1, stat8 & 0x2b, error_found, handle_error);
525 if(stat8 & 0x54)
526 hub_error(0, stat8 & 0x54, error_found, handle_error);
527 }
528}
529
530static void e752x_check_sysbus (struct e752x_error_info *info, int *error_found,
531 int handle_error)
532{
533 u32 stat32, error32;
534
535 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
536 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
537
538 if (stat32 == 0)
539 return; /* no errors */
540
541 error32 = (stat32 >> 16) & 0x3ff;
542 stat32 = stat32 & 0x3ff;
543 if(stat32 & 0x083)
544 sysbus_error(1, stat32 & 0x083, error_found, handle_error);
545 if(stat32 & 0x37c)
546 sysbus_error(0, stat32 & 0x37c, error_found, handle_error);
547 if(error32 & 0x083)
548 sysbus_error(1, error32 & 0x083, error_found, handle_error);
549 if(error32 & 0x37c)
550 sysbus_error(0, error32 & 0x37c, error_found, handle_error);
551}
552
553static void e752x_check_membuf (struct e752x_error_info *info, int *error_found,
554 int handle_error)
555{
556 u8 stat8;
557
558 stat8 = info->buf_ferr;
559 if (stat8 & 0x0f) { /* Error, so process */
560 stat8 &= 0x0f;
561 membuf_error(stat8, error_found, handle_error);
562 }
563 stat8 = info->buf_nerr;
564 if (stat8 & 0x0f) { /* Error, so process */
565 stat8 &= 0x0f;
566 membuf_error(stat8, error_found, handle_error);
567 }
568}
569
570static void e752x_check_dram (struct mem_ctl_info *mci,
571 struct e752x_error_info *info, int *error_found, int handle_error)
572{
573 u16 error_one, error_next;
574
575 error_one = info->dram_ferr;
576 error_next = info->dram_nerr;
577
578 /* decode and report errors */
579 if(error_one & 0x0101) /* check first error correctable */
580 process_ce(mci, error_one, info->dram_sec1_add,
581 info->dram_sec1_syndrome, error_found,
582 handle_error);
583
584 if(error_next & 0x0101) /* check next error correctable */
585 process_ce(mci, error_next, info->dram_sec2_add,
586 info->dram_sec2_syndrome, error_found,
587 handle_error);
588
589 if(error_one & 0x4040)
590 process_ue_no_info_wr(mci, error_found, handle_error);
591
592 if(error_next & 0x4040)
593 process_ue_no_info_wr(mci, error_found, handle_error);
594
595 if(error_one & 0x2020)
596 process_ded_retry(mci, error_one, info->dram_retr_add,
597 error_found, handle_error);
598
599 if(error_next & 0x2020)
600 process_ded_retry(mci, error_next, info->dram_retr_add,
601 error_found, handle_error);
602
603 if(error_one & 0x0808)
604 process_threshold_ce(mci, error_one, error_found,
605 handle_error);
606
607 if(error_next & 0x0808)
608 process_threshold_ce(mci, error_next, error_found,
609 handle_error);
610
611 if(error_one & 0x0606)
612 process_ue(mci, error_one, info->dram_ded_add,
613 info->dram_scrb_add, error_found, handle_error);
614
615 if(error_next & 0x0606)
616 process_ue(mci, error_next, info->dram_ded_add,
617 info->dram_scrb_add, error_found, handle_error);
618}
619
620static void e752x_get_error_info (struct mem_ctl_info *mci,
621 struct e752x_error_info *info)
622{
623 struct pci_dev *dev;
624 struct e752x_pvt *pvt;
625
626 memset(info, 0, sizeof(*info));
627 pvt = (struct e752x_pvt *) mci->pvt_info;
628 dev = pvt->dev_d0f1;
629
630 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
631
632 if (info->ferr_global) {
633 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr);
634 pci_read_config_word(dev, E752X_SYSBUS_FERR,
635 &info->sysbus_ferr);
636 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
637 pci_read_config_word(dev, E752X_DRAM_FERR,
638 &info->dram_ferr);
639 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
640 &info->dram_sec1_add);
641 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
642 &info->dram_sec1_syndrome);
643 pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
644 &info->dram_ded_add);
645 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
646 &info->dram_scrb_add);
647 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
648 &info->dram_retr_add);
649
650 if (info->hi_ferr & 0x7f)
651 pci_write_config_byte(dev, E752X_HI_FERR,
652 info->hi_ferr);
653
654 if (info->sysbus_ferr)
655 pci_write_config_word(dev, E752X_SYSBUS_FERR,
656 info->sysbus_ferr);
657
658 if (info->buf_ferr & 0x0f)
659 pci_write_config_byte(dev, E752X_BUF_FERR,
660 info->buf_ferr);
661
662 if (info->dram_ferr)
663 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
664 info->dram_ferr, info->dram_ferr);
665
666 pci_write_config_dword(dev, E752X_FERR_GLOBAL,
667 info->ferr_global);
668 }
669
670 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
671
672 if (info->nerr_global) {
673 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr);
674 pci_read_config_word(dev, E752X_SYSBUS_NERR,
675 &info->sysbus_nerr);
676 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
677 pci_read_config_word(dev, E752X_DRAM_NERR,
678 &info->dram_nerr);
679 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
680 &info->dram_sec2_add);
681 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
682 &info->dram_sec2_syndrome);
683
684 if (info->hi_nerr & 0x7f)
685 pci_write_config_byte(dev, E752X_HI_NERR,
686 info->hi_nerr);
687
688 if (info->sysbus_nerr)
689 pci_write_config_word(dev, E752X_SYSBUS_NERR,
690 info->sysbus_nerr);
691
692 if (info->buf_nerr & 0x0f)
693 pci_write_config_byte(dev, E752X_BUF_NERR,
694 info->buf_nerr);
695
696 if (info->dram_nerr)
697 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
698 info->dram_nerr, info->dram_nerr);
699
700 pci_write_config_dword(dev, E752X_NERR_GLOBAL,
701 info->nerr_global);
702 }
703}
704
705static int e752x_process_error_info (struct mem_ctl_info *mci,
706 struct e752x_error_info *info, int handle_errors)
707{
708 u32 error32, stat32;
709 int error_found;
710
711 error_found = 0;
712 error32 = (info->ferr_global >> 18) & 0x3ff;
713 stat32 = (info->ferr_global >> 4) & 0x7ff;
714
715 if (error32)
716 global_error(1, error32, &error_found, handle_errors);
717
718 if (stat32)
719 global_error(0, stat32, &error_found, handle_errors);
720
721 error32 = (info->nerr_global >> 18) & 0x3ff;
722 stat32 = (info->nerr_global >> 4) & 0x7ff;
723
724 if (error32)
725 global_error(1, error32, &error_found, handle_errors);
726
727 if (stat32)
728 global_error(0, stat32, &error_found, handle_errors);
729
730 e752x_check_hub_interface(info, &error_found, handle_errors);
731 e752x_check_sysbus(info, &error_found, handle_errors);
732 e752x_check_membuf(info, &error_found, handle_errors);
733 e752x_check_dram(mci, info, &error_found, handle_errors);
734 return error_found;
735}
736
737static void e752x_check(struct mem_ctl_info *mci)
738{
739 struct e752x_error_info info;
537fba28 740 debugf3("%s()\n", __func__);
806c35f5
AC		 741 e752x_get_error_info(mci, &info);
742 e752x_process_error_info(mci, &info, 1);
743}
744
745static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
746{
747 int rc = -ENODEV;
748 int index;
3847bccc 749 u16 pci_data;
806c35f5
AC		 750 u8 stat8;
751 struct mem_ctl_info *mci = NULL;
752 struct e752x_pvt *pvt = NULL;
753 u16 ddrcsr;
754 u32 drc;
755 int drc_chan; /* Number of channels 0=1chan,1=2chan */
756 int drc_drbg; /* DRB granularity 0=64mb,1=128mb */
757 int drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
758 u32 dra;
759 unsigned long last_cumul_size;
806c35f5 760 struct pci_dev *dev = NULL;
749ede57 761 struct e752x_error_info discard;
806c35f5 762
537fba28 763 debugf0("%s(): mci\n", __func__);
806c35f5
AC		 764 debugf0("Starting Probe1\n");
765
766 /* enable device 0 function 1 */
767 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
768 stat8 |= (1 << 5);
769 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
770
771 /* need to find out the number of channels */
772 pci_read_config_dword(pdev, E752X_DRC, &drc);
773 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
774 /* FIXME: should check >>12 or 0xf, true for all? */
775 /* Dual channel = 1, Single channel = 0 */
776 drc_chan = (((ddrcsr >> 12) & 3) == 3);
777 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
778 drc_ddim = (drc >> 20) & 0x3;
779
780 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1);
781
782 if (mci == NULL) {
783 rc = -ENOMEM;
784 goto fail;
785 }
786
537fba28 787 debugf3("%s(): init mci\n", __func__);
806c35f5
AC		 788
789 mci->mtype_cap = MEM_FLAG_RDDR;
790 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
791 EDAC_FLAG_S4ECD4ED;
792 /* FIXME - what if different memory types are in different csrows? */
680cbbbb 793 mci->mod_name = EDAC_MOD_STR;
806c35f5
AC		 794 mci->mod_ver = "$Revision: 1.5.2.11 $";
795 mci->pdev = pdev;
796
537fba28 797 debugf3("%s(): init pvt\n", __func__);
806c35f5
AC		 798 pvt = (struct e752x_pvt *) mci->pvt_info;
799 pvt->dev_info = &e752x_devs[dev_idx];
800 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
801 pvt->dev_info->err_dev,
802 pvt->bridge_ck);
803 if (pvt->bridge_ck == NULL)
804 pvt->bridge_ck = pci_scan_single_device(pdev->bus,
805 PCI_DEVFN(0, 1));
806 if (pvt->bridge_ck == NULL) {
537fba28 807 e752x_printk(KERN_ERR, "error reporting device not found:"
806c35f5
AC		 808 "vendor %x device 0x%x (broken BIOS?)\n",
809 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
810 goto fail;
811 }
812 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
813
537fba28 814 debugf3("%s(): more mci init\n", __func__);
806c35f5
AC		 815 mci->ctl_name = pvt->dev_info->ctl_name;
816 mci->edac_check = e752x_check;
817 mci->ctl_page_to_phys = ctl_page_to_phys;
818
819 /* find out the device types */
820 pci_read_config_dword(pdev, E752X_DRA, &dra);
821
822 /*
823 * The dram row boundary (DRB) reg values are boundary address for
824 * each DRAM row with a granularity of 64 or 128MB (single/dual
825 * channel operation). DRB regs are cumulative; therefore DRB7 will
826 * contain the total memory contained in all eight rows.
827 */
828 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
829 u8 value;
830 u32 cumul_size;
831 /* mem_dev 0=x8, 1=x4 */
832 int mem_dev = (dra >> (index * 4 + 2)) & 0x3;
833 struct csrow_info *csrow = &mci->csrows[index];
834
835 mem_dev = (mem_dev == 2);
836 pci_read_config_byte(mci->pdev, E752X_DRB + index, &value);
837 /* convert a 128 or 64 MiB DRB to a page size. */
838 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
537fba28
DP		 839 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
840 cumul_size);
806c35f5
AC		 841 if (cumul_size == last_cumul_size)
842 continue; /* not populated */
843
844 csrow->first_page = last_cumul_size;
845 csrow->last_page = cumul_size - 1;
846 csrow->nr_pages = cumul_size - last_cumul_size;
847 last_cumul_size = cumul_size;
848 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
849 csrow->mtype = MEM_RDDR; /* only one type supported */
850 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
851
852 /*
853 * if single channel or x8 devices then SECDED
854 * if dual channel and x4 then S4ECD4ED
855 */
856 if (drc_ddim) {
857 if (drc_chan && mem_dev) {
858 csrow->edac_mode = EDAC_S4ECD4ED;
859 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
860 } else {
861 csrow->edac_mode = EDAC_SECDED;
862 mci->edac_cap |= EDAC_FLAG_SECDED;
863 }
864 } else
865 csrow->edac_mode = EDAC_NONE;
866 }
867
868 /* Fill in the memory map table */
869 {
870 u8 value;
871 u8 last = 0;
872 u8 row = 0;
873 for (index = 0; index < 8; index += 2) {
874
875 pci_read_config_byte(mci->pdev, E752X_DRB + index,
876 &value);
877 /* test if there is a dimm in this slot */
878 if (value == last) {
879 /* no dimm in the slot, so flag it as empty */
880 pvt->map[index] = 0xff;
881 pvt->map[index + 1] = 0xff;
882 } else { /* there is a dimm in the slot */
883 pvt->map[index] = row;
884 row++;
885 last = value;
886 /* test the next value to see if the dimm is
887 double sided */
888 pci_read_config_byte(mci->pdev,
889 E752X_DRB + index + 1,
890 &value);
891 pvt->map[index + 1] = (value == last) ?
892 0xff : /* the dimm is single sided,
893 so flag as empty */
894 row; /* this is a double sided dimm
895 to save the next row # */
896 row++;
897 last = value;
898 }
899 }
900 }
901
902 /* set the map type. 1 = normal, 0 = reversed */
903 pci_read_config_byte(mci->pdev, E752X_DRM, &stat8);
904 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
905
906 mci->edac_cap |= EDAC_FLAG_NONE;
907
537fba28 908 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
806c35f5
AC		 909 /* load the top of low memory, remap base, and remap limit vars */
910 pci_read_config_word(mci->pdev, E752X_TOLM, &pci_data);
911 pvt->tolm = ((u32) pci_data) << 4;
912 pci_read_config_word(mci->pdev, E752X_REMAPBASE, &pci_data);
913 pvt->remapbase = ((u32) pci_data) << 14;
914 pci_read_config_word(mci->pdev, E752X_REMAPLIMIT, &pci_data);
915 pvt->remaplimit = ((u32) pci_data) << 14;
537fba28
DP		 916 e752x_printk(KERN_INFO,
917 "tolm = %x, remapbase = %x, remaplimit = %x\n",
918 pvt->tolm, pvt->remapbase, pvt->remaplimit);
806c35f5
AC		 919
920 if (edac_mc_add_mc(mci)) {
537fba28 921 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
806c35f5
AC		 922 goto fail;
923 }
924
3847bccc
DP		 925 dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev,
926 NULL);
806c35f5 927 pvt->dev_d0f0 = dev;
806c35f5
AC		 928 /* find the error reporting device and clear errors */
929 dev = pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
930 /* Turn off error disable & SMI in case the BIOS turned it on */
931 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
932 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
933 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00);
934 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
935 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
936 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
937 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
938 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
939 /* clear other MCH errors */
749ede57 940 e752x_get_error_info(mci, &discard);
806c35f5
AC		 941
942 /* get this far and it's successful */
537fba28 943 debugf3("%s(): success\n", __func__);
806c35f5
AC		 944 return 0;
945
946fail:
947 if (mci) {
948 if (pvt->dev_d0f0)
949 pci_dev_put(pvt->dev_d0f0);
950 if (pvt->dev_d0f1)
951 pci_dev_put(pvt->dev_d0f1);
952 if (pvt->bridge_ck)
953 pci_dev_put(pvt->bridge_ck);
954 edac_mc_free(mci);
955 }
956 return rc;
957}
958
959/* returns count (>= 0), or negative on error */
960static int __devinit e752x_init_one(struct pci_dev *pdev,
961 const struct pci_device_id *ent)
962{
537fba28 963 debugf0("%s()\n", __func__);
806c35f5
AC		 964
965 /* wake up and enable device */
966 if(pci_enable_device(pdev) < 0)
967 return -EIO;
968 return e752x_probe1(pdev, ent->driver_data);
969}
970
971
972static void __devexit e752x_remove_one(struct pci_dev *pdev)
973{
974 struct mem_ctl_info *mci;
975 struct e752x_pvt *pvt;
976
537fba28 977 debugf0("%s()\n", __func__);
806c35f5 978
18dbc337 979 if ((mci = edac_mc_del_mc(pdev)) == NULL)
806c35f5
AC		 980 return;
981
982 pvt = (struct e752x_pvt *) mci->pvt_info;
983 pci_dev_put(pvt->dev_d0f0);
984 pci_dev_put(pvt->dev_d0f1);
985 pci_dev_put(pvt->bridge_ck);
986 edac_mc_free(mci);
987}
988
989
990static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
991 {PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
992 E7520},
993 {PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
994 E7525},
995 {PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
996 E7320},
997 {0,} /* 0 terminated list. */
998};
999
1000MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1001
1002
1003static struct pci_driver e752x_driver = {
680cbbbb 1004 .name = EDAC_MOD_STR,
0d38b049
RD		 1005 .probe = e752x_init_one,
1006 .remove = __devexit_p(e752x_remove_one),
1007 .id_table = e752x_pci_tbl,
806c35f5
AC		 1008};
1009
1010
da9bb1d2 1011static int __init e752x_init(void)
806c35f5
AC		 1012{
1013 int pci_rc;
1014
537fba28 1015 debugf3("%s()\n", __func__);
806c35f5
AC		 1016 pci_rc = pci_register_driver(&e752x_driver);
1017 return (pci_rc < 0) ? pci_rc : 0;
1018}
1019
1020
1021static void __exit e752x_exit(void)
1022{
537fba28 1023 debugf3("%s()\n", __func__);
806c35f5
AC		 1024 pci_unregister_driver(&e752x_driver);
1025}
1026
1027
1028module_init(e752x_init);
1029module_exit(e752x_exit);
1030
1031MODULE_LICENSE("GPL");
1032MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1033MODULE_DESCRIPTION("MC support for Intel e752x memory controllers");
Linux kernel - Deliverables
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