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7c9281d7 DT |
1 | /* |
2 | * Defines, structures, APIs for edac_core module | |
3 | * | |
4 | * (C) 2007 Linux Networx (http://lnxi.com) | |
5 | * This file may be distributed under the terms of the | |
6 | * GNU General Public License. | |
7 | * | |
8 | * Written by Thayne Harbaugh | |
9 | * Based on work by Dan Hollis <goemon at anime dot net> and others. | |
10 | * http://www.anime.net/~goemon/linux-ecc/ | |
11 | * | |
12 | * NMI handling support added by | |
13 | * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com> | |
14 | * | |
15 | * Refactored for multi-source files: | |
16 | * Doug Thompson <norsk5@xmission.com> | |
17 | * | |
18 | */ | |
19 | ||
20 | #ifndef _EDAC_CORE_H_ | |
21 | #define _EDAC_CORE_H_ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/smp.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/time.h> | |
30 | #include <linux/nmi.h> | |
31 | #include <linux/rcupdate.h> | |
32 | #include <linux/completion.h> | |
33 | #include <linux/kobject.h> | |
34 | #include <linux/platform_device.h> | |
e27e3dac DT |
35 | #include <linux/sysdev.h> |
36 | #include <linux/workqueue.h> | |
37 | #include <linux/version.h> | |
7c9281d7 DT |
38 | |
39 | #define EDAC_MC_LABEL_LEN 31 | |
e27e3dac DT |
40 | #define EDAC_DEVICE_NAME_LEN 31 |
41 | #define EDAC_ATTRIB_VALUE_LEN 15 | |
42 | #define MC_PROC_NAME_MAX_LEN 7 | |
7c9281d7 DT |
43 | |
44 | #if PAGE_SHIFT < 20 | |
45 | #define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) ) | |
46 | #else /* PAGE_SHIFT > 20 */ | |
47 | #define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) ) | |
48 | #endif | |
49 | ||
50 | #define edac_printk(level, prefix, fmt, arg...) \ | |
51 | printk(level "EDAC " prefix ": " fmt, ##arg) | |
52 | ||
53 | #define edac_mc_printk(mci, level, fmt, arg...) \ | |
54 | printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg) | |
55 | ||
56 | #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \ | |
57 | printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg) | |
58 | ||
e27e3dac DT |
59 | /* edac_device printk */ |
60 | #define edac_device_printk(ctl, level, fmt, arg...) \ | |
61 | printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg) | |
62 | ||
91b99041 DJ |
63 | /* edac_pci printk */ |
64 | #define edac_pci_printk(ctl, level, fmt, arg...) \ | |
65 | printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg) | |
66 | ||
7c9281d7 DT |
67 | /* prefixes for edac_printk() and edac_mc_printk() */ |
68 | #define EDAC_MC "MC" | |
69 | #define EDAC_PCI "PCI" | |
70 | #define EDAC_DEBUG "DEBUG" | |
71 | ||
72 | #ifdef CONFIG_EDAC_DEBUG | |
73 | extern int edac_debug_level; | |
74 | ||
75 | #define edac_debug_printk(level, fmt, arg...) \ | |
76 | do { \ | |
77 | if (level <= edac_debug_level) \ | |
e27e3dac | 78 | edac_printk(KERN_EMERG, EDAC_DEBUG, fmt, ##arg); \ |
7c9281d7 DT |
79 | } while(0) |
80 | ||
81 | #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ ) | |
82 | #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ ) | |
83 | #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ ) | |
84 | #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ ) | |
85 | #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ ) | |
86 | ||
87 | #else /* !CONFIG_EDAC_DEBUG */ | |
88 | ||
89 | #define debugf0( ... ) | |
90 | #define debugf1( ... ) | |
91 | #define debugf2( ... ) | |
92 | #define debugf3( ... ) | |
93 | #define debugf4( ... ) | |
94 | ||
95 | #endif /* !CONFIG_EDAC_DEBUG */ | |
96 | ||
97 | #define BIT(x) (1 << (x)) | |
98 | ||
99 | #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \ | |
100 | PCI_DEVICE_ID_ ## vend ## _ ## dev | |
101 | ||
c4192705 | 102 | #define dev_name(dev) (dev)->dev_name |
7c9281d7 DT |
103 | |
104 | /* memory devices */ | |
105 | enum dev_type { | |
106 | DEV_UNKNOWN = 0, | |
107 | DEV_X1, | |
108 | DEV_X2, | |
109 | DEV_X4, | |
110 | DEV_X8, | |
111 | DEV_X16, | |
112 | DEV_X32, /* Do these parts exist? */ | |
113 | DEV_X64 /* Do these parts exist? */ | |
114 | }; | |
115 | ||
116 | #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN) | |
117 | #define DEV_FLAG_X1 BIT(DEV_X1) | |
118 | #define DEV_FLAG_X2 BIT(DEV_X2) | |
119 | #define DEV_FLAG_X4 BIT(DEV_X4) | |
120 | #define DEV_FLAG_X8 BIT(DEV_X8) | |
121 | #define DEV_FLAG_X16 BIT(DEV_X16) | |
122 | #define DEV_FLAG_X32 BIT(DEV_X32) | |
123 | #define DEV_FLAG_X64 BIT(DEV_X64) | |
124 | ||
125 | /* memory types */ | |
126 | enum mem_type { | |
127 | MEM_EMPTY = 0, /* Empty csrow */ | |
128 | MEM_RESERVED, /* Reserved csrow type */ | |
129 | MEM_UNKNOWN, /* Unknown csrow type */ | |
130 | MEM_FPM, /* Fast page mode */ | |
131 | MEM_EDO, /* Extended data out */ | |
132 | MEM_BEDO, /* Burst Extended data out */ | |
133 | MEM_SDR, /* Single data rate SDRAM */ | |
134 | MEM_RDR, /* Registered single data rate SDRAM */ | |
135 | MEM_DDR, /* Double data rate SDRAM */ | |
136 | MEM_RDDR, /* Registered Double data rate SDRAM */ | |
137 | MEM_RMBS, /* Rambus DRAM */ | |
138 | MEM_DDR2, /* DDR2 RAM */ | |
139 | MEM_FB_DDR2, /* fully buffered DDR2 */ | |
140 | MEM_RDDR2, /* Registered DDR2 RAM */ | |
141 | }; | |
142 | ||
143 | #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) | |
144 | #define MEM_FLAG_RESERVED BIT(MEM_RESERVED) | |
145 | #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN) | |
146 | #define MEM_FLAG_FPM BIT(MEM_FPM) | |
147 | #define MEM_FLAG_EDO BIT(MEM_EDO) | |
148 | #define MEM_FLAG_BEDO BIT(MEM_BEDO) | |
149 | #define MEM_FLAG_SDR BIT(MEM_SDR) | |
150 | #define MEM_FLAG_RDR BIT(MEM_RDR) | |
151 | #define MEM_FLAG_DDR BIT(MEM_DDR) | |
152 | #define MEM_FLAG_RDDR BIT(MEM_RDDR) | |
153 | #define MEM_FLAG_RMBS BIT(MEM_RMBS) | |
154 | #define MEM_FLAG_DDR2 BIT(MEM_DDR2) | |
155 | #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2) | |
156 | #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2) | |
157 | ||
158 | /* chipset Error Detection and Correction capabilities and mode */ | |
159 | enum edac_type { | |
160 | EDAC_UNKNOWN = 0, /* Unknown if ECC is available */ | |
161 | EDAC_NONE, /* Doesnt support ECC */ | |
162 | EDAC_RESERVED, /* Reserved ECC type */ | |
163 | EDAC_PARITY, /* Detects parity errors */ | |
164 | EDAC_EC, /* Error Checking - no correction */ | |
165 | EDAC_SECDED, /* Single bit error correction, Double detection */ | |
166 | EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */ | |
167 | EDAC_S4ECD4ED, /* Chipkill x4 devices */ | |
168 | EDAC_S8ECD8ED, /* Chipkill x8 devices */ | |
169 | EDAC_S16ECD16ED, /* Chipkill x16 devices */ | |
170 | }; | |
171 | ||
172 | #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN) | |
173 | #define EDAC_FLAG_NONE BIT(EDAC_NONE) | |
174 | #define EDAC_FLAG_PARITY BIT(EDAC_PARITY) | |
175 | #define EDAC_FLAG_EC BIT(EDAC_EC) | |
176 | #define EDAC_FLAG_SECDED BIT(EDAC_SECDED) | |
177 | #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED) | |
178 | #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED) | |
179 | #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED) | |
180 | #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED) | |
181 | ||
182 | /* scrubbing capabilities */ | |
183 | enum scrub_type { | |
184 | SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */ | |
185 | SCRUB_NONE, /* No scrubber */ | |
186 | SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */ | |
187 | SCRUB_SW_SRC, /* Software scrub only errors */ | |
188 | SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */ | |
189 | SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */ | |
190 | SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */ | |
191 | SCRUB_HW_SRC, /* Hardware scrub only errors */ | |
192 | SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */ | |
193 | SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */ | |
194 | }; | |
195 | ||
196 | #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG) | |
522a94bd DT |
197 | #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC) |
198 | #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC) | |
7c9281d7 DT |
199 | #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE) |
200 | #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG) | |
522a94bd DT |
201 | #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC) |
202 | #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC) | |
7c9281d7 DT |
203 | #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE) |
204 | ||
205 | /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */ | |
206 | ||
91b99041 DJ |
207 | /* EDAC internal operation states */ |
208 | #define OP_ALLOC 0x100 | |
209 | #define OP_RUNNING_POLL 0x201 | |
210 | #define OP_RUNNING_INTERRUPT 0x202 | |
211 | #define OP_RUNNING_POLL_INTR 0x203 | |
212 | #define OP_OFFLINE 0x300 | |
213 | ||
e27e3dac DT |
214 | extern char * edac_align_ptr(void *ptr, unsigned size); |
215 | ||
7c9281d7 DT |
216 | /* |
217 | * There are several things to be aware of that aren't at all obvious: | |
218 | * | |
219 | * | |
220 | * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc.. | |
221 | * | |
222 | * These are some of the many terms that are thrown about that don't always | |
223 | * mean what people think they mean (Inconceivable!). In the interest of | |
224 | * creating a common ground for discussion, terms and their definitions | |
225 | * will be established. | |
226 | * | |
227 | * Memory devices: The individual chip on a memory stick. These devices | |
228 | * commonly output 4 and 8 bits each. Grouping several | |
229 | * of these in parallel provides 64 bits which is common | |
230 | * for a memory stick. | |
231 | * | |
232 | * Memory Stick: A printed circuit board that agregates multiple | |
233 | * memory devices in parallel. This is the atomic | |
234 | * memory component that is purchaseable by Joe consumer | |
235 | * and loaded into a memory socket. | |
236 | * | |
237 | * Socket: A physical connector on the motherboard that accepts | |
238 | * a single memory stick. | |
239 | * | |
240 | * Channel: Set of memory devices on a memory stick that must be | |
241 | * grouped in parallel with one or more additional | |
242 | * channels from other memory sticks. This parallel | |
243 | * grouping of the output from multiple channels are | |
244 | * necessary for the smallest granularity of memory access. | |
245 | * Some memory controllers are capable of single channel - | |
246 | * which means that memory sticks can be loaded | |
247 | * individually. Other memory controllers are only | |
248 | * capable of dual channel - which means that memory | |
249 | * sticks must be loaded as pairs (see "socket set"). | |
250 | * | |
251 | * Chip-select row: All of the memory devices that are selected together. | |
252 | * for a single, minimum grain of memory access. | |
253 | * This selects all of the parallel memory devices across | |
254 | * all of the parallel channels. Common chip-select rows | |
255 | * for single channel are 64 bits, for dual channel 128 | |
256 | * bits. | |
257 | * | |
258 | * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory. | |
259 | * Motherboards commonly drive two chip-select pins to | |
260 | * a memory stick. A single-ranked stick, will occupy | |
261 | * only one of those rows. The other will be unused. | |
262 | * | |
263 | * Double-Ranked stick: A double-ranked stick has two chip-select rows which | |
264 | * access different sets of memory devices. The two | |
265 | * rows cannot be accessed concurrently. | |
266 | * | |
267 | * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick. | |
268 | * A double-sided stick has two chip-select rows which | |
269 | * access different sets of memory devices. The two | |
270 | * rows cannot be accessed concurrently. "Double-sided" | |
271 | * is irrespective of the memory devices being mounted | |
272 | * on both sides of the memory stick. | |
273 | * | |
274 | * Socket set: All of the memory sticks that are required for for | |
275 | * a single memory access or all of the memory sticks | |
276 | * spanned by a chip-select row. A single socket set | |
277 | * has two chip-select rows and if double-sided sticks | |
278 | * are used these will occupy those chip-select rows. | |
279 | * | |
280 | * Bank: This term is avoided because it is unclear when | |
281 | * needing to distinguish between chip-select rows and | |
282 | * socket sets. | |
283 | * | |
284 | * Controller pages: | |
285 | * | |
286 | * Physical pages: | |
287 | * | |
288 | * Virtual pages: | |
289 | * | |
290 | * | |
291 | * STRUCTURE ORGANIZATION AND CHOICES | |
292 | * | |
293 | * | |
294 | * | |
295 | * PS - I enjoyed writing all that about as much as you enjoyed reading it. | |
296 | */ | |
297 | ||
298 | struct channel_info { | |
299 | int chan_idx; /* channel index */ | |
300 | u32 ce_count; /* Correctable Errors for this CHANNEL */ | |
301 | char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */ | |
302 | struct csrow_info *csrow; /* the parent */ | |
303 | }; | |
304 | ||
305 | struct csrow_info { | |
306 | unsigned long first_page; /* first page number in dimm */ | |
307 | unsigned long last_page; /* last page number in dimm */ | |
308 | unsigned long page_mask; /* used for interleaving - | |
309 | * 0UL for non intlv | |
310 | */ | |
311 | u32 nr_pages; /* number of pages in csrow */ | |
312 | u32 grain; /* granularity of reported error in bytes */ | |
313 | int csrow_idx; /* the chip-select row */ | |
314 | enum dev_type dtype; /* memory device type */ | |
315 | u32 ue_count; /* Uncorrectable Errors for this csrow */ | |
316 | u32 ce_count; /* Correctable Errors for this csrow */ | |
317 | enum mem_type mtype; /* memory csrow type */ | |
318 | enum edac_type edac_mode; /* EDAC mode for this csrow */ | |
319 | struct mem_ctl_info *mci; /* the parent */ | |
320 | ||
321 | struct kobject kobj; /* sysfs kobject for this csrow */ | |
322 | struct completion kobj_complete; | |
323 | ||
324 | /* FIXME the number of CHANNELs might need to become dynamic */ | |
325 | u32 nr_channels; | |
326 | struct channel_info *channels; | |
327 | }; | |
328 | ||
329 | struct mem_ctl_info { | |
330 | struct list_head link; /* for global list of mem_ctl_info structs */ | |
331 | unsigned long mtype_cap; /* memory types supported by mc */ | |
332 | unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */ | |
333 | unsigned long edac_cap; /* configuration capabilities - this is | |
334 | * closely related to edac_ctl_cap. The | |
335 | * difference is that the controller may be | |
336 | * capable of s4ecd4ed which would be listed | |
337 | * in edac_ctl_cap, but if channels aren't | |
338 | * capable of s4ecd4ed then the edac_cap would | |
339 | * not have that capability. | |
340 | */ | |
341 | unsigned long scrub_cap; /* chipset scrub capabilities */ | |
342 | enum scrub_type scrub_mode; /* current scrub mode */ | |
343 | ||
344 | /* Translates sdram memory scrub rate given in bytes/sec to the | |
345 | internal representation and configures whatever else needs | |
346 | to be configured. | |
347 | */ | |
348 | int (*set_sdram_scrub_rate) (struct mem_ctl_info *mci, u32 *bw); | |
349 | ||
350 | /* Get the current sdram memory scrub rate from the internal | |
351 | representation and converts it to the closest matching | |
352 | bandwith in bytes/sec. | |
353 | */ | |
354 | int (*get_sdram_scrub_rate) (struct mem_ctl_info *mci, u32 *bw); | |
355 | ||
356 | /* pointer to edac checking routine */ | |
357 | void (*edac_check) (struct mem_ctl_info * mci); | |
358 | ||
359 | /* | |
360 | * Remaps memory pages: controller pages to physical pages. | |
361 | * For most MC's, this will be NULL. | |
362 | */ | |
363 | /* FIXME - why not send the phys page to begin with? */ | |
364 | unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci, | |
365 | unsigned long page); | |
366 | int mc_idx; | |
367 | int nr_csrows; | |
368 | struct csrow_info *csrows; | |
369 | /* | |
370 | * FIXME - what about controllers on other busses? - IDs must be | |
371 | * unique. dev pointer should be sufficiently unique, but | |
372 | * BUS:SLOT.FUNC numbers may not be unique. | |
373 | */ | |
374 | struct device *dev; | |
375 | const char *mod_name; | |
376 | const char *mod_ver; | |
377 | const char *ctl_name; | |
c4192705 | 378 | const char *dev_name; |
7c9281d7 DT |
379 | char proc_name[MC_PROC_NAME_MAX_LEN + 1]; |
380 | void *pvt_info; | |
381 | u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */ | |
382 | u32 ce_noinfo_count; /* Correctable Errors w/o info */ | |
383 | u32 ue_count; /* Total Uncorrectable Errors for this MC */ | |
384 | u32 ce_count; /* Total Correctable Errors for this MC */ | |
385 | unsigned long start_time; /* mci load start time (in jiffies) */ | |
386 | ||
387 | /* this stuff is for safe removal of mc devices from global list while | |
388 | * NMI handlers may be traversing list | |
389 | */ | |
390 | struct rcu_head rcu; | |
391 | struct completion complete; | |
392 | ||
393 | /* edac sysfs device control */ | |
394 | struct kobject edac_mci_kobj; | |
395 | struct completion kobj_complete; | |
81d87cb1 DJ |
396 | |
397 | /* work struct for this MC */ | |
398 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) | |
399 | struct delayed_work work; | |
400 | #else | |
401 | struct work_struct work; | |
402 | #endif | |
403 | /* the internal state of this controller instance */ | |
404 | int op_state; | |
7c9281d7 DT |
405 | }; |
406 | ||
e27e3dac DT |
407 | /* |
408 | * The following are the structures to provide for a generice | |
409 | * or abstract 'edac_device'. This set of structures and the | |
410 | * code that implements the APIs for the same, provide for | |
411 | * registering EDAC type devices which are NOT standard memory. | |
412 | * | |
413 | * CPU caches (L1 and L2) | |
414 | * DMA engines | |
415 | * Core CPU swithces | |
416 | * Fabric switch units | |
417 | * PCIe interface controllers | |
418 | * other EDAC/ECC type devices that can be monitored for | |
419 | * errors, etc. | |
420 | * | |
421 | * It allows for a 2 level set of hiearchry. For example: | |
422 | * | |
423 | * cache could be composed of L1, L2 and L3 levels of cache. | |
424 | * Each CPU core would have its own L1 cache, while sharing | |
425 | * L2 and maybe L3 caches. | |
426 | * | |
427 | * View them arranged, via the sysfs presentation: | |
428 | * /sys/devices/system/edac/.. | |
429 | * | |
430 | * mc/ <existing memory device directory> | |
431 | * cpu/cpu0/.. <L1 and L2 block directory> | |
432 | * /L1-cache/ce_count | |
433 | * /ue_count | |
434 | * /L2-cache/ce_count | |
435 | * /ue_count | |
436 | * cpu/cpu1/.. <L1 and L2 block directory> | |
437 | * /L1-cache/ce_count | |
438 | * /ue_count | |
439 | * /L2-cache/ce_count | |
440 | * /ue_count | |
441 | * ... | |
442 | * | |
443 | * the L1 and L2 directories would be "edac_device_block's" | |
444 | */ | |
445 | ||
446 | struct edac_device_counter { | |
447 | u32 ue_count; | |
448 | u32 ce_count; | |
449 | }; | |
450 | ||
451 | #define INC_COUNTER(cnt) (cnt++) | |
452 | ||
453 | /* | |
454 | * An array of these is passed to the alloc() function | |
455 | * to specify attributes of the edac_block | |
456 | */ | |
457 | struct edac_attrib_spec { | |
458 | char name[EDAC_DEVICE_NAME_LEN + 1]; | |
459 | ||
460 | int type; | |
461 | #define EDAC_ATTR_INT 0x01 | |
462 | #define EDAC_ATTR_CHAR 0x02 | |
463 | }; | |
464 | ||
465 | ||
466 | /* Attribute control structure | |
467 | * In this structure is a pointer to the driver's edac_attrib_spec | |
468 | * The life of this pointer is inclusive in the life of the driver's | |
469 | * life cycle. | |
470 | */ | |
471 | struct edac_attrib { | |
472 | struct edac_device_block *block; /* Up Pointer */ | |
473 | ||
474 | struct edac_attrib_spec *spec; /* ptr to module spec entry */ | |
475 | ||
476 | union { /* actual value */ | |
477 | int edac_attrib_int_value; | |
478 | char edac_attrib_char_value[EDAC_ATTRIB_VALUE_LEN + 1]; | |
479 | } edac_attrib_value; | |
480 | }; | |
481 | ||
482 | /* device block control structure */ | |
483 | struct edac_device_block { | |
484 | struct edac_device_instance *instance; /* Up Pointer */ | |
485 | char name[EDAC_DEVICE_NAME_LEN + 1]; | |
486 | ||
487 | struct edac_device_counter counters; /* basic UE and CE counters */ | |
488 | ||
489 | int nr_attribs; /* how many attributes */ | |
490 | struct edac_attrib *attribs; /* this block's attributes */ | |
491 | ||
492 | /* edac sysfs device control */ | |
493 | struct kobject kobj; | |
494 | struct completion kobj_complete; | |
495 | }; | |
496 | ||
497 | /* device instance control structure */ | |
498 | struct edac_device_instance { | |
499 | struct edac_device_ctl_info *ctl; /* Up pointer */ | |
500 | char name[EDAC_DEVICE_NAME_LEN + 4]; | |
501 | ||
502 | struct edac_device_counter counters; /* instance counters */ | |
503 | ||
504 | u32 nr_blocks; /* how many blocks */ | |
505 | struct edac_device_block *blocks; /* block array */ | |
506 | ||
507 | /* edac sysfs device control */ | |
508 | struct kobject kobj; | |
509 | struct completion kobj_complete; | |
510 | }; | |
511 | ||
512 | ||
513 | /* | |
514 | * Abstract edac_device control info structure | |
515 | * | |
516 | */ | |
517 | struct edac_device_ctl_info { | |
518 | /* for global list of edac_device_ctl_info structs */ | |
519 | struct list_head link; | |
520 | ||
521 | int dev_idx; | |
522 | ||
523 | /* Per instance controls for this edac_device */ | |
524 | int log_ue; /* boolean for logging UEs */ | |
525 | int log_ce; /* boolean for logging CEs */ | |
526 | int panic_on_ue; /* boolean for panic'ing on an UE */ | |
527 | unsigned poll_msec; /* number of milliseconds to poll interval */ | |
528 | unsigned long delay; /* number of jiffies for poll_msec */ | |
529 | ||
530 | struct sysdev_class *edac_class; /* pointer to class */ | |
531 | ||
532 | /* the internal state of this controller instance */ | |
533 | int op_state; | |
e27e3dac DT |
534 | /* work struct for this instance */ |
535 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) | |
536 | struct delayed_work work; | |
537 | #else | |
538 | struct work_struct work; | |
539 | #endif | |
540 | ||
541 | /* pointer to edac polling checking routine: | |
542 | * If NOT NULL: points to polling check routine | |
543 | * If NULL: Then assumes INTERRUPT operation, where | |
544 | * MC driver will receive events | |
545 | */ | |
546 | void (*edac_check) (struct edac_device_ctl_info * edac_dev); | |
547 | ||
548 | struct device *dev; /* pointer to device structure */ | |
549 | ||
550 | const char *mod_name; /* module name */ | |
551 | const char *ctl_name; /* edac controller name */ | |
c4192705 | 552 | const char *dev_name; /* pci/platform/etc... name */ |
e27e3dac DT |
553 | |
554 | void *pvt_info; /* pointer to 'private driver' info */ | |
555 | ||
556 | unsigned long start_time;/* edac_device load start time (jiffies)*/ | |
557 | ||
558 | /* these are for safe removal of mc devices from global list while | |
559 | * NMI handlers may be traversing list | |
560 | */ | |
561 | struct rcu_head rcu; | |
562 | struct completion complete; | |
563 | ||
564 | /* sysfs top name under 'edac' directory | |
565 | * and instance name: | |
566 | * cpu/cpu0/... | |
567 | * cpu/cpu1/... | |
568 | * cpu/cpu2/... | |
569 | * ... | |
570 | */ | |
571 | char name[EDAC_DEVICE_NAME_LEN + 1]; | |
572 | ||
573 | /* Number of instances supported on this control structure | |
574 | * and the array of those instances | |
575 | */ | |
576 | u32 nr_instances; | |
577 | struct edac_device_instance *instances; | |
578 | ||
579 | /* Event counters for the this whole EDAC Device */ | |
580 | struct edac_device_counter counters; | |
581 | ||
582 | /* edac sysfs device control for the 'name' | |
583 | * device this structure controls | |
584 | */ | |
585 | struct kobject kobj; | |
586 | struct completion kobj_complete; | |
587 | }; | |
588 | ||
589 | /* To get from the instance's wq to the beginning of the ctl structure */ | |
81d87cb1 DJ |
590 | #define to_edac_mem_ctl_work(w) \ |
591 | container_of(w, struct mem_ctl_info, work) | |
592 | ||
e27e3dac DT |
593 | #define to_edac_device_ctl_work(w) \ |
594 | container_of(w,struct edac_device_ctl_info,work) | |
595 | ||
596 | /* Function to calc the number of delay jiffies from poll_msec */ | |
597 | static inline void edac_device_calc_delay( | |
598 | struct edac_device_ctl_info *edac_dev) | |
599 | { | |
600 | /* convert from msec to jiffies */ | |
601 | edac_dev->delay = edac_dev->poll_msec * HZ / 1000; | |
602 | } | |
603 | ||
81d87cb1 DJ |
604 | #define edac_calc_delay(dev) dev->delay = dev->poll_msec * HZ / 1000; |
605 | ||
e27e3dac DT |
606 | /* |
607 | * The alloc() and free() functions for the 'edac_device' control info | |
608 | * structure. A MC driver will allocate one of these for each edac_device | |
609 | * it is going to control/register with the EDAC CORE. | |
610 | */ | |
611 | extern struct edac_device_ctl_info *edac_device_alloc_ctl_info( | |
612 | unsigned sizeof_private, | |
613 | char *edac_device_name, | |
614 | unsigned nr_instances, | |
615 | char *edac_block_name, | |
616 | unsigned nr_blocks, | |
617 | unsigned offset_value, | |
618 | struct edac_attrib_spec *attrib_spec, | |
619 | unsigned nr_attribs | |
620 | ); | |
621 | ||
622 | /* The offset value can be: | |
623 | * -1 indicating no offset value | |
624 | * 0 for zero-based block numbers | |
625 | * 1 for 1-based block number | |
626 | * other for other-based block number | |
627 | */ | |
628 | #define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1) | |
629 | ||
630 | extern void edac_device_free_ctl_info( struct edac_device_ctl_info *ctl_info); | |
631 | ||
7c9281d7 DT |
632 | #ifdef CONFIG_PCI |
633 | ||
91b99041 DJ |
634 | struct edac_pci_counter { |
635 | atomic_t pe_count; | |
636 | atomic_t npe_count; | |
637 | }; | |
638 | ||
639 | /* | |
640 | * Abstract edac_pci control info structure | |
641 | * | |
642 | */ | |
643 | struct edac_pci_ctl_info { | |
644 | /* for global list of edac_pci_ctl_info structs */ | |
645 | struct list_head link; | |
646 | ||
647 | int pci_idx; | |
648 | ||
91b99041 DJ |
649 | struct sysdev_class *edac_class; /* pointer to class */ |
650 | ||
651 | /* the internal state of this controller instance */ | |
652 | int op_state; | |
653 | /* work struct for this instance */ | |
654 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) | |
655 | struct delayed_work work; | |
656 | #else | |
657 | struct work_struct work; | |
658 | #endif | |
659 | ||
660 | /* pointer to edac polling checking routine: | |
661 | * If NOT NULL: points to polling check routine | |
662 | * If NULL: Then assumes INTERRUPT operation, where | |
663 | * MC driver will receive events | |
664 | */ | |
665 | void (*edac_check) (struct edac_pci_ctl_info * edac_dev); | |
666 | ||
667 | struct device *dev; /* pointer to device structure */ | |
668 | ||
669 | const char *mod_name; /* module name */ | |
670 | const char *ctl_name; /* edac controller name */ | |
671 | const char *dev_name; /* pci/platform/etc... name */ | |
672 | ||
673 | void *pvt_info; /* pointer to 'private driver' info */ | |
674 | ||
675 | unsigned long start_time;/* edac_pci load start time (jiffies)*/ | |
676 | ||
677 | /* these are for safe removal of devices from global list while | |
678 | * NMI handlers may be traversing list | |
679 | */ | |
680 | struct rcu_head rcu; | |
681 | struct completion complete; | |
682 | ||
683 | /* sysfs top name under 'edac' directory | |
684 | * and instance name: | |
685 | * cpu/cpu0/... | |
686 | * cpu/cpu1/... | |
687 | * cpu/cpu2/... | |
688 | * ... | |
689 | */ | |
690 | char name[EDAC_DEVICE_NAME_LEN + 1]; | |
691 | ||
692 | /* Event counters for the this whole EDAC Device */ | |
693 | struct edac_pci_counter counters; | |
694 | ||
695 | /* edac sysfs device control for the 'name' | |
696 | * device this structure controls | |
697 | */ | |
698 | struct kobject kobj; | |
699 | struct completion kobj_complete; | |
700 | }; | |
701 | ||
702 | #define to_edac_pci_ctl_work(w) \ | |
703 | container_of(w, struct edac_pci_ctl_info,work) | |
704 | ||
7c9281d7 DT |
705 | /* write all or some bits in a byte-register*/ |
706 | static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value, | |
707 | u8 mask) | |
708 | { | |
709 | if (mask != 0xff) { | |
710 | u8 buf; | |
711 | ||
712 | pci_read_config_byte(pdev, offset, &buf); | |
713 | value &= mask; | |
714 | buf &= ~mask; | |
715 | value |= buf; | |
716 | } | |
717 | ||
718 | pci_write_config_byte(pdev, offset, value); | |
719 | } | |
720 | ||
721 | /* write all or some bits in a word-register*/ | |
722 | static inline void pci_write_bits16(struct pci_dev *pdev, int offset, | |
723 | u16 value, u16 mask) | |
724 | { | |
725 | if (mask != 0xffff) { | |
726 | u16 buf; | |
727 | ||
728 | pci_read_config_word(pdev, offset, &buf); | |
729 | value &= mask; | |
730 | buf &= ~mask; | |
731 | value |= buf; | |
732 | } | |
733 | ||
734 | pci_write_config_word(pdev, offset, value); | |
735 | } | |
736 | ||
737 | /* write all or some bits in a dword-register*/ | |
738 | static inline void pci_write_bits32(struct pci_dev *pdev, int offset, | |
739 | u32 value, u32 mask) | |
740 | { | |
741 | if (mask != 0xffff) { | |
742 | u32 buf; | |
743 | ||
744 | pci_read_config_dword(pdev, offset, &buf); | |
745 | value &= mask; | |
746 | buf &= ~mask; | |
747 | value |= buf; | |
748 | } | |
749 | ||
750 | pci_write_config_dword(pdev, offset, value); | |
751 | } | |
752 | ||
753 | #endif /* CONFIG_PCI */ | |
754 | ||
755 | extern struct mem_ctl_info * edac_mc_find(int idx); | |
756 | extern int edac_mc_add_mc(struct mem_ctl_info *mci,int mc_idx); | |
757 | extern struct mem_ctl_info * edac_mc_del_mc(struct device *dev); | |
758 | extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, | |
759 | unsigned long page); | |
760 | ||
761 | /* | |
762 | * The no info errors are used when error overflows are reported. | |
763 | * There are a limited number of error logging registers that can | |
764 | * be exausted. When all registers are exhausted and an additional | |
765 | * error occurs then an error overflow register records that an | |
766 | * error occured and the type of error, but doesn't have any | |
767 | * further information. The ce/ue versions make for cleaner | |
768 | * reporting logic and function interface - reduces conditional | |
769 | * statement clutter and extra function arguments. | |
770 | */ | |
771 | extern void edac_mc_handle_ce(struct mem_ctl_info *mci, | |
772 | unsigned long page_frame_number, unsigned long offset_in_page, | |
773 | unsigned long syndrome, int row, int channel, | |
774 | const char *msg); | |
775 | extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci, | |
776 | const char *msg); | |
777 | extern void edac_mc_handle_ue(struct mem_ctl_info *mci, | |
778 | unsigned long page_frame_number, unsigned long offset_in_page, | |
779 | int row, const char *msg); | |
780 | extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci, | |
781 | const char *msg); | |
782 | extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, | |
783 | unsigned int csrow, | |
784 | unsigned int channel0, | |
785 | unsigned int channel1, | |
786 | char *msg); | |
787 | extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, | |
788 | unsigned int csrow, | |
789 | unsigned int channel, | |
790 | char *msg); | |
791 | ||
792 | /* | |
e27e3dac | 793 | * edac_device APIs |
7c9281d7 DT |
794 | */ |
795 | extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows, | |
796 | unsigned nr_chans); | |
7c9281d7 | 797 | extern void edac_mc_free(struct mem_ctl_info *mci); |
e27e3dac DT |
798 | extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev, int edac_idx); |
799 | extern struct edac_device_ctl_info * edac_device_del_device(struct device *dev); | |
800 | extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev, | |
801 | int inst_nr, int block_nr, const char *msg); | |
802 | extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev, | |
803 | int inst_nr, int block_nr, const char *msg); | |
804 | ||
91b99041 DJ |
805 | /* |
806 | * edac_pci APIs | |
807 | */ | |
808 | extern struct edac_pci_ctl_info * | |
809 | edac_pci_alloc_ctl_info(unsigned int sz_pvt, const char *edac_pci_name); | |
810 | ||
811 | extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci); | |
812 | ||
813 | extern void | |
814 | edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci, unsigned long value); | |
815 | ||
816 | extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx); | |
817 | extern struct edac_pci_ctl_info * edac_pci_del_device(struct device *dev); | |
818 | ||
819 | extern struct edac_pci_ctl_info * | |
820 | edac_pci_create_generic_ctl(struct device *dev, const char *mod_name); | |
821 | ||
822 | extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci); | |
823 | extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci); | |
824 | extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci); | |
825 | ||
826 | /* | |
827 | * edac misc APIs | |
828 | */ | |
829 | extern char * edac_op_state_toString(int op_state); | |
7c9281d7 DT |
830 | |
831 | #endif /* _EDAC_CORE_H_ */ |