[deliverable/linux.git] / drivers / edac / edac_mc.h

/*
 * MC kernel module
 * (C) 2003 Linux Networx (http://lnxi.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Thayne Harbaugh
 * Based on work by Dan Hollis <goemon at anime dot net> and others.
 *	http://www.anime.net/~goemon/linux-ecc/
 *
 * NMI handling support added by
 *     Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
 *
 * $Id: edac_mc.h,v 1.4.2.10 2005/10/05 00:43:44 dsp_llnl Exp $
 *
 */

#ifndef _EDAC_MC_H_
#define _EDAC_MC_H_

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/smp.h>
#include <linux/pci.h>
#include <linux/time.h>
#include <linux/nmi.h>
#include <linux/rcupdate.h>
#include <linux/completion.h>
#include <linux/kobject.h>

#define EDAC_MC_LABEL_LEN	31
#define MC_PROC_NAME_MAX_LEN 7

#if PAGE_SHIFT < 20
#define PAGES_TO_MiB( pages )	( ( pages ) >> ( 20 - PAGE_SHIFT ) )
#else				/* PAGE_SHIFT > 20 */
#define PAGES_TO_MiB( pages )	( ( pages ) << ( PAGE_SHIFT - 20 ) )
#endif

#define edac_printk(level, prefix, fmt, arg...) \
	printk(level "EDAC " prefix ": " fmt, ##arg)

#define edac_mc_printk(mci, level, fmt, arg...) \
	printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)

#define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
	printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)

/* prefixes for edac_printk() and edac_mc_printk() */
#define EDAC_MC "MC"
#define EDAC_PCI "PCI"
#define EDAC_DEBUG "DEBUG"

#ifdef CONFIG_EDAC_DEBUG
extern int edac_debug_level;

#define edac_debug_printk(level, fmt, arg...)                            \
	do {                                                             \
		if (level <= edac_debug_level)                           \
			edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \
	} while(0)

#define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
#define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
#define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
#define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
#define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )

#else  /* !CONFIG_EDAC_DEBUG */

#define debugf0( ... )
#define debugf1( ... )
#define debugf2( ... )
#define debugf3( ... )
#define debugf4( ... )

#endif  /* !CONFIG_EDAC_DEBUG */

#define BIT(x) (1 << (x))

#define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
	PCI_DEVICE_ID_ ## vend ## _ ## dev

#if defined(CONFIG_X86) && defined(CONFIG_PCI)
#define dev_name(dev) pci_name(to_pci_dev(dev))
#else
#define dev_name(dev) to_platform_device(dev)->name
#endif

/* memory devices */
enum dev_type {
	DEV_UNKNOWN = 0,
	DEV_X1,
	DEV_X2,
	DEV_X4,
	DEV_X8,
	DEV_X16,
	DEV_X32,		/* Do these parts exist? */
	DEV_X64			/* Do these parts exist? */
};

#define DEV_FLAG_UNKNOWN	BIT(DEV_UNKNOWN)
#define DEV_FLAG_X1		BIT(DEV_X1)
#define DEV_FLAG_X2		BIT(DEV_X2)
#define DEV_FLAG_X4		BIT(DEV_X4)
#define DEV_FLAG_X8		BIT(DEV_X8)
#define DEV_FLAG_X16		BIT(DEV_X16)
#define DEV_FLAG_X32		BIT(DEV_X32)
#define DEV_FLAG_X64		BIT(DEV_X64)

/* memory types */
enum mem_type {
	MEM_EMPTY = 0,		/* Empty csrow */
	MEM_RESERVED,		/* Reserved csrow type */
	MEM_UNKNOWN,		/* Unknown csrow type */
	MEM_FPM,		/* Fast page mode */
	MEM_EDO,		/* Extended data out */
	MEM_BEDO,		/* Burst Extended data out */
	MEM_SDR,		/* Single data rate SDRAM */
	MEM_RDR,		/* Registered single data rate SDRAM */
	MEM_DDR,		/* Double data rate SDRAM */
	MEM_RDDR,		/* Registered Double data rate SDRAM */
	MEM_RMBS		/* Rambus DRAM */
};

#define MEM_FLAG_EMPTY		BIT(MEM_EMPTY)
#define MEM_FLAG_RESERVED	BIT(MEM_RESERVED)
#define MEM_FLAG_UNKNOWN	BIT(MEM_UNKNOWN)
#define MEM_FLAG_FPM		BIT(MEM_FPM)
#define MEM_FLAG_EDO		BIT(MEM_EDO)
#define MEM_FLAG_BEDO		BIT(MEM_BEDO)
#define MEM_FLAG_SDR		BIT(MEM_SDR)
#define MEM_FLAG_RDR		BIT(MEM_RDR)
#define MEM_FLAG_DDR		BIT(MEM_DDR)
#define MEM_FLAG_RDDR		BIT(MEM_RDDR)
#define MEM_FLAG_RMBS		BIT(MEM_RMBS)

/* chipset Error Detection and Correction capabilities and mode */
enum edac_type {
	EDAC_UNKNOWN = 0,	/* Unknown if ECC is available */
	EDAC_NONE,		/* Doesnt support ECC */
	EDAC_RESERVED,		/* Reserved ECC type */
	EDAC_PARITY,		/* Detects parity errors */
	EDAC_EC,		/* Error Checking - no correction */
	EDAC_SECDED,		/* Single bit error correction, Double detection */
	EDAC_S2ECD2ED,		/* Chipkill x2 devices - do these exist? */
	EDAC_S4ECD4ED,		/* Chipkill x4 devices */
	EDAC_S8ECD8ED,		/* Chipkill x8 devices */
	EDAC_S16ECD16ED,	/* Chipkill x16 devices */
};

#define EDAC_FLAG_UNKNOWN	BIT(EDAC_UNKNOWN)
#define EDAC_FLAG_NONE		BIT(EDAC_NONE)
#define EDAC_FLAG_PARITY	BIT(EDAC_PARITY)
#define EDAC_FLAG_EC		BIT(EDAC_EC)
#define EDAC_FLAG_SECDED	BIT(EDAC_SECDED)
#define EDAC_FLAG_S2ECD2ED	BIT(EDAC_S2ECD2ED)
#define EDAC_FLAG_S4ECD4ED	BIT(EDAC_S4ECD4ED)
#define EDAC_FLAG_S8ECD8ED	BIT(EDAC_S8ECD8ED)
#define EDAC_FLAG_S16ECD16ED	BIT(EDAC_S16ECD16ED)

/* scrubbing capabilities */
enum scrub_type {
	SCRUB_UNKNOWN = 0,	/* Unknown if scrubber is available */
	SCRUB_NONE,		/* No scrubber */
	SCRUB_SW_PROG,		/* SW progressive (sequential) scrubbing */
	SCRUB_SW_SRC,		/* Software scrub only errors */
	SCRUB_SW_PROG_SRC,	/* Progressive software scrub from an error */
	SCRUB_SW_TUNABLE,	/* Software scrub frequency is tunable */
	SCRUB_HW_PROG,		/* HW progressive (sequential) scrubbing */
	SCRUB_HW_SRC,		/* Hardware scrub only errors */
	SCRUB_HW_PROG_SRC,	/* Progressive hardware scrub from an error */
	SCRUB_HW_TUNABLE	/* Hardware scrub frequency is tunable */
};

#define SCRUB_FLAG_SW_PROG	BIT(SCRUB_SW_PROG)
#define SCRUB_FLAG_SW_SRC	BIT(SCRUB_SW_SRC_CORR)
#define SCRUB_FLAG_SW_PROG_SRC	BIT(SCRUB_SW_PROG_SRC_CORR)
#define SCRUB_FLAG_SW_TUN	BIT(SCRUB_SW_SCRUB_TUNABLE)
#define SCRUB_FLAG_HW_PROG	BIT(SCRUB_HW_PROG)
#define SCRUB_FLAG_HW_SRC	BIT(SCRUB_HW_SRC_CORR)
#define SCRUB_FLAG_HW_PROG_SRC	BIT(SCRUB_HW_PROG_SRC_CORR)
#define SCRUB_FLAG_HW_TUN	BIT(SCRUB_HW_TUNABLE)

/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */

/*
 * There are several things to be aware of that aren't at all obvious:
 *
 *
 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
 *
 * These are some of the many terms that are thrown about that don't always
 * mean what people think they mean (Inconceivable!).  In the interest of
 * creating a common ground for discussion, terms and their definitions
 * will be established.
 *
 * Memory devices:	The individual chip on a memory stick.  These devices
 *			commonly output 4 and 8 bits each.  Grouping several
 *			of these in parallel provides 64 bits which is common
 *			for a memory stick.
 *
 * Memory Stick:	A printed circuit board that agregates multiple
 *			memory devices in parallel.  This is the atomic
 *			memory component that is purchaseable by Joe consumer
 *			and loaded into a memory socket.
 *
 * Socket:		A physical connector on the motherboard that accepts
 *			a single memory stick.
 *
 * Channel:		Set of memory devices on a memory stick that must be
 *			grouped in parallel with one or more additional
 *			channels from other memory sticks.  This parallel
 *			grouping of the output from multiple channels are
 *			necessary for the smallest granularity of memory access.
 *			Some memory controllers are capable of single channel -
 *			which means that memory sticks can be loaded
 *			individually.  Other memory controllers are only
 *			capable of dual channel - which means that memory
 *			sticks must be loaded as pairs (see "socket set").
 *
 * Chip-select row:	All of the memory devices that are selected together.
 *			for a single, minimum grain of memory access.
 *			This selects all of the parallel memory devices across
 *			all of the parallel channels.  Common chip-select rows
 *			for single channel are 64 bits, for dual channel 128
 *			bits.
 *
 * Single-Ranked stick:	A Single-ranked stick has 1 chip-select row of memmory.
 *			Motherboards commonly drive two chip-select pins to
 *			a memory stick. A single-ranked stick, will occupy
 *			only one of those rows. The other will be unused.
 *
 * Double-Ranked stick:	A double-ranked stick has two chip-select rows which
 *			access different sets of memory devices.  The two
 *			rows cannot be accessed concurrently.
 *
 * Double-sided stick:	DEPRECATED TERM, see Double-Ranked stick.
 *			A double-sided stick has two chip-select rows which
 *			access different sets of memory devices.  The two
 *			rows cannot be accessed concurrently.  "Double-sided"
 *			is irrespective of the memory devices being mounted
 *			on both sides of the memory stick.
 *
 * Socket set:		All of the memory sticks that are required for for
 *			a single memory access or all of the memory sticks
 *			spanned by a chip-select row.  A single socket set
 *			has two chip-select rows and if double-sided sticks
 *			are used these will occupy those chip-select rows.
 *
 * Bank:		This term is avoided because it is unclear when
 *			needing to distinguish between chip-select rows and
 *			socket sets.
 *
 * Controller pages:
 *
 * Physical pages:
 *
 * Virtual pages:
 *
 *
 * STRUCTURE ORGANIZATION AND CHOICES
 *
 *
 *
 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
 */

struct channel_info {
	int chan_idx;		/* channel index */
	u32 ce_count;		/* Correctable Errors for this CHANNEL */
	char label[EDAC_MC_LABEL_LEN + 1];  /* DIMM label on motherboard */
	struct csrow_info *csrow;	/* the parent */
};

struct csrow_info {
	unsigned long first_page;	/* first page number in dimm */
	unsigned long last_page;	/* last page number in dimm */
	unsigned long page_mask;	/* used for interleaving -
					 * 0UL for non intlv
					 */
	u32 nr_pages;		/* number of pages in csrow */
	u32 grain;		/* granularity of reported error in bytes */
	int csrow_idx;		/* the chip-select row */
	enum dev_type dtype;	/* memory device type */
	u32 ue_count;		/* Uncorrectable Errors for this csrow */
	u32 ce_count;		/* Correctable Errors for this csrow */
	enum mem_type mtype;	/* memory csrow type */
	enum edac_type edac_mode;	/* EDAC mode for this csrow */
	struct mem_ctl_info *mci;	/* the parent */

	struct kobject kobj;	/* sysfs kobject for this csrow */
	struct completion kobj_complete;

	/* FIXME the number of CHANNELs might need to become dynamic */
	u32 nr_channels;
	struct channel_info *channels;
};

struct mem_ctl_info {
	struct list_head link;  /* for global list of mem_ctl_info structs */
	unsigned long mtype_cap;	/* memory types supported by mc */
	unsigned long edac_ctl_cap;	/* Mem controller EDAC capabilities */
	unsigned long edac_cap;	/* configuration capabilities - this is
				 * closely related to edac_ctl_cap.  The
				 * difference is that the controller may be
				 * capable of s4ecd4ed which would be listed
				 * in edac_ctl_cap, but if channels aren't
				 * capable of s4ecd4ed then the edac_cap would
				 * not have that capability.
				 */
	unsigned long scrub_cap;	/* chipset scrub capabilities */
	enum scrub_type scrub_mode;	/* current scrub mode */

	/* pointer to edac checking routine */
	void (*edac_check) (struct mem_ctl_info * mci);
	/*
	 * Remaps memory pages: controller pages to physical pages.
	 * For most MC's, this will be NULL.
	 */
	/* FIXME - why not send the phys page to begin with? */
	unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
					unsigned long page);
	int mc_idx;
	int nr_csrows;
	struct csrow_info *csrows;
	/*
	 * FIXME - what about controllers on other busses? - IDs must be
	 * unique.  dev pointer should be sufficiently unique, but
	 * BUS:SLOT.FUNC numbers may not be unique.
	 */
	struct device *dev;
	const char *mod_name;
	const char *mod_ver;
	const char *ctl_name;
	char proc_name[MC_PROC_NAME_MAX_LEN + 1];
	void *pvt_info;
	u32 ue_noinfo_count;	/* Uncorrectable Errors w/o info */
	u32 ce_noinfo_count;	/* Correctable Errors w/o info */
	u32 ue_count;		/* Total Uncorrectable Errors for this MC */
	u32 ce_count;		/* Total Correctable Errors for this MC */
	unsigned long start_time;	/* mci load start time (in jiffies) */

	/* this stuff is for safe removal of mc devices from global list while
	 * NMI handlers may be traversing list
	 */
	struct rcu_head rcu;
	struct completion complete;

	/* edac sysfs device control */
	struct kobject edac_mci_kobj;
	struct completion kobj_complete;
};

#ifdef CONFIG_PCI

/* write all or some bits in a byte-register*/
static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
		u8 mask)
{
	if (mask != 0xff) {
		u8 buf;

		pci_read_config_byte(pdev, offset, &buf);
		value &= mask;
		buf &= ~mask;
		value |= buf;
	}

	pci_write_config_byte(pdev, offset, value);
}

/* write all or some bits in a word-register*/
static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
		u16 value, u16 mask)
{
	if (mask != 0xffff) {
		u16 buf;

		pci_read_config_word(pdev, offset, &buf);
		value &= mask;
		buf &= ~mask;
		value |= buf;
	}

	pci_write_config_word(pdev, offset, value);
}

/* write all or some bits in a dword-register*/
static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
		u32 value, u32 mask)
{
	if (mask != 0xffff) {
		u32 buf;

		pci_read_config_dword(pdev, offset, &buf);
		value &= mask;
		buf &= ~mask;
		value |= buf;
	}

	pci_write_config_dword(pdev, offset, value);
}

#endif /* CONFIG_PCI */

#ifdef CONFIG_EDAC_DEBUG
void edac_mc_dump_channel(struct channel_info *chan);
void edac_mc_dump_mci(struct mem_ctl_info *mci);
void edac_mc_dump_csrow(struct csrow_info *csrow);
#endif  /* CONFIG_EDAC_DEBUG */

extern int edac_mc_add_mc(struct mem_ctl_info *mci,int mc_idx);
extern struct mem_ctl_info * edac_mc_del_mc(struct device *dev);
extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
					unsigned long page);
extern void edac_mc_scrub_block(unsigned long page, unsigned long offset,
		u32 size);

/*
 * The no info errors are used when error overflows are reported.
 * There are a limited number of error logging registers that can
 * be exausted.  When all registers are exhausted and an additional
 * error occurs then an error overflow register records that an
 * error occured and the type of error, but doesn't have any
 * further information.  The ce/ue versions make for cleaner
 * reporting logic and function interface - reduces conditional
 * statement clutter and extra function arguments.
 */
extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
		unsigned long page_frame_number, unsigned long offset_in_page,
		unsigned long syndrome, int row, int channel,
		const char *msg);
extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
		const char *msg);
extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
		unsigned long page_frame_number, unsigned long offset_in_page,
		int row, const char *msg);
extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
		const char *msg);

/*
 * This kmalloc's and initializes all the structures.
 * Can't be used if all structures don't have the same lifetime.
 */
extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
		unsigned nr_chans);

/* Free an mc previously allocated by edac_mc_alloc() */
extern void edac_mc_free(struct mem_ctl_info *mci);

#endif				/* _EDAC_MC_H_ */
Commit	Line	Data
da9bb1d2 AC	1	/*
	2	* MC kernel module
	3	* (C) 2003 Linux Networx (http://lnxi.com)
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* Written by Thayne Harbaugh
	8	* Based on work by Dan Hollis <goemon at anime dot net> and others.
	9	* http://www.anime.net/~goemon/linux-ecc/
	10	*
	11	* NMI handling support added by
	12	* Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
	13	*
	14	* $Id: edac_mc.h,v 1.4.2.10 2005/10/05 00:43:44 dsp_llnl Exp $
	15	*
	16	*/
	17
da9bb1d2 AC	18	#ifndef _EDAC_MC_H_
	19	#define _EDAC_MC_H_
	20
da9bb1d2 AC	21	#include <linux/kernel.h>
	22	#include <linux/types.h>
	23	#include <linux/module.h>
	24	#include <linux/spinlock.h>
	25	#include <linux/smp.h>
	26	#include <linux/pci.h>
	27	#include <linux/time.h>
	28	#include <linux/nmi.h>
	29	#include <linux/rcupdate.h>
	30	#include <linux/completion.h>
	31	#include <linux/kobject.h>
	32
da9bb1d2 AC	33	#define EDAC_MC_LABEL_LEN 31
	34	#define MC_PROC_NAME_MAX_LEN 7
	35
	36	#if PAGE_SHIFT < 20
	37	#define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
	38	#else /* PAGE_SHIFT > 20 */
	39	#define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) )
	40	#endif
	41
537fba28	42	#define edac_printk(level, prefix, fmt, arg...) \
e7ecd891	43	printk(level "EDAC " prefix ": " fmt, ##arg)
537fba28 DP	44
537fba28 DP	45	#define edac_mc_printk(mci, level, fmt, arg...) \
e7ecd891	46	printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
537fba28 DP	47
537fba28 DP	48	#define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
e7ecd891	49	printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
537fba28 DP	50
	51	/* prefixes for edac_printk() and edac_mc_printk() */
	52	#define EDAC_MC "MC"
	53	#define EDAC_PCI "PCI"
	54	#define EDAC_DEBUG "DEBUG"
	55
da9bb1d2 AC	56	#ifdef CONFIG_EDAC_DEBUG
da9bb1d2 AC	57	extern int edac_debug_level;
537fba28 DP	58
	59	#define edac_debug_printk(level, fmt, arg...) \
	60	do { \
	61	if (level <= edac_debug_level) \
	62	edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \
	63	} while(0)
	64
da9bb1d2 AC	65	#define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
	66	#define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
	67	#define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
	68	#define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
	69	#define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
e7ecd891 DP	70
	71	#else /* !CONFIG_EDAC_DEBUG */
	72
da9bb1d2 AC	73	#define debugf0( ... )
	74	#define debugf1( ... )
	75	#define debugf2( ... )
	76	#define debugf3( ... )
	77	#define debugf4( ... )
da9bb1d2	78
e7ecd891	79	#endif /* !CONFIG_EDAC_DEBUG */
da9bb1d2	80
da9bb1d2 AC	81	#define BIT(x) (1 << (x))
da9bb1d2 AC	82
e7ecd891 DP	83	#define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
e7ecd891 DP	84	PCI_DEVICE_ID_ ## vend ## _ ## dev
da9bb1d2	85
37f04581 DT	86	#if defined(CONFIG_X86) && defined(CONFIG_PCI)
	87	#define dev_name(dev) pci_name(to_pci_dev(dev))
	88	#else
	89	#define dev_name(dev) to_platform_device(dev)->name
	90	#endif
	91
da9bb1d2 AC	92	/* memory devices */
	93	enum dev_type {
	94	DEV_UNKNOWN = 0,
	95	DEV_X1,
	96	DEV_X2,
	97	DEV_X4,
	98	DEV_X8,
	99	DEV_X16,
	100	DEV_X32, /* Do these parts exist? */
	101	DEV_X64 /* Do these parts exist? */
	102	};
	103
	104	#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
	105	#define DEV_FLAG_X1 BIT(DEV_X1)
	106	#define DEV_FLAG_X2 BIT(DEV_X2)
	107	#define DEV_FLAG_X4 BIT(DEV_X4)
	108	#define DEV_FLAG_X8 BIT(DEV_X8)
	109	#define DEV_FLAG_X16 BIT(DEV_X16)
	110	#define DEV_FLAG_X32 BIT(DEV_X32)
	111	#define DEV_FLAG_X64 BIT(DEV_X64)
	112
	113	/* memory types */
	114	enum mem_type {
	115	MEM_EMPTY = 0, /* Empty csrow */
	116	MEM_RESERVED, /* Reserved csrow type */
	117	MEM_UNKNOWN, /* Unknown csrow type */
	118	MEM_FPM, /* Fast page mode */
	119	MEM_EDO, /* Extended data out */
	120	MEM_BEDO, /* Burst Extended data out */
	121	MEM_SDR, /* Single data rate SDRAM */
	122	MEM_RDR, /* Registered single data rate SDRAM */
	123	MEM_DDR, /* Double data rate SDRAM */
	124	MEM_RDDR, /* Registered Double data rate SDRAM */
	125	MEM_RMBS /* Rambus DRAM */
	126	};
	127
	128	#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
	129	#define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
	130	#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
	131	#define MEM_FLAG_FPM BIT(MEM_FPM)
	132	#define MEM_FLAG_EDO BIT(MEM_EDO)
	133	#define MEM_FLAG_BEDO BIT(MEM_BEDO)
	134	#define MEM_FLAG_SDR BIT(MEM_SDR)
	135	#define MEM_FLAG_RDR BIT(MEM_RDR)
	136	#define MEM_FLAG_DDR BIT(MEM_DDR)
	137	#define MEM_FLAG_RDDR BIT(MEM_RDDR)
	138	#define MEM_FLAG_RMBS BIT(MEM_RMBS)
	139
da9bb1d2 AC	140	/* chipset Error Detection and Correction capabilities and mode */
	141	enum edac_type {
	142	EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
	143	EDAC_NONE, /* Doesnt support ECC */
	144	EDAC_RESERVED, /* Reserved ECC type */
	145	EDAC_PARITY, /* Detects parity errors */
	146	EDAC_EC, /* Error Checking - no correction */
	147	EDAC_SECDED, /* Single bit error correction, Double detection */
	148	EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
	149	EDAC_S4ECD4ED, /* Chipkill x4 devices */
	150	EDAC_S8ECD8ED, /* Chipkill x8 devices */
	151	EDAC_S16ECD16ED, /* Chipkill x16 devices */
	152	};
	153
	154	#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
	155	#define EDAC_FLAG_NONE BIT(EDAC_NONE)
	156	#define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
	157	#define EDAC_FLAG_EC BIT(EDAC_EC)
	158	#define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
	159	#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
	160	#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
	161	#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
	162	#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
	163
da9bb1d2 AC	164	/* scrubbing capabilities */
	165	enum scrub_type {
	166	SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
	167	SCRUB_NONE, /* No scrubber */
	168	SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
	169	SCRUB_SW_SRC, /* Software scrub only errors */
	170	SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
	171	SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
	172	SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
	173	SCRUB_HW_SRC, /* Hardware scrub only errors */
	174	SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
	175	SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
	176	};
	177
	178	#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
	179	#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC_CORR)
	180	#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC_CORR)
	181	#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
	182	#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
	183	#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC_CORR)
	184	#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC_CORR)
	185	#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
	186
da9bb1d2 AC	187	/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
	188
	189	/*
	190	* There are several things to be aware of that aren't at all obvious:
	191	*
	192	*
	193	* SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
	194	*
	195	* These are some of the many terms that are thrown about that don't always
	196	* mean what people think they mean (Inconceivable!). In the interest of
	197	* creating a common ground for discussion, terms and their definitions
	198	* will be established.
	199	*
	200	* Memory devices: The individual chip on a memory stick. These devices
	201	* commonly output 4 and 8 bits each. Grouping several
	202	* of these in parallel provides 64 bits which is common
	203	* for a memory stick.
	204	*
	205	* Memory Stick: A printed circuit board that agregates multiple
	206	* memory devices in parallel. This is the atomic
	207	* memory component that is purchaseable by Joe consumer
	208	* and loaded into a memory socket.
	209	*
	210	* Socket: A physical connector on the motherboard that accepts
	211	* a single memory stick.
	212	*
	213	* Channel: Set of memory devices on a memory stick that must be
	214	* grouped in parallel with one or more additional
	215	* channels from other memory sticks. This parallel
	216	* grouping of the output from multiple channels are
	217	* necessary for the smallest granularity of memory access.
	218	* Some memory controllers are capable of single channel -
	219	* which means that memory sticks can be loaded
	220	* individually. Other memory controllers are only
	221	* capable of dual channel - which means that memory
	222	* sticks must be loaded as pairs (see "socket set").
	223	*
	224	* Chip-select row: All of the memory devices that are selected together.
	225	* for a single, minimum grain of memory access.
	226	* This selects all of the parallel memory devices across
	227	* all of the parallel channels. Common chip-select rows
	228	* for single channel are 64 bits, for dual channel 128
	229	* bits.
	230	*
	231	* Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
	232	* Motherboards commonly drive two chip-select pins to
	233	* a memory stick. A single-ranked stick, will occupy
	234	* only one of those rows. The other will be unused.
	235	*
	236	* Double-Ranked stick: A double-ranked stick has two chip-select rows which
	237	* access different sets of memory devices. The two
	238	* rows cannot be accessed concurrently.
	239	*
	240	* Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
	241	* A double-sided stick has two chip-select rows which
	242	* access different sets of memory devices. The two
	243	* rows cannot be accessed concurrently. "Double-sided"
	244	* is irrespective of the memory devices being mounted
	245	* on both sides of the memory stick.
	246	*
	247	* Socket set: All of the memory sticks that are required for for
	248	* a single memory access or all of the memory sticks
	249	* spanned by a chip-select row. A single socket set
	250	* has two chip-select rows and if double-sided sticks
251	* are used these will occupy those chip-select rows.
252	*
253	* Bank: This term is avoided because it is unclear when
254	* needing to distinguish between chip-select rows and
255	* socket sets.
256	*
257	* Controller pages:
258	*
259	* Physical pages:
260	*
261	* Virtual pages:
262	*
263	*
264	* STRUCTURE ORGANIZATION AND CHOICES
265	*
266	*
267	*
268	* PS - I enjoyed writing all that about as much as you enjoyed reading it.
269	*/
270
da9bb1d2 AC	271	struct channel_info {
	272	int chan_idx; /* channel index */
	273	u32 ce_count; /* Correctable Errors for this CHANNEL */
e7ecd891	274	char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
da9bb1d2 AC	275	struct csrow_info csrow; / the parent */
	276	};
	277
da9bb1d2 AC	278	struct csrow_info {
	279	unsigned long first_page; /* first page number in dimm */
	280	unsigned long last_page; /* last page number in dimm */
	281	unsigned long page_mask; /* used for interleaving -
e7ecd891 DP	282	* 0UL for non intlv
e7ecd891 DP	283	*/
da9bb1d2 AC	284	u32 nr_pages; /* number of pages in csrow */
	285	u32 grain; /* granularity of reported error in bytes */
	286	int csrow_idx; /* the chip-select row */
	287	enum dev_type dtype; /* memory device type */
	288	u32 ue_count; /* Uncorrectable Errors for this csrow */
	289	u32 ce_count; /* Correctable Errors for this csrow */
	290	enum mem_type mtype; /* memory csrow type */
	291	enum edac_type edac_mode; /* EDAC mode for this csrow */
	292	struct mem_ctl_info mci; / the parent */
	293
	294	struct kobject kobj; /* sysfs kobject for this csrow */
472678eb	295	struct completion kobj_complete;
da9bb1d2 AC	296
	297	/* FIXME the number of CHANNELs might need to become dynamic */
	298	u32 nr_channels;
	299	struct channel_info *channels;
	300	};
	301
da9bb1d2 AC	302	struct mem_ctl_info {
	303	struct list_head link; /* for global list of mem_ctl_info structs */
	304	unsigned long mtype_cap; /* memory types supported by mc */
	305	unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
	306	unsigned long edac_cap; /* configuration capabilities - this is
e7ecd891 DP	307	* closely related to edac_ctl_cap. The
	308	* difference is that the controller may be
	309	* capable of s4ecd4ed which would be listed
	310	* in edac_ctl_cap, but if channels aren't
	311	* capable of s4ecd4ed then the edac_cap would
	312	* not have that capability.
	313	*/
da9bb1d2 AC	314	unsigned long scrub_cap; /* chipset scrub capabilities */
	315	enum scrub_type scrub_mode; /* current scrub mode */
	316
da9bb1d2 AC	317	/* pointer to edac checking routine */
	318	void (edac_check) (struct mem_ctl_info mci);
	319	/*
	320	* Remaps memory pages: controller pages to physical pages.
	321	* For most MC's, this will be NULL.
	322	*/
	323	/* FIXME - why not send the phys page to begin with? */
	324	unsigned long (ctl_page_to_phys) (struct mem_ctl_info mci,
e7ecd891	325	unsigned long page);
da9bb1d2 AC	326	int mc_idx;
	327	int nr_csrows;
	328	struct csrow_info *csrows;
	329	/*
	330	* FIXME - what about controllers on other busses? - IDs must be
37f04581	331	* unique. dev pointer should be sufficiently unique, but
da9bb1d2 AC	332	* BUS:SLOT.FUNC numbers may not be unique.
da9bb1d2 AC	333	*/
37f04581	334	struct device *dev;
da9bb1d2 AC	335	const char *mod_name;
	336	const char *mod_ver;
	337	const char *ctl_name;
	338	char proc_name[MC_PROC_NAME_MAX_LEN + 1];
	339	void *pvt_info;
	340	u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */
	341	u32 ce_noinfo_count; /* Correctable Errors w/o info */
	342	u32 ue_count; /* Total Uncorrectable Errors for this MC */
	343	u32 ce_count; /* Total Correctable Errors for this MC */
	344	unsigned long start_time; /* mci load start time (in jiffies) */
	345
	346	/* this stuff is for safe removal of mc devices from global list while
	347	* NMI handlers may be traversing list
	348	*/
	349	struct rcu_head rcu;
	350	struct completion complete;
	351
	352	/* edac sysfs device control */
	353	struct kobject edac_mci_kobj;
472678eb	354	struct completion kobj_complete;
da9bb1d2 AC	355	};
da9bb1d2 AC	356
37f04581 DT	357	#ifdef CONFIG_PCI
37f04581 DT	358
da9bb1d2	359	/* write all or some bits in a byte-register*/
e7ecd891 DP	360	static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
e7ecd891 DP	361	u8 mask)
da9bb1d2 AC	362	{
	363	if (mask != 0xff) {
	364	u8 buf;
e7ecd891	365
da9bb1d2 AC	366	pci_read_config_byte(pdev, offset, &buf);
	367	value &= mask;
	368	buf &= ~mask;
	369	value \|= buf;
	370	}
e7ecd891	371
da9bb1d2 AC	372	pci_write_config_byte(pdev, offset, value);
	373	}
	374
da9bb1d2 AC	375	/* write all or some bits in a word-register*/
da9bb1d2 AC	376	static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
e7ecd891	377	u16 value, u16 mask)
da9bb1d2 AC	378	{
	379	if (mask != 0xffff) {
	380	u16 buf;
e7ecd891	381
da9bb1d2 AC	382	pci_read_config_word(pdev, offset, &buf);
	383	value &= mask;
	384	buf &= ~mask;
	385	value \|= buf;
	386	}
e7ecd891	387
da9bb1d2 AC	388	pci_write_config_word(pdev, offset, value);
	389	}
	390
da9bb1d2 AC	391	/* write all or some bits in a dword-register*/
da9bb1d2 AC	392	static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
e7ecd891	393	u32 value, u32 mask)
da9bb1d2 AC	394	{
	395	if (mask != 0xffff) {
	396	u32 buf;
e7ecd891	397
da9bb1d2 AC	398	pci_read_config_dword(pdev, offset, &buf);
	399	value &= mask;
	400	buf &= ~mask;
	401	value \|= buf;
	402	}
e7ecd891	403
da9bb1d2 AC	404	pci_write_config_dword(pdev, offset, value);
	405	}
	406
37f04581 DT	407	#endif /* CONFIG_PCI */
37f04581 DT	408
da9bb1d2 AC	409	#ifdef CONFIG_EDAC_DEBUG
	410	void edac_mc_dump_channel(struct channel_info *chan);
	411	void edac_mc_dump_mci(struct mem_ctl_info *mci);
	412	void edac_mc_dump_csrow(struct csrow_info *csrow);
e7ecd891	413	#endif /* CONFIG_EDAC_DEBUG */
da9bb1d2	414
2d7bbb91	415	extern int edac_mc_add_mc(struct mem_ctl_info *mci,int mc_idx);
37f04581	416	extern struct mem_ctl_info * edac_mc_del_mc(struct device *dev);
da9bb1d2	417	extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
e7ecd891 DP	418	unsigned long page);
	419	extern void edac_mc_scrub_block(unsigned long page, unsigned long offset,
	420	u32 size);
da9bb1d2 AC	421
	422	/*
	423	* The no info errors are used when error overflows are reported.
	424	* There are a limited number of error logging registers that can
	425	* be exausted. When all registers are exhausted and an additional
	426	* error occurs then an error overflow register records that an
	427	* error occured and the type of error, but doesn't have any
	428	* further information. The ce/ue versions make for cleaner
	429	* reporting logic and function interface - reduces conditional
	430	* statement clutter and extra function arguments.
	431	*/
	432	extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
e7ecd891 DP	433	unsigned long page_frame_number, unsigned long offset_in_page,
	434	unsigned long syndrome, int row, int channel,
	435	const char *msg);
da9bb1d2	436	extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
e7ecd891	437	const char *msg);
da9bb1d2	438	extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
e7ecd891 DP	439	unsigned long page_frame_number, unsigned long offset_in_page,
e7ecd891 DP	440	int row, const char *msg);
da9bb1d2	441	extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
e7ecd891	442	const char *msg);
da9bb1d2 AC	443
	444	/*
	445	* This kmalloc's and initializes all the structures.
	446	* Can't be used if all structures don't have the same lifetime.
	447	*/
e7ecd891 DP	448	extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
e7ecd891 DP	449	unsigned nr_chans);
da9bb1d2 AC	450
	451	/* Free an mc previously allocated by edac_mc_alloc() */
	452	extern void edac_mc_free(struct mem_ctl_info *mci);
	453
da9bb1d2	454	#endif /* _EDAC_MC_H_ */