mrf24j40: add device managed APIs
[deliverable/linux.git] / drivers / edac / edac_mc_sysfs.c
CommitLineData
7c9281d7
DT
1/*
2 * edac_mc kernel module
42a8e397
DT
3 * (C) 2005-2007 Linux Networx (http://lnxi.com)
4 *
7c9281d7
DT
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
42a8e397 8 * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com
7c9281d7 9 *
37e59f87 10 * (c) 2012-2013 - Mauro Carvalho Chehab
7a623c03
MCC
11 * The entire API were re-written, and ported to use struct device
12 *
7c9281d7
DT
13 */
14
7c9281d7 15#include <linux/ctype.h>
5a0e3ad6 16#include <linux/slab.h>
30e1f7a8 17#include <linux/edac.h>
8096cfaf 18#include <linux/bug.h>
7a623c03 19#include <linux/pm_runtime.h>
452a6bf9 20#include <linux/uaccess.h>
7c9281d7 21
20bcb7a8 22#include "edac_core.h"
7c9281d7
DT
23#include "edac_module.h"
24
25/* MC EDAC Controls, setable by module parameter, and sysfs */
4de78c68
DJ
26static int edac_mc_log_ue = 1;
27static int edac_mc_log_ce = 1;
f044091c 28static int edac_mc_panic_on_ue;
4de78c68 29static int edac_mc_poll_msec = 1000;
7c9281d7
DT
30
31/* Getter functions for above */
4de78c68 32int edac_mc_get_log_ue(void)
7c9281d7 33{
4de78c68 34 return edac_mc_log_ue;
7c9281d7
DT
35}
36
4de78c68 37int edac_mc_get_log_ce(void)
7c9281d7 38{
4de78c68 39 return edac_mc_log_ce;
7c9281d7
DT
40}
41
4de78c68 42int edac_mc_get_panic_on_ue(void)
7c9281d7 43{
4de78c68 44 return edac_mc_panic_on_ue;
7c9281d7
DT
45}
46
81d87cb1
DJ
47/* this is temporary */
48int edac_mc_get_poll_msec(void)
49{
4de78c68 50 return edac_mc_poll_msec;
7c9281d7
DT
51}
52
096846e2
AJ
53static int edac_set_poll_msec(const char *val, struct kernel_param *kp)
54{
9da21b15 55 unsigned long l;
096846e2
AJ
56 int ret;
57
58 if (!val)
59 return -EINVAL;
60
9da21b15 61 ret = kstrtoul(val, 0, &l);
c542b53d
JH
62 if (ret)
63 return ret;
9da21b15
BP
64
65 if (l < 1000)
096846e2 66 return -EINVAL;
9da21b15
BP
67
68 *((unsigned long *)kp->arg) = l;
096846e2
AJ
69
70 /* notify edac_mc engine to reset the poll period */
71 edac_mc_reset_delay_period(l);
72
73 return 0;
74}
75
7c9281d7 76/* Parameter declarations for above */
4de78c68
DJ
77module_param(edac_mc_panic_on_ue, int, 0644);
78MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on");
79module_param(edac_mc_log_ue, int, 0644);
80MODULE_PARM_DESC(edac_mc_log_ue,
079708b9 81 "Log uncorrectable error to console: 0=off 1=on");
4de78c68
DJ
82module_param(edac_mc_log_ce, int, 0644);
83MODULE_PARM_DESC(edac_mc_log_ce,
079708b9 84 "Log correctable error to console: 0=off 1=on");
096846e2
AJ
85module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int,
86 &edac_mc_poll_msec, 0644);
4de78c68 87MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds");
7c9281d7 88
de3910eb 89static struct device *mci_pdev;
7a623c03 90
7c9281d7
DT
91/*
92 * various constants for Memory Controllers
93 */
8b7719e0 94static const char * const mem_types[] = {
7c9281d7
DT
95 [MEM_EMPTY] = "Empty",
96 [MEM_RESERVED] = "Reserved",
97 [MEM_UNKNOWN] = "Unknown",
98 [MEM_FPM] = "FPM",
99 [MEM_EDO] = "EDO",
100 [MEM_BEDO] = "BEDO",
101 [MEM_SDR] = "Unbuffered-SDR",
102 [MEM_RDR] = "Registered-SDR",
103 [MEM_DDR] = "Unbuffered-DDR",
104 [MEM_RDDR] = "Registered-DDR",
1a9b85e6
DJ
105 [MEM_RMBS] = "RMBS",
106 [MEM_DDR2] = "Unbuffered-DDR2",
107 [MEM_FB_DDR2] = "FullyBuffered-DDR2",
1d5f726c 108 [MEM_RDDR2] = "Registered-DDR2",
b1cfebc9
YS
109 [MEM_XDR] = "XDR",
110 [MEM_DDR3] = "Unbuffered-DDR3",
111 [MEM_RDDR3] = "Registered-DDR3"
7c9281d7
DT
112};
113
8b7719e0 114static const char * const dev_types[] = {
7c9281d7
DT
115 [DEV_UNKNOWN] = "Unknown",
116 [DEV_X1] = "x1",
117 [DEV_X2] = "x2",
118 [DEV_X4] = "x4",
119 [DEV_X8] = "x8",
120 [DEV_X16] = "x16",
121 [DEV_X32] = "x32",
122 [DEV_X64] = "x64"
123};
124
8b7719e0 125static const char * const edac_caps[] = {
7c9281d7
DT
126 [EDAC_UNKNOWN] = "Unknown",
127 [EDAC_NONE] = "None",
128 [EDAC_RESERVED] = "Reserved",
129 [EDAC_PARITY] = "PARITY",
130 [EDAC_EC] = "EC",
131 [EDAC_SECDED] = "SECDED",
132 [EDAC_S2ECD2ED] = "S2ECD2ED",
133 [EDAC_S4ECD4ED] = "S4ECD4ED",
134 [EDAC_S8ECD8ED] = "S8ECD8ED",
135 [EDAC_S16ECD16ED] = "S16ECD16ED"
136};
137
19974710 138#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03
MCC
139/*
140 * EDAC sysfs CSROW data structures and methods
141 */
142
143#define to_csrow(k) container_of(k, struct csrow_info, dev)
144
145/*
146 * We need it to avoid namespace conflicts between the legacy API
147 * and the per-dimm/per-rank one
7c9281d7 148 */
7a623c03 149#define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
fbe2d361 150 static struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
7a623c03
MCC
151
152struct dev_ch_attribute {
153 struct device_attribute attr;
154 int channel;
155};
156
157#define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \
158 struct dev_ch_attribute dev_attr_legacy_##_name = \
159 { __ATTR(_name, _mode, _show, _store), (_var) }
160
161#define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel)
7c9281d7
DT
162
163/* Set of more default csrow<id> attribute show/store functions */
7a623c03
MCC
164static ssize_t csrow_ue_count_show(struct device *dev,
165 struct device_attribute *mattr, char *data)
7c9281d7 166{
7a623c03
MCC
167 struct csrow_info *csrow = to_csrow(dev);
168
079708b9 169 return sprintf(data, "%u\n", csrow->ue_count);
7c9281d7
DT
170}
171
7a623c03
MCC
172static ssize_t csrow_ce_count_show(struct device *dev,
173 struct device_attribute *mattr, char *data)
7c9281d7 174{
7a623c03
MCC
175 struct csrow_info *csrow = to_csrow(dev);
176
079708b9 177 return sprintf(data, "%u\n", csrow->ce_count);
7c9281d7
DT
178}
179
7a623c03
MCC
180static ssize_t csrow_size_show(struct device *dev,
181 struct device_attribute *mattr, char *data)
7c9281d7 182{
7a623c03 183 struct csrow_info *csrow = to_csrow(dev);
a895bf8b
MCC
184 int i;
185 u32 nr_pages = 0;
186
187 for (i = 0; i < csrow->nr_channels; i++)
de3910eb 188 nr_pages += csrow->channels[i]->dimm->nr_pages;
a895bf8b 189 return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
7c9281d7
DT
190}
191
7a623c03
MCC
192static ssize_t csrow_mem_type_show(struct device *dev,
193 struct device_attribute *mattr, char *data)
7c9281d7 194{
7a623c03
MCC
195 struct csrow_info *csrow = to_csrow(dev);
196
de3910eb 197 return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]);
7c9281d7
DT
198}
199
7a623c03
MCC
200static ssize_t csrow_dev_type_show(struct device *dev,
201 struct device_attribute *mattr, char *data)
7c9281d7 202{
7a623c03
MCC
203 struct csrow_info *csrow = to_csrow(dev);
204
de3910eb 205 return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]);
7c9281d7
DT
206}
207
7a623c03
MCC
208static ssize_t csrow_edac_mode_show(struct device *dev,
209 struct device_attribute *mattr,
210 char *data)
7c9281d7 211{
7a623c03
MCC
212 struct csrow_info *csrow = to_csrow(dev);
213
de3910eb 214 return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]);
7c9281d7
DT
215}
216
217/* show/store functions for DIMM Label attributes */
7a623c03
MCC
218static ssize_t channel_dimm_label_show(struct device *dev,
219 struct device_attribute *mattr,
220 char *data)
7c9281d7 221{
7a623c03
MCC
222 struct csrow_info *csrow = to_csrow(dev);
223 unsigned chan = to_channel(mattr);
de3910eb 224 struct rank_info *rank = csrow->channels[chan];
7a623c03 225
124682c7 226 /* if field has not been initialized, there is nothing to send */
7a623c03 227 if (!rank->dimm->label[0])
124682c7
AJ
228 return 0;
229
230 return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n",
7a623c03 231 rank->dimm->label);
7c9281d7
DT
232}
233
7a623c03
MCC
234static ssize_t channel_dimm_label_store(struct device *dev,
235 struct device_attribute *mattr,
236 const char *data, size_t count)
7c9281d7 237{
7a623c03
MCC
238 struct csrow_info *csrow = to_csrow(dev);
239 unsigned chan = to_channel(mattr);
de3910eb 240 struct rank_info *rank = csrow->channels[chan];
7a623c03 241
7c9281d7
DT
242 ssize_t max_size = 0;
243
079708b9 244 max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
7a623c03
MCC
245 strncpy(rank->dimm->label, data, max_size);
246 rank->dimm->label[max_size] = '\0';
7c9281d7
DT
247
248 return max_size;
249}
250
251/* show function for dynamic chX_ce_count attribute */
7a623c03
MCC
252static ssize_t channel_ce_count_show(struct device *dev,
253 struct device_attribute *mattr, char *data)
7c9281d7 254{
7a623c03
MCC
255 struct csrow_info *csrow = to_csrow(dev);
256 unsigned chan = to_channel(mattr);
de3910eb 257 struct rank_info *rank = csrow->channels[chan];
7a623c03
MCC
258
259 return sprintf(data, "%u\n", rank->ce_count);
7c9281d7
DT
260}
261
7a623c03
MCC
262/* cwrow<id>/attribute files */
263DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL);
264DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL);
265DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL);
266DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL);
267DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL);
268DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL);
7c9281d7 269
7a623c03
MCC
270/* default attributes of the CSROW<id> object */
271static struct attribute *csrow_attrs[] = {
272 &dev_attr_legacy_dev_type.attr,
273 &dev_attr_legacy_mem_type.attr,
274 &dev_attr_legacy_edac_mode.attr,
275 &dev_attr_legacy_size_mb.attr,
276 &dev_attr_legacy_ue_count.attr,
277 &dev_attr_legacy_ce_count.attr,
278 NULL,
279};
7c9281d7 280
7a623c03
MCC
281static struct attribute_group csrow_attr_grp = {
282 .attrs = csrow_attrs,
283};
7c9281d7 284
7a623c03
MCC
285static const struct attribute_group *csrow_attr_groups[] = {
286 &csrow_attr_grp,
287 NULL
288};
7c9281d7 289
de3910eb 290static void csrow_attr_release(struct device *dev)
7c9281d7 291{
de3910eb
MCC
292 struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
293
956b9ba1 294 edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
de3910eb 295 kfree(csrow);
7c9281d7
DT
296}
297
7a623c03
MCC
298static struct device_type csrow_attr_type = {
299 .groups = csrow_attr_groups,
300 .release = csrow_attr_release,
7c9281d7
DT
301};
302
7a623c03
MCC
303/*
304 * possible dynamic channel DIMM Label attribute files
305 *
306 */
7c9281d7 307
7a623c03 308#define EDAC_NR_CHANNELS 6
7c9281d7 309
7a623c03 310DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 311 channel_dimm_label_show, channel_dimm_label_store, 0);
7a623c03 312DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 313 channel_dimm_label_show, channel_dimm_label_store, 1);
7a623c03 314DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 315 channel_dimm_label_show, channel_dimm_label_store, 2);
7a623c03 316DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 317 channel_dimm_label_show, channel_dimm_label_store, 3);
7a623c03 318DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 319 channel_dimm_label_show, channel_dimm_label_store, 4);
7a623c03 320DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 321 channel_dimm_label_show, channel_dimm_label_store, 5);
7c9281d7
DT
322
323/* Total possible dynamic DIMM Label attribute file table */
7a623c03
MCC
324static struct device_attribute *dynamic_csrow_dimm_attr[] = {
325 &dev_attr_legacy_ch0_dimm_label.attr,
326 &dev_attr_legacy_ch1_dimm_label.attr,
327 &dev_attr_legacy_ch2_dimm_label.attr,
328 &dev_attr_legacy_ch3_dimm_label.attr,
329 &dev_attr_legacy_ch4_dimm_label.attr,
330 &dev_attr_legacy_ch5_dimm_label.attr
7c9281d7
DT
331};
332
333/* possible dynamic channel ce_count attribute files */
c8c64d16 334DEVICE_CHANNEL(ch0_ce_count, S_IRUGO,
7a623c03 335 channel_ce_count_show, NULL, 0);
c8c64d16 336DEVICE_CHANNEL(ch1_ce_count, S_IRUGO,
7a623c03 337 channel_ce_count_show, NULL, 1);
c8c64d16 338DEVICE_CHANNEL(ch2_ce_count, S_IRUGO,
7a623c03 339 channel_ce_count_show, NULL, 2);
c8c64d16 340DEVICE_CHANNEL(ch3_ce_count, S_IRUGO,
7a623c03 341 channel_ce_count_show, NULL, 3);
c8c64d16 342DEVICE_CHANNEL(ch4_ce_count, S_IRUGO,
7a623c03 343 channel_ce_count_show, NULL, 4);
c8c64d16 344DEVICE_CHANNEL(ch5_ce_count, S_IRUGO,
7a623c03 345 channel_ce_count_show, NULL, 5);
7c9281d7
DT
346
347/* Total possible dynamic ce_count attribute file table */
7a623c03
MCC
348static struct device_attribute *dynamic_csrow_ce_count_attr[] = {
349 &dev_attr_legacy_ch0_ce_count.attr,
350 &dev_attr_legacy_ch1_ce_count.attr,
351 &dev_attr_legacy_ch2_ce_count.attr,
352 &dev_attr_legacy_ch3_ce_count.attr,
353 &dev_attr_legacy_ch4_ce_count.attr,
354 &dev_attr_legacy_ch5_ce_count.attr
7c9281d7
DT
355};
356
e39f4ea9
MCC
357static inline int nr_pages_per_csrow(struct csrow_info *csrow)
358{
359 int chan, nr_pages = 0;
360
361 for (chan = 0; chan < csrow->nr_channels; chan++)
de3910eb 362 nr_pages += csrow->channels[chan]->dimm->nr_pages;
e39f4ea9
MCC
363
364 return nr_pages;
365}
366
7a623c03
MCC
367/* Create a CSROW object under specifed edac_mc_device */
368static int edac_create_csrow_object(struct mem_ctl_info *mci,
369 struct csrow_info *csrow, int index)
7c9281d7 370{
7a623c03 371 int err, chan;
7c9281d7 372
7a623c03
MCC
373 if (csrow->nr_channels >= EDAC_NR_CHANNELS)
374 return -ENODEV;
7c9281d7 375
7a623c03 376 csrow->dev.type = &csrow_attr_type;
88d84ac9 377 csrow->dev.bus = mci->bus;
7a623c03
MCC
378 device_initialize(&csrow->dev);
379 csrow->dev.parent = &mci->dev;
921a6899 380 csrow->mci = mci;
7a623c03
MCC
381 dev_set_name(&csrow->dev, "csrow%d", index);
382 dev_set_drvdata(&csrow->dev, csrow);
7c9281d7 383
956b9ba1
JP
384 edac_dbg(0, "creating (virtual) csrow node %s\n",
385 dev_name(&csrow->dev));
7c9281d7 386
7a623c03
MCC
387 err = device_add(&csrow->dev);
388 if (err < 0)
389 return err;
7c9281d7 390
7a623c03 391 for (chan = 0; chan < csrow->nr_channels; chan++) {
e39f4ea9 392 /* Only expose populated DIMMs */
de3910eb 393 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 394 continue;
7a623c03
MCC
395 err = device_create_file(&csrow->dev,
396 dynamic_csrow_dimm_attr[chan]);
397 if (err < 0)
398 goto error;
399 err = device_create_file(&csrow->dev,
400 dynamic_csrow_ce_count_attr[chan]);
401 if (err < 0) {
402 device_remove_file(&csrow->dev,
403 dynamic_csrow_dimm_attr[chan]);
404 goto error;
405 }
406 }
8096cfaf 407
7a623c03 408 return 0;
8096cfaf 409
7a623c03
MCC
410error:
411 for (--chan; chan >= 0; chan--) {
412 device_remove_file(&csrow->dev,
413 dynamic_csrow_dimm_attr[chan]);
414 device_remove_file(&csrow->dev,
415 dynamic_csrow_ce_count_attr[chan]);
416 }
417 put_device(&csrow->dev);
7c9281d7 418
7a623c03
MCC
419 return err;
420}
7c9281d7
DT
421
422/* Create a CSROW object under specifed edac_mc_device */
7a623c03 423static int edac_create_csrow_objects(struct mem_ctl_info *mci)
7c9281d7 424{
7a623c03
MCC
425 int err, i, chan;
426 struct csrow_info *csrow;
7c9281d7 427
7a623c03 428 for (i = 0; i < mci->nr_csrows; i++) {
de3910eb 429 csrow = mci->csrows[i];
e39f4ea9
MCC
430 if (!nr_pages_per_csrow(csrow))
431 continue;
de3910eb 432 err = edac_create_csrow_object(mci, mci->csrows[i], i);
3d958823
MCC
433 if (err < 0) {
434 edac_dbg(1,
435 "failure: create csrow objects for csrow %d\n",
436 i);
7a623c03 437 goto error;
3d958823 438 }
7a623c03
MCC
439 }
440 return 0;
8096cfaf 441
7a623c03
MCC
442error:
443 for (--i; i >= 0; i--) {
de3910eb 444 csrow = mci->csrows[i];
e39f4ea9
MCC
445 if (!nr_pages_per_csrow(csrow))
446 continue;
7a623c03 447 for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
de3910eb 448 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 449 continue;
7a623c03
MCC
450 device_remove_file(&csrow->dev,
451 dynamic_csrow_dimm_attr[chan]);
452 device_remove_file(&csrow->dev,
453 dynamic_csrow_ce_count_attr[chan]);
454 }
de3910eb 455 put_device(&mci->csrows[i]->dev);
8096cfaf 456 }
7c9281d7 457
7a623c03
MCC
458 return err;
459}
8096cfaf 460
7a623c03
MCC
461static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
462{
463 int i, chan;
464 struct csrow_info *csrow;
8096cfaf 465
7a623c03 466 for (i = mci->nr_csrows - 1; i >= 0; i--) {
de3910eb 467 csrow = mci->csrows[i];
e39f4ea9
MCC
468 if (!nr_pages_per_csrow(csrow))
469 continue;
7a623c03 470 for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
de3910eb 471 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 472 continue;
956b9ba1
JP
473 edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n",
474 i, chan);
7a623c03
MCC
475 device_remove_file(&csrow->dev,
476 dynamic_csrow_dimm_attr[chan]);
477 device_remove_file(&csrow->dev,
478 dynamic_csrow_ce_count_attr[chan]);
7c9281d7 479 }
44d22e24 480 device_unregister(&mci->csrows[i]->dev);
7c9281d7 481 }
7c9281d7 482}
19974710
MCC
483#endif
484
485/*
486 * Per-dimm (or per-rank) devices
487 */
488
489#define to_dimm(k) container_of(k, struct dimm_info, dev)
490
491/* show/store functions for DIMM Label attributes */
492static ssize_t dimmdev_location_show(struct device *dev,
493 struct device_attribute *mattr, char *data)
494{
495 struct dimm_info *dimm = to_dimm(dev);
19974710 496
6e84d359 497 return edac_dimm_info_location(dimm, data, PAGE_SIZE);
19974710
MCC
498}
499
500static ssize_t dimmdev_label_show(struct device *dev,
501 struct device_attribute *mattr, char *data)
502{
503 struct dimm_info *dimm = to_dimm(dev);
504
505 /* if field has not been initialized, there is nothing to send */
506 if (!dimm->label[0])
507 return 0;
508
509 return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label);
510}
511
512static ssize_t dimmdev_label_store(struct device *dev,
513 struct device_attribute *mattr,
514 const char *data,
515 size_t count)
516{
517 struct dimm_info *dimm = to_dimm(dev);
518
519 ssize_t max_size = 0;
520
521 max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
522 strncpy(dimm->label, data, max_size);
523 dimm->label[max_size] = '\0';
524
525 return max_size;
526}
527
528static ssize_t dimmdev_size_show(struct device *dev,
529 struct device_attribute *mattr, char *data)
530{
531 struct dimm_info *dimm = to_dimm(dev);
532
533 return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages));
534}
535
536static ssize_t dimmdev_mem_type_show(struct device *dev,
537 struct device_attribute *mattr, char *data)
538{
539 struct dimm_info *dimm = to_dimm(dev);
540
541 return sprintf(data, "%s\n", mem_types[dimm->mtype]);
542}
543
544static ssize_t dimmdev_dev_type_show(struct device *dev,
545 struct device_attribute *mattr, char *data)
546{
547 struct dimm_info *dimm = to_dimm(dev);
548
549 return sprintf(data, "%s\n", dev_types[dimm->dtype]);
550}
551
552static ssize_t dimmdev_edac_mode_show(struct device *dev,
553 struct device_attribute *mattr,
554 char *data)
555{
556 struct dimm_info *dimm = to_dimm(dev);
557
558 return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]);
559}
560
561/* dimm/rank attribute files */
562static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR,
563 dimmdev_label_show, dimmdev_label_store);
564static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL);
565static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL);
566static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL);
567static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL);
568static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL);
569
570/* attributes of the dimm<id>/rank<id> object */
571static struct attribute *dimm_attrs[] = {
572 &dev_attr_dimm_label.attr,
573 &dev_attr_dimm_location.attr,
574 &dev_attr_size.attr,
575 &dev_attr_dimm_mem_type.attr,
576 &dev_attr_dimm_dev_type.attr,
577 &dev_attr_dimm_edac_mode.attr,
578 NULL,
579};
580
581static struct attribute_group dimm_attr_grp = {
582 .attrs = dimm_attrs,
583};
584
585static const struct attribute_group *dimm_attr_groups[] = {
586 &dimm_attr_grp,
587 NULL
588};
589
de3910eb 590static void dimm_attr_release(struct device *dev)
19974710 591{
de3910eb
MCC
592 struct dimm_info *dimm = container_of(dev, struct dimm_info, dev);
593
956b9ba1 594 edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev));
de3910eb 595 kfree(dimm);
19974710
MCC
596}
597
598static struct device_type dimm_attr_type = {
599 .groups = dimm_attr_groups,
600 .release = dimm_attr_release,
601};
602
603/* Create a DIMM object under specifed memory controller device */
604static int edac_create_dimm_object(struct mem_ctl_info *mci,
605 struct dimm_info *dimm,
606 int index)
607{
608 int err;
609 dimm->mci = mci;
610
611 dimm->dev.type = &dimm_attr_type;
88d84ac9 612 dimm->dev.bus = mci->bus;
19974710
MCC
613 device_initialize(&dimm->dev);
614
615 dimm->dev.parent = &mci->dev;
9713faec 616 if (mci->csbased)
19974710
MCC
617 dev_set_name(&dimm->dev, "rank%d", index);
618 else
619 dev_set_name(&dimm->dev, "dimm%d", index);
620 dev_set_drvdata(&dimm->dev, dimm);
621 pm_runtime_forbid(&mci->dev);
622
623 err = device_add(&dimm->dev);
624
956b9ba1 625 edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev));
19974710
MCC
626
627 return err;
628}
7c9281d7 629
7a623c03
MCC
630/*
631 * Memory controller device
632 */
633
634#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
7c9281d7 635
7a623c03
MCC
636static ssize_t mci_reset_counters_store(struct device *dev,
637 struct device_attribute *mattr,
079708b9 638 const char *data, size_t count)
7c9281d7 639{
7a623c03
MCC
640 struct mem_ctl_info *mci = to_mci(dev);
641 int cnt, row, chan, i;
5926ff50
MCC
642 mci->ue_mc = 0;
643 mci->ce_mc = 0;
7a623c03
MCC
644 mci->ue_noinfo_count = 0;
645 mci->ce_noinfo_count = 0;
7c9281d7
DT
646
647 for (row = 0; row < mci->nr_csrows; row++) {
de3910eb 648 struct csrow_info *ri = mci->csrows[row];
7c9281d7
DT
649
650 ri->ue_count = 0;
651 ri->ce_count = 0;
652
653 for (chan = 0; chan < ri->nr_channels; chan++)
de3910eb 654 ri->channels[chan]->ce_count = 0;
7c9281d7
DT
655 }
656
7a623c03
MCC
657 cnt = 1;
658 for (i = 0; i < mci->n_layers; i++) {
659 cnt *= mci->layers[i].size;
660 memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32));
661 memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32));
662 }
663
7c9281d7
DT
664 mci->start_time = jiffies;
665 return count;
666}
667
39094443
BP
668/* Memory scrubbing interface:
669 *
670 * A MC driver can limit the scrubbing bandwidth based on the CPU type.
671 * Therefore, ->set_sdram_scrub_rate should be made to return the actual
672 * bandwidth that is accepted or 0 when scrubbing is to be disabled.
673 *
674 * Negative value still means that an error has occurred while setting
675 * the scrub rate.
676 */
7a623c03
MCC
677static ssize_t mci_sdram_scrub_rate_store(struct device *dev,
678 struct device_attribute *mattr,
eba042a8 679 const char *data, size_t count)
7c9281d7 680{
7a623c03 681 struct mem_ctl_info *mci = to_mci(dev);
eba042a8 682 unsigned long bandwidth = 0;
39094443 683 int new_bw = 0;
7c9281d7 684
c7f62fc8 685 if (kstrtoul(data, 10, &bandwidth) < 0)
eba042a8 686 return -EINVAL;
7c9281d7 687
39094443 688 new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
4949603a
MT
689 if (new_bw < 0) {
690 edac_printk(KERN_WARNING, EDAC_MC,
691 "Error setting scrub rate to: %lu\n", bandwidth);
692 return -EINVAL;
7c9281d7 693 }
39094443 694
4949603a 695 return count;
7c9281d7
DT
696}
697
39094443
BP
698/*
699 * ->get_sdram_scrub_rate() return value semantics same as above.
700 */
7a623c03
MCC
701static ssize_t mci_sdram_scrub_rate_show(struct device *dev,
702 struct device_attribute *mattr,
703 char *data)
7c9281d7 704{
7a623c03 705 struct mem_ctl_info *mci = to_mci(dev);
39094443 706 int bandwidth = 0;
eba042a8 707
39094443
BP
708 bandwidth = mci->get_sdram_scrub_rate(mci);
709 if (bandwidth < 0) {
eba042a8 710 edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
39094443 711 return bandwidth;
7c9281d7 712 }
39094443 713
39094443 714 return sprintf(data, "%d\n", bandwidth);
7c9281d7
DT
715}
716
717/* default attribute files for the MCI object */
7a623c03
MCC
718static ssize_t mci_ue_count_show(struct device *dev,
719 struct device_attribute *mattr,
720 char *data)
7c9281d7 721{
7a623c03
MCC
722 struct mem_ctl_info *mci = to_mci(dev);
723
5926ff50 724 return sprintf(data, "%d\n", mci->ue_mc);
7c9281d7
DT
725}
726
7a623c03
MCC
727static ssize_t mci_ce_count_show(struct device *dev,
728 struct device_attribute *mattr,
729 char *data)
7c9281d7 730{
7a623c03
MCC
731 struct mem_ctl_info *mci = to_mci(dev);
732
5926ff50 733 return sprintf(data, "%d\n", mci->ce_mc);
7c9281d7
DT
734}
735
7a623c03
MCC
736static ssize_t mci_ce_noinfo_show(struct device *dev,
737 struct device_attribute *mattr,
738 char *data)
7c9281d7 739{
7a623c03
MCC
740 struct mem_ctl_info *mci = to_mci(dev);
741
079708b9 742 return sprintf(data, "%d\n", mci->ce_noinfo_count);
7c9281d7
DT
743}
744
7a623c03
MCC
745static ssize_t mci_ue_noinfo_show(struct device *dev,
746 struct device_attribute *mattr,
747 char *data)
7c9281d7 748{
7a623c03
MCC
749 struct mem_ctl_info *mci = to_mci(dev);
750
079708b9 751 return sprintf(data, "%d\n", mci->ue_noinfo_count);
7c9281d7
DT
752}
753
7a623c03
MCC
754static ssize_t mci_seconds_show(struct device *dev,
755 struct device_attribute *mattr,
756 char *data)
7c9281d7 757{
7a623c03
MCC
758 struct mem_ctl_info *mci = to_mci(dev);
759
079708b9 760 return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ);
7c9281d7
DT
761}
762
7a623c03
MCC
763static ssize_t mci_ctl_name_show(struct device *dev,
764 struct device_attribute *mattr,
765 char *data)
7c9281d7 766{
7a623c03
MCC
767 struct mem_ctl_info *mci = to_mci(dev);
768
079708b9 769 return sprintf(data, "%s\n", mci->ctl_name);
7c9281d7
DT
770}
771
7a623c03
MCC
772static ssize_t mci_size_mb_show(struct device *dev,
773 struct device_attribute *mattr,
774 char *data)
7c9281d7 775{
7a623c03 776 struct mem_ctl_info *mci = to_mci(dev);
a895bf8b 777 int total_pages = 0, csrow_idx, j;
7c9281d7 778
a895bf8b 779 for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
de3910eb 780 struct csrow_info *csrow = mci->csrows[csrow_idx];
7c9281d7 781
1eef1282
MCC
782 for (j = 0; j < csrow->nr_channels; j++) {
783 struct dimm_info *dimm = csrow->channels[j]->dimm;
3c062276 784
1eef1282 785 total_pages += dimm->nr_pages;
a895bf8b 786 }
7c9281d7
DT
787 }
788
079708b9 789 return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
7c9281d7
DT
790}
791
8ad6c78a
MCC
792static ssize_t mci_max_location_show(struct device *dev,
793 struct device_attribute *mattr,
794 char *data)
795{
796 struct mem_ctl_info *mci = to_mci(dev);
797 int i;
798 char *p = data;
799
800 for (i = 0; i < mci->n_layers; i++) {
801 p += sprintf(p, "%s %d ",
802 edac_layer_name[mci->layers[i].type],
803 mci->layers[i].size - 1);
804 }
805
806 return p - data;
807}
808
452a6bf9
MCC
809#ifdef CONFIG_EDAC_DEBUG
810static ssize_t edac_fake_inject_write(struct file *file,
811 const char __user *data,
812 size_t count, loff_t *ppos)
813{
814 struct device *dev = file->private_data;
815 struct mem_ctl_info *mci = to_mci(dev);
816 static enum hw_event_mc_err_type type;
38ced28b
MCC
817 u16 errcount = mci->fake_inject_count;
818
819 if (!errcount)
820 errcount = 1;
452a6bf9
MCC
821
822 type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED
823 : HW_EVENT_ERR_CORRECTED;
824
825 printk(KERN_DEBUG
38ced28b
MCC
826 "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",
827 errcount,
452a6bf9 828 (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",
38ced28b 829 errcount > 1 ? "s" : "",
452a6bf9
MCC
830 mci->fake_inject_layer[0],
831 mci->fake_inject_layer[1],
832 mci->fake_inject_layer[2]
833 );
38ced28b 834 edac_mc_handle_error(type, mci, errcount, 0, 0, 0,
452a6bf9
MCC
835 mci->fake_inject_layer[0],
836 mci->fake_inject_layer[1],
837 mci->fake_inject_layer[2],
03f7eae8 838 "FAKE ERROR", "for EDAC testing only");
452a6bf9
MCC
839
840 return count;
841}
842
452a6bf9 843static const struct file_operations debug_fake_inject_fops = {
db7312a2 844 .open = simple_open,
452a6bf9
MCC
845 .write = edac_fake_inject_write,
846 .llseek = generic_file_llseek,
847};
848#endif
849
7c9281d7 850/* default Control file */
7a623c03 851DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store);
7c9281d7
DT
852
853/* default Attribute files */
7a623c03
MCC
854DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL);
855DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL);
856DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL);
857DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL);
858DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL);
859DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL);
860DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL);
8ad6c78a 861DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL);
7c9281d7
DT
862
863/* memory scrubber attribute file */
e7100478 864DEVICE_ATTR(sdram_scrub_rate, 0, NULL, NULL);
7c9281d7 865
7a623c03
MCC
866static struct attribute *mci_attrs[] = {
867 &dev_attr_reset_counters.attr,
868 &dev_attr_mc_name.attr,
869 &dev_attr_size_mb.attr,
870 &dev_attr_seconds_since_reset.attr,
871 &dev_attr_ue_noinfo_count.attr,
872 &dev_attr_ce_noinfo_count.attr,
873 &dev_attr_ue_count.attr,
874 &dev_attr_ce_count.attr,
8ad6c78a 875 &dev_attr_max_location.attr,
7c9281d7
DT
876 NULL
877};
878
7a623c03
MCC
879static struct attribute_group mci_attr_grp = {
880 .attrs = mci_attrs,
cc301b3a
MCC
881};
882
7a623c03
MCC
883static const struct attribute_group *mci_attr_groups[] = {
884 &mci_attr_grp,
885 NULL
cc301b3a
MCC
886};
887
de3910eb 888static void mci_attr_release(struct device *dev)
42a8e397 889{
de3910eb
MCC
890 struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
891
956b9ba1 892 edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
de3910eb 893 kfree(mci);
42a8e397
DT
894}
895
7a623c03
MCC
896static struct device_type mci_attr_type = {
897 .groups = mci_attr_groups,
898 .release = mci_attr_release,
899};
8096cfaf 900
452a6bf9 901#ifdef CONFIG_EDAC_DEBUG
e7930ba4
RH
902static struct dentry *edac_debugfs;
903
904int __init edac_debugfs_init(void)
905{
906 edac_debugfs = debugfs_create_dir("edac", NULL);
907 if (IS_ERR(edac_debugfs)) {
908 edac_debugfs = NULL;
909 return -ENOMEM;
910 }
911 return 0;
912}
913
914void __exit edac_debugfs_exit(void)
915{
916 debugfs_remove(edac_debugfs);
917}
918
95285933 919static int edac_create_debug_nodes(struct mem_ctl_info *mci)
452a6bf9
MCC
920{
921 struct dentry *d, *parent;
922 char name[80];
923 int i;
924
e7930ba4
RH
925 if (!edac_debugfs)
926 return -ENODEV;
927
928 d = debugfs_create_dir(mci->dev.kobj.name, edac_debugfs);
452a6bf9
MCC
929 if (!d)
930 return -ENOMEM;
931 parent = d;
932
933 for (i = 0; i < mci->n_layers; i++) {
934 sprintf(name, "fake_inject_%s",
935 edac_layer_name[mci->layers[i].type]);
936 d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent,
937 &mci->fake_inject_layer[i]);
938 if (!d)
939 goto nomem;
940 }
941
942 d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent,
943 &mci->fake_inject_ue);
944 if (!d)
945 goto nomem;
946
38ced28b
MCC
947 d = debugfs_create_u16("fake_inject_count", S_IRUGO | S_IWUSR, parent,
948 &mci->fake_inject_count);
949 if (!d)
950 goto nomem;
951
452a6bf9
MCC
952 d = debugfs_create_file("fake_inject", S_IWUSR, parent,
953 &mci->dev,
954 &debug_fake_inject_fops);
955 if (!d)
956 goto nomem;
957
e7930ba4 958 mci->debugfs = parent;
452a6bf9
MCC
959 return 0;
960nomem:
961 debugfs_remove(mci->debugfs);
962 return -ENOMEM;
963}
964#endif
965
7c9281d7
DT
966/*
967 * Create a new Memory Controller kobject instance,
968 * mc<id> under the 'mc' directory
969 *
970 * Return:
971 * 0 Success
972 * !0 Failure
973 */
974int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
975{
7a623c03 976 int i, err;
7c9281d7 977
de3910eb
MCC
978 /*
979 * The memory controller needs its own bus, in order to avoid
980 * namespace conflicts at /sys/bus/edac.
981 */
88d84ac9
BP
982 mci->bus->name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
983 if (!mci->bus->name)
de3910eb 984 return -ENOMEM;
88d84ac9
BP
985
986 edac_dbg(0, "creating bus %s\n", mci->bus->name);
987
988 err = bus_register(mci->bus);
de3910eb
MCC
989 if (err < 0)
990 return err;
7c9281d7 991
7a623c03 992 /* get the /sys/devices/system/edac subsys reference */
7a623c03
MCC
993 mci->dev.type = &mci_attr_type;
994 device_initialize(&mci->dev);
7c9281d7 995
de3910eb 996 mci->dev.parent = mci_pdev;
88d84ac9 997 mci->dev.bus = mci->bus;
7a623c03
MCC
998 dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
999 dev_set_drvdata(&mci->dev, mci);
1000 pm_runtime_forbid(&mci->dev);
1001
956b9ba1 1002 edac_dbg(0, "creating device %s\n", dev_name(&mci->dev));
7a623c03
MCC
1003 err = device_add(&mci->dev);
1004 if (err < 0) {
3d958823 1005 edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev));
88d84ac9
BP
1006 bus_unregister(mci->bus);
1007 kfree(mci->bus->name);
7a623c03 1008 return err;
42a8e397
DT
1009 }
1010
e7100478
MCC
1011 if (mci->set_sdram_scrub_rate || mci->get_sdram_scrub_rate) {
1012 if (mci->get_sdram_scrub_rate) {
1013 dev_attr_sdram_scrub_rate.attr.mode |= S_IRUGO;
1014 dev_attr_sdram_scrub_rate.show = &mci_sdram_scrub_rate_show;
1015 }
1016 if (mci->set_sdram_scrub_rate) {
1017 dev_attr_sdram_scrub_rate.attr.mode |= S_IWUSR;
1018 dev_attr_sdram_scrub_rate.store = &mci_sdram_scrub_rate_store;
1019 }
1020 err = device_create_file(&mci->dev,
1021 &dev_attr_sdram_scrub_rate);
1022 if (err) {
1023 edac_dbg(1, "failure: create sdram_scrub_rate\n");
1024 goto fail2;
1025 }
1026 }
7a623c03
MCC
1027 /*
1028 * Create the dimm/rank devices
7c9281d7 1029 */
7a623c03 1030 for (i = 0; i < mci->tot_dimms; i++) {
de3910eb 1031 struct dimm_info *dimm = mci->dimms[i];
7a623c03
MCC
1032 /* Only expose populated DIMMs */
1033 if (dimm->nr_pages == 0)
1034 continue;
1035#ifdef CONFIG_EDAC_DEBUG
956b9ba1 1036 edac_dbg(1, "creating dimm%d, located at ", i);
7a623c03
MCC
1037 if (edac_debug_level >= 1) {
1038 int lay;
1039 for (lay = 0; lay < mci->n_layers; lay++)
1040 printk(KERN_CONT "%s %d ",
1041 edac_layer_name[mci->layers[lay].type],
1042 dimm->location[lay]);
1043 printk(KERN_CONT "\n");
7c9281d7 1044 }
7a623c03 1045#endif
19974710
MCC
1046 err = edac_create_dimm_object(mci, dimm, i);
1047 if (err) {
956b9ba1 1048 edac_dbg(1, "failure: create dimm %d obj\n", i);
19974710
MCC
1049 goto fail;
1050 }
7c9281d7
DT
1051 }
1052
19974710 1053#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03
MCC
1054 err = edac_create_csrow_objects(mci);
1055 if (err < 0)
1056 goto fail;
19974710 1057#endif
7a623c03 1058
452a6bf9
MCC
1059#ifdef CONFIG_EDAC_DEBUG
1060 edac_create_debug_nodes(mci);
1061#endif
7c9281d7
DT
1062 return 0;
1063
7a623c03 1064fail:
079708b9 1065 for (i--; i >= 0; i--) {
de3910eb 1066 struct dimm_info *dimm = mci->dimms[i];
7a623c03
MCC
1067 if (dimm->nr_pages == 0)
1068 continue;
44d22e24 1069 device_unregister(&dimm->dev);
7c9281d7 1070 }
e7100478 1071fail2:
44d22e24 1072 device_unregister(&mci->dev);
88d84ac9
BP
1073 bus_unregister(mci->bus);
1074 kfree(mci->bus->name);
7c9281d7
DT
1075 return err;
1076}
1077
1078/*
1079 * remove a Memory Controller instance
1080 */
1081void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
1082{
7a623c03 1083 int i;
7c9281d7 1084
956b9ba1 1085 edac_dbg(0, "\n");
7c9281d7 1086
452a6bf9
MCC
1087#ifdef CONFIG_EDAC_DEBUG
1088 debugfs_remove(mci->debugfs);
1089#endif
19974710 1090#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03 1091 edac_delete_csrow_objects(mci);
19974710 1092#endif
7c9281d7 1093
7a623c03 1094 for (i = 0; i < mci->tot_dimms; i++) {
de3910eb 1095 struct dimm_info *dimm = mci->dimms[i];
7a623c03
MCC
1096 if (dimm->nr_pages == 0)
1097 continue;
956b9ba1 1098 edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev));
44d22e24 1099 device_unregister(&dimm->dev);
6fe1108f 1100 }
7c9281d7 1101}
8096cfaf 1102
7a623c03
MCC
1103void edac_unregister_sysfs(struct mem_ctl_info *mci)
1104{
956b9ba1 1105 edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
44d22e24 1106 device_unregister(&mci->dev);
88d84ac9
BP
1107 bus_unregister(mci->bus);
1108 kfree(mci->bus->name);
7a623c03 1109}
8096cfaf 1110
de3910eb 1111static void mc_attr_release(struct device *dev)
7a623c03 1112{
de3910eb
MCC
1113 /*
1114 * There's no container structure here, as this is just the mci
1115 * parent device, used to create the /sys/devices/mc sysfs node.
1116 * So, there are no attributes on it.
1117 */
956b9ba1 1118 edac_dbg(1, "Releasing device %s\n", dev_name(dev));
de3910eb 1119 kfree(dev);
7a623c03 1120}
8096cfaf 1121
7a623c03
MCC
1122static struct device_type mc_attr_type = {
1123 .release = mc_attr_release,
1124};
8096cfaf 1125/*
7a623c03 1126 * Init/exit code for the module. Basically, creates/removes /sys/class/rc
8096cfaf 1127 */
7a623c03 1128int __init edac_mc_sysfs_init(void)
8096cfaf 1129{
fe5ff8b8 1130 struct bus_type *edac_subsys;
7a623c03 1131 int err;
8096cfaf 1132
fe5ff8b8
KS
1133 /* get the /sys/devices/system/edac subsys reference */
1134 edac_subsys = edac_get_sysfs_subsys();
1135 if (edac_subsys == NULL) {
956b9ba1 1136 edac_dbg(1, "no edac_subsys\n");
2d56b109
DK
1137 err = -EINVAL;
1138 goto out;
8096cfaf
DT
1139 }
1140
de3910eb 1141 mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL);
2d56b109
DK
1142 if (!mci_pdev) {
1143 err = -ENOMEM;
1144 goto out_put_sysfs;
1145 }
de3910eb
MCC
1146
1147 mci_pdev->bus = edac_subsys;
1148 mci_pdev->type = &mc_attr_type;
1149 device_initialize(mci_pdev);
1150 dev_set_name(mci_pdev, "mc");
8096cfaf 1151
de3910eb 1152 err = device_add(mci_pdev);
7a623c03 1153 if (err < 0)
2d56b109 1154 goto out_dev_free;
8096cfaf 1155
956b9ba1 1156 edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
de3910eb 1157
8096cfaf 1158 return 0;
2d56b109
DK
1159
1160 out_dev_free:
1161 kfree(mci_pdev);
1162 out_put_sysfs:
1163 edac_put_sysfs_subsys();
1164 out:
1165 return err;
8096cfaf
DT
1166}
1167
7a623c03 1168void __exit edac_mc_sysfs_exit(void)
8096cfaf 1169{
44d22e24 1170 device_unregister(mci_pdev);
fe5ff8b8 1171 edac_put_sysfs_subsys();
8096cfaf 1172}
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