EDAC: Fix the leak of mci->bus->name when bus_register fails
[deliverable/linux.git] / drivers / edac / edac_mc_sysfs.c
CommitLineData
7c9281d7
DT
1/*
2 * edac_mc kernel module
42a8e397
DT
3 * (C) 2005-2007 Linux Networx (http://lnxi.com)
4 *
7c9281d7
DT
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
42a8e397 8 * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com
7c9281d7 9 *
37e59f87 10 * (c) 2012-2013 - Mauro Carvalho Chehab
7a623c03
MCC
11 * The entire API were re-written, and ported to use struct device
12 *
7c9281d7
DT
13 */
14
7c9281d7 15#include <linux/ctype.h>
5a0e3ad6 16#include <linux/slab.h>
30e1f7a8 17#include <linux/edac.h>
8096cfaf 18#include <linux/bug.h>
7a623c03 19#include <linux/pm_runtime.h>
452a6bf9 20#include <linux/uaccess.h>
7c9281d7 21
20bcb7a8 22#include "edac_core.h"
7c9281d7
DT
23#include "edac_module.h"
24
25/* MC EDAC Controls, setable by module parameter, and sysfs */
4de78c68
DJ
26static int edac_mc_log_ue = 1;
27static int edac_mc_log_ce = 1;
f044091c 28static int edac_mc_panic_on_ue;
4de78c68 29static int edac_mc_poll_msec = 1000;
7c9281d7
DT
30
31/* Getter functions for above */
4de78c68 32int edac_mc_get_log_ue(void)
7c9281d7 33{
4de78c68 34 return edac_mc_log_ue;
7c9281d7
DT
35}
36
4de78c68 37int edac_mc_get_log_ce(void)
7c9281d7 38{
4de78c68 39 return edac_mc_log_ce;
7c9281d7
DT
40}
41
4de78c68 42int edac_mc_get_panic_on_ue(void)
7c9281d7 43{
4de78c68 44 return edac_mc_panic_on_ue;
7c9281d7
DT
45}
46
81d87cb1
DJ
47/* this is temporary */
48int edac_mc_get_poll_msec(void)
49{
4de78c68 50 return edac_mc_poll_msec;
7c9281d7
DT
51}
52
096846e2
AJ
53static int edac_set_poll_msec(const char *val, struct kernel_param *kp)
54{
9da21b15 55 unsigned long l;
096846e2
AJ
56 int ret;
57
58 if (!val)
59 return -EINVAL;
60
9da21b15 61 ret = kstrtoul(val, 0, &l);
c542b53d
JH
62 if (ret)
63 return ret;
9da21b15
BP
64
65 if (l < 1000)
096846e2 66 return -EINVAL;
9da21b15
BP
67
68 *((unsigned long *)kp->arg) = l;
096846e2
AJ
69
70 /* notify edac_mc engine to reset the poll period */
71 edac_mc_reset_delay_period(l);
72
73 return 0;
74}
75
7c9281d7 76/* Parameter declarations for above */
4de78c68
DJ
77module_param(edac_mc_panic_on_ue, int, 0644);
78MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on");
79module_param(edac_mc_log_ue, int, 0644);
80MODULE_PARM_DESC(edac_mc_log_ue,
079708b9 81 "Log uncorrectable error to console: 0=off 1=on");
4de78c68
DJ
82module_param(edac_mc_log_ce, int, 0644);
83MODULE_PARM_DESC(edac_mc_log_ce,
079708b9 84 "Log correctable error to console: 0=off 1=on");
096846e2
AJ
85module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int,
86 &edac_mc_poll_msec, 0644);
4de78c68 87MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds");
7c9281d7 88
de3910eb 89static struct device *mci_pdev;
7a623c03 90
7c9281d7
DT
91/*
92 * various constants for Memory Controllers
93 */
8b7719e0 94static const char * const mem_types[] = {
7c9281d7
DT
95 [MEM_EMPTY] = "Empty",
96 [MEM_RESERVED] = "Reserved",
97 [MEM_UNKNOWN] = "Unknown",
98 [MEM_FPM] = "FPM",
99 [MEM_EDO] = "EDO",
100 [MEM_BEDO] = "BEDO",
101 [MEM_SDR] = "Unbuffered-SDR",
102 [MEM_RDR] = "Registered-SDR",
103 [MEM_DDR] = "Unbuffered-DDR",
104 [MEM_RDDR] = "Registered-DDR",
1a9b85e6
DJ
105 [MEM_RMBS] = "RMBS",
106 [MEM_DDR2] = "Unbuffered-DDR2",
107 [MEM_FB_DDR2] = "FullyBuffered-DDR2",
1d5f726c 108 [MEM_RDDR2] = "Registered-DDR2",
b1cfebc9
YS
109 [MEM_XDR] = "XDR",
110 [MEM_DDR3] = "Unbuffered-DDR3",
7b827835
AR
111 [MEM_RDDR3] = "Registered-DDR3",
112 [MEM_DDR4] = "Unbuffered-DDR4",
113 [MEM_RDDR4] = "Registered-DDR4"
7c9281d7
DT
114};
115
8b7719e0 116static const char * const dev_types[] = {
7c9281d7
DT
117 [DEV_UNKNOWN] = "Unknown",
118 [DEV_X1] = "x1",
119 [DEV_X2] = "x2",
120 [DEV_X4] = "x4",
121 [DEV_X8] = "x8",
122 [DEV_X16] = "x16",
123 [DEV_X32] = "x32",
124 [DEV_X64] = "x64"
125};
126
8b7719e0 127static const char * const edac_caps[] = {
7c9281d7
DT
128 [EDAC_UNKNOWN] = "Unknown",
129 [EDAC_NONE] = "None",
130 [EDAC_RESERVED] = "Reserved",
131 [EDAC_PARITY] = "PARITY",
132 [EDAC_EC] = "EC",
133 [EDAC_SECDED] = "SECDED",
134 [EDAC_S2ECD2ED] = "S2ECD2ED",
135 [EDAC_S4ECD4ED] = "S4ECD4ED",
136 [EDAC_S8ECD8ED] = "S8ECD8ED",
137 [EDAC_S16ECD16ED] = "S16ECD16ED"
138};
139
19974710 140#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03
MCC
141/*
142 * EDAC sysfs CSROW data structures and methods
143 */
144
145#define to_csrow(k) container_of(k, struct csrow_info, dev)
146
147/*
148 * We need it to avoid namespace conflicts between the legacy API
149 * and the per-dimm/per-rank one
7c9281d7 150 */
7a623c03 151#define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
fbe2d361 152 static struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
7a623c03
MCC
153
154struct dev_ch_attribute {
155 struct device_attribute attr;
156 int channel;
157};
158
159#define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \
160 struct dev_ch_attribute dev_attr_legacy_##_name = \
161 { __ATTR(_name, _mode, _show, _store), (_var) }
162
163#define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel)
7c9281d7
DT
164
165/* Set of more default csrow<id> attribute show/store functions */
7a623c03
MCC
166static ssize_t csrow_ue_count_show(struct device *dev,
167 struct device_attribute *mattr, char *data)
7c9281d7 168{
7a623c03
MCC
169 struct csrow_info *csrow = to_csrow(dev);
170
079708b9 171 return sprintf(data, "%u\n", csrow->ue_count);
7c9281d7
DT
172}
173
7a623c03
MCC
174static ssize_t csrow_ce_count_show(struct device *dev,
175 struct device_attribute *mattr, char *data)
7c9281d7 176{
7a623c03
MCC
177 struct csrow_info *csrow = to_csrow(dev);
178
079708b9 179 return sprintf(data, "%u\n", csrow->ce_count);
7c9281d7
DT
180}
181
7a623c03
MCC
182static ssize_t csrow_size_show(struct device *dev,
183 struct device_attribute *mattr, char *data)
7c9281d7 184{
7a623c03 185 struct csrow_info *csrow = to_csrow(dev);
a895bf8b
MCC
186 int i;
187 u32 nr_pages = 0;
188
189 for (i = 0; i < csrow->nr_channels; i++)
de3910eb 190 nr_pages += csrow->channels[i]->dimm->nr_pages;
a895bf8b 191 return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
7c9281d7
DT
192}
193
7a623c03
MCC
194static ssize_t csrow_mem_type_show(struct device *dev,
195 struct device_attribute *mattr, char *data)
7c9281d7 196{
7a623c03
MCC
197 struct csrow_info *csrow = to_csrow(dev);
198
de3910eb 199 return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]);
7c9281d7
DT
200}
201
7a623c03
MCC
202static ssize_t csrow_dev_type_show(struct device *dev,
203 struct device_attribute *mattr, char *data)
7c9281d7 204{
7a623c03
MCC
205 struct csrow_info *csrow = to_csrow(dev);
206
de3910eb 207 return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]);
7c9281d7
DT
208}
209
7a623c03
MCC
210static ssize_t csrow_edac_mode_show(struct device *dev,
211 struct device_attribute *mattr,
212 char *data)
7c9281d7 213{
7a623c03
MCC
214 struct csrow_info *csrow = to_csrow(dev);
215
de3910eb 216 return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]);
7c9281d7
DT
217}
218
219/* show/store functions for DIMM Label attributes */
7a623c03
MCC
220static ssize_t channel_dimm_label_show(struct device *dev,
221 struct device_attribute *mattr,
222 char *data)
7c9281d7 223{
7a623c03
MCC
224 struct csrow_info *csrow = to_csrow(dev);
225 unsigned chan = to_channel(mattr);
de3910eb 226 struct rank_info *rank = csrow->channels[chan];
7a623c03 227
124682c7 228 /* if field has not been initialized, there is nothing to send */
7a623c03 229 if (!rank->dimm->label[0])
124682c7
AJ
230 return 0;
231
232 return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n",
7a623c03 233 rank->dimm->label);
7c9281d7
DT
234}
235
7a623c03
MCC
236static ssize_t channel_dimm_label_store(struct device *dev,
237 struct device_attribute *mattr,
238 const char *data, size_t count)
7c9281d7 239{
7a623c03
MCC
240 struct csrow_info *csrow = to_csrow(dev);
241 unsigned chan = to_channel(mattr);
de3910eb 242 struct rank_info *rank = csrow->channels[chan];
7a623c03 243
7c9281d7
DT
244 ssize_t max_size = 0;
245
079708b9 246 max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
7a623c03
MCC
247 strncpy(rank->dimm->label, data, max_size);
248 rank->dimm->label[max_size] = '\0';
7c9281d7
DT
249
250 return max_size;
251}
252
253/* show function for dynamic chX_ce_count attribute */
7a623c03
MCC
254static ssize_t channel_ce_count_show(struct device *dev,
255 struct device_attribute *mattr, char *data)
7c9281d7 256{
7a623c03
MCC
257 struct csrow_info *csrow = to_csrow(dev);
258 unsigned chan = to_channel(mattr);
de3910eb 259 struct rank_info *rank = csrow->channels[chan];
7a623c03
MCC
260
261 return sprintf(data, "%u\n", rank->ce_count);
7c9281d7
DT
262}
263
7a623c03
MCC
264/* cwrow<id>/attribute files */
265DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL);
266DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL);
267DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL);
268DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL);
269DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL);
270DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL);
7c9281d7 271
7a623c03
MCC
272/* default attributes of the CSROW<id> object */
273static struct attribute *csrow_attrs[] = {
274 &dev_attr_legacy_dev_type.attr,
275 &dev_attr_legacy_mem_type.attr,
276 &dev_attr_legacy_edac_mode.attr,
277 &dev_attr_legacy_size_mb.attr,
278 &dev_attr_legacy_ue_count.attr,
279 &dev_attr_legacy_ce_count.attr,
280 NULL,
281};
7c9281d7 282
7a623c03
MCC
283static struct attribute_group csrow_attr_grp = {
284 .attrs = csrow_attrs,
285};
7c9281d7 286
7a623c03
MCC
287static const struct attribute_group *csrow_attr_groups[] = {
288 &csrow_attr_grp,
289 NULL
290};
7c9281d7 291
de3910eb 292static void csrow_attr_release(struct device *dev)
7c9281d7 293{
de3910eb
MCC
294 struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
295
956b9ba1 296 edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
de3910eb 297 kfree(csrow);
7c9281d7
DT
298}
299
7a623c03
MCC
300static struct device_type csrow_attr_type = {
301 .groups = csrow_attr_groups,
302 .release = csrow_attr_release,
7c9281d7
DT
303};
304
7a623c03
MCC
305/*
306 * possible dynamic channel DIMM Label attribute files
307 *
308 */
7c9281d7 309
7a623c03 310#define EDAC_NR_CHANNELS 6
7c9281d7 311
7a623c03 312DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 313 channel_dimm_label_show, channel_dimm_label_store, 0);
7a623c03 314DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 315 channel_dimm_label_show, channel_dimm_label_store, 1);
7a623c03 316DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 317 channel_dimm_label_show, channel_dimm_label_store, 2);
7a623c03 318DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 319 channel_dimm_label_show, channel_dimm_label_store, 3);
7a623c03 320DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 321 channel_dimm_label_show, channel_dimm_label_store, 4);
7a623c03 322DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 323 channel_dimm_label_show, channel_dimm_label_store, 5);
7c9281d7
DT
324
325/* Total possible dynamic DIMM Label attribute file table */
7a623c03
MCC
326static struct device_attribute *dynamic_csrow_dimm_attr[] = {
327 &dev_attr_legacy_ch0_dimm_label.attr,
328 &dev_attr_legacy_ch1_dimm_label.attr,
329 &dev_attr_legacy_ch2_dimm_label.attr,
330 &dev_attr_legacy_ch3_dimm_label.attr,
331 &dev_attr_legacy_ch4_dimm_label.attr,
332 &dev_attr_legacy_ch5_dimm_label.attr
7c9281d7
DT
333};
334
335/* possible dynamic channel ce_count attribute files */
c8c64d16 336DEVICE_CHANNEL(ch0_ce_count, S_IRUGO,
7a623c03 337 channel_ce_count_show, NULL, 0);
c8c64d16 338DEVICE_CHANNEL(ch1_ce_count, S_IRUGO,
7a623c03 339 channel_ce_count_show, NULL, 1);
c8c64d16 340DEVICE_CHANNEL(ch2_ce_count, S_IRUGO,
7a623c03 341 channel_ce_count_show, NULL, 2);
c8c64d16 342DEVICE_CHANNEL(ch3_ce_count, S_IRUGO,
7a623c03 343 channel_ce_count_show, NULL, 3);
c8c64d16 344DEVICE_CHANNEL(ch4_ce_count, S_IRUGO,
7a623c03 345 channel_ce_count_show, NULL, 4);
c8c64d16 346DEVICE_CHANNEL(ch5_ce_count, S_IRUGO,
7a623c03 347 channel_ce_count_show, NULL, 5);
7c9281d7
DT
348
349/* Total possible dynamic ce_count attribute file table */
7a623c03
MCC
350static struct device_attribute *dynamic_csrow_ce_count_attr[] = {
351 &dev_attr_legacy_ch0_ce_count.attr,
352 &dev_attr_legacy_ch1_ce_count.attr,
353 &dev_attr_legacy_ch2_ce_count.attr,
354 &dev_attr_legacy_ch3_ce_count.attr,
355 &dev_attr_legacy_ch4_ce_count.attr,
356 &dev_attr_legacy_ch5_ce_count.attr
7c9281d7
DT
357};
358
e39f4ea9
MCC
359static inline int nr_pages_per_csrow(struct csrow_info *csrow)
360{
361 int chan, nr_pages = 0;
362
363 for (chan = 0; chan < csrow->nr_channels; chan++)
de3910eb 364 nr_pages += csrow->channels[chan]->dimm->nr_pages;
e39f4ea9
MCC
365
366 return nr_pages;
367}
368
7a623c03
MCC
369/* Create a CSROW object under specifed edac_mc_device */
370static int edac_create_csrow_object(struct mem_ctl_info *mci,
371 struct csrow_info *csrow, int index)
7c9281d7 372{
7a623c03 373 int err, chan;
7c9281d7 374
50043e25 375 if (csrow->nr_channels > EDAC_NR_CHANNELS)
7a623c03 376 return -ENODEV;
7c9281d7 377
7a623c03 378 csrow->dev.type = &csrow_attr_type;
88d84ac9 379 csrow->dev.bus = mci->bus;
7a623c03
MCC
380 device_initialize(&csrow->dev);
381 csrow->dev.parent = &mci->dev;
921a6899 382 csrow->mci = mci;
7a623c03
MCC
383 dev_set_name(&csrow->dev, "csrow%d", index);
384 dev_set_drvdata(&csrow->dev, csrow);
7c9281d7 385
956b9ba1
JP
386 edac_dbg(0, "creating (virtual) csrow node %s\n",
387 dev_name(&csrow->dev));
7c9281d7 388
7a623c03
MCC
389 err = device_add(&csrow->dev);
390 if (err < 0)
391 return err;
7c9281d7 392
7a623c03 393 for (chan = 0; chan < csrow->nr_channels; chan++) {
e39f4ea9 394 /* Only expose populated DIMMs */
de3910eb 395 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 396 continue;
7a623c03
MCC
397 err = device_create_file(&csrow->dev,
398 dynamic_csrow_dimm_attr[chan]);
399 if (err < 0)
400 goto error;
401 err = device_create_file(&csrow->dev,
402 dynamic_csrow_ce_count_attr[chan]);
403 if (err < 0) {
404 device_remove_file(&csrow->dev,
405 dynamic_csrow_dimm_attr[chan]);
406 goto error;
407 }
408 }
8096cfaf 409
7a623c03 410 return 0;
8096cfaf 411
7a623c03
MCC
412error:
413 for (--chan; chan >= 0; chan--) {
414 device_remove_file(&csrow->dev,
415 dynamic_csrow_dimm_attr[chan]);
416 device_remove_file(&csrow->dev,
417 dynamic_csrow_ce_count_attr[chan]);
418 }
419 put_device(&csrow->dev);
7c9281d7 420
7a623c03
MCC
421 return err;
422}
7c9281d7
DT
423
424/* Create a CSROW object under specifed edac_mc_device */
7a623c03 425static int edac_create_csrow_objects(struct mem_ctl_info *mci)
7c9281d7 426{
7a623c03
MCC
427 int err, i, chan;
428 struct csrow_info *csrow;
7c9281d7 429
7a623c03 430 for (i = 0; i < mci->nr_csrows; i++) {
de3910eb 431 csrow = mci->csrows[i];
e39f4ea9
MCC
432 if (!nr_pages_per_csrow(csrow))
433 continue;
de3910eb 434 err = edac_create_csrow_object(mci, mci->csrows[i], i);
3d958823
MCC
435 if (err < 0) {
436 edac_dbg(1,
437 "failure: create csrow objects for csrow %d\n",
438 i);
7a623c03 439 goto error;
3d958823 440 }
7a623c03
MCC
441 }
442 return 0;
8096cfaf 443
7a623c03
MCC
444error:
445 for (--i; i >= 0; i--) {
de3910eb 446 csrow = mci->csrows[i];
e39f4ea9
MCC
447 if (!nr_pages_per_csrow(csrow))
448 continue;
7a623c03 449 for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
de3910eb 450 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 451 continue;
7a623c03
MCC
452 device_remove_file(&csrow->dev,
453 dynamic_csrow_dimm_attr[chan]);
454 device_remove_file(&csrow->dev,
455 dynamic_csrow_ce_count_attr[chan]);
456 }
de3910eb 457 put_device(&mci->csrows[i]->dev);
8096cfaf 458 }
7c9281d7 459
7a623c03
MCC
460 return err;
461}
8096cfaf 462
7a623c03
MCC
463static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
464{
465 int i, chan;
466 struct csrow_info *csrow;
8096cfaf 467
7a623c03 468 for (i = mci->nr_csrows - 1; i >= 0; i--) {
de3910eb 469 csrow = mci->csrows[i];
e39f4ea9
MCC
470 if (!nr_pages_per_csrow(csrow))
471 continue;
7a623c03 472 for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
de3910eb 473 if (!csrow->channels[chan]->dimm->nr_pages)
e39f4ea9 474 continue;
956b9ba1
JP
475 edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n",
476 i, chan);
7a623c03
MCC
477 device_remove_file(&csrow->dev,
478 dynamic_csrow_dimm_attr[chan]);
479 device_remove_file(&csrow->dev,
480 dynamic_csrow_ce_count_attr[chan]);
7c9281d7 481 }
44d22e24 482 device_unregister(&mci->csrows[i]->dev);
7c9281d7 483 }
7c9281d7 484}
19974710
MCC
485#endif
486
487/*
488 * Per-dimm (or per-rank) devices
489 */
490
491#define to_dimm(k) container_of(k, struct dimm_info, dev)
492
493/* show/store functions for DIMM Label attributes */
494static ssize_t dimmdev_location_show(struct device *dev,
495 struct device_attribute *mattr, char *data)
496{
497 struct dimm_info *dimm = to_dimm(dev);
19974710 498
6e84d359 499 return edac_dimm_info_location(dimm, data, PAGE_SIZE);
19974710
MCC
500}
501
502static ssize_t dimmdev_label_show(struct device *dev,
503 struct device_attribute *mattr, char *data)
504{
505 struct dimm_info *dimm = to_dimm(dev);
506
507 /* if field has not been initialized, there is nothing to send */
508 if (!dimm->label[0])
509 return 0;
510
511 return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label);
512}
513
514static ssize_t dimmdev_label_store(struct device *dev,
515 struct device_attribute *mattr,
516 const char *data,
517 size_t count)
518{
519 struct dimm_info *dimm = to_dimm(dev);
520
521 ssize_t max_size = 0;
522
523 max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
524 strncpy(dimm->label, data, max_size);
525 dimm->label[max_size] = '\0';
526
527 return max_size;
528}
529
530static ssize_t dimmdev_size_show(struct device *dev,
531 struct device_attribute *mattr, char *data)
532{
533 struct dimm_info *dimm = to_dimm(dev);
534
535 return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages));
536}
537
538static ssize_t dimmdev_mem_type_show(struct device *dev,
539 struct device_attribute *mattr, char *data)
540{
541 struct dimm_info *dimm = to_dimm(dev);
542
543 return sprintf(data, "%s\n", mem_types[dimm->mtype]);
544}
545
546static ssize_t dimmdev_dev_type_show(struct device *dev,
547 struct device_attribute *mattr, char *data)
548{
549 struct dimm_info *dimm = to_dimm(dev);
550
551 return sprintf(data, "%s\n", dev_types[dimm->dtype]);
552}
553
554static ssize_t dimmdev_edac_mode_show(struct device *dev,
555 struct device_attribute *mattr,
556 char *data)
557{
558 struct dimm_info *dimm = to_dimm(dev);
559
560 return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]);
561}
562
563/* dimm/rank attribute files */
564static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR,
565 dimmdev_label_show, dimmdev_label_store);
566static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL);
567static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL);
568static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL);
569static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL);
570static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL);
571
572/* attributes of the dimm<id>/rank<id> object */
573static struct attribute *dimm_attrs[] = {
574 &dev_attr_dimm_label.attr,
575 &dev_attr_dimm_location.attr,
576 &dev_attr_size.attr,
577 &dev_attr_dimm_mem_type.attr,
578 &dev_attr_dimm_dev_type.attr,
579 &dev_attr_dimm_edac_mode.attr,
580 NULL,
581};
582
583static struct attribute_group dimm_attr_grp = {
584 .attrs = dimm_attrs,
585};
586
587static const struct attribute_group *dimm_attr_groups[] = {
588 &dimm_attr_grp,
589 NULL
590};
591
de3910eb 592static void dimm_attr_release(struct device *dev)
19974710 593{
de3910eb
MCC
594 struct dimm_info *dimm = container_of(dev, struct dimm_info, dev);
595
956b9ba1 596 edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev));
de3910eb 597 kfree(dimm);
19974710
MCC
598}
599
600static struct device_type dimm_attr_type = {
601 .groups = dimm_attr_groups,
602 .release = dimm_attr_release,
603};
604
605/* Create a DIMM object under specifed memory controller device */
606static int edac_create_dimm_object(struct mem_ctl_info *mci,
607 struct dimm_info *dimm,
608 int index)
609{
610 int err;
611 dimm->mci = mci;
612
613 dimm->dev.type = &dimm_attr_type;
88d84ac9 614 dimm->dev.bus = mci->bus;
19974710
MCC
615 device_initialize(&dimm->dev);
616
617 dimm->dev.parent = &mci->dev;
9713faec 618 if (mci->csbased)
19974710
MCC
619 dev_set_name(&dimm->dev, "rank%d", index);
620 else
621 dev_set_name(&dimm->dev, "dimm%d", index);
622 dev_set_drvdata(&dimm->dev, dimm);
623 pm_runtime_forbid(&mci->dev);
624
625 err = device_add(&dimm->dev);
626
956b9ba1 627 edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev));
19974710
MCC
628
629 return err;
630}
7c9281d7 631
7a623c03
MCC
632/*
633 * Memory controller device
634 */
635
636#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
7c9281d7 637
7a623c03
MCC
638static ssize_t mci_reset_counters_store(struct device *dev,
639 struct device_attribute *mattr,
079708b9 640 const char *data, size_t count)
7c9281d7 641{
7a623c03
MCC
642 struct mem_ctl_info *mci = to_mci(dev);
643 int cnt, row, chan, i;
5926ff50
MCC
644 mci->ue_mc = 0;
645 mci->ce_mc = 0;
7a623c03
MCC
646 mci->ue_noinfo_count = 0;
647 mci->ce_noinfo_count = 0;
7c9281d7
DT
648
649 for (row = 0; row < mci->nr_csrows; row++) {
de3910eb 650 struct csrow_info *ri = mci->csrows[row];
7c9281d7
DT
651
652 ri->ue_count = 0;
653 ri->ce_count = 0;
654
655 for (chan = 0; chan < ri->nr_channels; chan++)
de3910eb 656 ri->channels[chan]->ce_count = 0;
7c9281d7
DT
657 }
658
7a623c03
MCC
659 cnt = 1;
660 for (i = 0; i < mci->n_layers; i++) {
661 cnt *= mci->layers[i].size;
662 memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32));
663 memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32));
664 }
665
7c9281d7
DT
666 mci->start_time = jiffies;
667 return count;
668}
669
39094443
BP
670/* Memory scrubbing interface:
671 *
672 * A MC driver can limit the scrubbing bandwidth based on the CPU type.
673 * Therefore, ->set_sdram_scrub_rate should be made to return the actual
674 * bandwidth that is accepted or 0 when scrubbing is to be disabled.
675 *
676 * Negative value still means that an error has occurred while setting
677 * the scrub rate.
678 */
7a623c03
MCC
679static ssize_t mci_sdram_scrub_rate_store(struct device *dev,
680 struct device_attribute *mattr,
eba042a8 681 const char *data, size_t count)
7c9281d7 682{
7a623c03 683 struct mem_ctl_info *mci = to_mci(dev);
eba042a8 684 unsigned long bandwidth = 0;
39094443 685 int new_bw = 0;
7c9281d7 686
c7f62fc8 687 if (kstrtoul(data, 10, &bandwidth) < 0)
eba042a8 688 return -EINVAL;
7c9281d7 689
39094443 690 new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
4949603a
MT
691 if (new_bw < 0) {
692 edac_printk(KERN_WARNING, EDAC_MC,
693 "Error setting scrub rate to: %lu\n", bandwidth);
694 return -EINVAL;
7c9281d7 695 }
39094443 696
4949603a 697 return count;
7c9281d7
DT
698}
699
39094443
BP
700/*
701 * ->get_sdram_scrub_rate() return value semantics same as above.
702 */
7a623c03
MCC
703static ssize_t mci_sdram_scrub_rate_show(struct device *dev,
704 struct device_attribute *mattr,
705 char *data)
7c9281d7 706{
7a623c03 707 struct mem_ctl_info *mci = to_mci(dev);
39094443 708 int bandwidth = 0;
eba042a8 709
39094443
BP
710 bandwidth = mci->get_sdram_scrub_rate(mci);
711 if (bandwidth < 0) {
eba042a8 712 edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
39094443 713 return bandwidth;
7c9281d7 714 }
39094443 715
39094443 716 return sprintf(data, "%d\n", bandwidth);
7c9281d7
DT
717}
718
719/* default attribute files for the MCI object */
7a623c03
MCC
720static ssize_t mci_ue_count_show(struct device *dev,
721 struct device_attribute *mattr,
722 char *data)
7c9281d7 723{
7a623c03
MCC
724 struct mem_ctl_info *mci = to_mci(dev);
725
5926ff50 726 return sprintf(data, "%d\n", mci->ue_mc);
7c9281d7
DT
727}
728
7a623c03
MCC
729static ssize_t mci_ce_count_show(struct device *dev,
730 struct device_attribute *mattr,
731 char *data)
7c9281d7 732{
7a623c03
MCC
733 struct mem_ctl_info *mci = to_mci(dev);
734
5926ff50 735 return sprintf(data, "%d\n", mci->ce_mc);
7c9281d7
DT
736}
737
7a623c03
MCC
738static ssize_t mci_ce_noinfo_show(struct device *dev,
739 struct device_attribute *mattr,
740 char *data)
7c9281d7 741{
7a623c03
MCC
742 struct mem_ctl_info *mci = to_mci(dev);
743
079708b9 744 return sprintf(data, "%d\n", mci->ce_noinfo_count);
7c9281d7
DT
745}
746
7a623c03
MCC
747static ssize_t mci_ue_noinfo_show(struct device *dev,
748 struct device_attribute *mattr,
749 char *data)
7c9281d7 750{
7a623c03
MCC
751 struct mem_ctl_info *mci = to_mci(dev);
752
079708b9 753 return sprintf(data, "%d\n", mci->ue_noinfo_count);
7c9281d7
DT
754}
755
7a623c03
MCC
756static ssize_t mci_seconds_show(struct device *dev,
757 struct device_attribute *mattr,
758 char *data)
7c9281d7 759{
7a623c03
MCC
760 struct mem_ctl_info *mci = to_mci(dev);
761
079708b9 762 return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ);
7c9281d7
DT
763}
764
7a623c03
MCC
765static ssize_t mci_ctl_name_show(struct device *dev,
766 struct device_attribute *mattr,
767 char *data)
7c9281d7 768{
7a623c03
MCC
769 struct mem_ctl_info *mci = to_mci(dev);
770
079708b9 771 return sprintf(data, "%s\n", mci->ctl_name);
7c9281d7
DT
772}
773
7a623c03
MCC
774static ssize_t mci_size_mb_show(struct device *dev,
775 struct device_attribute *mattr,
776 char *data)
7c9281d7 777{
7a623c03 778 struct mem_ctl_info *mci = to_mci(dev);
a895bf8b 779 int total_pages = 0, csrow_idx, j;
7c9281d7 780
a895bf8b 781 for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
de3910eb 782 struct csrow_info *csrow = mci->csrows[csrow_idx];
7c9281d7 783
1eef1282
MCC
784 for (j = 0; j < csrow->nr_channels; j++) {
785 struct dimm_info *dimm = csrow->channels[j]->dimm;
3c062276 786
1eef1282 787 total_pages += dimm->nr_pages;
a895bf8b 788 }
7c9281d7
DT
789 }
790
079708b9 791 return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
7c9281d7
DT
792}
793
8ad6c78a
MCC
794static ssize_t mci_max_location_show(struct device *dev,
795 struct device_attribute *mattr,
796 char *data)
797{
798 struct mem_ctl_info *mci = to_mci(dev);
799 int i;
800 char *p = data;
801
802 for (i = 0; i < mci->n_layers; i++) {
803 p += sprintf(p, "%s %d ",
804 edac_layer_name[mci->layers[i].type],
805 mci->layers[i].size - 1);
806 }
807
808 return p - data;
809}
810
452a6bf9
MCC
811#ifdef CONFIG_EDAC_DEBUG
812static ssize_t edac_fake_inject_write(struct file *file,
813 const char __user *data,
814 size_t count, loff_t *ppos)
815{
816 struct device *dev = file->private_data;
817 struct mem_ctl_info *mci = to_mci(dev);
818 static enum hw_event_mc_err_type type;
38ced28b
MCC
819 u16 errcount = mci->fake_inject_count;
820
821 if (!errcount)
822 errcount = 1;
452a6bf9
MCC
823
824 type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED
825 : HW_EVENT_ERR_CORRECTED;
826
827 printk(KERN_DEBUG
38ced28b
MCC
828 "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",
829 errcount,
452a6bf9 830 (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",
38ced28b 831 errcount > 1 ? "s" : "",
452a6bf9
MCC
832 mci->fake_inject_layer[0],
833 mci->fake_inject_layer[1],
834 mci->fake_inject_layer[2]
835 );
38ced28b 836 edac_mc_handle_error(type, mci, errcount, 0, 0, 0,
452a6bf9
MCC
837 mci->fake_inject_layer[0],
838 mci->fake_inject_layer[1],
839 mci->fake_inject_layer[2],
03f7eae8 840 "FAKE ERROR", "for EDAC testing only");
452a6bf9
MCC
841
842 return count;
843}
844
452a6bf9 845static const struct file_operations debug_fake_inject_fops = {
db7312a2 846 .open = simple_open,
452a6bf9
MCC
847 .write = edac_fake_inject_write,
848 .llseek = generic_file_llseek,
849};
850#endif
851
7c9281d7 852/* default Control file */
7a623c03 853DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store);
7c9281d7
DT
854
855/* default Attribute files */
7a623c03
MCC
856DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL);
857DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL);
858DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL);
859DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL);
860DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL);
861DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL);
862DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL);
8ad6c78a 863DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL);
7c9281d7
DT
864
865/* memory scrubber attribute file */
e7100478 866DEVICE_ATTR(sdram_scrub_rate, 0, NULL, NULL);
7c9281d7 867
7a623c03
MCC
868static struct attribute *mci_attrs[] = {
869 &dev_attr_reset_counters.attr,
870 &dev_attr_mc_name.attr,
871 &dev_attr_size_mb.attr,
872 &dev_attr_seconds_since_reset.attr,
873 &dev_attr_ue_noinfo_count.attr,
874 &dev_attr_ce_noinfo_count.attr,
875 &dev_attr_ue_count.attr,
876 &dev_attr_ce_count.attr,
8ad6c78a 877 &dev_attr_max_location.attr,
7c9281d7
DT
878 NULL
879};
880
7a623c03
MCC
881static struct attribute_group mci_attr_grp = {
882 .attrs = mci_attrs,
cc301b3a
MCC
883};
884
7a623c03
MCC
885static const struct attribute_group *mci_attr_groups[] = {
886 &mci_attr_grp,
887 NULL
cc301b3a
MCC
888};
889
de3910eb 890static void mci_attr_release(struct device *dev)
42a8e397 891{
de3910eb
MCC
892 struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
893
956b9ba1 894 edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
de3910eb 895 kfree(mci);
42a8e397
DT
896}
897
7a623c03
MCC
898static struct device_type mci_attr_type = {
899 .groups = mci_attr_groups,
900 .release = mci_attr_release,
901};
8096cfaf 902
452a6bf9 903#ifdef CONFIG_EDAC_DEBUG
e7930ba4
RH
904static struct dentry *edac_debugfs;
905
906int __init edac_debugfs_init(void)
907{
908 edac_debugfs = debugfs_create_dir("edac", NULL);
909 if (IS_ERR(edac_debugfs)) {
910 edac_debugfs = NULL;
911 return -ENOMEM;
912 }
913 return 0;
914}
915
916void __exit edac_debugfs_exit(void)
917{
918 debugfs_remove(edac_debugfs);
919}
920
95285933 921static int edac_create_debug_nodes(struct mem_ctl_info *mci)
452a6bf9
MCC
922{
923 struct dentry *d, *parent;
924 char name[80];
925 int i;
926
e7930ba4
RH
927 if (!edac_debugfs)
928 return -ENODEV;
929
930 d = debugfs_create_dir(mci->dev.kobj.name, edac_debugfs);
452a6bf9
MCC
931 if (!d)
932 return -ENOMEM;
933 parent = d;
934
935 for (i = 0; i < mci->n_layers; i++) {
936 sprintf(name, "fake_inject_%s",
937 edac_layer_name[mci->layers[i].type]);
938 d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent,
939 &mci->fake_inject_layer[i]);
940 if (!d)
941 goto nomem;
942 }
943
944 d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent,
945 &mci->fake_inject_ue);
946 if (!d)
947 goto nomem;
948
38ced28b
MCC
949 d = debugfs_create_u16("fake_inject_count", S_IRUGO | S_IWUSR, parent,
950 &mci->fake_inject_count);
951 if (!d)
952 goto nomem;
953
452a6bf9
MCC
954 d = debugfs_create_file("fake_inject", S_IWUSR, parent,
955 &mci->dev,
956 &debug_fake_inject_fops);
957 if (!d)
958 goto nomem;
959
e7930ba4 960 mci->debugfs = parent;
452a6bf9
MCC
961 return 0;
962nomem:
963 debugfs_remove(mci->debugfs);
964 return -ENOMEM;
965}
966#endif
967
7c9281d7
DT
968/*
969 * Create a new Memory Controller kobject instance,
970 * mc<id> under the 'mc' directory
971 *
972 * Return:
973 * 0 Success
974 * !0 Failure
975 */
976int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
977{
7a623c03 978 int i, err;
7c9281d7 979
de3910eb
MCC
980 /*
981 * The memory controller needs its own bus, in order to avoid
982 * namespace conflicts at /sys/bus/edac.
983 */
88d84ac9
BP
984 mci->bus->name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
985 if (!mci->bus->name)
de3910eb 986 return -ENOMEM;
88d84ac9
BP
987
988 edac_dbg(0, "creating bus %s\n", mci->bus->name);
989
990 err = bus_register(mci->bus);
de3910eb 991 if (err < 0)
1bf1950c 992 goto fail_free_name;
7c9281d7 993
7a623c03 994 /* get the /sys/devices/system/edac subsys reference */
7a623c03
MCC
995 mci->dev.type = &mci_attr_type;
996 device_initialize(&mci->dev);
7c9281d7 997
de3910eb 998 mci->dev.parent = mci_pdev;
88d84ac9 999 mci->dev.bus = mci->bus;
7a623c03
MCC
1000 dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
1001 dev_set_drvdata(&mci->dev, mci);
1002 pm_runtime_forbid(&mci->dev);
1003
956b9ba1 1004 edac_dbg(0, "creating device %s\n", dev_name(&mci->dev));
7a623c03
MCC
1005 err = device_add(&mci->dev);
1006 if (err < 0) {
3d958823 1007 edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev));
1bf1950c 1008 goto fail_unregister_bus;
42a8e397
DT
1009 }
1010
e7100478
MCC
1011 if (mci->set_sdram_scrub_rate || mci->get_sdram_scrub_rate) {
1012 if (mci->get_sdram_scrub_rate) {
1013 dev_attr_sdram_scrub_rate.attr.mode |= S_IRUGO;
1014 dev_attr_sdram_scrub_rate.show = &mci_sdram_scrub_rate_show;
1015 }
1bf1950c 1016
e7100478
MCC
1017 if (mci->set_sdram_scrub_rate) {
1018 dev_attr_sdram_scrub_rate.attr.mode |= S_IWUSR;
1019 dev_attr_sdram_scrub_rate.store = &mci_sdram_scrub_rate_store;
1020 }
1bf1950c
JM
1021
1022 err = device_create_file(&mci->dev, &dev_attr_sdram_scrub_rate);
e7100478
MCC
1023 if (err) {
1024 edac_dbg(1, "failure: create sdram_scrub_rate\n");
1bf1950c 1025 goto fail_unregister_dev;
e7100478
MCC
1026 }
1027 }
7a623c03
MCC
1028 /*
1029 * Create the dimm/rank devices
7c9281d7 1030 */
7a623c03 1031 for (i = 0; i < mci->tot_dimms; i++) {
de3910eb 1032 struct dimm_info *dimm = mci->dimms[i];
7a623c03 1033 /* Only expose populated DIMMs */
1bf1950c 1034 if (!dimm->nr_pages)
7a623c03 1035 continue;
1bf1950c 1036
7a623c03 1037#ifdef CONFIG_EDAC_DEBUG
956b9ba1 1038 edac_dbg(1, "creating dimm%d, located at ", i);
7a623c03
MCC
1039 if (edac_debug_level >= 1) {
1040 int lay;
1041 for (lay = 0; lay < mci->n_layers; lay++)
1042 printk(KERN_CONT "%s %d ",
1043 edac_layer_name[mci->layers[lay].type],
1044 dimm->location[lay]);
1045 printk(KERN_CONT "\n");
7c9281d7 1046 }
7a623c03 1047#endif
19974710
MCC
1048 err = edac_create_dimm_object(mci, dimm, i);
1049 if (err) {
956b9ba1 1050 edac_dbg(1, "failure: create dimm %d obj\n", i);
1bf1950c 1051 goto fail_unregister_dimm;
19974710 1052 }
7c9281d7
DT
1053 }
1054
19974710 1055#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03
MCC
1056 err = edac_create_csrow_objects(mci);
1057 if (err < 0)
1bf1950c 1058 goto fail_unregister_dimm;
19974710 1059#endif
7a623c03 1060
452a6bf9
MCC
1061#ifdef CONFIG_EDAC_DEBUG
1062 edac_create_debug_nodes(mci);
1063#endif
7c9281d7
DT
1064 return 0;
1065
1bf1950c 1066fail_unregister_dimm:
079708b9 1067 for (i--; i >= 0; i--) {
de3910eb 1068 struct dimm_info *dimm = mci->dimms[i];
1bf1950c 1069 if (!dimm->nr_pages)
7a623c03 1070 continue;
1bf1950c 1071
44d22e24 1072 device_unregister(&dimm->dev);
7c9281d7 1073 }
1bf1950c 1074fail_unregister_dev:
44d22e24 1075 device_unregister(&mci->dev);
1bf1950c 1076fail_unregister_bus:
88d84ac9 1077 bus_unregister(mci->bus);
1bf1950c 1078fail_free_name:
88d84ac9 1079 kfree(mci->bus->name);
7c9281d7
DT
1080 return err;
1081}
1082
1083/*
1084 * remove a Memory Controller instance
1085 */
1086void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
1087{
7a623c03 1088 int i;
7c9281d7 1089
956b9ba1 1090 edac_dbg(0, "\n");
7c9281d7 1091
452a6bf9
MCC
1092#ifdef CONFIG_EDAC_DEBUG
1093 debugfs_remove(mci->debugfs);
1094#endif
19974710 1095#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03 1096 edac_delete_csrow_objects(mci);
19974710 1097#endif
7c9281d7 1098
7a623c03 1099 for (i = 0; i < mci->tot_dimms; i++) {
de3910eb 1100 struct dimm_info *dimm = mci->dimms[i];
7a623c03
MCC
1101 if (dimm->nr_pages == 0)
1102 continue;
956b9ba1 1103 edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev));
44d22e24 1104 device_unregister(&dimm->dev);
6fe1108f 1105 }
7c9281d7 1106}
8096cfaf 1107
7a623c03
MCC
1108void edac_unregister_sysfs(struct mem_ctl_info *mci)
1109{
956b9ba1 1110 edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
44d22e24 1111 device_unregister(&mci->dev);
88d84ac9
BP
1112 bus_unregister(mci->bus);
1113 kfree(mci->bus->name);
7a623c03 1114}
8096cfaf 1115
de3910eb 1116static void mc_attr_release(struct device *dev)
7a623c03 1117{
de3910eb
MCC
1118 /*
1119 * There's no container structure here, as this is just the mci
1120 * parent device, used to create the /sys/devices/mc sysfs node.
1121 * So, there are no attributes on it.
1122 */
956b9ba1 1123 edac_dbg(1, "Releasing device %s\n", dev_name(dev));
de3910eb 1124 kfree(dev);
7a623c03 1125}
8096cfaf 1126
7a623c03
MCC
1127static struct device_type mc_attr_type = {
1128 .release = mc_attr_release,
1129};
8096cfaf 1130/*
7a623c03 1131 * Init/exit code for the module. Basically, creates/removes /sys/class/rc
8096cfaf 1132 */
7a623c03 1133int __init edac_mc_sysfs_init(void)
8096cfaf 1134{
fe5ff8b8 1135 struct bus_type *edac_subsys;
7a623c03 1136 int err;
8096cfaf 1137
fe5ff8b8
KS
1138 /* get the /sys/devices/system/edac subsys reference */
1139 edac_subsys = edac_get_sysfs_subsys();
1140 if (edac_subsys == NULL) {
956b9ba1 1141 edac_dbg(1, "no edac_subsys\n");
2d56b109
DK
1142 err = -EINVAL;
1143 goto out;
8096cfaf
DT
1144 }
1145
de3910eb 1146 mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL);
2d56b109
DK
1147 if (!mci_pdev) {
1148 err = -ENOMEM;
1149 goto out_put_sysfs;
1150 }
de3910eb
MCC
1151
1152 mci_pdev->bus = edac_subsys;
1153 mci_pdev->type = &mc_attr_type;
1154 device_initialize(mci_pdev);
1155 dev_set_name(mci_pdev, "mc");
8096cfaf 1156
de3910eb 1157 err = device_add(mci_pdev);
7a623c03 1158 if (err < 0)
2d56b109 1159 goto out_dev_free;
8096cfaf 1160
956b9ba1 1161 edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
de3910eb 1162
8096cfaf 1163 return 0;
2d56b109
DK
1164
1165 out_dev_free:
1166 kfree(mci_pdev);
1167 out_put_sysfs:
1168 edac_put_sysfs_subsys();
1169 out:
1170 return err;
8096cfaf
DT
1171}
1172
7a623c03 1173void __exit edac_mc_sysfs_exit(void)
8096cfaf 1174{
44d22e24 1175 device_unregister(mci_pdev);
fe5ff8b8 1176 edac_put_sysfs_subsys();
8096cfaf 1177}
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