edac: Only expose csrows/channels on legacy API if they're populated
[deliverable/linux.git] / drivers / edac / edac_mc_sysfs.c
CommitLineData
7c9281d7
DT
1/*
2 * edac_mc kernel module
42a8e397
DT
3 * (C) 2005-2007 Linux Networx (http://lnxi.com)
4 *
7c9281d7
DT
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
42a8e397 8 * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com
7c9281d7 9 *
7a623c03
MCC
10 * (c) 2012 - Mauro Carvalho Chehab <mchehab@redhat.com>
11 * The entire API were re-written, and ported to use struct device
12 *
7c9281d7
DT
13 */
14
7c9281d7 15#include <linux/ctype.h>
5a0e3ad6 16#include <linux/slab.h>
30e1f7a8 17#include <linux/edac.h>
8096cfaf 18#include <linux/bug.h>
7a623c03 19#include <linux/pm_runtime.h>
452a6bf9 20#include <linux/uaccess.h>
7c9281d7 21
20bcb7a8 22#include "edac_core.h"
7c9281d7
DT
23#include "edac_module.h"
24
25/* MC EDAC Controls, setable by module parameter, and sysfs */
4de78c68
DJ
26static int edac_mc_log_ue = 1;
27static int edac_mc_log_ce = 1;
f044091c 28static int edac_mc_panic_on_ue;
4de78c68 29static int edac_mc_poll_msec = 1000;
7c9281d7
DT
30
31/* Getter functions for above */
4de78c68 32int edac_mc_get_log_ue(void)
7c9281d7 33{
4de78c68 34 return edac_mc_log_ue;
7c9281d7
DT
35}
36
4de78c68 37int edac_mc_get_log_ce(void)
7c9281d7 38{
4de78c68 39 return edac_mc_log_ce;
7c9281d7
DT
40}
41
4de78c68 42int edac_mc_get_panic_on_ue(void)
7c9281d7 43{
4de78c68 44 return edac_mc_panic_on_ue;
7c9281d7
DT
45}
46
81d87cb1
DJ
47/* this is temporary */
48int edac_mc_get_poll_msec(void)
49{
4de78c68 50 return edac_mc_poll_msec;
7c9281d7
DT
51}
52
096846e2
AJ
53static int edac_set_poll_msec(const char *val, struct kernel_param *kp)
54{
55 long l;
56 int ret;
57
58 if (!val)
59 return -EINVAL;
60
61 ret = strict_strtol(val, 0, &l);
62 if (ret == -EINVAL || ((int)l != l))
63 return -EINVAL;
64 *((int *)kp->arg) = l;
65
66 /* notify edac_mc engine to reset the poll period */
67 edac_mc_reset_delay_period(l);
68
69 return 0;
70}
71
7c9281d7 72/* Parameter declarations for above */
4de78c68
DJ
73module_param(edac_mc_panic_on_ue, int, 0644);
74MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on");
75module_param(edac_mc_log_ue, int, 0644);
76MODULE_PARM_DESC(edac_mc_log_ue,
079708b9 77 "Log uncorrectable error to console: 0=off 1=on");
4de78c68
DJ
78module_param(edac_mc_log_ce, int, 0644);
79MODULE_PARM_DESC(edac_mc_log_ce,
079708b9 80 "Log correctable error to console: 0=off 1=on");
096846e2
AJ
81module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int,
82 &edac_mc_poll_msec, 0644);
4de78c68 83MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds");
7c9281d7 84
7a623c03
MCC
85static struct device mci_pdev;
86
7c9281d7
DT
87/*
88 * various constants for Memory Controllers
89 */
90static const char *mem_types[] = {
91 [MEM_EMPTY] = "Empty",
92 [MEM_RESERVED] = "Reserved",
93 [MEM_UNKNOWN] = "Unknown",
94 [MEM_FPM] = "FPM",
95 [MEM_EDO] = "EDO",
96 [MEM_BEDO] = "BEDO",
97 [MEM_SDR] = "Unbuffered-SDR",
98 [MEM_RDR] = "Registered-SDR",
99 [MEM_DDR] = "Unbuffered-DDR",
100 [MEM_RDDR] = "Registered-DDR",
1a9b85e6
DJ
101 [MEM_RMBS] = "RMBS",
102 [MEM_DDR2] = "Unbuffered-DDR2",
103 [MEM_FB_DDR2] = "FullyBuffered-DDR2",
1d5f726c 104 [MEM_RDDR2] = "Registered-DDR2",
b1cfebc9
YS
105 [MEM_XDR] = "XDR",
106 [MEM_DDR3] = "Unbuffered-DDR3",
107 [MEM_RDDR3] = "Registered-DDR3"
7c9281d7
DT
108};
109
110static const char *dev_types[] = {
111 [DEV_UNKNOWN] = "Unknown",
112 [DEV_X1] = "x1",
113 [DEV_X2] = "x2",
114 [DEV_X4] = "x4",
115 [DEV_X8] = "x8",
116 [DEV_X16] = "x16",
117 [DEV_X32] = "x32",
118 [DEV_X64] = "x64"
119};
120
121static const char *edac_caps[] = {
122 [EDAC_UNKNOWN] = "Unknown",
123 [EDAC_NONE] = "None",
124 [EDAC_RESERVED] = "Reserved",
125 [EDAC_PARITY] = "PARITY",
126 [EDAC_EC] = "EC",
127 [EDAC_SECDED] = "SECDED",
128 [EDAC_S2ECD2ED] = "S2ECD2ED",
129 [EDAC_S4ECD4ED] = "S4ECD4ED",
130 [EDAC_S8ECD8ED] = "S8ECD8ED",
131 [EDAC_S16ECD16ED] = "S16ECD16ED"
132};
133
19974710 134#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03
MCC
135/*
136 * EDAC sysfs CSROW data structures and methods
137 */
138
139#define to_csrow(k) container_of(k, struct csrow_info, dev)
140
141/*
142 * We need it to avoid namespace conflicts between the legacy API
143 * and the per-dimm/per-rank one
7c9281d7 144 */
7a623c03
MCC
145#define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
146 struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
147
148struct dev_ch_attribute {
149 struct device_attribute attr;
150 int channel;
151};
152
153#define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \
154 struct dev_ch_attribute dev_attr_legacy_##_name = \
155 { __ATTR(_name, _mode, _show, _store), (_var) }
156
157#define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel)
7c9281d7
DT
158
159/* Set of more default csrow<id> attribute show/store functions */
7a623c03
MCC
160static ssize_t csrow_ue_count_show(struct device *dev,
161 struct device_attribute *mattr, char *data)
7c9281d7 162{
7a623c03
MCC
163 struct csrow_info *csrow = to_csrow(dev);
164
079708b9 165 return sprintf(data, "%u\n", csrow->ue_count);
7c9281d7
DT
166}
167
7a623c03
MCC
168static ssize_t csrow_ce_count_show(struct device *dev,
169 struct device_attribute *mattr, char *data)
7c9281d7 170{
7a623c03
MCC
171 struct csrow_info *csrow = to_csrow(dev);
172
079708b9 173 return sprintf(data, "%u\n", csrow->ce_count);
7c9281d7
DT
174}
175
7a623c03
MCC
176static ssize_t csrow_size_show(struct device *dev,
177 struct device_attribute *mattr, char *data)
7c9281d7 178{
7a623c03 179 struct csrow_info *csrow = to_csrow(dev);
a895bf8b
MCC
180 int i;
181 u32 nr_pages = 0;
182
183 for (i = 0; i < csrow->nr_channels; i++)
184 nr_pages += csrow->channels[i].dimm->nr_pages;
a895bf8b 185 return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
7c9281d7
DT
186}
187
7a623c03
MCC
188static ssize_t csrow_mem_type_show(struct device *dev,
189 struct device_attribute *mattr, char *data)
7c9281d7 190{
7a623c03
MCC
191 struct csrow_info *csrow = to_csrow(dev);
192
084a4fcc 193 return sprintf(data, "%s\n", mem_types[csrow->channels[0].dimm->mtype]);
7c9281d7
DT
194}
195
7a623c03
MCC
196static ssize_t csrow_dev_type_show(struct device *dev,
197 struct device_attribute *mattr, char *data)
7c9281d7 198{
7a623c03
MCC
199 struct csrow_info *csrow = to_csrow(dev);
200
084a4fcc 201 return sprintf(data, "%s\n", dev_types[csrow->channels[0].dimm->dtype]);
7c9281d7
DT
202}
203
7a623c03
MCC
204static ssize_t csrow_edac_mode_show(struct device *dev,
205 struct device_attribute *mattr,
206 char *data)
7c9281d7 207{
7a623c03
MCC
208 struct csrow_info *csrow = to_csrow(dev);
209
084a4fcc 210 return sprintf(data, "%s\n", edac_caps[csrow->channels[0].dimm->edac_mode]);
7c9281d7
DT
211}
212
213/* show/store functions for DIMM Label attributes */
7a623c03
MCC
214static ssize_t channel_dimm_label_show(struct device *dev,
215 struct device_attribute *mattr,
216 char *data)
7c9281d7 217{
7a623c03
MCC
218 struct csrow_info *csrow = to_csrow(dev);
219 unsigned chan = to_channel(mattr);
220 struct rank_info *rank = &csrow->channels[chan];
221
124682c7 222 /* if field has not been initialized, there is nothing to send */
7a623c03 223 if (!rank->dimm->label[0])
124682c7
AJ
224 return 0;
225
226 return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n",
7a623c03 227 rank->dimm->label);
7c9281d7
DT
228}
229
7a623c03
MCC
230static ssize_t channel_dimm_label_store(struct device *dev,
231 struct device_attribute *mattr,
232 const char *data, size_t count)
7c9281d7 233{
7a623c03
MCC
234 struct csrow_info *csrow = to_csrow(dev);
235 unsigned chan = to_channel(mattr);
236 struct rank_info *rank = &csrow->channels[chan];
237
7c9281d7
DT
238 ssize_t max_size = 0;
239
079708b9 240 max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
7a623c03
MCC
241 strncpy(rank->dimm->label, data, max_size);
242 rank->dimm->label[max_size] = '\0';
7c9281d7
DT
243
244 return max_size;
245}
246
247/* show function for dynamic chX_ce_count attribute */
7a623c03
MCC
248static ssize_t channel_ce_count_show(struct device *dev,
249 struct device_attribute *mattr, char *data)
7c9281d7 250{
7a623c03
MCC
251 struct csrow_info *csrow = to_csrow(dev);
252 unsigned chan = to_channel(mattr);
253 struct rank_info *rank = &csrow->channels[chan];
254
255 return sprintf(data, "%u\n", rank->ce_count);
7c9281d7
DT
256}
257
7a623c03
MCC
258/* cwrow<id>/attribute files */
259DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL);
260DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL);
261DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL);
262DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL);
263DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL);
264DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL);
7c9281d7 265
7a623c03
MCC
266/* default attributes of the CSROW<id> object */
267static struct attribute *csrow_attrs[] = {
268 &dev_attr_legacy_dev_type.attr,
269 &dev_attr_legacy_mem_type.attr,
270 &dev_attr_legacy_edac_mode.attr,
271 &dev_attr_legacy_size_mb.attr,
272 &dev_attr_legacy_ue_count.attr,
273 &dev_attr_legacy_ce_count.attr,
274 NULL,
275};
7c9281d7 276
7a623c03
MCC
277static struct attribute_group csrow_attr_grp = {
278 .attrs = csrow_attrs,
279};
7c9281d7 280
7a623c03
MCC
281static const struct attribute_group *csrow_attr_groups[] = {
282 &csrow_attr_grp,
283 NULL
284};
7c9281d7 285
7a623c03 286static void csrow_attr_release(struct device *device)
7c9281d7 287{
7a623c03 288 debugf1("Releasing csrow device %s\n", dev_name(device));
7c9281d7
DT
289}
290
7a623c03
MCC
291static struct device_type csrow_attr_type = {
292 .groups = csrow_attr_groups,
293 .release = csrow_attr_release,
7c9281d7
DT
294};
295
7a623c03
MCC
296/*
297 * possible dynamic channel DIMM Label attribute files
298 *
299 */
7c9281d7 300
7a623c03 301#define EDAC_NR_CHANNELS 6
7c9281d7 302
7a623c03 303DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 304 channel_dimm_label_show, channel_dimm_label_store, 0);
7a623c03 305DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 306 channel_dimm_label_show, channel_dimm_label_store, 1);
7a623c03 307DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 308 channel_dimm_label_show, channel_dimm_label_store, 2);
7a623c03 309DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 310 channel_dimm_label_show, channel_dimm_label_store, 3);
7a623c03 311DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 312 channel_dimm_label_show, channel_dimm_label_store, 4);
7a623c03 313DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR,
052dfb45 314 channel_dimm_label_show, channel_dimm_label_store, 5);
7c9281d7
DT
315
316/* Total possible dynamic DIMM Label attribute file table */
7a623c03
MCC
317static struct device_attribute *dynamic_csrow_dimm_attr[] = {
318 &dev_attr_legacy_ch0_dimm_label.attr,
319 &dev_attr_legacy_ch1_dimm_label.attr,
320 &dev_attr_legacy_ch2_dimm_label.attr,
321 &dev_attr_legacy_ch3_dimm_label.attr,
322 &dev_attr_legacy_ch4_dimm_label.attr,
323 &dev_attr_legacy_ch5_dimm_label.attr
7c9281d7
DT
324};
325
326/* possible dynamic channel ce_count attribute files */
7a623c03
MCC
327DEVICE_CHANNEL(ch0_ce_count, S_IRUGO | S_IWUSR,
328 channel_ce_count_show, NULL, 0);
329DEVICE_CHANNEL(ch1_ce_count, S_IRUGO | S_IWUSR,
330 channel_ce_count_show, NULL, 1);
331DEVICE_CHANNEL(ch2_ce_count, S_IRUGO | S_IWUSR,
332 channel_ce_count_show, NULL, 2);
333DEVICE_CHANNEL(ch3_ce_count, S_IRUGO | S_IWUSR,
334 channel_ce_count_show, NULL, 3);
335DEVICE_CHANNEL(ch4_ce_count, S_IRUGO | S_IWUSR,
336 channel_ce_count_show, NULL, 4);
337DEVICE_CHANNEL(ch5_ce_count, S_IRUGO | S_IWUSR,
338 channel_ce_count_show, NULL, 5);
7c9281d7
DT
339
340/* Total possible dynamic ce_count attribute file table */
7a623c03
MCC
341static struct device_attribute *dynamic_csrow_ce_count_attr[] = {
342 &dev_attr_legacy_ch0_ce_count.attr,
343 &dev_attr_legacy_ch1_ce_count.attr,
344 &dev_attr_legacy_ch2_ce_count.attr,
345 &dev_attr_legacy_ch3_ce_count.attr,
346 &dev_attr_legacy_ch4_ce_count.attr,
347 &dev_attr_legacy_ch5_ce_count.attr
7c9281d7
DT
348};
349
e39f4ea9
MCC
350static inline int nr_pages_per_csrow(struct csrow_info *csrow)
351{
352 int chan, nr_pages = 0;
353
354 for (chan = 0; chan < csrow->nr_channels; chan++)
355 nr_pages += csrow->channels[chan].dimm->nr_pages;
356
357 return nr_pages;
358}
359
7a623c03
MCC
360/* Create a CSROW object under specifed edac_mc_device */
361static int edac_create_csrow_object(struct mem_ctl_info *mci,
362 struct csrow_info *csrow, int index)
7c9281d7 363{
7a623c03 364 int err, chan;
7c9281d7 365
7a623c03
MCC
366 if (csrow->nr_channels >= EDAC_NR_CHANNELS)
367 return -ENODEV;
7c9281d7 368
7a623c03
MCC
369 csrow->dev.type = &csrow_attr_type;
370 csrow->dev.bus = &mci->bus;
371 device_initialize(&csrow->dev);
372 csrow->dev.parent = &mci->dev;
373 dev_set_name(&csrow->dev, "csrow%d", index);
374 dev_set_drvdata(&csrow->dev, csrow);
7c9281d7 375
7a623c03
MCC
376 debugf0("%s(): creating (virtual) csrow node %s\n", __func__,
377 dev_name(&csrow->dev));
7c9281d7 378
7a623c03
MCC
379 err = device_add(&csrow->dev);
380 if (err < 0)
381 return err;
7c9281d7 382
7a623c03 383 for (chan = 0; chan < csrow->nr_channels; chan++) {
e39f4ea9
MCC
384 /* Only expose populated DIMMs */
385 if (!csrow->channels[chan].dimm->nr_pages)
386 continue;
7a623c03
MCC
387 err = device_create_file(&csrow->dev,
388 dynamic_csrow_dimm_attr[chan]);
389 if (err < 0)
390 goto error;
391 err = device_create_file(&csrow->dev,
392 dynamic_csrow_ce_count_attr[chan]);
393 if (err < 0) {
394 device_remove_file(&csrow->dev,
395 dynamic_csrow_dimm_attr[chan]);
396 goto error;
397 }
398 }
8096cfaf 399
7a623c03 400 return 0;
8096cfaf 401
7a623c03
MCC
402error:
403 for (--chan; chan >= 0; chan--) {
404 device_remove_file(&csrow->dev,
405 dynamic_csrow_dimm_attr[chan]);
406 device_remove_file(&csrow->dev,
407 dynamic_csrow_ce_count_attr[chan]);
408 }
409 put_device(&csrow->dev);
7c9281d7 410
7a623c03
MCC
411 return err;
412}
7c9281d7
DT
413
414/* Create a CSROW object under specifed edac_mc_device */
7a623c03 415static int edac_create_csrow_objects(struct mem_ctl_info *mci)
7c9281d7 416{
7a623c03
MCC
417 int err, i, chan;
418 struct csrow_info *csrow;
7c9281d7 419
7a623c03 420 for (i = 0; i < mci->nr_csrows; i++) {
e39f4ea9
MCC
421 csrow = &mci->csrows[i];
422 if (!nr_pages_per_csrow(csrow))
423 continue;
7a623c03
MCC
424 err = edac_create_csrow_object(mci, &mci->csrows[i], i);
425 if (err < 0)
426 goto error;
427 }
428 return 0;
8096cfaf 429
7a623c03
MCC
430error:
431 for (--i; i >= 0; i--) {
432 csrow = &mci->csrows[i];
e39f4ea9
MCC
433 if (!nr_pages_per_csrow(csrow))
434 continue;
7a623c03 435 for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
e39f4ea9
MCC
436 if (!csrow->channels[chan].dimm->nr_pages)
437 continue;
7a623c03
MCC
438 device_remove_file(&csrow->dev,
439 dynamic_csrow_dimm_attr[chan]);
440 device_remove_file(&csrow->dev,
441 dynamic_csrow_ce_count_attr[chan]);
442 }
443 put_device(&mci->csrows[i].dev);
8096cfaf 444 }
7c9281d7 445
7a623c03
MCC
446 return err;
447}
8096cfaf 448
7a623c03
MCC
449static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
450{
451 int i, chan;
452 struct csrow_info *csrow;
8096cfaf 453
7a623c03
MCC
454 for (i = mci->nr_csrows - 1; i >= 0; i--) {
455 csrow = &mci->csrows[i];
e39f4ea9
MCC
456 if (!nr_pages_per_csrow(csrow))
457 continue;
7a623c03 458 for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
e39f4ea9
MCC
459 if (!csrow->channels[chan].dimm->nr_pages)
460 continue;
7a623c03
MCC
461 debugf1("Removing csrow %d channel %d sysfs nodes\n",
462 i, chan);
463 device_remove_file(&csrow->dev,
464 dynamic_csrow_dimm_attr[chan]);
465 device_remove_file(&csrow->dev,
466 dynamic_csrow_ce_count_attr[chan]);
7c9281d7 467 }
7a623c03
MCC
468 put_device(&mci->csrows[i].dev);
469 device_del(&mci->csrows[i].dev);
7c9281d7 470 }
7c9281d7 471}
19974710
MCC
472#endif
473
474/*
475 * Per-dimm (or per-rank) devices
476 */
477
478#define to_dimm(k) container_of(k, struct dimm_info, dev)
479
480/* show/store functions for DIMM Label attributes */
481static ssize_t dimmdev_location_show(struct device *dev,
482 struct device_attribute *mattr, char *data)
483{
484 struct dimm_info *dimm = to_dimm(dev);
485 struct mem_ctl_info *mci = dimm->mci;
486 int i;
487 char *p = data;
488
489 for (i = 0; i < mci->n_layers; i++) {
490 p += sprintf(p, "%s %d ",
491 edac_layer_name[mci->layers[i].type],
492 dimm->location[i]);
493 }
494
495 return p - data;
496}
497
498static ssize_t dimmdev_label_show(struct device *dev,
499 struct device_attribute *mattr, char *data)
500{
501 struct dimm_info *dimm = to_dimm(dev);
502
503 /* if field has not been initialized, there is nothing to send */
504 if (!dimm->label[0])
505 return 0;
506
507 return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label);
508}
509
510static ssize_t dimmdev_label_store(struct device *dev,
511 struct device_attribute *mattr,
512 const char *data,
513 size_t count)
514{
515 struct dimm_info *dimm = to_dimm(dev);
516
517 ssize_t max_size = 0;
518
519 max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
520 strncpy(dimm->label, data, max_size);
521 dimm->label[max_size] = '\0';
522
523 return max_size;
524}
525
526static ssize_t dimmdev_size_show(struct device *dev,
527 struct device_attribute *mattr, char *data)
528{
529 struct dimm_info *dimm = to_dimm(dev);
530
531 return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages));
532}
533
534static ssize_t dimmdev_mem_type_show(struct device *dev,
535 struct device_attribute *mattr, char *data)
536{
537 struct dimm_info *dimm = to_dimm(dev);
538
539 return sprintf(data, "%s\n", mem_types[dimm->mtype]);
540}
541
542static ssize_t dimmdev_dev_type_show(struct device *dev,
543 struct device_attribute *mattr, char *data)
544{
545 struct dimm_info *dimm = to_dimm(dev);
546
547 return sprintf(data, "%s\n", dev_types[dimm->dtype]);
548}
549
550static ssize_t dimmdev_edac_mode_show(struct device *dev,
551 struct device_attribute *mattr,
552 char *data)
553{
554 struct dimm_info *dimm = to_dimm(dev);
555
556 return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]);
557}
558
559/* dimm/rank attribute files */
560static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR,
561 dimmdev_label_show, dimmdev_label_store);
562static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL);
563static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL);
564static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL);
565static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL);
566static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL);
567
568/* attributes of the dimm<id>/rank<id> object */
569static struct attribute *dimm_attrs[] = {
570 &dev_attr_dimm_label.attr,
571 &dev_attr_dimm_location.attr,
572 &dev_attr_size.attr,
573 &dev_attr_dimm_mem_type.attr,
574 &dev_attr_dimm_dev_type.attr,
575 &dev_attr_dimm_edac_mode.attr,
576 NULL,
577};
578
579static struct attribute_group dimm_attr_grp = {
580 .attrs = dimm_attrs,
581};
582
583static const struct attribute_group *dimm_attr_groups[] = {
584 &dimm_attr_grp,
585 NULL
586};
587
588static void dimm_attr_release(struct device *device)
589{
590 debugf1("Releasing dimm device %s\n", dev_name(device));
591}
592
593static struct device_type dimm_attr_type = {
594 .groups = dimm_attr_groups,
595 .release = dimm_attr_release,
596};
597
598/* Create a DIMM object under specifed memory controller device */
599static int edac_create_dimm_object(struct mem_ctl_info *mci,
600 struct dimm_info *dimm,
601 int index)
602{
603 int err;
604 dimm->mci = mci;
605
606 dimm->dev.type = &dimm_attr_type;
607 dimm->dev.bus = &mci->bus;
608 device_initialize(&dimm->dev);
609
610 dimm->dev.parent = &mci->dev;
611 if (mci->mem_is_per_rank)
612 dev_set_name(&dimm->dev, "rank%d", index);
613 else
614 dev_set_name(&dimm->dev, "dimm%d", index);
615 dev_set_drvdata(&dimm->dev, dimm);
616 pm_runtime_forbid(&mci->dev);
617
618 err = device_add(&dimm->dev);
619
620 debugf0("%s(): creating rank/dimm device %s\n", __func__,
621 dev_name(&dimm->dev));
622
623 return err;
624}
7c9281d7 625
7a623c03
MCC
626/*
627 * Memory controller device
628 */
629
630#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
7c9281d7 631
7a623c03
MCC
632static ssize_t mci_reset_counters_store(struct device *dev,
633 struct device_attribute *mattr,
079708b9 634 const char *data, size_t count)
7c9281d7 635{
7a623c03
MCC
636 struct mem_ctl_info *mci = to_mci(dev);
637 int cnt, row, chan, i;
5926ff50
MCC
638 mci->ue_mc = 0;
639 mci->ce_mc = 0;
7a623c03
MCC
640 mci->ue_noinfo_count = 0;
641 mci->ce_noinfo_count = 0;
7c9281d7
DT
642
643 for (row = 0; row < mci->nr_csrows; row++) {
644 struct csrow_info *ri = &mci->csrows[row];
645
646 ri->ue_count = 0;
647 ri->ce_count = 0;
648
649 for (chan = 0; chan < ri->nr_channels; chan++)
650 ri->channels[chan].ce_count = 0;
651 }
652
7a623c03
MCC
653 cnt = 1;
654 for (i = 0; i < mci->n_layers; i++) {
655 cnt *= mci->layers[i].size;
656 memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32));
657 memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32));
658 }
659
7c9281d7
DT
660 mci->start_time = jiffies;
661 return count;
662}
663
39094443
BP
664/* Memory scrubbing interface:
665 *
666 * A MC driver can limit the scrubbing bandwidth based on the CPU type.
667 * Therefore, ->set_sdram_scrub_rate should be made to return the actual
668 * bandwidth that is accepted or 0 when scrubbing is to be disabled.
669 *
670 * Negative value still means that an error has occurred while setting
671 * the scrub rate.
672 */
7a623c03
MCC
673static ssize_t mci_sdram_scrub_rate_store(struct device *dev,
674 struct device_attribute *mattr,
eba042a8 675 const char *data, size_t count)
7c9281d7 676{
7a623c03 677 struct mem_ctl_info *mci = to_mci(dev);
eba042a8 678 unsigned long bandwidth = 0;
39094443 679 int new_bw = 0;
7c9281d7 680
39094443 681 if (!mci->set_sdram_scrub_rate)
5e8e19bf 682 return -ENODEV;
7c9281d7 683
eba042a8
BP
684 if (strict_strtoul(data, 10, &bandwidth) < 0)
685 return -EINVAL;
7c9281d7 686
39094443 687 new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
4949603a
MT
688 if (new_bw < 0) {
689 edac_printk(KERN_WARNING, EDAC_MC,
690 "Error setting scrub rate to: %lu\n", bandwidth);
691 return -EINVAL;
7c9281d7 692 }
39094443 693
4949603a 694 return count;
7c9281d7
DT
695}
696
39094443
BP
697/*
698 * ->get_sdram_scrub_rate() return value semantics same as above.
699 */
7a623c03
MCC
700static ssize_t mci_sdram_scrub_rate_show(struct device *dev,
701 struct device_attribute *mattr,
702 char *data)
7c9281d7 703{
7a623c03 704 struct mem_ctl_info *mci = to_mci(dev);
39094443 705 int bandwidth = 0;
eba042a8 706
39094443 707 if (!mci->get_sdram_scrub_rate)
5e8e19bf 708 return -ENODEV;
eba042a8 709
39094443
BP
710 bandwidth = mci->get_sdram_scrub_rate(mci);
711 if (bandwidth < 0) {
eba042a8 712 edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
39094443 713 return bandwidth;
7c9281d7 714 }
39094443 715
39094443 716 return sprintf(data, "%d\n", bandwidth);
7c9281d7
DT
717}
718
719/* default attribute files for the MCI object */
7a623c03
MCC
720static ssize_t mci_ue_count_show(struct device *dev,
721 struct device_attribute *mattr,
722 char *data)
7c9281d7 723{
7a623c03
MCC
724 struct mem_ctl_info *mci = to_mci(dev);
725
5926ff50 726 return sprintf(data, "%d\n", mci->ue_mc);
7c9281d7
DT
727}
728
7a623c03
MCC
729static ssize_t mci_ce_count_show(struct device *dev,
730 struct device_attribute *mattr,
731 char *data)
7c9281d7 732{
7a623c03
MCC
733 struct mem_ctl_info *mci = to_mci(dev);
734
5926ff50 735 return sprintf(data, "%d\n", mci->ce_mc);
7c9281d7
DT
736}
737
7a623c03
MCC
738static ssize_t mci_ce_noinfo_show(struct device *dev,
739 struct device_attribute *mattr,
740 char *data)
7c9281d7 741{
7a623c03
MCC
742 struct mem_ctl_info *mci = to_mci(dev);
743
079708b9 744 return sprintf(data, "%d\n", mci->ce_noinfo_count);
7c9281d7
DT
745}
746
7a623c03
MCC
747static ssize_t mci_ue_noinfo_show(struct device *dev,
748 struct device_attribute *mattr,
749 char *data)
7c9281d7 750{
7a623c03
MCC
751 struct mem_ctl_info *mci = to_mci(dev);
752
079708b9 753 return sprintf(data, "%d\n", mci->ue_noinfo_count);
7c9281d7
DT
754}
755
7a623c03
MCC
756static ssize_t mci_seconds_show(struct device *dev,
757 struct device_attribute *mattr,
758 char *data)
7c9281d7 759{
7a623c03
MCC
760 struct mem_ctl_info *mci = to_mci(dev);
761
079708b9 762 return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ);
7c9281d7
DT
763}
764
7a623c03
MCC
765static ssize_t mci_ctl_name_show(struct device *dev,
766 struct device_attribute *mattr,
767 char *data)
7c9281d7 768{
7a623c03
MCC
769 struct mem_ctl_info *mci = to_mci(dev);
770
079708b9 771 return sprintf(data, "%s\n", mci->ctl_name);
7c9281d7
DT
772}
773
7a623c03
MCC
774static ssize_t mci_size_mb_show(struct device *dev,
775 struct device_attribute *mattr,
776 char *data)
7c9281d7 777{
7a623c03 778 struct mem_ctl_info *mci = to_mci(dev);
a895bf8b 779 int total_pages = 0, csrow_idx, j;
7c9281d7 780
a895bf8b 781 for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
7c9281d7
DT
782 struct csrow_info *csrow = &mci->csrows[csrow_idx];
783
a895bf8b
MCC
784 for (j = 0; j < csrow->nr_channels; j++) {
785 struct dimm_info *dimm = csrow->channels[j].dimm;
7c9281d7 786
a895bf8b
MCC
787 total_pages += dimm->nr_pages;
788 }
7c9281d7
DT
789 }
790
079708b9 791 return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
7c9281d7
DT
792}
793
8ad6c78a
MCC
794static ssize_t mci_max_location_show(struct device *dev,
795 struct device_attribute *mattr,
796 char *data)
797{
798 struct mem_ctl_info *mci = to_mci(dev);
799 int i;
800 char *p = data;
801
802 for (i = 0; i < mci->n_layers; i++) {
803 p += sprintf(p, "%s %d ",
804 edac_layer_name[mci->layers[i].type],
805 mci->layers[i].size - 1);
806 }
807
808 return p - data;
809}
810
452a6bf9
MCC
811#ifdef CONFIG_EDAC_DEBUG
812static ssize_t edac_fake_inject_write(struct file *file,
813 const char __user *data,
814 size_t count, loff_t *ppos)
815{
816 struct device *dev = file->private_data;
817 struct mem_ctl_info *mci = to_mci(dev);
818 static enum hw_event_mc_err_type type;
819
820 type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED
821 : HW_EVENT_ERR_CORRECTED;
822
823 printk(KERN_DEBUG
824 "Generating a %s fake error to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",
825 (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",
826 mci->fake_inject_layer[0],
827 mci->fake_inject_layer[1],
828 mci->fake_inject_layer[2]
829 );
830 edac_mc_handle_error(type, mci, 0, 0, 0,
831 mci->fake_inject_layer[0],
832 mci->fake_inject_layer[1],
833 mci->fake_inject_layer[2],
834 "FAKE ERROR", "for EDAC testing only", NULL);
835
836 return count;
837}
838
839static int debugfs_open(struct inode *inode, struct file *file)
840{
841 file->private_data = inode->i_private;
842 return 0;
843}
844
845static const struct file_operations debug_fake_inject_fops = {
846 .open = debugfs_open,
847 .write = edac_fake_inject_write,
848 .llseek = generic_file_llseek,
849};
850#endif
851
7c9281d7 852/* default Control file */
7a623c03 853DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store);
7c9281d7
DT
854
855/* default Attribute files */
7a623c03
MCC
856DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL);
857DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL);
858DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL);
859DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL);
860DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL);
861DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL);
862DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL);
8ad6c78a 863DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL);
7c9281d7
DT
864
865/* memory scrubber attribute file */
7a623c03 866DEVICE_ATTR(sdram_scrub_rate, S_IRUGO | S_IWUSR, mci_sdram_scrub_rate_show,
052dfb45 867 mci_sdram_scrub_rate_store);
7c9281d7 868
7a623c03
MCC
869static struct attribute *mci_attrs[] = {
870 &dev_attr_reset_counters.attr,
871 &dev_attr_mc_name.attr,
872 &dev_attr_size_mb.attr,
873 &dev_attr_seconds_since_reset.attr,
874 &dev_attr_ue_noinfo_count.attr,
875 &dev_attr_ce_noinfo_count.attr,
876 &dev_attr_ue_count.attr,
877 &dev_attr_ce_count.attr,
878 &dev_attr_sdram_scrub_rate.attr,
8ad6c78a 879 &dev_attr_max_location.attr,
7c9281d7
DT
880 NULL
881};
882
7a623c03
MCC
883static struct attribute_group mci_attr_grp = {
884 .attrs = mci_attrs,
cc301b3a
MCC
885};
886
7a623c03
MCC
887static const struct attribute_group *mci_attr_groups[] = {
888 &mci_attr_grp,
889 NULL
cc301b3a
MCC
890};
891
7a623c03 892static void mci_attr_release(struct device *device)
42a8e397 893{
7a623c03 894 debugf1("Releasing mci device %s\n", dev_name(device));
42a8e397
DT
895}
896
7a623c03
MCC
897static struct device_type mci_attr_type = {
898 .groups = mci_attr_groups,
899 .release = mci_attr_release,
900};
8096cfaf 901
452a6bf9
MCC
902#ifdef CONFIG_EDAC_DEBUG
903int edac_create_debug_nodes(struct mem_ctl_info *mci)
904{
905 struct dentry *d, *parent;
906 char name[80];
907 int i;
908
909 d = debugfs_create_dir(mci->dev.kobj.name, mci->debugfs);
910 if (!d)
911 return -ENOMEM;
912 parent = d;
913
914 for (i = 0; i < mci->n_layers; i++) {
915 sprintf(name, "fake_inject_%s",
916 edac_layer_name[mci->layers[i].type]);
917 d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent,
918 &mci->fake_inject_layer[i]);
919 if (!d)
920 goto nomem;
921 }
922
923 d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent,
924 &mci->fake_inject_ue);
925 if (!d)
926 goto nomem;
927
928 d = debugfs_create_file("fake_inject", S_IWUSR, parent,
929 &mci->dev,
930 &debug_fake_inject_fops);
931 if (!d)
932 goto nomem;
933
934 return 0;
935nomem:
936 debugfs_remove(mci->debugfs);
937 return -ENOMEM;
938}
939#endif
940
7c9281d7
DT
941/*
942 * Create a new Memory Controller kobject instance,
943 * mc<id> under the 'mc' directory
944 *
945 * Return:
946 * 0 Success
947 * !0 Failure
948 */
949int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
950{
7a623c03 951 int i, err;
7c9281d7
DT
952
953 debugf0("%s() idx=%d\n", __func__, mci->mc_idx);
7c9281d7 954
7a623c03 955 /* get the /sys/devices/system/edac subsys reference */
b968759e 956
7a623c03
MCC
957 mci->dev.type = &mci_attr_type;
958 device_initialize(&mci->dev);
7c9281d7 959
7a623c03
MCC
960 mci->dev.parent = &mci_pdev;
961 mci->dev.bus = &mci->bus;
962 dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
963 dev_set_drvdata(&mci->dev, mci);
964 pm_runtime_forbid(&mci->dev);
965
966 /*
967 * The memory controller needs its own bus, in order to avoid
968 * namespace conflicts at /sys/bus/edac.
42a8e397 969 */
7a623c03
MCC
970 debugf0("creating bus %s\n",mci->bus.name);
971 mci->bus.name = kstrdup(dev_name(&mci->dev), GFP_KERNEL);
972 err = bus_register(&mci->bus);
973 if (err < 0)
974 return err;
975
976 debugf0("%s(): creating device %s\n", __func__,
977 dev_name(&mci->dev));
978 err = device_add(&mci->dev);
979 if (err < 0) {
980 bus_unregister(&mci->bus);
981 kfree(mci->bus.name);
982 return err;
42a8e397
DT
983 }
984
7a623c03
MCC
985 /*
986 * Create the dimm/rank devices
7c9281d7 987 */
7a623c03
MCC
988 for (i = 0; i < mci->tot_dimms; i++) {
989 struct dimm_info *dimm = &mci->dimms[i];
990 /* Only expose populated DIMMs */
991 if (dimm->nr_pages == 0)
992 continue;
993#ifdef CONFIG_EDAC_DEBUG
994 debugf1("%s creating dimm%d, located at ",
995 __func__, i);
996 if (edac_debug_level >= 1) {
997 int lay;
998 for (lay = 0; lay < mci->n_layers; lay++)
999 printk(KERN_CONT "%s %d ",
1000 edac_layer_name[mci->layers[lay].type],
1001 dimm->location[lay]);
1002 printk(KERN_CONT "\n");
7c9281d7 1003 }
7a623c03 1004#endif
19974710
MCC
1005 err = edac_create_dimm_object(mci, dimm, i);
1006 if (err) {
1007 debugf1("%s() failure: create dimm %d obj\n",
1008 __func__, i);
1009 goto fail;
1010 }
7c9281d7
DT
1011 }
1012
19974710 1013#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03
MCC
1014 err = edac_create_csrow_objects(mci);
1015 if (err < 0)
1016 goto fail;
19974710 1017#endif
7a623c03 1018
452a6bf9
MCC
1019#ifdef CONFIG_EDAC_DEBUG
1020 edac_create_debug_nodes(mci);
1021#endif
7c9281d7
DT
1022 return 0;
1023
7a623c03 1024fail:
079708b9 1025 for (i--; i >= 0; i--) {
7a623c03
MCC
1026 struct dimm_info *dimm = &mci->dimms[i];
1027 if (dimm->nr_pages == 0)
1028 continue;
1029 put_device(&dimm->dev);
1030 device_del(&dimm->dev);
7c9281d7 1031 }
7a623c03
MCC
1032 put_device(&mci->dev);
1033 device_del(&mci->dev);
1034 bus_unregister(&mci->bus);
1035 kfree(mci->bus.name);
7c9281d7
DT
1036 return err;
1037}
1038
1039/*
1040 * remove a Memory Controller instance
1041 */
1042void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
1043{
7a623c03 1044 int i;
7c9281d7
DT
1045
1046 debugf0("%s()\n", __func__);
1047
452a6bf9
MCC
1048#ifdef CONFIG_EDAC_DEBUG
1049 debugfs_remove(mci->debugfs);
1050#endif
19974710 1051#ifdef CONFIG_EDAC_LEGACY_SYSFS
7a623c03 1052 edac_delete_csrow_objects(mci);
19974710 1053#endif
7c9281d7 1054
7a623c03
MCC
1055 for (i = 0; i < mci->tot_dimms; i++) {
1056 struct dimm_info *dimm = &mci->dimms[i];
1057 if (dimm->nr_pages == 0)
1058 continue;
1059 debugf0("%s(): removing device %s\n", __func__,
1060 dev_name(&dimm->dev));
1061 put_device(&dimm->dev);
1062 device_del(&dimm->dev);
6fe1108f 1063 }
7c9281d7 1064}
8096cfaf 1065
7a623c03
MCC
1066void edac_unregister_sysfs(struct mem_ctl_info *mci)
1067{
1068 debugf1("Unregistering device %s\n", dev_name(&mci->dev));
1069 put_device(&mci->dev);
1070 device_del(&mci->dev);
1071 bus_unregister(&mci->bus);
1072 kfree(mci->bus.name);
1073}
8096cfaf 1074
7a623c03
MCC
1075static void mc_attr_release(struct device *device)
1076{
1077 debugf1("Releasing device %s\n", dev_name(device));
1078}
8096cfaf 1079
7a623c03
MCC
1080static struct device_type mc_attr_type = {
1081 .release = mc_attr_release,
1082};
8096cfaf 1083/*
7a623c03 1084 * Init/exit code for the module. Basically, creates/removes /sys/class/rc
8096cfaf 1085 */
7a623c03 1086int __init edac_mc_sysfs_init(void)
8096cfaf 1087{
fe5ff8b8 1088 struct bus_type *edac_subsys;
7a623c03 1089 int err;
8096cfaf 1090
fe5ff8b8
KS
1091 /* get the /sys/devices/system/edac subsys reference */
1092 edac_subsys = edac_get_sysfs_subsys();
1093 if (edac_subsys == NULL) {
7a623c03
MCC
1094 debugf1("%s() no edac_subsys\n", __func__);
1095 return -EINVAL;
8096cfaf
DT
1096 }
1097
7a623c03
MCC
1098 mci_pdev.bus = edac_subsys;
1099 mci_pdev.type = &mc_attr_type;
1100 device_initialize(&mci_pdev);
1101 dev_set_name(&mci_pdev, "mc");
8096cfaf 1102
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MCC
1103 err = device_add(&mci_pdev);
1104 if (err < 0)
1105 return err;
8096cfaf
DT
1106
1107 return 0;
8096cfaf
DT
1108}
1109
7a623c03 1110void __exit edac_mc_sysfs_exit(void)
8096cfaf 1111{
7a623c03
MCC
1112 put_device(&mci_pdev);
1113 device_del(&mci_pdev);
fe5ff8b8 1114 edac_put_sysfs_subsys();
8096cfaf 1115}
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