[deliverable/linux.git] / drivers / edac / edac_mce_amd.c

#include <linux/module.h>
#include "edac_mce_amd.h"

static bool report_gart_errors;
static void (*nb_bus_decoder)(int node_id, struct mce *m, u32 nbcfg);

void amd_report_gart_errors(bool v)
{
	report_gart_errors = v;
}
EXPORT_SYMBOL_GPL(amd_report_gart_errors);

void amd_register_ecc_decoder(void (*f)(int, struct mce *, u32))
{
	nb_bus_decoder = f;
}
EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);

void amd_unregister_ecc_decoder(void (*f)(int, struct mce *, u32))
{
	if (nb_bus_decoder) {
		WARN_ON(nb_bus_decoder != f);

		nb_bus_decoder = NULL;
	}
}
EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);

/*
 * string representation for the different MCA reported error types, see F3x48
 * or MSR0000_0411.
 */

/* transaction type */
const char *tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
EXPORT_SYMBOL_GPL(tt_msgs);

/* cache level */
const char *ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
EXPORT_SYMBOL_GPL(ll_msgs);

/* memory transaction type */
const char *rrrr_msgs[] = {
       "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
};
EXPORT_SYMBOL_GPL(rrrr_msgs);

/* participating processor */
const char *pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
EXPORT_SYMBOL_GPL(pp_msgs);

/* request timeout */
const char *to_msgs[] = { "no timeout",	"timed out" };
EXPORT_SYMBOL_GPL(to_msgs);

/* memory or i/o */
const char *ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
EXPORT_SYMBOL_GPL(ii_msgs);

/*
 * Map the 4 or 5 (family-specific) bits of Extended Error code to the
 * string table.
 */
const char *ext_msgs[] = {
	"K8 ECC error",					/* 0_0000b */
	"CRC error on link",				/* 0_0001b */
	"Sync error packets on link",			/* 0_0010b */
	"Master Abort during link operation",		/* 0_0011b */
	"Target Abort during link operation",		/* 0_0100b */
	"Invalid GART PTE entry during table walk",	/* 0_0101b */
	"Unsupported atomic RMW command received",	/* 0_0110b */
	"WDT error: NB transaction timeout",		/* 0_0111b */
	"ECC/ChipKill ECC error",			/* 0_1000b */
	"SVM DEV Error",				/* 0_1001b */
	"Link Data error",				/* 0_1010b */
	"Link/L3/Probe Filter Protocol error",		/* 0_1011b */
	"NB Internal Arrays Parity error",		/* 0_1100b */
	"DRAM Address/Control Parity error",		/* 0_1101b */
	"Link Transmission error",			/* 0_1110b */
	"GART/DEV Table Walk Data error"		/* 0_1111b */
	"Res 0x100 error",				/* 1_0000b */
	"Res 0x101 error",				/* 1_0001b */
	"Res 0x102 error",				/* 1_0010b */
	"Res 0x103 error",				/* 1_0011b */
	"Res 0x104 error",				/* 1_0100b */
	"Res 0x105 error",				/* 1_0101b */
	"Res 0x106 error",				/* 1_0110b */
	"Res 0x107 error",				/* 1_0111b */
	"Res 0x108 error",				/* 1_1000b */
	"Res 0x109 error",				/* 1_1001b */
	"Res 0x10A error",				/* 1_1010b */
	"Res 0x10B error",				/* 1_1011b */
	"ECC error in L3 Cache Data",			/* 1_1100b */
	"L3 Cache Tag error",				/* 1_1101b */
	"L3 Cache LRU Parity error",			/* 1_1110b */
	"Probe Filter error"				/* 1_1111b */
};
EXPORT_SYMBOL_GPL(ext_msgs);

static void amd_decode_dc_mce(struct mce *m)
{
	u32 ec  = m->status & 0xffff;
	u32 xec = (m->status >> 16) & 0xf;

	pr_emerg(HW_ERR "Data Cache Error: ");

	if (xec == 1 && TLB_ERROR(ec))
		pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
	else if (xec == 0) {
		if (m->status & (1ULL << 40))
			pr_cont(" during Data Scrub.\n");
		else if (TLB_ERROR(ec))
			pr_cont(": %s TLB parity error.\n", LL_MSG(ec));
		else if (MEM_ERROR(ec)) {
			u8 ll   = ec & 0x3;
			u8 tt   = (ec >> 2) & 0x3;
			u8 rrrr = (ec >> 4) & 0xf;

			/* see F10h BKDG (31116), Table 92. */
			if (ll == 0x1) {
				if (tt != 0x1)
					goto wrong_dc_mce;

				pr_cont(": Data/Tag %s error.\n", RRRR_MSG(ec));

			} else if (ll == 0x2 && rrrr == 0x3)
				pr_cont(" during L1 linefill from L2.\n");
			else
				goto wrong_dc_mce;
		} else if (BUS_ERROR(ec) && boot_cpu_data.x86 == 0xf)
			pr_cont(" during system linefill.\n");
		else
			goto wrong_dc_mce;
	} else
		goto wrong_dc_mce;

	return;

wrong_dc_mce:
	pr_emerg(HW_ERR "Corrupted DC MCE info?\n");
}

static void amd_decode_ic_mce(struct mce *m)
{
	u32 ec  = m->status & 0xffff;
	u32 xec = (m->status >> 16) & 0xf;

	pr_emerg(HW_ERR "Instruction Cache Error");

	if (xec == 1 && TLB_ERROR(ec))
		pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
	else if (xec == 0) {
		if (TLB_ERROR(ec))
			pr_cont(": %s TLB Parity error.\n", LL_MSG(ec));
		else if (BUS_ERROR(ec)) {
			if (boot_cpu_data.x86 == 0xf &&
			    (m->status & BIT(58)))
				pr_cont(" during system linefill.\n");
			else
				pr_cont(" during attempted NB data read.\n");
		} else if (MEM_ERROR(ec)) {
			u8 ll   = ec & 0x3;
			u8 rrrr = (ec >> 4) & 0xf;

			if (ll == 0x2)
				pr_cont(" during a linefill from L2.\n");
			else if (ll == 0x1) {

				switch (rrrr) {
				case 0x5:
					pr_cont(": Parity error during "
					       "data load.\n");
					break;

				case 0x7:
					pr_cont(": Copyback Parity/Victim"
						" error.\n");
					break;

				case 0x8:
					pr_cont(": Tag Snoop error.\n");
					break;

				default:
					goto wrong_ic_mce;
					break;
				}
			}
		} else
			goto wrong_ic_mce;
	} else
		goto wrong_ic_mce;

	return;

wrong_ic_mce:
	pr_emerg(HW_ERR "Corrupted IC MCE info?\n");
}

static void amd_decode_bu_mce(struct mce *m)
{
	u32 ec = m->status & 0xffff;
	u32 xec = (m->status >> 16) & 0xf;

	pr_emerg(HW_ERR "Bus Unit Error");

	if (xec == 0x1)
		pr_cont(" in the write data buffers.\n");
	else if (xec == 0x3)
		pr_cont(" in the victim data buffers.\n");
	else if (xec == 0x2 && MEM_ERROR(ec))
		pr_cont(": %s error in the L2 cache tags.\n", RRRR_MSG(ec));
	else if (xec == 0x0) {
		if (TLB_ERROR(ec))
			pr_cont(": %s error in a Page Descriptor Cache or "
				"Guest TLB.\n", TT_MSG(ec));
		else if (BUS_ERROR(ec))
			pr_cont(": %s/ECC error in data read from NB: %s.\n",
				RRRR_MSG(ec), PP_MSG(ec));
		else if (MEM_ERROR(ec)) {
			u8 rrrr = (ec >> 4) & 0xf;

			if (rrrr >= 0x7)
				pr_cont(": %s error during data copyback.\n",
					RRRR_MSG(ec));
			else if (rrrr <= 0x1)
				pr_cont(": %s parity/ECC error during data "
					"access from L2.\n", RRRR_MSG(ec));
			else
				goto wrong_bu_mce;
		} else
			goto wrong_bu_mce;
	} else
		goto wrong_bu_mce;

	return;

wrong_bu_mce:
	pr_emerg(HW_ERR "Corrupted BU MCE info?\n");
}

static void amd_decode_ls_mce(struct mce *m)
{
	u32 ec  = m->status & 0xffff;
	u32 xec = (m->status >> 16) & 0xf;

	pr_emerg(HW_ERR "Load Store Error");

	if (xec == 0x0) {
		u8 rrrr = (ec >> 4) & 0xf;

		if (!BUS_ERROR(ec) || (rrrr != 0x3 && rrrr != 0x4))
			goto wrong_ls_mce;

		pr_cont(" during %s.\n", RRRR_MSG(ec));
	}
	return;

wrong_ls_mce:
	pr_emerg(HW_ERR "Corrupted LS MCE info?\n");
}

void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
{
	u32 ec   = m->status & 0xffff;
	u32 nbsh = (u32)(m->status >> 32);
	u32 nbsl = (u32)m->status;

	/*
	 * GART TLB error reporting is disabled by default. Bail out early.
	 */
	if (TLB_ERROR(ec) && !report_gart_errors)
		return;

	pr_emerg(HW_ERR "Northbridge Error, node %d", node_id);

	/*
	 * F10h, revD can disable ErrCpu[3:0] so check that first and also the
	 * value encoding has changed so interpret those differently
	 */
	if ((boot_cpu_data.x86 == 0x10) &&
	    (boot_cpu_data.x86_model > 7)) {
		if (nbsh & K8_NBSH_ERR_CPU_VAL)
			pr_cont(", core: %u\n", (u8)(nbsh & 0xf));
	} else {
		u8 assoc_cpus = nbsh & 0xf;

		if (assoc_cpus > 0)
			pr_cont(", core: %d", fls(assoc_cpus) - 1);

		pr_cont("\n");
	}

	pr_emerg(HW_ERR "%s.\n", EXT_ERR_MSG(nbsl));

	if (BUS_ERROR(ec) && nb_bus_decoder)
		nb_bus_decoder(node_id, m, nbcfg);
}
EXPORT_SYMBOL_GPL(amd_decode_nb_mce);

static void amd_decode_fr_mce(struct mce *m)
{
	/* we have only one error signature so match all fields at once. */
	if ((m->status & 0xffff) == 0x0f0f)
		pr_emerg(HW_ERR " FR Error: CPU Watchdog timer expire.\n");
	else
		pr_emerg(HW_ERR "Corrupted FR MCE info?\n");
}

static inline void amd_decode_err_code(u16 ec)
{
	if (TLB_ERROR(ec)) {
		pr_emerg(HW_ERR "Transaction: %s, Cache Level: %s\n",
			 TT_MSG(ec), LL_MSG(ec));
	} else if (MEM_ERROR(ec)) {
		pr_emerg(HW_ERR "Transaction: %s, Type: %s, Cache Level: %s\n",
			 RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
	} else if (BUS_ERROR(ec)) {
		pr_emerg(HW_ERR "Transaction: %s (%s), %s, Cache Level: %s, "
			 "Participating Processor: %s\n",
			  RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
			  PP_MSG(ec));
	} else
		pr_emerg(HW_ERR "Huh? Unknown MCE error 0x%x\n", ec);
}

int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
{
	struct mce *m = (struct mce *)data;
	int node, ecc;

	pr_emerg(HW_ERR "MC%d_STATUS: ", m->bank);

	pr_cont("%sorrected error, other errors lost: %s, "
		 "CPU context corrupt: %s",
		 ((m->status & MCI_STATUS_UC) ? "Unc"  : "C"),
		 ((m->status & MCI_STATUS_OVER) ? "yes"  : "no"),
		 ((m->status & MCI_STATUS_PCC) ? "yes" : "no"));

	/* do the two bits[14:13] together */
	ecc = (m->status >> 45) & 0x3;
	if (ecc)
		pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));

	pr_cont("\n");

	switch (m->bank) {
	case 0:
		amd_decode_dc_mce(m);
		break;

	case 1:
		amd_decode_ic_mce(m);
		break;

	case 2:
		amd_decode_bu_mce(m);
		break;

	case 3:
		amd_decode_ls_mce(m);
		break;

	case 4:
		node = amd_get_nb_id(m->extcpu);
		amd_decode_nb_mce(node, m, 0);
		break;

	case 5:
		amd_decode_fr_mce(m);
		break;

	default:
		break;
	}

	amd_decode_err_code(m->status & 0xffff);

	return NOTIFY_STOP;
}
EXPORT_SYMBOL_GPL(amd_decode_mce);

static struct notifier_block amd_mce_dec_nb = {
	.notifier_call	= amd_decode_mce,
};

static int __init mce_amd_init(void)
{
	/*
	 * We can decode MCEs for K8, F10h and F11h CPUs:
	 */
	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
		return 0;

	if (boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11)
		return 0;

	atomic_notifier_chain_register(&x86_mce_decoder_chain, &amd_mce_dec_nb);

	return 0;
}
early_initcall(mce_amd_init);

#ifdef MODULE
static void __exit mce_amd_exit(void)
{
	atomic_notifier_chain_unregister(&x86_mce_decoder_chain, &amd_mce_dec_nb);
}

MODULE_DESCRIPTION("AMD MCE decoder");
MODULE_ALIAS("edac-mce-amd");
MODULE_LICENSE("GPL");
module_exit(mce_amd_exit);
#endif
Commit	Line	Data
b70ef010 BP	1	#include <linux/module.h>
b70ef010 BP	2	#include "edac_mce_amd.h"
b52401ce	3
549d042d	4	static bool report_gart_errors;
7cfd4a87	5	static void (nb_bus_decoder)(int node_id, struct mce m, u32 nbcfg);
549d042d BP	6
	7	void amd_report_gart_errors(bool v)
	8	{
	9	report_gart_errors = v;
	10	}
	11	EXPORT_SYMBOL_GPL(amd_report_gart_errors);
	12
7cfd4a87	13	void amd_register_ecc_decoder(void (f)(int, struct mce , u32))
549d042d BP	14	{
	15	nb_bus_decoder = f;
	16	}
	17	EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
	18
7cfd4a87	19	void amd_unregister_ecc_decoder(void (f)(int, struct mce , u32))
549d042d BP	20	{
	21	if (nb_bus_decoder) {
	22	WARN_ON(nb_bus_decoder != f);
	23
	24	nb_bus_decoder = NULL;
	25	}
	26	}
	27	EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
	28
b52401ce DT	29	/*
	30	* string representation for the different MCA reported error types, see F3x48
	31	* or MSR0000_0411.
	32	*/
6337583d BP	33
	34	/* transaction type */
	35	const char *tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
b70ef010	36	EXPORT_SYMBOL_GPL(tt_msgs);
b52401ce	37
6337583d BP	38	/* cache level */
6337583d BP	39	const char *ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
b70ef010	40	EXPORT_SYMBOL_GPL(ll_msgs);
b52401ce	41
6337583d	42	/* memory transaction type */
b52401ce	43	const char *rrrr_msgs[] = {
6337583d	44	"GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
b52401ce	45	};
b70ef010	46	EXPORT_SYMBOL_GPL(rrrr_msgs);
b52401ce	47
6337583d BP	48	/* participating processor */
6337583d BP	49	const char *pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
b70ef010	50	EXPORT_SYMBOL_GPL(pp_msgs);
b52401ce	51
6337583d BP	52	/* request timeout */
6337583d BP	53	const char *to_msgs[] = { "no timeout", "timed out" };
b70ef010	54	EXPORT_SYMBOL_GPL(to_msgs);
b52401ce	55
6337583d BP	56	/* memory or i/o */
6337583d BP	57	const char *ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
b70ef010	58	EXPORT_SYMBOL_GPL(ii_msgs);
b52401ce	59
1c43f2e2 BP	60	/*
	61	* Map the 4 or 5 (family-specific) bits of Extended Error code to the
	62	* string table.
	63	*/
	64	const char *ext_msgs[] = {
	65	"K8 ECC error", /* 0_0000b */
	66	"CRC error on link", /* 0_0001b */
	67	"Sync error packets on link", /* 0_0010b */
	68	"Master Abort during link operation", /* 0_0011b */
	69	"Target Abort during link operation", /* 0_0100b */
	70	"Invalid GART PTE entry during table walk", /* 0_0101b */
	71	"Unsupported atomic RMW command received", /* 0_0110b */
	72	"WDT error: NB transaction timeout", /* 0_0111b */
	73	"ECC/ChipKill ECC error", /* 0_1000b */
	74	"SVM DEV Error", /* 0_1001b */
	75	"Link Data error", /* 0_1010b */
	76	"Link/L3/Probe Filter Protocol error", /* 0_1011b */
	77	"NB Internal Arrays Parity error", /* 0_1100b */
	78	"DRAM Address/Control Parity error", /* 0_1101b */
	79	"Link Transmission error", /* 0_1110b */
	80	"GART/DEV Table Walk Data error" /* 0_1111b */
	81	"Res 0x100 error", /* 1_0000b */
	82	"Res 0x101 error", /* 1_0001b */
	83	"Res 0x102 error", /* 1_0010b */
	84	"Res 0x103 error", /* 1_0011b */
	85	"Res 0x104 error", /* 1_0100b */
	86	"Res 0x105 error", /* 1_0101b */
	87	"Res 0x106 error", /* 1_0110b */
	88	"Res 0x107 error", /* 1_0111b */
	89	"Res 0x108 error", /* 1_1000b */
	90	"Res 0x109 error", /* 1_1001b */
	91	"Res 0x10A error", /* 1_1010b */
	92	"Res 0x10B error", /* 1_1011b */
	93	"ECC error in L3 Cache Data", /* 1_1100b */
	94	"L3 Cache Tag error", /* 1_1101b */
	95	"L3 Cache LRU Parity error", /* 1_1110b */
	96	"Probe Filter error" /* 1_1111b */
b52401ce	97	};
b70ef010	98	EXPORT_SYMBOL_GPL(ext_msgs);
549d042d	99
7cfd4a87	100	static void amd_decode_dc_mce(struct mce *m)
51966241	101	{
7cfd4a87 BP	102	u32 ec = m->status & 0xffff;
7cfd4a87 BP	103	u32 xec = (m->status >> 16) & 0xf;
51966241	104
c9f281fd	105	pr_emerg(HW_ERR "Data Cache Error: ");
51966241 BP	106
	107	if (xec == 1 && TLB_ERROR(ec))
	108	pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
	109	else if (xec == 0) {
7cfd4a87	110	if (m->status & (1ULL << 40))
51966241 BP	111	pr_cont(" during Data Scrub.\n");
	112	else if (TLB_ERROR(ec))
	113	pr_cont(": %s TLB parity error.\n", LL_MSG(ec));
	114	else if (MEM_ERROR(ec)) {
	115	u8 ll = ec & 0x3;
	116	u8 tt = (ec >> 2) & 0x3;
	117	u8 rrrr = (ec >> 4) & 0xf;
	118
	119	/* see F10h BKDG (31116), Table 92. */
	120	if (ll == 0x1) {
	121	if (tt != 0x1)
	122	goto wrong_dc_mce;
	123
	124	pr_cont(": Data/Tag %s error.\n", RRRR_MSG(ec));
	125
	126	} else if (ll == 0x2 && rrrr == 0x3)
	127	pr_cont(" during L1 linefill from L2.\n");
	128	else
	129	goto wrong_dc_mce;
	130	} else if (BUS_ERROR(ec) && boot_cpu_data.x86 == 0xf)
	131	pr_cont(" during system linefill.\n");
	132	else
	133	goto wrong_dc_mce;
	134	} else
	135	goto wrong_dc_mce;
	136
	137	return;
	138
	139	wrong_dc_mce:
c9f281fd	140	pr_emerg(HW_ERR "Corrupted DC MCE info?\n");
51966241 BP	141	}
51966241 BP	142
7cfd4a87	143	static void amd_decode_ic_mce(struct mce *m)
ab5535e7	144	{
7cfd4a87 BP	145	u32 ec = m->status & 0xffff;
7cfd4a87 BP	146	u32 xec = (m->status >> 16) & 0xf;
ab5535e7	147
c9f281fd	148	pr_emerg(HW_ERR "Instruction Cache Error");
ab5535e7 BP	149
	150	if (xec == 1 && TLB_ERROR(ec))
	151	pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
	152	else if (xec == 0) {
	153	if (TLB_ERROR(ec))
	154	pr_cont(": %s TLB Parity error.\n", LL_MSG(ec));
	155	else if (BUS_ERROR(ec)) {
	156	if (boot_cpu_data.x86 == 0xf &&
7cfd4a87	157	(m->status & BIT(58)))
ab5535e7 BP	158	pr_cont(" during system linefill.\n");
	159	else
	160	pr_cont(" during attempted NB data read.\n");
	161	} else if (MEM_ERROR(ec)) {
	162	u8 ll = ec & 0x3;
	163	u8 rrrr = (ec >> 4) & 0xf;
	164
	165	if (ll == 0x2)
	166	pr_cont(" during a linefill from L2.\n");
	167	else if (ll == 0x1) {
	168
	169	switch (rrrr) {
	170	case 0x5:
	171	pr_cont(": Parity error during "
	172	"data load.\n");
	173	break;
	174
	175	case 0x7:
	176	pr_cont(": Copyback Parity/Victim"
	177	" error.\n");
	178	break;
	179
	180	case 0x8:
	181	pr_cont(": Tag Snoop error.\n");
	182	break;
	183
	184	default:
	185	goto wrong_ic_mce;
	186	break;
	187	}
	188	}
	189	} else
	190	goto wrong_ic_mce;
	191	} else
	192	goto wrong_ic_mce;
	193
	194	return;
	195
	196	wrong_ic_mce:
c9f281fd	197	pr_emerg(HW_ERR "Corrupted IC MCE info?\n");
ab5535e7 BP	198	}
ab5535e7 BP	199
7cfd4a87	200	static void amd_decode_bu_mce(struct mce *m)
56cad2d6	201	{
7cfd4a87 BP	202	u32 ec = m->status & 0xffff;
7cfd4a87 BP	203	u32 xec = (m->status >> 16) & 0xf;
56cad2d6	204
c9f281fd	205	pr_emerg(HW_ERR "Bus Unit Error");
56cad2d6 BP	206
	207	if (xec == 0x1)
	208	pr_cont(" in the write data buffers.\n");
	209	else if (xec == 0x3)
	210	pr_cont(" in the victim data buffers.\n");
	211	else if (xec == 0x2 && MEM_ERROR(ec))
	212	pr_cont(": %s error in the L2 cache tags.\n", RRRR_MSG(ec));
	213	else if (xec == 0x0) {
	214	if (TLB_ERROR(ec))
	215	pr_cont(": %s error in a Page Descriptor Cache or "
	216	"Guest TLB.\n", TT_MSG(ec));
	217	else if (BUS_ERROR(ec))
	218	pr_cont(": %s/ECC error in data read from NB: %s.\n",
	219	RRRR_MSG(ec), PP_MSG(ec));
	220	else if (MEM_ERROR(ec)) {
	221	u8 rrrr = (ec >> 4) & 0xf;
	222
	223	if (rrrr >= 0x7)
	224	pr_cont(": %s error during data copyback.\n",
	225	RRRR_MSG(ec));
	226	else if (rrrr <= 0x1)
	227	pr_cont(": %s parity/ECC error during data "
	228	"access from L2.\n", RRRR_MSG(ec));
	229	else
	230	goto wrong_bu_mce;
	231	} else
	232	goto wrong_bu_mce;
	233	} else
	234	goto wrong_bu_mce;
	235
	236	return;
	237
	238	wrong_bu_mce:
c9f281fd	239	pr_emerg(HW_ERR "Corrupted BU MCE info?\n");
56cad2d6 BP	240	}
56cad2d6 BP	241
7cfd4a87	242	static void amd_decode_ls_mce(struct mce *m)
f9350efd	243	{
7cfd4a87 BP	244	u32 ec = m->status & 0xffff;
7cfd4a87 BP	245	u32 xec = (m->status >> 16) & 0xf;
f9350efd	246
c9f281fd	247	pr_emerg(HW_ERR "Load Store Error");
f9350efd BP	248
	249	if (xec == 0x0) {
	250	u8 rrrr = (ec >> 4) & 0xf;
	251
	252	if (!BUS_ERROR(ec) \|\| (rrrr != 0x3 && rrrr != 0x4))
	253	goto wrong_ls_mce;
	254
	255	pr_cont(" during %s.\n", RRRR_MSG(ec));
	256	}
	257	return;
	258
	259	wrong_ls_mce:
c9f281fd	260	pr_emerg(HW_ERR "Corrupted LS MCE info?\n");
f9350efd BP	261	}
f9350efd BP	262
7cfd4a87	263	void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
549d042d	264	{
7cfd4a87 BP	265	u32 ec = m->status & 0xffff;
	266	u32 nbsh = (u32)(m->status >> 32);
	267	u32 nbsl = (u32)m->status;
549d042d	268
256f7276 BP	269	/*
	270	* GART TLB error reporting is disabled by default. Bail out early.
	271	*/
	272	if (TLB_ERROR(ec) && !report_gart_errors)
	273	return;
	274
c9f281fd	275	pr_emerg(HW_ERR "Northbridge Error, node %d", node_id);
549d042d BP	276
	277	/*
	278	* F10h, revD can disable ErrCpu[3:0] so check that first and also the
	279	* value encoding has changed so interpret those differently
	280	*/
	281	if ((boot_cpu_data.x86 == 0x10) &&
cec7924f	282	(boot_cpu_data.x86_model > 7)) {
7cfd4a87 BP	283	if (nbsh & K8_NBSH_ERR_CPU_VAL)
7cfd4a87 BP	284	pr_cont(", core: %u\n", (u8)(nbsh & 0xf));
549d042d	285	} else {
7cfd4a87	286	u8 assoc_cpus = nbsh & 0xf;
5b89d2f9 BP	287
	288	if (assoc_cpus > 0)
	289	pr_cont(", core: %d", fls(assoc_cpus) - 1);
	290
	291	pr_cont("\n");
549d042d BP	292	}
549d042d BP	293
7cfd4a87	294	pr_emerg(HW_ERR "%s.\n", EXT_ERR_MSG(nbsl));
d93cc222 BP	295
d93cc222 BP	296	if (BUS_ERROR(ec) && nb_bus_decoder)
7cfd4a87	297	nb_bus_decoder(node_id, m, nbcfg);
d93cc222 BP	298	}
	299	EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
	300
7cfd4a87	301	static void amd_decode_fr_mce(struct mce *m)
53bd5fed BP	302	{
53bd5fed BP	303	/* we have only one error signature so match all fields at once. */
7cfd4a87	304	if ((m->status & 0xffff) == 0x0f0f)
c9f281fd	305	pr_emerg(HW_ERR " FR Error: CPU Watchdog timer expire.\n");
53bd5fed	306	else
c9f281fd	307	pr_emerg(HW_ERR "Corrupted FR MCE info?\n");
53bd5fed BP	308	}
53bd5fed BP	309
6337583d	310	static inline void amd_decode_err_code(u16 ec)
d93cc222	311	{
549d042d	312	if (TLB_ERROR(ec)) {
c9f281fd	313	pr_emerg(HW_ERR "Transaction: %s, Cache Level: %s\n",
549d042d BP	314	TT_MSG(ec), LL_MSG(ec));
549d042d BP	315	} else if (MEM_ERROR(ec)) {
6337583d	316	pr_emerg(HW_ERR "Transaction: %s, Type: %s, Cache Level: %s\n",
549d042d BP	317	RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
549d042d BP	318	} else if (BUS_ERROR(ec)) {
6337583d	319	pr_emerg(HW_ERR "Transaction: %s (%s), %s, Cache Level: %s, "
d93cc222 BP	320	"Participating Processor: %s\n",
	321	RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
	322	PP_MSG(ec));
	323	} else
c9f281fd	324	pr_emerg(HW_ERR "Huh? Unknown MCE error 0x%x\n", ec);
549d042d	325	}
549d042d	326
9cdeb404	327	int amd_decode_mce(struct notifier_block nb, unsigned long val, void data)
549d042d	328	{
fb253195	329	struct mce m = (struct mce )data;
b69b29de	330	int node, ecc;
549d042d	331
c9f281fd	332	pr_emerg(HW_ERR "MC%d_STATUS: ", m->bank);
549d042d	333
37b7370a	334	pr_cont("%sorrected error, other errors lost: %s, "
b69b29de BP	335	"CPU context corrupt: %s",
b69b29de BP	336	((m->status & MCI_STATUS_UC) ? "Unc" : "C"),
37b7370a	337	((m->status & MCI_STATUS_OVER) ? "yes" : "no"),
b69b29de	338	((m->status & MCI_STATUS_PCC) ? "yes" : "no"));
549d042d	339
b69b29de	340	/* do the two bits[14:13] together */
35d824b2	341	ecc = (m->status >> 45) & 0x3;
b69b29de BP	342	if (ecc)
	343	pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));
	344
	345	pr_cont("\n");
	346
51966241 BP	347	switch (m->bank) {
51966241 BP	348	case 0:
7cfd4a87	349	amd_decode_dc_mce(m);
51966241	350	break;
d93cc222	351
ab5535e7	352	case 1:
7cfd4a87	353	amd_decode_ic_mce(m);
ab5535e7 BP	354	break;
ab5535e7 BP	355
56cad2d6	356	case 2:
7cfd4a87	357	amd_decode_bu_mce(m);
56cad2d6 BP	358	break;
56cad2d6 BP	359
f9350efd	360	case 3:
7cfd4a87	361	amd_decode_ls_mce(m);
f9350efd BP	362	break;
f9350efd BP	363
51966241	364	case 4:
7cfd4a87 BP	365	node = amd_get_nb_id(m->extcpu);
7cfd4a87 BP	366	amd_decode_nb_mce(node, m, 0);
51966241 BP	367	break;
51966241 BP	368
53bd5fed	369	case 5:
7cfd4a87	370	amd_decode_fr_mce(m);
53bd5fed BP	371	break;
53bd5fed BP	372
51966241 BP	373	default:
51966241 BP	374	break;
b69b29de	375	}
51966241 BP	376
51966241 BP	377	amd_decode_err_code(m->status & 0xffff);
fb253195 BP	378
fb253195 BP	379	return NOTIFY_STOP;
549d042d	380	}
9cdeb404	381	EXPORT_SYMBOL_GPL(amd_decode_mce);
f436f8bb	382
fb253195 BP	383	static struct notifier_block amd_mce_dec_nb = {
	384	.notifier_call = amd_decode_mce,
	385	};
	386
f436f8bb IM	387	static int __init mce_amd_init(void)
	388	{
	389	/*
e045c291	390	* We can decode MCEs for K8, F10h and F11h CPUs:
f436f8bb	391	*/
e045c291 BP	392	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
	393	return 0;
	394
	395	if (boot_cpu_data.x86 < 0xf \|\| boot_cpu_data.x86 > 0x11)
	396	return 0;
	397
	398	atomic_notifier_chain_register(&x86_mce_decoder_chain, &amd_mce_dec_nb);
f436f8bb IM	399
	400	return 0;
	401	}
	402	early_initcall(mce_amd_init);
0d18b2e3 BP	403
	404	#ifdef MODULE
	405	static void __exit mce_amd_exit(void)
	406	{
fb253195	407	atomic_notifier_chain_unregister(&x86_mce_decoder_chain, &amd_mce_dec_nb);
0d18b2e3 BP	408	}
	409
	410	MODULE_DESCRIPTION("AMD MCE decoder");
	411	MODULE_ALIAS("edac-mce-amd");
	412	MODULE_LICENSE("GPL");
	413	module_exit(mce_amd_exit);
	414	#endif