[deliverable/linux.git] / drivers / edac / edac_mce_amd.c

#include <linux/module.h>
#include "edac_mce_amd.h"

static bool report_gart_errors;
static void (*nb_bus_decoder)(int node_id, struct err_regs *regs);
static void (*orig_mce_callback)(struct mce *m);

void amd_report_gart_errors(bool v)
{
	report_gart_errors = v;
}
EXPORT_SYMBOL_GPL(amd_report_gart_errors);

void amd_register_ecc_decoder(void (*f)(int, struct err_regs *))
{
	nb_bus_decoder = f;
}
EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);

void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *))
{
	if (nb_bus_decoder) {
		WARN_ON(nb_bus_decoder != f);

		nb_bus_decoder = NULL;
	}
}
EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);

/*
 * string representation for the different MCA reported error types, see F3x48
 * or MSR0000_0411.
 */
const char *tt_msgs[] = {        /* transaction type */
	"instruction",
	"data",
	"generic",
	"reserved"
};
EXPORT_SYMBOL_GPL(tt_msgs);

const char *ll_msgs[] = {	/* cache level */
	"L0",
	"L1",
	"L2",
	"L3/generic"
};
EXPORT_SYMBOL_GPL(ll_msgs);

const char *rrrr_msgs[] = {
	"generic",
	"generic read",
	"generic write",
	"data read",
	"data write",
	"inst fetch",
	"prefetch",
	"evict",
	"snoop",
	"reserved RRRR= 9",
	"reserved RRRR= 10",
	"reserved RRRR= 11",
	"reserved RRRR= 12",
	"reserved RRRR= 13",
	"reserved RRRR= 14",
	"reserved RRRR= 15"
};
EXPORT_SYMBOL_GPL(rrrr_msgs);

const char *pp_msgs[] = {	/* participating processor */
	"local node originated (SRC)",
	"local node responded to request (RES)",
	"local node observed as 3rd party (OBS)",
	"generic"
};
EXPORT_SYMBOL_GPL(pp_msgs);

const char *to_msgs[] = {
	"no timeout",
	"timed out"
};
EXPORT_SYMBOL_GPL(to_msgs);

const char *ii_msgs[] = {	/* memory or i/o */
	"mem access",
	"reserved",
	"i/o access",
	"generic"
};
EXPORT_SYMBOL_GPL(ii_msgs);

/*
 * Map the 4 or 5 (family-specific) bits of Extended Error code to the
 * string table.
 */
const char *ext_msgs[] = {
	"K8 ECC error",					/* 0_0000b */
	"CRC error on link",				/* 0_0001b */
	"Sync error packets on link",			/* 0_0010b */
	"Master Abort during link operation",		/* 0_0011b */
	"Target Abort during link operation",		/* 0_0100b */
	"Invalid GART PTE entry during table walk",	/* 0_0101b */
	"Unsupported atomic RMW command received",	/* 0_0110b */
	"WDT error: NB transaction timeout",		/* 0_0111b */
	"ECC/ChipKill ECC error",			/* 0_1000b */
	"SVM DEV Error",				/* 0_1001b */
	"Link Data error",				/* 0_1010b */
	"Link/L3/Probe Filter Protocol error",		/* 0_1011b */
	"NB Internal Arrays Parity error",		/* 0_1100b */
	"DRAM Address/Control Parity error",		/* 0_1101b */
	"Link Transmission error",			/* 0_1110b */
	"GART/DEV Table Walk Data error"		/* 0_1111b */
	"Res 0x100 error",				/* 1_0000b */
	"Res 0x101 error",				/* 1_0001b */
	"Res 0x102 error",				/* 1_0010b */
	"Res 0x103 error",				/* 1_0011b */
	"Res 0x104 error",				/* 1_0100b */
	"Res 0x105 error",				/* 1_0101b */
	"Res 0x106 error",				/* 1_0110b */
	"Res 0x107 error",				/* 1_0111b */
	"Res 0x108 error",				/* 1_1000b */
	"Res 0x109 error",				/* 1_1001b */
	"Res 0x10A error",				/* 1_1010b */
	"Res 0x10B error",				/* 1_1011b */
	"ECC error in L3 Cache Data",			/* 1_1100b */
	"L3 Cache Tag error",				/* 1_1101b */
	"L3 Cache LRU Parity error",			/* 1_1110b */
	"Probe Filter error"				/* 1_1111b */
};
EXPORT_SYMBOL_GPL(ext_msgs);

static void amd_decode_dc_mce(u64 mc0_status)
{
	u32 ec  = mc0_status & 0xffff;
	u32 xec = (mc0_status >> 16) & 0xf;

	pr_emerg(" Data Cache Error");

	if (xec == 1 && TLB_ERROR(ec))
		pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
	else if (xec == 0) {
		if (mc0_status & (1ULL << 40))
			pr_cont(" during Data Scrub.\n");
		else if (TLB_ERROR(ec))
			pr_cont(": %s TLB parity error.\n", LL_MSG(ec));
		else if (MEM_ERROR(ec)) {
			u8 ll   = ec & 0x3;
			u8 tt   = (ec >> 2) & 0x3;
			u8 rrrr = (ec >> 4) & 0xf;

			/* see F10h BKDG (31116), Table 92. */
			if (ll == 0x1) {
				if (tt != 0x1)
					goto wrong_dc_mce;

				pr_cont(": Data/Tag %s error.\n", RRRR_MSG(ec));

			} else if (ll == 0x2 && rrrr == 0x3)
				pr_cont(" during L1 linefill from L2.\n");
			else
				goto wrong_dc_mce;
		} else if (BUS_ERROR(ec) && boot_cpu_data.x86 == 0xf)
			pr_cont(" during system linefill.\n");
		else
			goto wrong_dc_mce;
	} else
		goto wrong_dc_mce;

	return;

wrong_dc_mce:
	pr_warning("Corrupted DC MCE info?\n");
}

static void amd_decode_ic_mce(u64 mc1_status)
{
	u32 ec  = mc1_status & 0xffff;
	u32 xec = (mc1_status >> 16) & 0xf;

	pr_emerg(" Instruction Cache Error");

	if (xec == 1 && TLB_ERROR(ec))
		pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
	else if (xec == 0) {
		if (TLB_ERROR(ec))
			pr_cont(": %s TLB Parity error.\n", LL_MSG(ec));
		else if (BUS_ERROR(ec)) {
			if (boot_cpu_data.x86 == 0xf &&
			    (mc1_status & (1ULL << 58)))
				pr_cont(" during system linefill.\n");
			else
				pr_cont(" during attempted NB data read.\n");
		} else if (MEM_ERROR(ec)) {
			u8 ll   = ec & 0x3;
			u8 rrrr = (ec >> 4) & 0xf;

			if (ll == 0x2)
				pr_cont(" during a linefill from L2.\n");
			else if (ll == 0x1) {

				switch (rrrr) {
				case 0x5:
					pr_cont(": Parity error during "
					       "data load.\n");
					break;

				case 0x7:
					pr_cont(": Copyback Parity/Victim"
						" error.\n");
					break;

				case 0x8:
					pr_cont(": Tag Snoop error.\n");
					break;

				default:
					goto wrong_ic_mce;
					break;
				}
			}
		} else
			goto wrong_ic_mce;
	} else
		goto wrong_ic_mce;

	return;

wrong_ic_mce:
	pr_warning("Corrupted IC MCE info?\n");
}

static void amd_decode_bu_mce(u64 mc2_status)
{
	u32 ec = mc2_status & 0xffff;
	u32 xec = (mc2_status >> 16) & 0xf;

	pr_emerg(" Bus Unit Error");

	if (xec == 0x1)
		pr_cont(" in the write data buffers.\n");
	else if (xec == 0x3)
		pr_cont(" in the victim data buffers.\n");
	else if (xec == 0x2 && MEM_ERROR(ec))
		pr_cont(": %s error in the L2 cache tags.\n", RRRR_MSG(ec));
	else if (xec == 0x0) {
		if (TLB_ERROR(ec))
			pr_cont(": %s error in a Page Descriptor Cache or "
				"Guest TLB.\n", TT_MSG(ec));
		else if (BUS_ERROR(ec))
			pr_cont(": %s/ECC error in data read from NB: %s.\n",
				RRRR_MSG(ec), PP_MSG(ec));
		else if (MEM_ERROR(ec)) {
			u8 rrrr = (ec >> 4) & 0xf;

			if (rrrr >= 0x7)
				pr_cont(": %s error during data copyback.\n",
					RRRR_MSG(ec));
			else if (rrrr <= 0x1)
				pr_cont(": %s parity/ECC error during data "
					"access from L2.\n", RRRR_MSG(ec));
			else
				goto wrong_bu_mce;
		} else
			goto wrong_bu_mce;
	} else
		goto wrong_bu_mce;

	return;

wrong_bu_mce:
	pr_warning("Corrupted BU MCE info?\n");
}

static void amd_decode_ls_mce(u64 mc3_status)
{
	u32 ec  = mc3_status & 0xffff;
	u32 xec = (mc3_status >> 16) & 0xf;

	pr_emerg(" Load Store Error");

	if (xec == 0x0) {
		u8 rrrr = (ec >> 4) & 0xf;

		if (!BUS_ERROR(ec) || (rrrr != 0x3 && rrrr != 0x4))
			goto wrong_ls_mce;

		pr_cont(" during %s.\n", RRRR_MSG(ec));
	}
	return;

wrong_ls_mce:
	pr_warning("Corrupted LS MCE info?\n");
}

void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
{
	u32 ec  = ERROR_CODE(regs->nbsl);
	u32 xec = EXT_ERROR_CODE(regs->nbsl);

	if (!handle_errors)
		return;

	pr_emerg(" Northbridge Error, node %d", node_id);

	/*
	 * F10h, revD can disable ErrCpu[3:0] so check that first and also the
	 * value encoding has changed so interpret those differently
	 */
	if ((boot_cpu_data.x86 == 0x10) &&
	    (boot_cpu_data.x86_model > 8)) {
		if (regs->nbsh & K8_NBSH_ERR_CPU_VAL)
			pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf));
	} else {
		pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf)));
	}


	pr_emerg("%s.\n", EXT_ERR_MSG(xec));

	if (BUS_ERROR(ec) && nb_bus_decoder)
		nb_bus_decoder(node_id, regs);
}
EXPORT_SYMBOL_GPL(amd_decode_nb_mce);

static void amd_decode_fr_mce(u64 mc5_status)
{
	/* we have only one error signature so match all fields at once. */
	if ((mc5_status & 0xffff) == 0x0f0f)
		pr_emerg(" FR Error: CPU Watchdog timer expire.\n");
	else
		pr_warning("Corrupted FR MCE info?\n");
}

static inline void amd_decode_err_code(unsigned int ec)
{
	if (TLB_ERROR(ec)) {
		/*
		 * GART errors are intended to help graphics driver developers
		 * to detect bad GART PTEs. It is recommended by AMD to disable
		 * GART table walk error reporting by default[1] (currently
		 * being disabled in mce_cpu_quirks()) and according to the
		 * comment in mce_cpu_quirks(), such GART errors can be
		 * incorrectly triggered. We may see these errors anyway and
		 * unless requested by the user, they won't be reported.
		 *
		 * [1] section 13.10.1 on BIOS and Kernel Developers Guide for
		 *     AMD NPT family 0Fh processors
		 */
		if (!report_gart_errors)
			return;

		pr_emerg(" Transaction: %s, Cache Level %s\n",
			 TT_MSG(ec), LL_MSG(ec));
	} else if (MEM_ERROR(ec)) {
		pr_emerg(" Transaction: %s, Type: %s, Cache Level: %s",
			 RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
	} else if (BUS_ERROR(ec)) {
		pr_emerg(" Transaction type: %s(%s), %s, Cache Level: %s, "
			 "Participating Processor: %s\n",
			  RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
			  PP_MSG(ec));
	} else
		pr_warning("Huh? Unknown MCE error 0x%x\n", ec);
}

static void amd_decode_mce(struct mce *m)
{
	struct err_regs regs;
	int node, ecc;

	pr_emerg("MC%d_STATUS: ", m->bank);

	pr_cont("%sorrected error, report: %s, MiscV: %svalid, "
		 "CPU context corrupt: %s",
		 ((m->status & MCI_STATUS_UC) ? "Unc"  : "C"),
		 ((m->status & MCI_STATUS_EN) ? "yes"  : "no"),
		 ((m->status & MCI_STATUS_MISCV) ? ""  : "in"),
		 ((m->status & MCI_STATUS_PCC) ? "yes" : "no"));

	/* do the two bits[14:13] together */
	ecc = m->status & (3ULL << 45);
	if (ecc)
		pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));

	pr_cont("\n");

	switch (m->bank) {
	case 0:
		amd_decode_dc_mce(m->status);
		break;

	case 1:
		amd_decode_ic_mce(m->status);
		break;

	case 2:
		amd_decode_bu_mce(m->status);
		break;

	case 3:
		amd_decode_ls_mce(m->status);
		break;

	case 4:
		regs.nbsl  = (u32) m->status;
		regs.nbsh  = (u32)(m->status >> 32);
		regs.nbeal = (u32) m->addr;
		regs.nbeah = (u32)(m->addr >> 32);
		node       = amd_get_nb_id(m->extcpu);

		amd_decode_nb_mce(node, &regs, 1);
		break;

	case 5:
		amd_decode_fr_mce(m->status);
		break;

	default:
		break;
	}

	amd_decode_err_code(m->status & 0xffff);
}

static int __init mce_amd_init(void)
{
	/*
	 * We can decode MCEs for Opteron and later CPUs:
	 */
	if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
	    (boot_cpu_data.x86 >= 0xf)) {
		/* safe the default decode mce callback */
		orig_mce_callback = x86_mce_decode_callback;

		x86_mce_decode_callback = amd_decode_mce;
	}

	return 0;
}
early_initcall(mce_amd_init);

#ifdef MODULE
static void __exit mce_amd_exit(void)
{
	x86_mce_decode_callback = orig_mce_callback;
}

MODULE_DESCRIPTION("AMD MCE decoder");
MODULE_ALIAS("edac-mce-amd");
MODULE_LICENSE("GPL");
module_exit(mce_amd_exit);
#endif
Commit	Line	Data
b70ef010 BP	1	#include <linux/module.h>
b70ef010 BP	2	#include "edac_mce_amd.h"
b52401ce	3
549d042d	4	static bool report_gart_errors;
b69b29de	5	static void (nb_bus_decoder)(int node_id, struct err_regs regs);
0d18b2e3	6	static void (orig_mce_callback)(struct mce m);
549d042d BP	7
	8	void amd_report_gart_errors(bool v)
	9	{
	10	report_gart_errors = v;
	11	}
	12	EXPORT_SYMBOL_GPL(amd_report_gart_errors);
	13
b69b29de	14	void amd_register_ecc_decoder(void (f)(int, struct err_regs ))
549d042d BP	15	{
	16	nb_bus_decoder = f;
	17	}
	18	EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
	19
b69b29de	20	void amd_unregister_ecc_decoder(void (f)(int, struct err_regs ))
549d042d BP	21	{
	22	if (nb_bus_decoder) {
	23	WARN_ON(nb_bus_decoder != f);
	24
	25	nb_bus_decoder = NULL;
	26	}
	27	}
	28	EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
	29
b52401ce DT	30	/*
	31	* string representation for the different MCA reported error types, see F3x48
	32	* or MSR0000_0411.
	33	*/
	34	const char tt_msgs[] = { / transaction type */
	35	"instruction",
	36	"data",
	37	"generic",
	38	"reserved"
	39	};
b70ef010	40	EXPORT_SYMBOL_GPL(tt_msgs);
b52401ce DT	41
	42	const char ll_msgs[] = { / cache level */
	43	"L0",
	44	"L1",
	45	"L2",
	46	"L3/generic"
	47	};
b70ef010	48	EXPORT_SYMBOL_GPL(ll_msgs);
b52401ce DT	49
	50	const char *rrrr_msgs[] = {
	51	"generic",
	52	"generic read",
	53	"generic write",
	54	"data read",
	55	"data write",
	56	"inst fetch",
	57	"prefetch",
	58	"evict",
	59	"snoop",
	60	"reserved RRRR= 9",
	61	"reserved RRRR= 10",
	62	"reserved RRRR= 11",
	63	"reserved RRRR= 12",
	64	"reserved RRRR= 13",
	65	"reserved RRRR= 14",
	66	"reserved RRRR= 15"
	67	};
b70ef010	68	EXPORT_SYMBOL_GPL(rrrr_msgs);
b52401ce DT	69
	70	const char pp_msgs[] = { / participating processor */
	71	"local node originated (SRC)",
	72	"local node responded to request (RES)",
	73	"local node observed as 3rd party (OBS)",
	74	"generic"
	75	};
b70ef010	76	EXPORT_SYMBOL_GPL(pp_msgs);
b52401ce DT	77
	78	const char *to_msgs[] = {
	79	"no timeout",
	80	"timed out"
	81	};
b70ef010	82	EXPORT_SYMBOL_GPL(to_msgs);
b52401ce DT	83
	84	const char ii_msgs[] = { / memory or i/o */
	85	"mem access",
	86	"reserved",
	87	"i/o access",
	88	"generic"
	89	};
b70ef010	90	EXPORT_SYMBOL_GPL(ii_msgs);
b52401ce	91
1c43f2e2 BP	92	/*
	93	* Map the 4 or 5 (family-specific) bits of Extended Error code to the
	94	* string table.
	95	*/
	96	const char *ext_msgs[] = {
	97	"K8 ECC error", /* 0_0000b */
	98	"CRC error on link", /* 0_0001b */
	99	"Sync error packets on link", /* 0_0010b */
	100	"Master Abort during link operation", /* 0_0011b */
	101	"Target Abort during link operation", /* 0_0100b */
	102	"Invalid GART PTE entry during table walk", /* 0_0101b */
	103	"Unsupported atomic RMW command received", /* 0_0110b */
	104	"WDT error: NB transaction timeout", /* 0_0111b */
	105	"ECC/ChipKill ECC error", /* 0_1000b */
	106	"SVM DEV Error", /* 0_1001b */
	107	"Link Data error", /* 0_1010b */
	108	"Link/L3/Probe Filter Protocol error", /* 0_1011b */
	109	"NB Internal Arrays Parity error", /* 0_1100b */
	110	"DRAM Address/Control Parity error", /* 0_1101b */
	111	"Link Transmission error", /* 0_1110b */
	112	"GART/DEV Table Walk Data error" /* 0_1111b */
	113	"Res 0x100 error", /* 1_0000b */
	114	"Res 0x101 error", /* 1_0001b */
	115	"Res 0x102 error", /* 1_0010b */
	116	"Res 0x103 error", /* 1_0011b */
	117	"Res 0x104 error", /* 1_0100b */
	118	"Res 0x105 error", /* 1_0101b */
	119	"Res 0x106 error", /* 1_0110b */
	120	"Res 0x107 error", /* 1_0111b */
	121	"Res 0x108 error", /* 1_1000b */
	122	"Res 0x109 error", /* 1_1001b */
	123	"Res 0x10A error", /* 1_1010b */
	124	"Res 0x10B error", /* 1_1011b */
	125	"ECC error in L3 Cache Data", /* 1_1100b */
	126	"L3 Cache Tag error", /* 1_1101b */
	127	"L3 Cache LRU Parity error", /* 1_1110b */
	128	"Probe Filter error" /* 1_1111b */
b52401ce	129	};
b70ef010	130	EXPORT_SYMBOL_GPL(ext_msgs);
549d042d	131
51966241 BP	132	static void amd_decode_dc_mce(u64 mc0_status)
	133	{
	134	u32 ec = mc0_status & 0xffff;
	135	u32 xec = (mc0_status >> 16) & 0xf;
	136
	137	pr_emerg(" Data Cache Error");
	138
	139	if (xec == 1 && TLB_ERROR(ec))
	140	pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
	141	else if (xec == 0) {
	142	if (mc0_status & (1ULL << 40))
	143	pr_cont(" during Data Scrub.\n");
	144	else if (TLB_ERROR(ec))
	145	pr_cont(": %s TLB parity error.\n", LL_MSG(ec));
	146	else if (MEM_ERROR(ec)) {
	147	u8 ll = ec & 0x3;
	148	u8 tt = (ec >> 2) & 0x3;
	149	u8 rrrr = (ec >> 4) & 0xf;
	150
	151	/* see F10h BKDG (31116), Table 92. */
	152	if (ll == 0x1) {
	153	if (tt != 0x1)
	154	goto wrong_dc_mce;
	155
	156	pr_cont(": Data/Tag %s error.\n", RRRR_MSG(ec));
	157
	158	} else if (ll == 0x2 && rrrr == 0x3)
	159	pr_cont(" during L1 linefill from L2.\n");
	160	else
	161	goto wrong_dc_mce;
	162	} else if (BUS_ERROR(ec) && boot_cpu_data.x86 == 0xf)
	163	pr_cont(" during system linefill.\n");
	164	else
	165	goto wrong_dc_mce;
	166	} else
	167	goto wrong_dc_mce;
	168
	169	return;
	170
	171	wrong_dc_mce:
	172	pr_warning("Corrupted DC MCE info?\n");
	173	}
	174
ab5535e7 BP	175	static void amd_decode_ic_mce(u64 mc1_status)
	176	{
	177	u32 ec = mc1_status & 0xffff;
	178	u32 xec = (mc1_status >> 16) & 0xf;
	179
	180	pr_emerg(" Instruction Cache Error");
	181
	182	if (xec == 1 && TLB_ERROR(ec))
	183	pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
	184	else if (xec == 0) {
	185	if (TLB_ERROR(ec))
	186	pr_cont(": %s TLB Parity error.\n", LL_MSG(ec));
	187	else if (BUS_ERROR(ec)) {
	188	if (boot_cpu_data.x86 == 0xf &&
	189	(mc1_status & (1ULL << 58)))
	190	pr_cont(" during system linefill.\n");
	191	else
	192	pr_cont(" during attempted NB data read.\n");
	193	} else if (MEM_ERROR(ec)) {
	194	u8 ll = ec & 0x3;
	195	u8 rrrr = (ec >> 4) & 0xf;
	196
	197	if (ll == 0x2)
	198	pr_cont(" during a linefill from L2.\n");
	199	else if (ll == 0x1) {
	200
	201	switch (rrrr) {
	202	case 0x5:
	203	pr_cont(": Parity error during "
	204	"data load.\n");
	205	break;
	206
	207	case 0x7:
	208	pr_cont(": Copyback Parity/Victim"
	209	" error.\n");
	210	break;
	211
	212	case 0x8:
	213	pr_cont(": Tag Snoop error.\n");
	214	break;
	215
	216	default:
	217	goto wrong_ic_mce;
	218	break;
	219	}
	220	}
	221	} else
	222	goto wrong_ic_mce;
	223	} else
	224	goto wrong_ic_mce;
	225
	226	return;
	227
	228	wrong_ic_mce:
	229	pr_warning("Corrupted IC MCE info?\n");
	230	}
	231
56cad2d6 BP	232	static void amd_decode_bu_mce(u64 mc2_status)
	233	{
	234	u32 ec = mc2_status & 0xffff;
	235	u32 xec = (mc2_status >> 16) & 0xf;
	236
	237	pr_emerg(" Bus Unit Error");
	238
	239	if (xec == 0x1)
	240	pr_cont(" in the write data buffers.\n");
	241	else if (xec == 0x3)
	242	pr_cont(" in the victim data buffers.\n");
	243	else if (xec == 0x2 && MEM_ERROR(ec))
	244	pr_cont(": %s error in the L2 cache tags.\n", RRRR_MSG(ec));
	245	else if (xec == 0x0) {
	246	if (TLB_ERROR(ec))
	247	pr_cont(": %s error in a Page Descriptor Cache or "
	248	"Guest TLB.\n", TT_MSG(ec));
	249	else if (BUS_ERROR(ec))
	250	pr_cont(": %s/ECC error in data read from NB: %s.\n",
	251	RRRR_MSG(ec), PP_MSG(ec));
	252	else if (MEM_ERROR(ec)) {
	253	u8 rrrr = (ec >> 4) & 0xf;
	254
	255	if (rrrr >= 0x7)
	256	pr_cont(": %s error during data copyback.\n",
	257	RRRR_MSG(ec));
	258	else if (rrrr <= 0x1)
	259	pr_cont(": %s parity/ECC error during data "
	260	"access from L2.\n", RRRR_MSG(ec));
	261	else
	262	goto wrong_bu_mce;
	263	} else
	264	goto wrong_bu_mce;
	265	} else
	266	goto wrong_bu_mce;
	267
	268	return;
	269
	270	wrong_bu_mce:
	271	pr_warning("Corrupted BU MCE info?\n");
	272	}
	273
f9350efd BP	274	static void amd_decode_ls_mce(u64 mc3_status)
	275	{
	276	u32 ec = mc3_status & 0xffff;
	277	u32 xec = (mc3_status >> 16) & 0xf;
	278
	279	pr_emerg(" Load Store Error");
	280
	281	if (xec == 0x0) {
	282	u8 rrrr = (ec >> 4) & 0xf;
	283
	284	if (!BUS_ERROR(ec) \|\| (rrrr != 0x3 && rrrr != 0x4))
	285	goto wrong_ls_mce;
	286
	287	pr_cont(" during %s.\n", RRRR_MSG(ec));
	288	}
	289	return;
	290
	291	wrong_ls_mce:
	292	pr_warning("Corrupted LS MCE info?\n");
	293	}
	294
549d042d BP	295	void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
549d042d BP	296	{
549d042d BP	297	u32 ec = ERROR_CODE(regs->nbsl);
	298	u32 xec = EXT_ERROR_CODE(regs->nbsl);
	299
	300	if (!handle_errors)
	301	return;
	302
	303	pr_emerg(" Northbridge Error, node %d", node_id);
	304
	305	/*
	306	* F10h, revD can disable ErrCpu[3:0] so check that first and also the
	307	* value encoding has changed so interpret those differently
	308	*/
	309	if ((boot_cpu_data.x86 == 0x10) &&
	310	(boot_cpu_data.x86_model > 8)) {
	311	if (regs->nbsh & K8_NBSH_ERR_CPU_VAL)
	312	pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf));
	313	} else {
	314	pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf)));
	315	}
	316
d93cc222 BP	317
	318	pr_emerg("%s.\n", EXT_ERR_MSG(xec));
	319
	320	if (BUS_ERROR(ec) && nb_bus_decoder)
	321	nb_bus_decoder(node_id, regs);
	322	}
	323	EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
	324
53bd5fed BP	325	static void amd_decode_fr_mce(u64 mc5_status)
	326	{
	327	/* we have only one error signature so match all fields at once. */
	328	if ((mc5_status & 0xffff) == 0x0f0f)
	329	pr_emerg(" FR Error: CPU Watchdog timer expire.\n");
	330	else
	331	pr_warning("Corrupted FR MCE info?\n");
	332	}
	333
d93cc222 BP	334	static inline void amd_decode_err_code(unsigned int ec)
d93cc222 BP	335	{
549d042d BP	336	if (TLB_ERROR(ec)) {
	337	/*
	338	* GART errors are intended to help graphics driver developers
	339	* to detect bad GART PTEs. It is recommended by AMD to disable
	340	* GART table walk error reporting by default[1] (currently
	341	* being disabled in mce_cpu_quirks()) and according to the
	342	* comment in mce_cpu_quirks(), such GART errors can be
	343	* incorrectly triggered. We may see these errors anyway and
	344	* unless requested by the user, they won't be reported.
	345	*
	346	* [1] section 13.10.1 on BIOS and Kernel Developers Guide for
	347	* AMD NPT family 0Fh processors
	348	*/
	349	if (!report_gart_errors)
	350	return;
	351
d93cc222	352	pr_emerg(" Transaction: %s, Cache Level %s\n",
549d042d BP	353	TT_MSG(ec), LL_MSG(ec));
549d042d BP	354	} else if (MEM_ERROR(ec)) {
d93cc222	355	pr_emerg(" Transaction: %s, Type: %s, Cache Level: %s",
549d042d BP	356	RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
549d042d BP	357	} else if (BUS_ERROR(ec)) {
d93cc222 BP	358	pr_emerg(" Transaction type: %s(%s), %s, Cache Level: %s, "
	359	"Participating Processor: %s\n",
	360	RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
	361	PP_MSG(ec));
	362	} else
	363	pr_warning("Huh? Unknown MCE error 0x%x\n", ec);
549d042d	364	}
549d042d	365
f436f8bb	366	static void amd_decode_mce(struct mce *m)
549d042d BP	367	{
549d042d BP	368	struct err_regs regs;
b69b29de	369	int node, ecc;
549d042d	370
d93cc222	371	pr_emerg("MC%d_STATUS: ", m->bank);
549d042d	372
d93cc222	373	pr_cont("%sorrected error, report: %s, MiscV: %svalid, "
b69b29de BP	374	"CPU context corrupt: %s",
	375	((m->status & MCI_STATUS_UC) ? "Unc" : "C"),
	376	((m->status & MCI_STATUS_EN) ? "yes" : "no"),
	377	((m->status & MCI_STATUS_MISCV) ? "" : "in"),
	378	((m->status & MCI_STATUS_PCC) ? "yes" : "no"));
549d042d	379
b69b29de BP	380	/* do the two bits[14:13] together */
	381	ecc = m->status & (3ULL << 45);
	382	if (ecc)
	383	pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));
	384
	385	pr_cont("\n");
	386
51966241 BP	387	switch (m->bank) {
	388	case 0:
	389	amd_decode_dc_mce(m->status);
	390	break;
d93cc222	391
ab5535e7 BP	392	case 1:
	393	amd_decode_ic_mce(m->status);
	394	break;
	395
56cad2d6 BP	396	case 2:
	397	amd_decode_bu_mce(m->status);
	398	break;
	399
f9350efd BP	400	case 3:
	401	amd_decode_ls_mce(m->status);
	402	break;
	403
51966241	404	case 4:
b69b29de BP	405	regs.nbsl = (u32) m->status;
	406	regs.nbsh = (u32)(m->status >> 32);
	407	regs.nbeal = (u32) m->addr;
	408	regs.nbeah = (u32)(m->addr >> 32);
6a812691	409	node = amd_get_nb_id(m->extcpu);
b69b29de BP	410
b69b29de BP	411	amd_decode_nb_mce(node, &regs, 1);
51966241 BP	412	break;
51966241 BP	413
53bd5fed BP	414	case 5:
	415	amd_decode_fr_mce(m->status);
	416	break;
	417
51966241 BP	418	default:
51966241 BP	419	break;
b69b29de	420	}
51966241 BP	421
51966241 BP	422	amd_decode_err_code(m->status & 0xffff);
549d042d	423	}
f436f8bb IM	424
	425	static int __init mce_amd_init(void)
	426	{
	427	/*
	428	* We can decode MCEs for Opteron and later CPUs:
	429	*/
	430	if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
0d18b2e3 BP	431	(boot_cpu_data.x86 >= 0xf)) {
	432	/* safe the default decode mce callback */
	433	orig_mce_callback = x86_mce_decode_callback;
	434
f436f8bb	435	x86_mce_decode_callback = amd_decode_mce;
0d18b2e3	436	}
f436f8bb IM	437
	438	return 0;
	439	}
	440	early_initcall(mce_amd_init);
0d18b2e3 BP	441
	442	#ifdef MODULE
	443	static void __exit mce_amd_exit(void)
	444	{
	445	x86_mce_decode_callback = orig_mce_callback;
	446	}
	447
	448	MODULE_DESCRIPTION("AMD MCE decoder");
	449	MODULE_ALIAS("edac-mce-amd");
	450	MODULE_LICENSE("GPL");
	451	module_exit(mce_amd_exit);
	452	#endif