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535c6a53 JU |
1 | /* |
2 | * Intel 3000/3010 Memory Controller kernel module | |
3 | * Copyright (C) 2007 Akamai Technologies, Inc. | |
4 | * Shamelessly copied from: | |
5 | * Intel D82875P Memory Controller kernel module | |
6 | * (C) 2003 Linux Networx (http://lnxi.com) | |
7 | * | |
8 | * This file may be distributed under the terms of the | |
9 | * GNU General Public License. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/pci_ids.h> | |
16 | #include <linux/slab.h> | |
17 | #include "edac_core.h" | |
18 | ||
19 | #define I3000_REVISION "1.1" | |
20 | ||
21 | #define EDAC_MOD_STR "i3000_edac" | |
22 | ||
23 | #define I3000_RANKS 8 | |
24 | #define I3000_RANKS_PER_CHANNEL 4 | |
25 | #define I3000_CHANNELS 2 | |
26 | ||
27 | /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */ | |
28 | ||
29 | #define I3000_MCHBAR 0x44 /* MCH Memory Mapped Register BAR */ | |
30 | #define I3000_MCHBAR_MASK 0xffffc000 | |
31 | #define I3000_MMR_WINDOW_SIZE 16384 | |
32 | ||
ce783d70 JU |
33 | #define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b) |
34 | * | |
35 | * 7:1 reserved | |
36 | * 0 bit 32 of address | |
37 | */ | |
38 | #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b) | |
39 | * | |
40 | * 31:7 address | |
41 | * 6:1 reserved | |
42 | * 0 Error channel 0/1 | |
43 | */ | |
44 | #define I3000_DEAP_GRAIN (1 << 7) | |
45 | #define I3000_DEAP_PFN(edeap, deap) ((((edeap) & 1) << (32 - PAGE_SHIFT)) \ | |
46 | | ((deap) >> PAGE_SHIFT)) | |
47 | #define I3000_DEAP_OFFSET(deap) ((deap) & ~(I3000_DEAP_GRAIN-1) & \ | |
48 | ~PAGE_MASK) | |
535c6a53 JU |
49 | #define I3000_DEAP_CHANNEL(deap) ((deap) & 1) |
50 | ||
ce783d70 JU |
51 | #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b) |
52 | * | |
53 | * 7:0 DRAM ECC Syndrome | |
54 | */ | |
55 | ||
56 | #define I3000_ERRSTS 0xc8 /* Error Status Register (16b) | |
57 | * | |
58 | * 15:12 reserved | |
59 | * 11 MCH Thermal Sensor Event | |
60 | * for SMI/SCI/SERR | |
61 | * 10 reserved | |
62 | * 9 LOCK to non-DRAM Memory Flag (LCKF) | |
63 | * 8 Received Refresh Timeout Flag (RRTOF) | |
64 | * 7:2 reserved | |
65 | * 1 Multi-bit DRAM ECC Error Flag (DMERR) | |
66 | * 0 Single-bit DRAM ECC Error Flag (DSERR) | |
67 | */ | |
535c6a53 JU |
68 | #define I3000_ERRSTS_BITS 0x0b03 /* bits which indicate errors */ |
69 | #define I3000_ERRSTS_UE 0x0002 | |
70 | #define I3000_ERRSTS_CE 0x0001 | |
71 | ||
ce783d70 JU |
72 | #define I3000_ERRCMD 0xca /* Error Command (16b) |
73 | * | |
74 | * 15:12 reserved | |
75 | * 11 SERR on MCH Thermal Sensor Event | |
76 | * (TSESERR) | |
77 | * 10 reserved | |
78 | * 9 SERR on LOCK to non-DRAM Memory | |
79 | * (LCKERR) | |
80 | * 8 SERR on DRAM Refresh Timeout | |
81 | * (DRTOERR) | |
82 | * 7:2 reserved | |
83 | * 1 SERR Multi-Bit DRAM ECC Error | |
84 | * (DMERR) | |
85 | * 0 SERR on Single-Bit ECC Error | |
86 | * (DSERR) | |
87 | */ | |
535c6a53 JU |
88 | |
89 | /* Intel MMIO register space - device 0 function 0 - MMR space */ | |
90 | ||
91 | #define I3000_DRB_SHIFT 25 /* 32MiB grain */ | |
92 | ||
ce783d70 JU |
93 | #define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4) |
94 | * | |
95 | * 7:0 Channel 0 DRAM Rank Boundary Address | |
96 | */ | |
97 | #define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4) | |
98 | * | |
99 | * 7:0 Channel 1 DRAM Rank Boundary Address | |
100 | */ | |
101 | ||
102 | #define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2) | |
103 | * | |
104 | * 7 reserved | |
105 | * 6:4 DRAM odd Rank Attribute | |
106 | * 3 reserved | |
107 | * 2:0 DRAM even Rank Attribute | |
108 | * | |
109 | * Each attribute defines the page | |
110 | * size of the corresponding rank: | |
111 | * 000: unpopulated | |
112 | * 001: reserved | |
113 | * 010: 4 KB | |
114 | * 011: 8 KB | |
115 | * 100: 16 KB | |
116 | * Others: reserved | |
117 | */ | |
118 | #define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */ | |
119 | #define ODD_RANK_ATTRIB(dra) (((dra) & 0x70) >> 4) | |
120 | #define EVEN_RANK_ATTRIB(dra) ((dra) & 0x07) | |
121 | ||
122 | #define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b) | |
123 | * | |
124 | * 31:30 reserved | |
125 | * 29 Initialization Complete (IC) | |
126 | * 28:11 reserved | |
127 | * 10:8 Refresh Mode Select (RMS) | |
128 | * 7 reserved | |
129 | * 6:4 Mode Select (SMS) | |
130 | * 3:2 reserved | |
131 | * 1:0 DRAM Type (DT) | |
132 | */ | |
133 | ||
134 | #define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b) | |
135 | * | |
136 | * 31 Enhanced Addressing Enable (ENHADE) | |
137 | * 30:0 reserved | |
138 | */ | |
535c6a53 | 139 | |
535c6a53 JU |
140 | enum i3000p_chips { |
141 | I3000 = 0, | |
142 | }; | |
143 | ||
144 | struct i3000_dev_info { | |
145 | const char *ctl_name; | |
146 | }; | |
147 | ||
148 | struct i3000_error_info { | |
149 | u16 errsts; | |
150 | u8 derrsyn; | |
151 | u8 edeap; | |
152 | u32 deap; | |
153 | u16 errsts2; | |
154 | }; | |
155 | ||
156 | static const struct i3000_dev_info i3000_devs[] = { | |
157 | [I3000] = { | |
052dfb45 | 158 | .ctl_name = "i3000"}, |
535c6a53 JU |
159 | }; |
160 | ||
f044091c | 161 | static struct pci_dev *mci_pdev; |
535c6a53 | 162 | static int i3000_registered = 1; |
456a2f95 | 163 | static struct edac_pci_ctl_info *i3000_pci; |
535c6a53 JU |
164 | |
165 | static void i3000_get_error_info(struct mem_ctl_info *mci, | |
36b8289e | 166 | struct i3000_error_info *info) |
535c6a53 JU |
167 | { |
168 | struct pci_dev *pdev; | |
169 | ||
170 | pdev = to_pci_dev(mci->dev); | |
171 | ||
172 | /* | |
173 | * This is a mess because there is no atomic way to read all the | |
174 | * registers at once and the registers can transition from CE being | |
175 | * overwritten by UE. | |
176 | */ | |
177 | pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts); | |
178 | if (!(info->errsts & I3000_ERRSTS_BITS)) | |
179 | return; | |
180 | pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap); | |
181 | pci_read_config_dword(pdev, I3000_DEAP, &info->deap); | |
182 | pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn); | |
183 | pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2); | |
184 | ||
185 | /* | |
186 | * If the error is the same for both reads then the first set | |
187 | * of reads is valid. If there is a change then there is a CE | |
188 | * with no info and the second set of reads is valid and | |
189 | * should be UE info. | |
190 | */ | |
191 | if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) { | |
36b8289e DJ |
192 | pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap); |
193 | pci_read_config_dword(pdev, I3000_DEAP, &info->deap); | |
194 | pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn); | |
535c6a53 JU |
195 | } |
196 | ||
ce783d70 JU |
197 | /* |
198 | * Clear any error bits. | |
535c6a53 JU |
199 | * (Yes, we really clear bits by writing 1 to them.) |
200 | */ | |
36b8289e DJ |
201 | pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS, |
202 | I3000_ERRSTS_BITS); | |
535c6a53 JU |
203 | } |
204 | ||
205 | static int i3000_process_error_info(struct mem_ctl_info *mci, | |
052dfb45 DT |
206 | struct i3000_error_info *info, |
207 | int handle_errors) | |
535c6a53 JU |
208 | { |
209 | int row, multi_chan; | |
210 | int pfn, offset, channel; | |
211 | ||
212 | multi_chan = mci->csrows[0].nr_channels - 1; | |
213 | ||
214 | if (!(info->errsts & I3000_ERRSTS_BITS)) | |
215 | return 0; | |
216 | ||
217 | if (!handle_errors) | |
218 | return 1; | |
219 | ||
220 | if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) { | |
221 | edac_mc_handle_ce_no_info(mci, "UE overwrote CE"); | |
222 | info->errsts = info->errsts2; | |
223 | } | |
224 | ||
225 | pfn = I3000_DEAP_PFN(info->edeap, info->deap); | |
226 | offset = I3000_DEAP_OFFSET(info->deap); | |
227 | channel = I3000_DEAP_CHANNEL(info->deap); | |
228 | ||
229 | row = edac_mc_find_csrow_by_page(mci, pfn); | |
230 | ||
231 | if (info->errsts & I3000_ERRSTS_UE) | |
232 | edac_mc_handle_ue(mci, pfn, offset, row, "i3000 UE"); | |
233 | else | |
234 | edac_mc_handle_ce(mci, pfn, offset, info->derrsyn, row, | |
052dfb45 | 235 | multi_chan ? channel : 0, "i3000 CE"); |
535c6a53 JU |
236 | |
237 | return 1; | |
238 | } | |
239 | ||
240 | static void i3000_check(struct mem_ctl_info *mci) | |
241 | { | |
242 | struct i3000_error_info info; | |
243 | ||
244 | debugf1("MC%d: %s()\n", mci->mc_idx, __func__); | |
245 | i3000_get_error_info(mci, &info); | |
246 | i3000_process_error_info(mci, &info, 1); | |
247 | } | |
248 | ||
249 | static int i3000_is_interleaved(const unsigned char *c0dra, | |
250 | const unsigned char *c1dra, | |
251 | const unsigned char *c0drb, | |
252 | const unsigned char *c1drb) | |
253 | { | |
254 | int i; | |
255 | ||
ce783d70 JU |
256 | /* |
257 | * If the channels aren't populated identically then | |
535c6a53 JU |
258 | * we're not interleaved. |
259 | */ | |
260 | for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++) | |
261 | if (ODD_RANK_ATTRIB(c0dra[i]) != ODD_RANK_ATTRIB(c1dra[i]) || | |
052dfb45 DT |
262 | EVEN_RANK_ATTRIB(c0dra[i]) != |
263 | EVEN_RANK_ATTRIB(c1dra[i])) | |
535c6a53 JU |
264 | return 0; |
265 | ||
ce783d70 JU |
266 | /* |
267 | * If the rank boundaries for the two channels are different | |
535c6a53 JU |
268 | * then we're not interleaved. |
269 | */ | |
270 | for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) | |
271 | if (c0drb[i] != c1drb[i]) | |
272 | return 0; | |
273 | ||
274 | return 1; | |
275 | } | |
276 | ||
277 | static int i3000_probe1(struct pci_dev *pdev, int dev_idx) | |
278 | { | |
279 | int rc; | |
280 | int i; | |
281 | struct mem_ctl_info *mci = NULL; | |
282 | unsigned long last_cumul_size; | |
283 | int interleaved, nr_channels; | |
284 | unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS]; | |
285 | unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2]; | |
286 | unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL]; | |
287 | unsigned long mchbar; | |
0bd8496b | 288 | void __iomem *window; |
535c6a53 JU |
289 | |
290 | debugf0("MC: %s()\n", __func__); | |
291 | ||
36b8289e | 292 | pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar); |
535c6a53 JU |
293 | mchbar &= I3000_MCHBAR_MASK; |
294 | window = ioremap_nocache(mchbar, I3000_MMR_WINDOW_SIZE); | |
295 | if (!window) { | |
36b8289e | 296 | printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n", |
052dfb45 | 297 | mchbar); |
535c6a53 JU |
298 | return -ENODEV; |
299 | } | |
300 | ||
36b8289e DJ |
301 | c0dra[0] = readb(window + I3000_C0DRA + 0); /* ranks 0,1 */ |
302 | c0dra[1] = readb(window + I3000_C0DRA + 1); /* ranks 2,3 */ | |
303 | c1dra[0] = readb(window + I3000_C1DRA + 0); /* ranks 0,1 */ | |
304 | c1dra[1] = readb(window + I3000_C1DRA + 1); /* ranks 2,3 */ | |
535c6a53 JU |
305 | |
306 | for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) { | |
307 | c0drb[i] = readb(window + I3000_C0DRB + i); | |
308 | c1drb[i] = readb(window + I3000_C1DRB + i); | |
309 | } | |
310 | ||
311 | iounmap(window); | |
312 | ||
ce783d70 JU |
313 | /* |
314 | * Figure out how many channels we have. | |
535c6a53 JU |
315 | * |
316 | * If we have what the datasheet calls "asymmetric channels" | |
317 | * (essentially the same as what was called "virtual single | |
318 | * channel mode" in the i82875) then it's a single channel as | |
319 | * far as EDAC is concerned. | |
320 | */ | |
321 | interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb); | |
322 | nr_channels = interleaved ? 2 : 1; | |
b8f6f975 | 323 | mci = edac_mc_alloc(0, I3000_RANKS / nr_channels, nr_channels, 0); |
535c6a53 JU |
324 | if (!mci) |
325 | return -ENOMEM; | |
326 | ||
327 | debugf3("MC: %s(): init mci\n", __func__); | |
328 | ||
329 | mci->dev = &pdev->dev; | |
330 | mci->mtype_cap = MEM_FLAG_DDR2; | |
331 | ||
332 | mci->edac_ctl_cap = EDAC_FLAG_SECDED; | |
333 | mci->edac_cap = EDAC_FLAG_SECDED; | |
334 | ||
335 | mci->mod_name = EDAC_MOD_STR; | |
336 | mci->mod_ver = I3000_REVISION; | |
337 | mci->ctl_name = i3000_devs[dev_idx].ctl_name; | |
338 | mci->dev_name = pci_name(pdev); | |
339 | mci->edac_check = i3000_check; | |
340 | mci->ctl_page_to_phys = NULL; | |
341 | ||
342 | /* | |
343 | * The dram rank boundary (DRB) reg values are boundary addresses | |
344 | * for each DRAM rank with a granularity of 32MB. DRB regs are | |
345 | * cumulative; the last one will contain the total memory | |
346 | * contained in all ranks. | |
347 | * | |
348 | * If we're in interleaved mode then we're only walking through | |
349 | * the ranks of controller 0, so we double all the values we see. | |
350 | */ | |
351 | for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) { | |
352 | u8 value; | |
353 | u32 cumul_size; | |
354 | struct csrow_info *csrow = &mci->csrows[i]; | |
355 | ||
356 | value = drb[i]; | |
357 | cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT); | |
358 | if (interleaved) | |
359 | cumul_size <<= 1; | |
360 | debugf3("MC: %s(): (%d) cumul_size 0x%x\n", | |
361 | __func__, i, cumul_size); | |
362 | if (cumul_size == last_cumul_size) { | |
363 | csrow->mtype = MEM_EMPTY; | |
364 | continue; | |
365 | } | |
366 | ||
367 | csrow->first_page = last_cumul_size; | |
368 | csrow->last_page = cumul_size - 1; | |
369 | csrow->nr_pages = cumul_size - last_cumul_size; | |
370 | last_cumul_size = cumul_size; | |
371 | csrow->grain = I3000_DEAP_GRAIN; | |
372 | csrow->mtype = MEM_DDR2; | |
373 | csrow->dtype = DEV_UNKNOWN; | |
374 | csrow->edac_mode = EDAC_UNKNOWN; | |
375 | } | |
376 | ||
ce783d70 JU |
377 | /* |
378 | * Clear any error bits. | |
535c6a53 JU |
379 | * (Yes, we really clear bits by writing 1 to them.) |
380 | */ | |
36b8289e DJ |
381 | pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS, |
382 | I3000_ERRSTS_BITS); | |
535c6a53 JU |
383 | |
384 | rc = -ENODEV; | |
b8f6f975 | 385 | if (edac_mc_add_mc(mci)) { |
535c6a53 JU |
386 | debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__); |
387 | goto fail; | |
388 | } | |
389 | ||
456a2f95 DJ |
390 | /* allocating generic PCI control info */ |
391 | i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); | |
392 | if (!i3000_pci) { | |
393 | printk(KERN_WARNING | |
394 | "%s(): Unable to create PCI control\n", | |
395 | __func__); | |
396 | printk(KERN_WARNING | |
397 | "%s(): PCI error report via EDAC not setup\n", | |
398 | __func__); | |
399 | } | |
400 | ||
535c6a53 JU |
401 | /* get this far and it's successful */ |
402 | debugf3("MC: %s(): success\n", __func__); | |
403 | return 0; | |
404 | ||
ce783d70 | 405 | fail: |
535c6a53 JU |
406 | if (mci) |
407 | edac_mc_free(mci); | |
408 | ||
409 | return rc; | |
410 | } | |
411 | ||
412 | /* returns count (>= 0), or negative on error */ | |
413 | static int __devinit i3000_init_one(struct pci_dev *pdev, | |
052dfb45 | 414 | const struct pci_device_id *ent) |
535c6a53 JU |
415 | { |
416 | int rc; | |
417 | ||
418 | debugf0("MC: %s()\n", __func__); | |
419 | ||
420 | if (pci_enable_device(pdev) < 0) | |
421 | return -EIO; | |
422 | ||
423 | rc = i3000_probe1(pdev, ent->driver_data); | |
ce783d70 | 424 | if (!mci_pdev) |
535c6a53 JU |
425 | mci_pdev = pci_dev_get(pdev); |
426 | ||
427 | return rc; | |
428 | } | |
429 | ||
430 | static void __devexit i3000_remove_one(struct pci_dev *pdev) | |
431 | { | |
432 | struct mem_ctl_info *mci; | |
433 | ||
434 | debugf0("%s()\n", __func__); | |
435 | ||
456a2f95 DJ |
436 | if (i3000_pci) |
437 | edac_pci_release_generic_ctl(i3000_pci); | |
438 | ||
ce783d70 JU |
439 | mci = edac_mc_del_mc(&pdev->dev); |
440 | if (!mci) | |
535c6a53 JU |
441 | return; |
442 | ||
443 | edac_mc_free(mci); | |
444 | } | |
445 | ||
446 | static const struct pci_device_id i3000_pci_tbl[] __devinitdata = { | |
447 | { | |
36b8289e DJ |
448 | PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
449 | I3000}, | |
535c6a53 | 450 | { |
36b8289e DJ |
451 | 0, |
452 | } /* 0 terminated list. */ | |
535c6a53 JU |
453 | }; |
454 | ||
455 | MODULE_DEVICE_TABLE(pci, i3000_pci_tbl); | |
456 | ||
457 | static struct pci_driver i3000_driver = { | |
458 | .name = EDAC_MOD_STR, | |
459 | .probe = i3000_init_one, | |
460 | .remove = __devexit_p(i3000_remove_one), | |
461 | .id_table = i3000_pci_tbl, | |
462 | }; | |
463 | ||
464 | static int __init i3000_init(void) | |
465 | { | |
466 | int pci_rc; | |
467 | ||
468 | debugf3("MC: %s()\n", __func__); | |
469 | pci_rc = pci_register_driver(&i3000_driver); | |
470 | if (pci_rc < 0) | |
471 | goto fail0; | |
472 | ||
ce783d70 | 473 | if (!mci_pdev) { |
535c6a53 JU |
474 | i3000_registered = 0; |
475 | mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
052dfb45 | 476 | PCI_DEVICE_ID_INTEL_3000_HB, NULL); |
535c6a53 JU |
477 | if (!mci_pdev) { |
478 | debugf0("i3000 pci_get_device fail\n"); | |
479 | pci_rc = -ENODEV; | |
480 | goto fail1; | |
481 | } | |
482 | ||
483 | pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl); | |
484 | if (pci_rc < 0) { | |
485 | debugf0("i3000 init fail\n"); | |
486 | pci_rc = -ENODEV; | |
487 | goto fail1; | |
488 | } | |
489 | } | |
490 | ||
491 | return 0; | |
492 | ||
052dfb45 | 493 | fail1: |
535c6a53 JU |
494 | pci_unregister_driver(&i3000_driver); |
495 | ||
052dfb45 | 496 | fail0: |
535c6a53 JU |
497 | if (mci_pdev) |
498 | pci_dev_put(mci_pdev); | |
499 | ||
500 | return pci_rc; | |
501 | } | |
502 | ||
503 | static void __exit i3000_exit(void) | |
504 | { | |
505 | debugf3("MC: %s()\n", __func__); | |
506 | ||
507 | pci_unregister_driver(&i3000_driver); | |
508 | if (!i3000_registered) { | |
509 | i3000_remove_one(mci_pdev); | |
510 | pci_dev_put(mci_pdev); | |
511 | } | |
512 | } | |
513 | ||
514 | module_init(i3000_init); | |
515 | module_exit(i3000_exit); | |
516 | ||
517 | MODULE_LICENSE("GPL"); | |
518 | MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott"); | |
519 | MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers"); |