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fcaf780b MCC |
1 | /* |
2 | * Intel 7300 class Memory Controllers kernel module (Clarksboro) | |
3 | * | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License version 2 only. | |
6 | * | |
7 | * Copyright (c) 2010 by: | |
8 | * Mauro Carvalho Chehab <mchehab@redhat.com> | |
9 | * | |
10 | * Red Hat Inc. http://www.redhat.com | |
11 | * | |
12 | * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet | |
13 | * http://www.intel.com/Assets/PDF/datasheet/318082.pdf | |
14 | * | |
15 | * TODO: The chipset allow checking for PCI Express errors also. Currently, | |
16 | * the driver covers only memory error errors | |
17 | * | |
18 | * This driver uses "csrows" EDAC attribute to represent DIMM slot# | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/pci_ids.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/edac.h> | |
27 | #include <linux/mmzone.h> | |
28 | ||
29 | #include "edac_core.h" | |
30 | ||
31 | /* | |
32 | * Alter this version for the I7300 module when modifications are made | |
33 | */ | |
34 | #define I7300_REVISION " Ver: 1.0.0 " __DATE__ | |
35 | ||
36 | #define EDAC_MOD_STR "i7300_edac" | |
37 | ||
38 | #define i7300_printk(level, fmt, arg...) \ | |
39 | edac_printk(level, "i7300", fmt, ##arg) | |
40 | ||
41 | #define i7300_mc_printk(mci, level, fmt, arg...) \ | |
42 | edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg) | |
43 | ||
44 | /* | |
45 | * Memory topology is organized as: | |
46 | * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0) | |
47 | * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0) | |
48 | * Each channel can have to 8 DIMM sets (called as SLOTS) | |
49 | * Slots should generally be filled in pairs | |
50 | * Except on Single Channel mode of operation | |
51 | * just slot 0/channel0 filled on this mode | |
52 | * On normal operation mode, the two channels on a branch should be | |
c3af2eaf | 53 | * filled together for the same SLOT# |
fcaf780b MCC |
54 | * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four |
55 | * channels on both branches should be filled | |
56 | */ | |
57 | ||
58 | /* Limits for i7300 */ | |
59 | #define MAX_SLOTS 8 | |
60 | #define MAX_BRANCHES 2 | |
61 | #define MAX_CH_PER_BRANCH 2 | |
62 | #define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES) | |
63 | #define MAX_MIR 3 | |
64 | ||
65 | #define to_channel(ch, branch) ((((branch)) << 1) | (ch)) | |
66 | ||
67 | #define to_csrow(slot, ch, branch) \ | |
68 | (to_channel(ch, branch) | ((slot) << 2)) | |
69 | ||
c3af2eaf MCC |
70 | /* |
71 | * I7300 devices | |
fcaf780b MCC |
72 | * All 3 functions of Device 16 (0,1,2) share the SAME DID and |
73 | * uses PCI_DEVICE_ID_INTEL_I7300_MCH_ERR for device 16 (0,1,2), | |
74 | * PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 and PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 | |
75 | * for device 21 (0,1). | |
c3af2eaf MCC |
76 | */ |
77 | ||
78 | /**************************************************** | |
79 | * i7300 Register definitions for memory enumberation | |
80 | ****************************************************/ | |
81 | ||
82 | /* | |
83 | * Device 16, | |
84 | * Function 0: System Address (not documented) | |
85 | * Function 1: Memory Branch Map, Control, Errors Register | |
fcaf780b MCC |
86 | */ |
87 | ||
88 | /* OFFSETS for Function 0 */ | |
af3d8831 MCC |
89 | #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ |
90 | #define MAXCH 0x56 /* Max Channel Number */ | |
91 | #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */ | |
fcaf780b MCC |
92 | |
93 | /* OFFSETS for Function 1 */ | |
af3d8831 | 94 | #define MC_SETTINGS 0x40 |
bb81a216 MCC |
95 | #define IS_MIRRORED(mc) ((mc) & (1 << 16)) |
96 | #define IS_ECC_ENABLED(mc) ((mc) & (1 << 5)) | |
97 | #define IS_RETRY_ENABLED(mc) ((mc) & (1 << 31)) | |
98 | #define IS_SCRBALGO_ENHANCED(mc) ((mc) & (1 << 8)) | |
fcaf780b | 99 | |
bb81a216 MCC |
100 | #define MC_SETTINGS_A 0x58 |
101 | #define IS_SINGLE_MODE(mca) ((mca) & (1 << 14)) | |
d7de2bdb | 102 | |
af3d8831 MCC |
103 | #define TOLM 0x6C |
104 | #define REDMEMB 0x7C | |
105 | ||
106 | #define MIR0 0x80 | |
107 | #define MIR1 0x84 | |
108 | #define MIR2 0x88 | |
fcaf780b | 109 | |
fcaf780b MCC |
110 | /* |
111 | * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available | |
112 | * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it | |
113 | * seems that we cannot use this information directly for the same usage. | |
114 | * Each memory slot may have up to 2 AMB interfaces, one for income and another | |
115 | * for outcome interface to the next slot. | |
116 | * For now, the driver just stores the AMB present registers, but rely only at | |
117 | * the MTR info to detect memory. | |
118 | * Datasheet is also not clear about how to map each AMBPRESENT registers to | |
119 | * one of the 4 available channels. | |
120 | */ | |
121 | #define AMBPRESENT_0 0x64 | |
122 | #define AMBPRESENT_1 0x66 | |
123 | ||
124 | const static u16 mtr_regs [MAX_SLOTS] = { | |
125 | 0x80, 0x84, 0x88, 0x8c, | |
126 | 0x82, 0x86, 0x8a, 0x8e | |
127 | }; | |
128 | ||
129 | /* Defines to extract the vaious fields from the | |
130 | * MTRx - Memory Technology Registers | |
131 | */ | |
132 | #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8)) | |
133 | #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7)) | |
134 | #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4) | |
135 | #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4) | |
136 | #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0) | |
137 | #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) | |
138 | #define MTR_DRAM_BANKS_ADDR_BITS 2 | |
139 | #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) | |
140 | #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) | |
141 | #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) | |
142 | ||
fcaf780b MCC |
143 | #ifdef CONFIG_EDAC_DEBUG |
144 | /* MTR NUMROW */ | |
145 | static const char *numrow_toString[] = { | |
146 | "8,192 - 13 rows", | |
147 | "16,384 - 14 rows", | |
148 | "32,768 - 15 rows", | |
149 | "65,536 - 16 rows" | |
150 | }; | |
151 | ||
152 | /* MTR NUMCOL */ | |
153 | static const char *numcol_toString[] = { | |
154 | "1,024 - 10 columns", | |
155 | "2,048 - 11 columns", | |
156 | "4,096 - 12 columns", | |
157 | "reserved" | |
158 | }; | |
159 | #endif | |
160 | ||
c3af2eaf MCC |
161 | /************************************************ |
162 | * i7300 Register definitions for error detection | |
163 | ************************************************/ | |
57021918 MCC |
164 | |
165 | /* | |
166 | * Device 16.1: FBD Error Registers | |
167 | */ | |
168 | #define FERR_FAT_FBD 0x98 | |
169 | static const char *ferr_fat_fbd_name[] = { | |
170 | [22] = "Non-Redundant Fast Reset Timeout", | |
171 | [2] = ">Tmid Thermal event with intelligent throttling disabled", | |
172 | [1] = "Memory or FBD configuration CRC read error", | |
173 | [0] = "Memory Write error on non-redundant retry or " | |
174 | "FBD configuration Write error on retry", | |
175 | }; | |
176 | #define GET_FBD_FAT_IDX(fbderr) (fbderr & (3 << 28)) | |
177 | #define FERR_FAT_FBD_ERR_MASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) | |
178 | ||
179 | #define FERR_NF_FBD 0xa0 | |
180 | static const char *ferr_nf_fbd_name[] = { | |
181 | [24] = "DIMM-Spare Copy Completed", | |
182 | [23] = "DIMM-Spare Copy Initiated", | |
183 | [22] = "Redundant Fast Reset Timeout", | |
184 | [21] = "Memory Write error on redundant retry", | |
185 | [18] = "SPD protocol Error", | |
186 | [17] = "FBD Northbound parity error on FBD Sync Status", | |
187 | [16] = "Correctable Patrol Data ECC", | |
188 | [15] = "Correctable Resilver- or Spare-Copy Data ECC", | |
189 | [14] = "Correctable Mirrored Demand Data ECC", | |
190 | [13] = "Correctable Non-Mirrored Demand Data ECC", | |
191 | [11] = "Memory or FBD configuration CRC read error", | |
192 | [10] = "FBD Configuration Write error on first attempt", | |
193 | [9] = "Memory Write error on first attempt", | |
194 | [8] = "Non-Aliased Uncorrectable Patrol Data ECC", | |
195 | [7] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", | |
196 | [6] = "Non-Aliased Uncorrectable Mirrored Demand Data ECC", | |
197 | [5] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC", | |
198 | [4] = "Aliased Uncorrectable Patrol Data ECC", | |
199 | [3] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", | |
200 | [2] = "Aliased Uncorrectable Mirrored Demand Data ECC", | |
201 | [1] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC", | |
202 | [0] = "Uncorrectable Data ECC on Replay", | |
203 | }; | |
204 | #define GET_FBD_NF_IDX(fbderr) (fbderr & (3 << 28)) | |
205 | #define FERR_NF_FBD_ERR_MASK ((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) |\ | |
206 | (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15) |\ | |
207 | (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10) |\ | |
208 | (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\ | |
209 | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\ | |
210 | (1 << 1) | (1 << 0)) | |
211 | ||
212 | #define EMASK_FBD 0xa8 | |
213 | #define EMASK_FBD_ERR_MASK ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) |\ | |
214 | (1 << 22) | (1 << 21) | (1 << 20) | (1 << 19) |\ | |
215 | (1 << 18) | (1 << 17) | (1 << 16) | (1 << 14) |\ | |
216 | (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) |\ | |
217 | (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\ | |
218 | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\ | |
219 | (1 << 1) | (1 << 0)) | |
220 | ||
c3af2eaf MCC |
221 | /* |
222 | * Device 16.2: Global Error Registers | |
223 | */ | |
224 | ||
5de6e07e MCC |
225 | #define FERR_GLOBAL_HI 0x48 |
226 | static const char *ferr_global_hi_name[] = { | |
227 | [3] = "FSB 3 Fatal Error", | |
228 | [2] = "FSB 2 Fatal Error", | |
229 | [1] = "FSB 1 Fatal Error", | |
230 | [0] = "FSB 0 Fatal Error", | |
231 | }; | |
232 | #define ferr_global_hi_is_fatal(errno) 1 | |
233 | ||
c3af2eaf | 234 | #define FERR_GLOBAL_LO 0x40 |
5de6e07e | 235 | static const char *ferr_global_lo_name[] = { |
c3af2eaf MCC |
236 | [31] = "Internal MCH Fatal Error", |
237 | [30] = "Intel QuickData Technology Device Fatal Error", | |
238 | [29] = "FSB1 Fatal Error", | |
239 | [28] = "FSB0 Fatal Error", | |
240 | [27] = "FBD Channel 3 Fatal Error", | |
241 | [26] = "FBD Channel 2 Fatal Error", | |
242 | [25] = "FBD Channel 1 Fatal Error", | |
243 | [24] = "FBD Channel 0 Fatal Error", | |
244 | [23] = "PCI Express Device 7Fatal Error", | |
245 | [22] = "PCI Express Device 6 Fatal Error", | |
246 | [21] = "PCI Express Device 5 Fatal Error", | |
247 | [20] = "PCI Express Device 4 Fatal Error", | |
248 | [19] = "PCI Express Device 3 Fatal Error", | |
249 | [18] = "PCI Express Device 2 Fatal Error", | |
250 | [17] = "PCI Express Device 1 Fatal Error", | |
251 | [16] = "ESI Fatal Error", | |
252 | [15] = "Internal MCH Non-Fatal Error", | |
253 | [14] = "Intel QuickData Technology Device Non Fatal Error", | |
254 | [13] = "FSB1 Non-Fatal Error", | |
255 | [12] = "FSB 0 Non-Fatal Error", | |
256 | [11] = "FBD Channel 3 Non-Fatal Error", | |
257 | [10] = "FBD Channel 2 Non-Fatal Error", | |
258 | [9] = "FBD Channel 1 Non-Fatal Error", | |
259 | [8] = "FBD Channel 0 Non-Fatal Error", | |
260 | [7] = "PCI Express Device 7 Non-Fatal Error", | |
261 | [6] = "PCI Express Device 6 Non-Fatal Error", | |
262 | [5] = "PCI Express Device 5 Non-Fatal Error", | |
263 | [4] = "PCI Express Device 4 Non-Fatal Error", | |
264 | [3] = "PCI Express Device 3 Non-Fatal Error", | |
265 | [2] = "PCI Express Device 2 Non-Fatal Error", | |
266 | [1] = "PCI Express Device 1 Non-Fatal Error", | |
267 | [0] = "ESI Non-Fatal Error", | |
268 | }; | |
5de6e07e | 269 | #define ferr_global_lo_is_fatal(errno) ((errno < 16) ? 0 : 1) |
fcaf780b | 270 | |
8199d8cc MCC |
271 | #define NRECMEMA 0xbe |
272 | #define NRECMEMA_BANK(v) (((v) >> 12) & 7) | |
273 | #define NRECMEMA_RANK(v) (((v) >> 8) & 15) | |
274 | ||
275 | #define NRECMEMB 0xc0 | |
276 | #define NRECMEMB_IS_WR(v) ((v) & (1 << 31)) | |
277 | #define NRECMEMB_CAS(v) (((v) >> 16) & 0x1fff) | |
278 | #define NRECMEMB_RAS(v) ((v) & 0xffff) | |
279 | ||
32f94726 MCC |
280 | #define REDMEMA 0xdc |
281 | ||
282 | #define RECMEMA 0xe0 | |
283 | #define RECMEMA_BANK(v) (((v) >> 12) & 7) | |
284 | #define RECMEMA_RANK(v) (((v) >> 8) & 15) | |
285 | ||
286 | #define RECMEMB 0xe4 | |
287 | #define RECMEMB_IS_WR(v) ((v) & (1 << 31)) | |
288 | #define RECMEMB_CAS(v) (((v) >> 16) & 0x1fff) | |
289 | #define RECMEMB_RAS(v) ((v) & 0xffff) | |
290 | ||
8199d8cc | 291 | |
fcaf780b MCC |
292 | /* Device name and register DID (Device ID) */ |
293 | struct i7300_dev_info { | |
294 | const char *ctl_name; /* name for this device */ | |
295 | u16 fsb_mapping_errors; /* DID for the branchmap,control */ | |
296 | }; | |
297 | ||
298 | /* Table of devices attributes supported by this driver */ | |
299 | static const struct i7300_dev_info i7300_devs[] = { | |
300 | { | |
301 | .ctl_name = "I7300", | |
302 | .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, | |
303 | }, | |
304 | }; | |
305 | ||
306 | struct i7300_dimm_info { | |
307 | int megabytes; /* size, 0 means not present */ | |
308 | }; | |
309 | ||
310 | /* driver private data structure */ | |
311 | struct i7300_pvt { | |
3e57eef6 MCC |
312 | struct pci_dev *pci_dev_16_0_fsb_ctlr; /* 16.0 */ |
313 | struct pci_dev *pci_dev_16_1_fsb_addr_map; /* 16.1 */ | |
314 | struct pci_dev *pci_dev_16_2_fsb_err_regs; /* 16.2 */ | |
315 | struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES]; /* 21.0 and 22.0 */ | |
fcaf780b MCC |
316 | |
317 | u16 tolm; /* top of low memory */ | |
318 | u64 ambase; /* AMB BAR */ | |
319 | ||
bb81a216 MCC |
320 | u32 mc_settings; /* Report several settings */ |
321 | u32 mc_settings_a; | |
322 | ||
323 | u16 mir[MAX_MIR]; /* Memory Interleave Reg*/ | |
fcaf780b MCC |
324 | |
325 | u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */ | |
326 | u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */ | |
327 | ||
328 | /* DIMM information matrix, allocating architecture maximums */ | |
329 | struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS]; | |
85580ea4 MCC |
330 | |
331 | /* Temporary buffer for use when preparing error messages */ | |
332 | char *tmp_prt_buffer; | |
fcaf780b MCC |
333 | }; |
334 | ||
fcaf780b MCC |
335 | /* FIXME: Why do we need to have this static? */ |
336 | static struct edac_pci_ctl_info *i7300_pci; | |
337 | ||
5de6e07e MCC |
338 | /******************************************** |
339 | * i7300 Functions related to error detection | |
340 | ********************************************/ | |
fcaf780b | 341 | |
5de6e07e | 342 | const char *get_err_from_table(const char *table[], int size, int pos) |
fcaf780b | 343 | { |
5de6e07e MCC |
344 | if (pos >= size) |
345 | return "Reserved"; | |
346 | ||
347 | return table[pos]; | |
fcaf780b MCC |
348 | } |
349 | ||
5de6e07e MCC |
350 | #define GET_ERR_FROM_TABLE(table, pos) \ |
351 | get_err_from_table(table, ARRAY_SIZE(table), pos) | |
352 | ||
fcaf780b | 353 | /* |
5de6e07e MCC |
354 | * i7300_process_error_global Retrieve the hardware error information from |
355 | * the hardware and cache it in the 'info' | |
356 | * structure | |
fcaf780b | 357 | */ |
f4277422 | 358 | static void i7300_process_error_global(struct mem_ctl_info *mci) |
fcaf780b | 359 | { |
5de6e07e MCC |
360 | struct i7300_pvt *pvt; |
361 | u32 errnum, value; | |
362 | unsigned long errors; | |
363 | const char *specific; | |
364 | bool is_fatal; | |
fcaf780b | 365 | |
5de6e07e | 366 | pvt = mci->pvt_info; |
fcaf780b | 367 | |
5de6e07e MCC |
368 | /* read in the 1st FATAL error register */ |
369 | pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
370 | FERR_GLOBAL_HI, &value); | |
371 | if (unlikely(value)) { | |
372 | errors = value; | |
373 | errnum = find_first_bit(&errors, | |
374 | ARRAY_SIZE(ferr_global_hi_name)); | |
375 | specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum); | |
376 | is_fatal = ferr_global_hi_is_fatal(errnum); | |
86002324 MCC |
377 | |
378 | /* Clear the error bit */ | |
379 | pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
380 | FERR_GLOBAL_HI, value); | |
381 | ||
5de6e07e | 382 | goto error_global; |
fcaf780b MCC |
383 | } |
384 | ||
5de6e07e MCC |
385 | pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, |
386 | FERR_GLOBAL_LO, &value); | |
387 | if (unlikely(value)) { | |
388 | errors = value; | |
389 | errnum = find_first_bit(&errors, | |
390 | ARRAY_SIZE(ferr_global_lo_name)); | |
391 | specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum); | |
392 | is_fatal = ferr_global_lo_is_fatal(errnum); | |
86002324 MCC |
393 | |
394 | /* Clear the error bit */ | |
395 | pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
396 | FERR_GLOBAL_LO, value); | |
397 | ||
5de6e07e MCC |
398 | goto error_global; |
399 | } | |
400 | return; | |
fcaf780b | 401 | |
5de6e07e MCC |
402 | error_global: |
403 | i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s\n", | |
404 | is_fatal ? "Fatal" : "NOT fatal", specific); | |
fcaf780b MCC |
405 | } |
406 | ||
57021918 MCC |
407 | /* |
408 | * i7300_process_fbd_error Retrieve the hardware error information from | |
409 | * the hardware and cache it in the 'info' | |
410 | * structure | |
411 | */ | |
f4277422 | 412 | static void i7300_process_fbd_error(struct mem_ctl_info *mci) |
57021918 MCC |
413 | { |
414 | struct i7300_pvt *pvt; | |
415 | u32 errnum, value; | |
8199d8cc | 416 | u16 val16; |
32f94726 MCC |
417 | unsigned branch, bank, rank, cas, ras; |
418 | u32 syndrome; | |
419 | ||
57021918 MCC |
420 | unsigned long errors; |
421 | const char *specific; | |
32f94726 | 422 | bool is_wr; |
57021918 MCC |
423 | |
424 | pvt = mci->pvt_info; | |
425 | ||
426 | /* read in the 1st FATAL error register */ | |
427 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
428 | FERR_FAT_FBD, &value); | |
429 | if (unlikely(value & FERR_FAT_FBD_ERR_MASK)) { | |
430 | errors = value & FERR_FAT_FBD_ERR_MASK ; | |
431 | errnum = find_first_bit(&errors, | |
432 | ARRAY_SIZE(ferr_fat_fbd_name)); | |
433 | specific = GET_ERR_FROM_TABLE(ferr_fat_fbd_name, errnum); | |
57021918 MCC |
434 | |
435 | branch = (GET_FBD_FAT_IDX(value) == 2) ? 1 : 0; | |
8199d8cc MCC |
436 | pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, |
437 | NRECMEMA, &val16); | |
438 | bank = NRECMEMA_BANK(val16); | |
439 | rank = NRECMEMA_RANK(val16); | |
440 | ||
441 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
442 | NRECMEMB, &value); | |
443 | ||
444 | is_wr = NRECMEMB_IS_WR(value); | |
445 | cas = NRECMEMB_CAS(value); | |
446 | ras = NRECMEMB_RAS(value); | |
447 | ||
448 | snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, | |
449 | "FATAL (Branch=%d DRAM-Bank=%d %s " | |
450 | "RAS=%d CAS=%d Err=0x%lx (%s))", | |
32f94726 | 451 | branch, bank, |
8199d8cc MCC |
452 | is_wr ? "RDWR" : "RD", |
453 | ras, cas, | |
454 | errors, specific); | |
455 | ||
456 | /* Call the helper to output message */ | |
457 | edac_mc_handle_fbd_ue(mci, rank, branch << 1, | |
458 | (branch << 1) + 1, | |
459 | pvt->tmp_prt_buffer); | |
57021918 MCC |
460 | } |
461 | ||
462 | /* read in the 1st NON-FATAL error register */ | |
463 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
464 | FERR_NF_FBD, &value); | |
465 | if (unlikely(value & FERR_NF_FBD_ERR_MASK)) { | |
466 | errors = value & FERR_NF_FBD_ERR_MASK; | |
467 | errnum = find_first_bit(&errors, | |
468 | ARRAY_SIZE(ferr_nf_fbd_name)); | |
469 | specific = GET_ERR_FROM_TABLE(ferr_nf_fbd_name, errnum); | |
57021918 MCC |
470 | |
471 | /* Clear the error bit */ | |
472 | pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
473 | FERR_GLOBAL_LO, value); | |
474 | ||
32f94726 MCC |
475 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, |
476 | REDMEMA, &syndrome); | |
477 | ||
478 | branch = (GET_FBD_FAT_IDX(value) == 2) ? 1 : 0; | |
479 | pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, | |
480 | RECMEMA, &val16); | |
481 | bank = RECMEMA_BANK(val16); | |
482 | rank = RECMEMA_RANK(val16); | |
483 | ||
484 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
485 | RECMEMB, &value); | |
57021918 | 486 | |
32f94726 MCC |
487 | is_wr = RECMEMB_IS_WR(value); |
488 | cas = RECMEMB_CAS(value); | |
489 | ras = RECMEMB_RAS(value); | |
8199d8cc | 490 | |
32f94726 MCC |
491 | /* Form out message */ |
492 | snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, | |
493 | "Corrected error (Branch=%d (channel %d or %d), " | |
494 | " DRAM-Bank=%d %s " | |
495 | "RAS=%d CAS=%d, CE Err=0x%lx, Syndrome=0x%08x(%s))", | |
496 | branch, branch << 1, (branch << 1) + 1, | |
497 | bank, | |
498 | is_wr ? "RDWR" : "RD", | |
499 | ras, cas, | |
500 | errors, syndrome, specific); | |
501 | ||
502 | /* | |
503 | * Call the helper to output message | |
504 | * NOTE: Errors are reported per-branch, and not per-channel | |
505 | * Currently, we don't know how to identify the right | |
506 | * channel. | |
507 | */ | |
508 | edac_mc_handle_fbd_ce(mci, rank, branch << 1, | |
509 | pvt->tmp_prt_buffer); | |
510 | } | |
511 | return; | |
57021918 MCC |
512 | } |
513 | ||
fcaf780b | 514 | /* |
f4277422 | 515 | * i7300_check_error Retrieve the hardware error information from |
5de6e07e MCC |
516 | * the hardware and cache it in the 'info' |
517 | * structure | |
fcaf780b | 518 | */ |
f4277422 | 519 | static void i7300_check_error(struct mem_ctl_info *mci) |
5de6e07e | 520 | { |
f4277422 MCC |
521 | i7300_process_error_global(mci); |
522 | i7300_process_fbd_error(mci); | |
5de6e07e | 523 | }; |
fcaf780b MCC |
524 | |
525 | /* | |
526 | * i7300_clear_error Retrieve any error from the hardware | |
527 | * but do NOT process that error. | |
528 | * Used for 'clearing' out of previous errors | |
529 | * Called by the Core module. | |
530 | */ | |
531 | static void i7300_clear_error(struct mem_ctl_info *mci) | |
532 | { | |
e4327605 MCC |
533 | struct i7300_pvt *pvt = mci->pvt_info; |
534 | u32 value; | |
535 | /* | |
536 | * All error values are RWC - we need to read and write 1 to the | |
537 | * bit that we want to cleanup | |
538 | */ | |
fcaf780b | 539 | |
e4327605 MCC |
540 | /* Clear global error registers */ |
541 | pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
542 | FERR_GLOBAL_HI, &value); | |
543 | pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
544 | FERR_GLOBAL_HI, value); | |
545 | ||
546 | pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
547 | FERR_GLOBAL_LO, &value); | |
548 | pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
549 | FERR_GLOBAL_LO, value); | |
550 | ||
551 | /* Clear FBD error registers */ | |
552 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
553 | FERR_FAT_FBD, &value); | |
554 | pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
555 | FERR_FAT_FBD, value); | |
556 | ||
557 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
558 | FERR_NF_FBD, &value); | |
559 | pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
560 | FERR_NF_FBD, value); | |
fcaf780b MCC |
561 | } |
562 | ||
fcaf780b MCC |
563 | /* |
564 | * i7300_enable_error_reporting | |
565 | * Turn on the memory reporting features of the hardware | |
566 | */ | |
567 | static void i7300_enable_error_reporting(struct mem_ctl_info *mci) | |
568 | { | |
57021918 MCC |
569 | struct i7300_pvt *pvt = mci->pvt_info; |
570 | u32 fbd_error_mask; | |
571 | ||
572 | /* Read the FBD Error Mask Register */ | |
573 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
574 | EMASK_FBD, &fbd_error_mask); | |
575 | ||
576 | /* Enable with a '0' */ | |
577 | fbd_error_mask &= ~(EMASK_FBD_ERR_MASK); | |
578 | ||
579 | pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
580 | EMASK_FBD, fbd_error_mask); | |
fcaf780b | 581 | } |
5de6e07e MCC |
582 | |
583 | /************************************************ | |
584 | * i7300 Functions related to memory enumberation | |
585 | ************************************************/ | |
fcaf780b MCC |
586 | |
587 | /* | |
588 | * determine_mtr(pvt, csrow, channel) | |
589 | * | |
590 | * return the proper MTR register as determine by the csrow and desired channel | |
591 | */ | |
592 | static int decode_mtr(struct i7300_pvt *pvt, | |
593 | int slot, int ch, int branch, | |
594 | struct i7300_dimm_info *dinfo, | |
595 | struct csrow_info *p_csrow) | |
596 | { | |
597 | int mtr, ans, addrBits, channel; | |
598 | ||
599 | channel = to_channel(ch, branch); | |
600 | ||
601 | mtr = pvt->mtr[slot][branch]; | |
602 | ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0; | |
603 | ||
604 | debugf2("\tMTR%d CH%d: DIMMs are %s (mtr)\n", | |
605 | slot, channel, | |
606 | ans ? "Present" : "NOT Present"); | |
607 | ||
608 | /* Determine if there is a DIMM present in this DIMM slot */ | |
609 | ||
610 | #if 0 | |
611 | if (!amb_present || !ans) | |
612 | return 0; | |
613 | #else | |
614 | if (!ans) | |
615 | return 0; | |
616 | #endif | |
617 | ||
618 | /* Start with the number of bits for a Bank | |
619 | * on the DRAM */ | |
620 | addrBits = MTR_DRAM_BANKS_ADDR_BITS; | |
621 | /* Add thenumber of ROW bits */ | |
622 | addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); | |
623 | /* add the number of COLUMN bits */ | |
624 | addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); | |
625 | /* add the number of RANK bits */ | |
626 | addrBits += MTR_DIMM_RANKS(mtr); | |
627 | ||
628 | addrBits += 6; /* add 64 bits per DIMM */ | |
629 | addrBits -= 20; /* divide by 2^^20 */ | |
630 | addrBits -= 3; /* 8 bits per bytes */ | |
631 | ||
632 | dinfo->megabytes = 1 << addrBits; | |
633 | ||
634 | debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); | |
635 | ||
636 | debugf2("\t\tELECTRICAL THROTTLING is %s\n", | |
637 | MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); | |
638 | ||
639 | debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); | |
640 | debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single"); | |
641 | debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]); | |
642 | debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]); | |
643 | debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes); | |
644 | ||
645 | p_csrow->grain = 8; | |
646 | p_csrow->nr_pages = dinfo->megabytes << 8; | |
647 | p_csrow->mtype = MEM_FB_DDR2; | |
116389ed MCC |
648 | |
649 | /* | |
15154c57 | 650 | * The type of error detection actually depends of the |
116389ed | 651 | * mode of operation. When it is just one single memory chip, at |
15154c57 MCC |
652 | * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code. |
653 | * In normal or mirrored mode, it uses Lockstep mode, | |
116389ed MCC |
654 | * with the possibility of using an extended algorithm for x8 memories |
655 | * See datasheet Sections 7.3.6 to 7.3.8 | |
656 | */ | |
15154c57 MCC |
657 | |
658 | if (IS_SINGLE_MODE(pvt->mc_settings_a)) { | |
659 | p_csrow->edac_mode = EDAC_SECDED; | |
3b330f67 | 660 | debugf2("\t\tECC code is 8-byte-over-32-byte SECDED+ code\n"); |
15154c57 | 661 | } else { |
3b330f67 | 662 | debugf2("\t\tECC code is on Lockstep mode\n"); |
28c2ce7c | 663 | if (MTR_DRAM_WIDTH(mtr) == 8) |
15154c57 MCC |
664 | p_csrow->edac_mode = EDAC_S8ECD8ED; |
665 | else | |
666 | p_csrow->edac_mode = EDAC_S4ECD4ED; | |
667 | } | |
fcaf780b MCC |
668 | |
669 | /* ask what device type on this row */ | |
28c2ce7c | 670 | if (MTR_DRAM_WIDTH(mtr) == 8) { |
3b330f67 | 671 | debugf2("\t\tScrub algorithm for x8 is on %s mode\n", |
d7de2bdb MCC |
672 | IS_SCRBALGO_ENHANCED(pvt->mc_settings) ? |
673 | "enhanced" : "normal"); | |
674 | ||
fcaf780b | 675 | p_csrow->dtype = DEV_X8; |
d7de2bdb | 676 | } else |
fcaf780b MCC |
677 | p_csrow->dtype = DEV_X4; |
678 | ||
679 | return mtr; | |
680 | } | |
681 | ||
682 | /* | |
683 | * print_dimm_size | |
684 | * | |
685 | * also will output a DIMM matrix map, if debug is enabled, for viewing | |
686 | * how the DIMMs are populated | |
687 | */ | |
688 | static void print_dimm_size(struct i7300_pvt *pvt) | |
689 | { | |
690 | struct i7300_dimm_info *dinfo; | |
85580ea4 | 691 | char *p; |
fcaf780b MCC |
692 | int space, n; |
693 | int channel, slot; | |
694 | ||
695 | space = PAGE_SIZE; | |
85580ea4 | 696 | p = pvt->tmp_prt_buffer; |
fcaf780b MCC |
697 | |
698 | n = snprintf(p, space, " "); | |
699 | p += n; | |
700 | space -= n; | |
701 | for (channel = 0; channel < MAX_CHANNELS; channel++) { | |
702 | n = snprintf(p, space, "channel %d | ", channel); | |
703 | p += n; | |
704 | space -= n; | |
705 | } | |
85580ea4 MCC |
706 | debugf2("%s\n", pvt->tmp_prt_buffer); |
707 | p = pvt->tmp_prt_buffer; | |
fcaf780b MCC |
708 | space = PAGE_SIZE; |
709 | n = snprintf(p, space, "-------------------------------" | |
710 | "------------------------------"); | |
711 | p += n; | |
712 | space -= n; | |
85580ea4 MCC |
713 | debugf2("%s\n", pvt->tmp_prt_buffer); |
714 | p = pvt->tmp_prt_buffer; | |
fcaf780b MCC |
715 | space = PAGE_SIZE; |
716 | ||
717 | for (slot = 0; slot < MAX_SLOTS; slot++) { | |
718 | n = snprintf(p, space, "csrow/SLOT %d ", slot); | |
719 | p += n; | |
720 | space -= n; | |
721 | ||
722 | for (channel = 0; channel < MAX_CHANNELS; channel++) { | |
723 | dinfo = &pvt->dimm_info[slot][channel]; | |
724 | n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); | |
725 | p += n; | |
726 | space -= n; | |
727 | } | |
728 | ||
85580ea4 MCC |
729 | debugf2("%s\n", pvt->tmp_prt_buffer); |
730 | p = pvt->tmp_prt_buffer; | |
fcaf780b MCC |
731 | space = PAGE_SIZE; |
732 | } | |
733 | ||
734 | n = snprintf(p, space, "-------------------------------" | |
735 | "------------------------------"); | |
736 | p += n; | |
737 | space -= n; | |
85580ea4 MCC |
738 | debugf2("%s\n", pvt->tmp_prt_buffer); |
739 | p = pvt->tmp_prt_buffer; | |
fcaf780b | 740 | space = PAGE_SIZE; |
fcaf780b MCC |
741 | } |
742 | ||
743 | /* | |
744 | * i7300_init_csrows Initialize the 'csrows' table within | |
745 | * the mci control structure with the | |
746 | * addressing of memory. | |
747 | * | |
748 | * return: | |
749 | * 0 success | |
750 | * 1 no actual memory found on this MC | |
751 | */ | |
752 | static int i7300_init_csrows(struct mem_ctl_info *mci) | |
753 | { | |
754 | struct i7300_pvt *pvt; | |
755 | struct i7300_dimm_info *dinfo; | |
756 | struct csrow_info *p_csrow; | |
757 | int empty; | |
758 | int mtr; | |
759 | int ch, branch, slot, channel; | |
760 | ||
761 | pvt = mci->pvt_info; | |
762 | ||
763 | empty = 1; /* Assume NO memory */ | |
764 | ||
765 | debugf2("Memory Technology Registers:\n"); | |
766 | ||
767 | /* Get the AMB present registers for the four channels */ | |
768 | for (branch = 0; branch < MAX_BRANCHES; branch++) { | |
769 | /* Read and dump branch 0's MTRs */ | |
770 | channel = to_channel(0, branch); | |
3e57eef6 | 771 | pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_0, |
fcaf780b MCC |
772 | &pvt->ambpresent[channel]); |
773 | debugf2("\t\tAMB-present CH%d = 0x%x:\n", | |
774 | channel, pvt->ambpresent[channel]); | |
775 | ||
776 | channel = to_channel(1, branch); | |
3e57eef6 | 777 | pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_1, |
fcaf780b MCC |
778 | &pvt->ambpresent[channel]); |
779 | debugf2("\t\tAMB-present CH%d = 0x%x:\n", | |
780 | channel, pvt->ambpresent[channel]); | |
781 | } | |
782 | ||
783 | /* Get the set of MTR[0-7] regs by each branch */ | |
784 | for (slot = 0; slot < MAX_SLOTS; slot++) { | |
785 | int where = mtr_regs[slot]; | |
786 | for (branch = 0; branch < MAX_BRANCHES; branch++) { | |
3e57eef6 | 787 | pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], |
fcaf780b MCC |
788 | where, |
789 | &pvt->mtr[slot][branch]); | |
790 | for (ch = 0; ch < MAX_BRANCHES; ch++) { | |
791 | int channel = to_channel(ch, branch); | |
792 | ||
793 | dinfo = &pvt->dimm_info[slot][channel]; | |
794 | p_csrow = &mci->csrows[slot]; | |
795 | ||
796 | mtr = decode_mtr(pvt, slot, ch, branch, | |
797 | dinfo, p_csrow); | |
798 | /* if no DIMMS on this row, continue */ | |
799 | if (!MTR_DIMMS_PRESENT(mtr)) | |
800 | continue; | |
801 | ||
802 | p_csrow->csrow_idx = slot; | |
803 | ||
804 | /* FAKE OUT VALUES, FIXME */ | |
805 | p_csrow->first_page = 0 + slot * 20; | |
806 | p_csrow->last_page = 9 + slot * 20; | |
807 | p_csrow->page_mask = 0xfff; | |
808 | ||
809 | empty = 0; | |
810 | } | |
811 | } | |
812 | } | |
813 | ||
814 | return empty; | |
815 | } | |
816 | ||
817 | static void decode_mir(int mir_no, u16 mir[MAX_MIR]) | |
818 | { | |
819 | if (mir[mir_no] & 3) | |
820 | debugf2("MIR%d: limit= 0x%x Branch(es) that participate: %s %s\n", | |
821 | mir_no, | |
822 | (mir[mir_no] >> 4) & 0xfff, | |
823 | (mir[mir_no] & 1) ? "B0" : "", | |
824 | (mir[mir_no] & 2) ? "B1": ""); | |
825 | } | |
826 | ||
827 | /* | |
828 | * i7300_get_mc_regs read in the necessary registers and | |
829 | * cache locally | |
830 | * | |
831 | * Fills in the private data members | |
832 | */ | |
833 | static int i7300_get_mc_regs(struct mem_ctl_info *mci) | |
834 | { | |
835 | struct i7300_pvt *pvt; | |
836 | u32 actual_tolm; | |
837 | int i, rc; | |
838 | ||
839 | pvt = mci->pvt_info; | |
840 | ||
3e57eef6 | 841 | pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE, |
fcaf780b MCC |
842 | (u32 *) &pvt->ambase); |
843 | ||
844 | debugf2("AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase); | |
845 | ||
846 | /* Get the Branch Map regs */ | |
3e57eef6 | 847 | pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm); |
fcaf780b MCC |
848 | pvt->tolm >>= 12; |
849 | debugf2("TOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm, | |
850 | pvt->tolm); | |
851 | ||
852 | actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); | |
853 | debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n", | |
854 | actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); | |
855 | ||
af3d8831 | 856 | /* Get memory controller settings */ |
3e57eef6 | 857 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS, |
af3d8831 | 858 | &pvt->mc_settings); |
bb81a216 MCC |
859 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A, |
860 | &pvt->mc_settings_a); | |
d7de2bdb | 861 | |
bb81a216 MCC |
862 | if (IS_SINGLE_MODE(pvt->mc_settings_a)) |
863 | debugf0("Memory controller operating on single mode\n"); | |
864 | else | |
865 | debugf0("Memory controller operating on %s mode\n", | |
d7de2bdb | 866 | IS_MIRRORED(pvt->mc_settings) ? "mirrored" : "non-mirrored"); |
bb81a216 | 867 | |
af3d8831 | 868 | debugf0("Error detection is %s\n", |
d7de2bdb MCC |
869 | IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); |
870 | debugf0("Retry is %s\n", | |
871 | IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); | |
af3d8831 MCC |
872 | |
873 | /* Get Memory Interleave Range registers */ | |
3e57eef6 MCC |
874 | pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0, &pvt->mir[0]); |
875 | pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1, &pvt->mir[1]); | |
876 | pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2, &pvt->mir[2]); | |
fcaf780b MCC |
877 | |
878 | /* Decode the MIR regs */ | |
879 | for (i = 0; i < MAX_MIR; i++) | |
880 | decode_mir(i, pvt->mir); | |
881 | ||
882 | rc = i7300_init_csrows(mci); | |
883 | if (rc < 0) | |
884 | return rc; | |
885 | ||
886 | /* Go and determine the size of each DIMM and place in an | |
887 | * orderly matrix */ | |
888 | print_dimm_size(pvt); | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
5de6e07e MCC |
893 | /************************************************* |
894 | * i7300 Functions related to device probe/release | |
895 | *************************************************/ | |
896 | ||
fcaf780b MCC |
897 | /* |
898 | * i7300_put_devices 'put' all the devices that we have | |
899 | * reserved via 'get' | |
900 | */ | |
901 | static void i7300_put_devices(struct mem_ctl_info *mci) | |
902 | { | |
903 | struct i7300_pvt *pvt; | |
904 | int branch; | |
905 | ||
906 | pvt = mci->pvt_info; | |
907 | ||
908 | /* Decrement usage count for devices */ | |
909 | for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++) | |
3e57eef6 MCC |
910 | pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]); |
911 | pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs); | |
912 | pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map); | |
fcaf780b MCC |
913 | } |
914 | ||
915 | /* | |
916 | * i7300_get_devices Find and perform 'get' operation on the MCH's | |
917 | * device/functions we want to reference for this driver | |
918 | * | |
919 | * Need to 'get' device 16 func 1 and func 2 | |
920 | */ | |
921 | static int i7300_get_devices(struct mem_ctl_info *mci, int dev_idx) | |
922 | { | |
923 | struct i7300_pvt *pvt; | |
924 | struct pci_dev *pdev; | |
925 | ||
926 | pvt = mci->pvt_info; | |
927 | ||
928 | /* Attempt to 'get' the MCH register we want */ | |
929 | pdev = NULL; | |
3e57eef6 | 930 | while (!pvt->pci_dev_16_1_fsb_addr_map || !pvt->pci_dev_16_2_fsb_err_regs) { |
fcaf780b MCC |
931 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
932 | PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev); | |
933 | if (!pdev) { | |
934 | /* End of list, leave */ | |
935 | i7300_printk(KERN_ERR, | |
936 | "'system address,Process Bus' " | |
937 | "device not found:" | |
938 | "vendor 0x%x device 0x%x ERR funcs " | |
939 | "(broken BIOS?)\n", | |
940 | PCI_VENDOR_ID_INTEL, | |
941 | PCI_DEVICE_ID_INTEL_I7300_MCH_ERR); | |
942 | goto error; | |
943 | } | |
944 | ||
945 | /* Store device 16 funcs 1 and 2 */ | |
946 | switch (PCI_FUNC(pdev->devfn)) { | |
947 | case 1: | |
3e57eef6 | 948 | pvt->pci_dev_16_1_fsb_addr_map = pdev; |
fcaf780b MCC |
949 | break; |
950 | case 2: | |
3e57eef6 | 951 | pvt->pci_dev_16_2_fsb_err_regs = pdev; |
fcaf780b MCC |
952 | break; |
953 | } | |
954 | } | |
955 | ||
956 | debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n", | |
3e57eef6 MCC |
957 | pci_name(pvt->pci_dev_16_0_fsb_ctlr), |
958 | pvt->pci_dev_16_0_fsb_ctlr->vendor, pvt->pci_dev_16_0_fsb_ctlr->device); | |
fcaf780b | 959 | debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", |
3e57eef6 MCC |
960 | pci_name(pvt->pci_dev_16_1_fsb_addr_map), |
961 | pvt->pci_dev_16_1_fsb_addr_map->vendor, pvt->pci_dev_16_1_fsb_addr_map->device); | |
fcaf780b | 962 | debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n", |
3e57eef6 MCC |
963 | pci_name(pvt->pci_dev_16_2_fsb_err_regs), |
964 | pvt->pci_dev_16_2_fsb_err_regs->vendor, pvt->pci_dev_16_2_fsb_err_regs->device); | |
fcaf780b | 965 | |
3e57eef6 | 966 | pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL, |
fcaf780b MCC |
967 | PCI_DEVICE_ID_INTEL_I7300_MCH_FB0, |
968 | NULL); | |
3e57eef6 | 969 | if (!pvt->pci_dev_2x_0_fbd_branch[0]) { |
fcaf780b MCC |
970 | i7300_printk(KERN_ERR, |
971 | "MC: 'BRANCH 0' device not found:" | |
972 | "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n", | |
973 | PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0); | |
974 | goto error; | |
975 | } | |
976 | ||
3e57eef6 | 977 | pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL, |
fcaf780b MCC |
978 | PCI_DEVICE_ID_INTEL_I7300_MCH_FB1, |
979 | NULL); | |
3e57eef6 | 980 | if (!pvt->pci_dev_2x_0_fbd_branch[1]) { |
fcaf780b MCC |
981 | i7300_printk(KERN_ERR, |
982 | "MC: 'BRANCH 1' device not found:" | |
983 | "vendor 0x%x device 0x%x Func 0 " | |
984 | "(broken BIOS?)\n", | |
985 | PCI_VENDOR_ID_INTEL, | |
986 | PCI_DEVICE_ID_INTEL_I7300_MCH_FB1); | |
987 | goto error; | |
988 | } | |
989 | ||
990 | return 0; | |
991 | ||
992 | error: | |
993 | i7300_put_devices(mci); | |
994 | return -ENODEV; | |
995 | } | |
996 | ||
997 | /* | |
998 | * i7300_probe1 Probe for ONE instance of device to see if it is | |
999 | * present. | |
1000 | * return: | |
1001 | * 0 for FOUND a device | |
1002 | * < 0 for error code | |
1003 | */ | |
1004 | static int i7300_probe1(struct pci_dev *pdev, int dev_idx) | |
1005 | { | |
1006 | struct mem_ctl_info *mci; | |
1007 | struct i7300_pvt *pvt; | |
1008 | int num_channels; | |
1009 | int num_dimms_per_channel; | |
1010 | int num_csrows; | |
1011 | ||
1012 | if (dev_idx >= ARRAY_SIZE(i7300_devs)) | |
1013 | return -EINVAL; | |
1014 | ||
1015 | debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n", | |
1016 | __func__, | |
1017 | pdev->bus->number, | |
1018 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
1019 | ||
1020 | /* We only are looking for func 0 of the set */ | |
1021 | if (PCI_FUNC(pdev->devfn) != 0) | |
1022 | return -ENODEV; | |
1023 | ||
1024 | /* As we don't have a motherboard identification routine to determine | |
1025 | * actual number of slots/dimms per channel, we thus utilize the | |
1026 | * resource as specified by the chipset. Thus, we might have | |
1027 | * have more DIMMs per channel than actually on the mobo, but this | |
1028 | * allows the driver to support upto the chipset max, without | |
1029 | * some fancy mobo determination. | |
1030 | */ | |
1031 | num_dimms_per_channel = MAX_SLOTS; | |
1032 | num_channels = MAX_CHANNELS; | |
1033 | num_csrows = MAX_SLOTS * MAX_CHANNELS; | |
1034 | ||
1035 | debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n", | |
1036 | __func__, num_channels, num_dimms_per_channel, num_csrows); | |
1037 | ||
1038 | /* allocate a new MC control structure */ | |
1039 | mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0); | |
1040 | ||
1041 | if (mci == NULL) | |
1042 | return -ENOMEM; | |
1043 | ||
1044 | debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci); | |
1045 | ||
1046 | mci->dev = &pdev->dev; /* record ptr to the generic device */ | |
1047 | ||
1048 | pvt = mci->pvt_info; | |
3e57eef6 | 1049 | pvt->pci_dev_16_0_fsb_ctlr = pdev; /* Record this device in our private */ |
fcaf780b | 1050 | |
85580ea4 MCC |
1051 | pvt->tmp_prt_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL); |
1052 | if (!pvt->tmp_prt_buffer) { | |
1053 | edac_mc_free(mci); | |
1054 | return -ENOMEM; | |
1055 | } | |
1056 | ||
fcaf780b MCC |
1057 | /* 'get' the pci devices we want to reserve for our use */ |
1058 | if (i7300_get_devices(mci, dev_idx)) | |
1059 | goto fail0; | |
1060 | ||
1061 | mci->mc_idx = 0; | |
1062 | mci->mtype_cap = MEM_FLAG_FB_DDR2; | |
1063 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
1064 | mci->edac_cap = EDAC_FLAG_NONE; | |
1065 | mci->mod_name = "i7300_edac.c"; | |
1066 | mci->mod_ver = I7300_REVISION; | |
1067 | mci->ctl_name = i7300_devs[dev_idx].ctl_name; | |
1068 | mci->dev_name = pci_name(pdev); | |
1069 | mci->ctl_page_to_phys = NULL; | |
1070 | ||
fcaf780b MCC |
1071 | /* Set the function pointer to an actual operation function */ |
1072 | mci->edac_check = i7300_check_error; | |
fcaf780b MCC |
1073 | |
1074 | /* initialize the MC control structure 'csrows' table | |
1075 | * with the mapping and control information */ | |
1076 | if (i7300_get_mc_regs(mci)) { | |
1077 | debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n" | |
1078 | " because i7300_init_csrows() returned nonzero " | |
1079 | "value\n"); | |
1080 | mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */ | |
1081 | } else { | |
fcaf780b MCC |
1082 | debugf1("MC: Enable error reporting now\n"); |
1083 | i7300_enable_error_reporting(mci); | |
fcaf780b MCC |
1084 | } |
1085 | ||
1086 | /* add this new MC control structure to EDAC's list of MCs */ | |
1087 | if (edac_mc_add_mc(mci)) { | |
1088 | debugf0("MC: " __FILE__ | |
1089 | ": %s(): failed edac_mc_add_mc()\n", __func__); | |
1090 | /* FIXME: perhaps some code should go here that disables error | |
1091 | * reporting if we just enabled it | |
1092 | */ | |
1093 | goto fail1; | |
1094 | } | |
1095 | ||
fcaf780b | 1096 | i7300_clear_error(mci); |
fcaf780b MCC |
1097 | |
1098 | /* allocating generic PCI control info */ | |
1099 | i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); | |
1100 | if (!i7300_pci) { | |
1101 | printk(KERN_WARNING | |
1102 | "%s(): Unable to create PCI control\n", | |
1103 | __func__); | |
1104 | printk(KERN_WARNING | |
1105 | "%s(): PCI error report via EDAC not setup\n", | |
1106 | __func__); | |
1107 | } | |
1108 | ||
1109 | return 0; | |
1110 | ||
1111 | /* Error exit unwinding stack */ | |
1112 | fail1: | |
1113 | ||
1114 | i7300_put_devices(mci); | |
1115 | ||
1116 | fail0: | |
85580ea4 | 1117 | kfree(pvt->tmp_prt_buffer); |
fcaf780b MCC |
1118 | edac_mc_free(mci); |
1119 | return -ENODEV; | |
1120 | } | |
1121 | ||
1122 | /* | |
1123 | * i7300_init_one constructor for one instance of device | |
1124 | * | |
1125 | * returns: | |
1126 | * negative on error | |
1127 | * count (>= 0) | |
1128 | */ | |
1129 | static int __devinit i7300_init_one(struct pci_dev *pdev, | |
1130 | const struct pci_device_id *id) | |
1131 | { | |
1132 | int rc; | |
1133 | ||
1134 | debugf0("MC: " __FILE__ ": %s()\n", __func__); | |
1135 | ||
1136 | /* wake up device */ | |
1137 | rc = pci_enable_device(pdev); | |
1138 | if (rc == -EIO) | |
1139 | return rc; | |
1140 | ||
1141 | /* now probe and enable the device */ | |
1142 | return i7300_probe1(pdev, id->driver_data); | |
1143 | } | |
1144 | ||
1145 | /* | |
1146 | * i7300_remove_one destructor for one instance of device | |
1147 | * | |
1148 | */ | |
1149 | static void __devexit i7300_remove_one(struct pci_dev *pdev) | |
1150 | { | |
1151 | struct mem_ctl_info *mci; | |
85580ea4 | 1152 | char *tmp; |
fcaf780b MCC |
1153 | |
1154 | debugf0(__FILE__ ": %s()\n", __func__); | |
1155 | ||
1156 | if (i7300_pci) | |
1157 | edac_pci_release_generic_ctl(i7300_pci); | |
1158 | ||
1159 | mci = edac_mc_del_mc(&pdev->dev); | |
1160 | if (!mci) | |
1161 | return; | |
1162 | ||
85580ea4 MCC |
1163 | tmp = ((struct i7300_pvt *)mci->pvt_info)->tmp_prt_buffer; |
1164 | ||
fcaf780b MCC |
1165 | /* retrieve references to resources, and free those resources */ |
1166 | i7300_put_devices(mci); | |
1167 | ||
85580ea4 | 1168 | kfree(tmp); |
fcaf780b MCC |
1169 | edac_mc_free(mci); |
1170 | } | |
1171 | ||
1172 | /* | |
1173 | * pci_device_id table for which devices we are looking for | |
1174 | * | |
1175 | * The "E500P" device is the first device supported. | |
1176 | */ | |
1177 | static const struct pci_device_id i7300_pci_tbl[] __devinitdata = { | |
1178 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)}, | |
1179 | {0,} /* 0 terminated list. */ | |
1180 | }; | |
1181 | ||
1182 | MODULE_DEVICE_TABLE(pci, i7300_pci_tbl); | |
1183 | ||
1184 | /* | |
1185 | * i7300_driver pci_driver structure for this module | |
1186 | * | |
1187 | */ | |
1188 | static struct pci_driver i7300_driver = { | |
1189 | .name = "i7300_edac", | |
1190 | .probe = i7300_init_one, | |
1191 | .remove = __devexit_p(i7300_remove_one), | |
1192 | .id_table = i7300_pci_tbl, | |
1193 | }; | |
1194 | ||
1195 | /* | |
1196 | * i7300_init Module entry function | |
1197 | * Try to initialize this module for its devices | |
1198 | */ | |
1199 | static int __init i7300_init(void) | |
1200 | { | |
1201 | int pci_rc; | |
1202 | ||
1203 | debugf2("MC: " __FILE__ ": %s()\n", __func__); | |
1204 | ||
1205 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | |
1206 | opstate_init(); | |
1207 | ||
1208 | pci_rc = pci_register_driver(&i7300_driver); | |
1209 | ||
1210 | return (pci_rc < 0) ? pci_rc : 0; | |
1211 | } | |
1212 | ||
1213 | /* | |
1214 | * i7300_exit() Module exit function | |
1215 | * Unregister the driver | |
1216 | */ | |
1217 | static void __exit i7300_exit(void) | |
1218 | { | |
1219 | debugf2("MC: " __FILE__ ": %s()\n", __func__); | |
1220 | pci_unregister_driver(&i7300_driver); | |
1221 | } | |
1222 | ||
1223 | module_init(i7300_init); | |
1224 | module_exit(i7300_exit); | |
1225 | ||
1226 | MODULE_LICENSE("GPL"); | |
1227 | MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); | |
1228 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); | |
1229 | MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - " | |
1230 | I7300_REVISION); | |
1231 | ||
1232 | module_param(edac_op_state, int, 0444); | |
1233 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |