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fcaf780b MCC |
1 | /* |
2 | * Intel 7300 class Memory Controllers kernel module (Clarksboro) | |
3 | * | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License version 2 only. | |
6 | * | |
7 | * Copyright (c) 2010 by: | |
8 | * Mauro Carvalho Chehab <mchehab@redhat.com> | |
9 | * | |
10 | * Red Hat Inc. http://www.redhat.com | |
11 | * | |
12 | * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet | |
13 | * http://www.intel.com/Assets/PDF/datasheet/318082.pdf | |
14 | * | |
15 | * TODO: The chipset allow checking for PCI Express errors also. Currently, | |
16 | * the driver covers only memory error errors | |
17 | * | |
18 | * This driver uses "csrows" EDAC attribute to represent DIMM slot# | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/pci_ids.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/edac.h> | |
27 | #include <linux/mmzone.h> | |
28 | ||
29 | #include "edac_core.h" | |
30 | ||
31 | /* | |
32 | * Alter this version for the I7300 module when modifications are made | |
33 | */ | |
34 | #define I7300_REVISION " Ver: 1.0.0 " __DATE__ | |
35 | ||
36 | #define EDAC_MOD_STR "i7300_edac" | |
37 | ||
38 | #define i7300_printk(level, fmt, arg...) \ | |
39 | edac_printk(level, "i7300", fmt, ##arg) | |
40 | ||
41 | #define i7300_mc_printk(mci, level, fmt, arg...) \ | |
42 | edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg) | |
43 | ||
44 | /* | |
45 | * Memory topology is organized as: | |
46 | * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0) | |
47 | * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0) | |
48 | * Each channel can have to 8 DIMM sets (called as SLOTS) | |
49 | * Slots should generally be filled in pairs | |
50 | * Except on Single Channel mode of operation | |
51 | * just slot 0/channel0 filled on this mode | |
52 | * On normal operation mode, the two channels on a branch should be | |
c3af2eaf | 53 | * filled together for the same SLOT# |
fcaf780b MCC |
54 | * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four |
55 | * channels on both branches should be filled | |
56 | */ | |
57 | ||
58 | /* Limits for i7300 */ | |
59 | #define MAX_SLOTS 8 | |
60 | #define MAX_BRANCHES 2 | |
61 | #define MAX_CH_PER_BRANCH 2 | |
62 | #define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES) | |
63 | #define MAX_MIR 3 | |
64 | ||
65 | #define to_channel(ch, branch) ((((branch)) << 1) | (ch)) | |
66 | ||
67 | #define to_csrow(slot, ch, branch) \ | |
68 | (to_channel(ch, branch) | ((slot) << 2)) | |
69 | ||
c3af2eaf MCC |
70 | /* |
71 | * I7300 devices | |
fcaf780b MCC |
72 | * All 3 functions of Device 16 (0,1,2) share the SAME DID and |
73 | * uses PCI_DEVICE_ID_INTEL_I7300_MCH_ERR for device 16 (0,1,2), | |
74 | * PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 and PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 | |
75 | * for device 21 (0,1). | |
c3af2eaf MCC |
76 | */ |
77 | ||
78 | /**************************************************** | |
79 | * i7300 Register definitions for memory enumberation | |
80 | ****************************************************/ | |
81 | ||
82 | /* | |
83 | * Device 16, | |
84 | * Function 0: System Address (not documented) | |
85 | * Function 1: Memory Branch Map, Control, Errors Register | |
fcaf780b MCC |
86 | */ |
87 | ||
88 | /* OFFSETS for Function 0 */ | |
af3d8831 MCC |
89 | #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ |
90 | #define MAXCH 0x56 /* Max Channel Number */ | |
91 | #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */ | |
fcaf780b MCC |
92 | |
93 | /* OFFSETS for Function 1 */ | |
af3d8831 | 94 | #define MC_SETTINGS 0x40 |
bb81a216 MCC |
95 | #define IS_MIRRORED(mc) ((mc) & (1 << 16)) |
96 | #define IS_ECC_ENABLED(mc) ((mc) & (1 << 5)) | |
97 | #define IS_RETRY_ENABLED(mc) ((mc) & (1 << 31)) | |
98 | #define IS_SCRBALGO_ENHANCED(mc) ((mc) & (1 << 8)) | |
fcaf780b | 99 | |
bb81a216 MCC |
100 | #define MC_SETTINGS_A 0x58 |
101 | #define IS_SINGLE_MODE(mca) ((mca) & (1 << 14)) | |
d7de2bdb | 102 | |
af3d8831 MCC |
103 | #define TOLM 0x6C |
104 | #define REDMEMB 0x7C | |
105 | ||
106 | #define MIR0 0x80 | |
107 | #define MIR1 0x84 | |
108 | #define MIR2 0x88 | |
fcaf780b | 109 | |
fcaf780b MCC |
110 | /* |
111 | * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available | |
112 | * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it | |
113 | * seems that we cannot use this information directly for the same usage. | |
114 | * Each memory slot may have up to 2 AMB interfaces, one for income and another | |
115 | * for outcome interface to the next slot. | |
116 | * For now, the driver just stores the AMB present registers, but rely only at | |
117 | * the MTR info to detect memory. | |
118 | * Datasheet is also not clear about how to map each AMBPRESENT registers to | |
119 | * one of the 4 available channels. | |
120 | */ | |
121 | #define AMBPRESENT_0 0x64 | |
122 | #define AMBPRESENT_1 0x66 | |
123 | ||
124 | const static u16 mtr_regs [MAX_SLOTS] = { | |
125 | 0x80, 0x84, 0x88, 0x8c, | |
126 | 0x82, 0x86, 0x8a, 0x8e | |
127 | }; | |
128 | ||
129 | /* Defines to extract the vaious fields from the | |
130 | * MTRx - Memory Technology Registers | |
131 | */ | |
132 | #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8)) | |
133 | #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7)) | |
134 | #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4) | |
135 | #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4) | |
136 | #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0) | |
137 | #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) | |
138 | #define MTR_DRAM_BANKS_ADDR_BITS 2 | |
139 | #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) | |
140 | #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) | |
141 | #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) | |
142 | ||
fcaf780b MCC |
143 | #ifdef CONFIG_EDAC_DEBUG |
144 | /* MTR NUMROW */ | |
145 | static const char *numrow_toString[] = { | |
146 | "8,192 - 13 rows", | |
147 | "16,384 - 14 rows", | |
148 | "32,768 - 15 rows", | |
149 | "65,536 - 16 rows" | |
150 | }; | |
151 | ||
152 | /* MTR NUMCOL */ | |
153 | static const char *numcol_toString[] = { | |
154 | "1,024 - 10 columns", | |
155 | "2,048 - 11 columns", | |
156 | "4,096 - 12 columns", | |
157 | "reserved" | |
158 | }; | |
159 | #endif | |
160 | ||
c3af2eaf MCC |
161 | /************************************************ |
162 | * i7300 Register definitions for error detection | |
163 | ************************************************/ | |
57021918 MCC |
164 | |
165 | /* | |
166 | * Device 16.1: FBD Error Registers | |
167 | */ | |
168 | #define FERR_FAT_FBD 0x98 | |
169 | static const char *ferr_fat_fbd_name[] = { | |
170 | [22] = "Non-Redundant Fast Reset Timeout", | |
171 | [2] = ">Tmid Thermal event with intelligent throttling disabled", | |
172 | [1] = "Memory or FBD configuration CRC read error", | |
173 | [0] = "Memory Write error on non-redundant retry or " | |
174 | "FBD configuration Write error on retry", | |
175 | }; | |
176 | #define GET_FBD_FAT_IDX(fbderr) (fbderr & (3 << 28)) | |
177 | #define FERR_FAT_FBD_ERR_MASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) | |
178 | ||
179 | #define FERR_NF_FBD 0xa0 | |
180 | static const char *ferr_nf_fbd_name[] = { | |
181 | [24] = "DIMM-Spare Copy Completed", | |
182 | [23] = "DIMM-Spare Copy Initiated", | |
183 | [22] = "Redundant Fast Reset Timeout", | |
184 | [21] = "Memory Write error on redundant retry", | |
185 | [18] = "SPD protocol Error", | |
186 | [17] = "FBD Northbound parity error on FBD Sync Status", | |
187 | [16] = "Correctable Patrol Data ECC", | |
188 | [15] = "Correctable Resilver- or Spare-Copy Data ECC", | |
189 | [14] = "Correctable Mirrored Demand Data ECC", | |
190 | [13] = "Correctable Non-Mirrored Demand Data ECC", | |
191 | [11] = "Memory or FBD configuration CRC read error", | |
192 | [10] = "FBD Configuration Write error on first attempt", | |
193 | [9] = "Memory Write error on first attempt", | |
194 | [8] = "Non-Aliased Uncorrectable Patrol Data ECC", | |
195 | [7] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", | |
196 | [6] = "Non-Aliased Uncorrectable Mirrored Demand Data ECC", | |
197 | [5] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC", | |
198 | [4] = "Aliased Uncorrectable Patrol Data ECC", | |
199 | [3] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", | |
200 | [2] = "Aliased Uncorrectable Mirrored Demand Data ECC", | |
201 | [1] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC", | |
202 | [0] = "Uncorrectable Data ECC on Replay", | |
203 | }; | |
204 | #define GET_FBD_NF_IDX(fbderr) (fbderr & (3 << 28)) | |
205 | #define FERR_NF_FBD_ERR_MASK ((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) |\ | |
206 | (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15) |\ | |
207 | (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10) |\ | |
208 | (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\ | |
209 | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\ | |
210 | (1 << 1) | (1 << 0)) | |
211 | ||
212 | #define EMASK_FBD 0xa8 | |
213 | #define EMASK_FBD_ERR_MASK ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) |\ | |
214 | (1 << 22) | (1 << 21) | (1 << 20) | (1 << 19) |\ | |
215 | (1 << 18) | (1 << 17) | (1 << 16) | (1 << 14) |\ | |
216 | (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) |\ | |
217 | (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\ | |
218 | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\ | |
219 | (1 << 1) | (1 << 0)) | |
220 | ||
c3af2eaf MCC |
221 | /* |
222 | * Device 16.2: Global Error Registers | |
223 | */ | |
224 | ||
5de6e07e MCC |
225 | #define FERR_GLOBAL_HI 0x48 |
226 | static const char *ferr_global_hi_name[] = { | |
227 | [3] = "FSB 3 Fatal Error", | |
228 | [2] = "FSB 2 Fatal Error", | |
229 | [1] = "FSB 1 Fatal Error", | |
230 | [0] = "FSB 0 Fatal Error", | |
231 | }; | |
232 | #define ferr_global_hi_is_fatal(errno) 1 | |
233 | ||
c3af2eaf | 234 | #define FERR_GLOBAL_LO 0x40 |
5de6e07e | 235 | static const char *ferr_global_lo_name[] = { |
c3af2eaf MCC |
236 | [31] = "Internal MCH Fatal Error", |
237 | [30] = "Intel QuickData Technology Device Fatal Error", | |
238 | [29] = "FSB1 Fatal Error", | |
239 | [28] = "FSB0 Fatal Error", | |
240 | [27] = "FBD Channel 3 Fatal Error", | |
241 | [26] = "FBD Channel 2 Fatal Error", | |
242 | [25] = "FBD Channel 1 Fatal Error", | |
243 | [24] = "FBD Channel 0 Fatal Error", | |
244 | [23] = "PCI Express Device 7Fatal Error", | |
245 | [22] = "PCI Express Device 6 Fatal Error", | |
246 | [21] = "PCI Express Device 5 Fatal Error", | |
247 | [20] = "PCI Express Device 4 Fatal Error", | |
248 | [19] = "PCI Express Device 3 Fatal Error", | |
249 | [18] = "PCI Express Device 2 Fatal Error", | |
250 | [17] = "PCI Express Device 1 Fatal Error", | |
251 | [16] = "ESI Fatal Error", | |
252 | [15] = "Internal MCH Non-Fatal Error", | |
253 | [14] = "Intel QuickData Technology Device Non Fatal Error", | |
254 | [13] = "FSB1 Non-Fatal Error", | |
255 | [12] = "FSB 0 Non-Fatal Error", | |
256 | [11] = "FBD Channel 3 Non-Fatal Error", | |
257 | [10] = "FBD Channel 2 Non-Fatal Error", | |
258 | [9] = "FBD Channel 1 Non-Fatal Error", | |
259 | [8] = "FBD Channel 0 Non-Fatal Error", | |
260 | [7] = "PCI Express Device 7 Non-Fatal Error", | |
261 | [6] = "PCI Express Device 6 Non-Fatal Error", | |
262 | [5] = "PCI Express Device 5 Non-Fatal Error", | |
263 | [4] = "PCI Express Device 4 Non-Fatal Error", | |
264 | [3] = "PCI Express Device 3 Non-Fatal Error", | |
265 | [2] = "PCI Express Device 2 Non-Fatal Error", | |
266 | [1] = "PCI Express Device 1 Non-Fatal Error", | |
267 | [0] = "ESI Non-Fatal Error", | |
268 | }; | |
5de6e07e | 269 | #define ferr_global_lo_is_fatal(errno) ((errno < 16) ? 0 : 1) |
fcaf780b MCC |
270 | |
271 | /* Device name and register DID (Device ID) */ | |
272 | struct i7300_dev_info { | |
273 | const char *ctl_name; /* name for this device */ | |
274 | u16 fsb_mapping_errors; /* DID for the branchmap,control */ | |
275 | }; | |
276 | ||
277 | /* Table of devices attributes supported by this driver */ | |
278 | static const struct i7300_dev_info i7300_devs[] = { | |
279 | { | |
280 | .ctl_name = "I7300", | |
281 | .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, | |
282 | }, | |
283 | }; | |
284 | ||
285 | struct i7300_dimm_info { | |
286 | int megabytes; /* size, 0 means not present */ | |
287 | }; | |
288 | ||
289 | /* driver private data structure */ | |
290 | struct i7300_pvt { | |
3e57eef6 MCC |
291 | struct pci_dev *pci_dev_16_0_fsb_ctlr; /* 16.0 */ |
292 | struct pci_dev *pci_dev_16_1_fsb_addr_map; /* 16.1 */ | |
293 | struct pci_dev *pci_dev_16_2_fsb_err_regs; /* 16.2 */ | |
294 | struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES]; /* 21.0 and 22.0 */ | |
fcaf780b MCC |
295 | |
296 | u16 tolm; /* top of low memory */ | |
297 | u64 ambase; /* AMB BAR */ | |
298 | ||
bb81a216 MCC |
299 | u32 mc_settings; /* Report several settings */ |
300 | u32 mc_settings_a; | |
301 | ||
302 | u16 mir[MAX_MIR]; /* Memory Interleave Reg*/ | |
fcaf780b MCC |
303 | |
304 | u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */ | |
305 | u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */ | |
306 | ||
307 | /* DIMM information matrix, allocating architecture maximums */ | |
308 | struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS]; | |
309 | }; | |
310 | ||
fcaf780b MCC |
311 | /* FIXME: Why do we need to have this static? */ |
312 | static struct edac_pci_ctl_info *i7300_pci; | |
313 | ||
5de6e07e MCC |
314 | /******************************************** |
315 | * i7300 Functions related to error detection | |
316 | ********************************************/ | |
fcaf780b | 317 | |
5de6e07e | 318 | const char *get_err_from_table(const char *table[], int size, int pos) |
fcaf780b | 319 | { |
5de6e07e MCC |
320 | if (pos >= size) |
321 | return "Reserved"; | |
322 | ||
323 | return table[pos]; | |
fcaf780b MCC |
324 | } |
325 | ||
5de6e07e MCC |
326 | #define GET_ERR_FROM_TABLE(table, pos) \ |
327 | get_err_from_table(table, ARRAY_SIZE(table), pos) | |
328 | ||
fcaf780b | 329 | /* |
5de6e07e MCC |
330 | * i7300_process_error_global Retrieve the hardware error information from |
331 | * the hardware and cache it in the 'info' | |
332 | * structure | |
fcaf780b | 333 | */ |
f4277422 | 334 | static void i7300_process_error_global(struct mem_ctl_info *mci) |
fcaf780b | 335 | { |
5de6e07e MCC |
336 | struct i7300_pvt *pvt; |
337 | u32 errnum, value; | |
338 | unsigned long errors; | |
339 | const char *specific; | |
340 | bool is_fatal; | |
fcaf780b | 341 | |
5de6e07e | 342 | pvt = mci->pvt_info; |
fcaf780b | 343 | |
5de6e07e MCC |
344 | /* read in the 1st FATAL error register */ |
345 | pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
346 | FERR_GLOBAL_HI, &value); | |
347 | if (unlikely(value)) { | |
348 | errors = value; | |
349 | errnum = find_first_bit(&errors, | |
350 | ARRAY_SIZE(ferr_global_hi_name)); | |
351 | specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum); | |
352 | is_fatal = ferr_global_hi_is_fatal(errnum); | |
86002324 MCC |
353 | |
354 | /* Clear the error bit */ | |
355 | pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
356 | FERR_GLOBAL_HI, value); | |
357 | ||
5de6e07e | 358 | goto error_global; |
fcaf780b MCC |
359 | } |
360 | ||
5de6e07e MCC |
361 | pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, |
362 | FERR_GLOBAL_LO, &value); | |
363 | if (unlikely(value)) { | |
364 | errors = value; | |
365 | errnum = find_first_bit(&errors, | |
366 | ARRAY_SIZE(ferr_global_lo_name)); | |
367 | specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum); | |
368 | is_fatal = ferr_global_lo_is_fatal(errnum); | |
86002324 MCC |
369 | |
370 | /* Clear the error bit */ | |
371 | pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
372 | FERR_GLOBAL_LO, value); | |
373 | ||
5de6e07e MCC |
374 | goto error_global; |
375 | } | |
376 | return; | |
fcaf780b | 377 | |
5de6e07e MCC |
378 | error_global: |
379 | i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s\n", | |
380 | is_fatal ? "Fatal" : "NOT fatal", specific); | |
fcaf780b MCC |
381 | } |
382 | ||
57021918 MCC |
383 | /* |
384 | * i7300_process_fbd_error Retrieve the hardware error information from | |
385 | * the hardware and cache it in the 'info' | |
386 | * structure | |
387 | */ | |
f4277422 | 388 | static void i7300_process_fbd_error(struct mem_ctl_info *mci) |
57021918 MCC |
389 | { |
390 | struct i7300_pvt *pvt; | |
391 | u32 errnum, value; | |
392 | int branch; | |
393 | unsigned long errors; | |
394 | const char *specific; | |
395 | bool is_fatal; | |
396 | ||
397 | pvt = mci->pvt_info; | |
398 | ||
399 | /* read in the 1st FATAL error register */ | |
400 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
401 | FERR_FAT_FBD, &value); | |
402 | if (unlikely(value & FERR_FAT_FBD_ERR_MASK)) { | |
403 | errors = value & FERR_FAT_FBD_ERR_MASK ; | |
404 | errnum = find_first_bit(&errors, | |
405 | ARRAY_SIZE(ferr_fat_fbd_name)); | |
406 | specific = GET_ERR_FROM_TABLE(ferr_fat_fbd_name, errnum); | |
407 | is_fatal = 1; | |
408 | ||
409 | branch = (GET_FBD_FAT_IDX(value) == 2) ? 1 : 0; | |
410 | ||
411 | goto error_fbd; | |
412 | } | |
413 | ||
414 | /* read in the 1st NON-FATAL error register */ | |
415 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
416 | FERR_NF_FBD, &value); | |
417 | if (unlikely(value & FERR_NF_FBD_ERR_MASK)) { | |
418 | errors = value & FERR_NF_FBD_ERR_MASK; | |
419 | errnum = find_first_bit(&errors, | |
420 | ARRAY_SIZE(ferr_nf_fbd_name)); | |
421 | specific = GET_ERR_FROM_TABLE(ferr_nf_fbd_name, errnum); | |
422 | is_fatal = 0; | |
423 | ||
424 | /* Clear the error bit */ | |
425 | pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
426 | FERR_GLOBAL_LO, value); | |
427 | ||
428 | goto error_fbd; | |
429 | } | |
430 | return; | |
431 | ||
432 | error_fbd: | |
433 | i7300_mc_printk(mci, KERN_EMERG, "%s FBD error on branch %d: %s\n", | |
434 | is_fatal ? "Fatal" : "NOT fatal", branch, specific); | |
435 | } | |
436 | ||
fcaf780b | 437 | /* |
f4277422 | 438 | * i7300_check_error Retrieve the hardware error information from |
5de6e07e MCC |
439 | * the hardware and cache it in the 'info' |
440 | * structure | |
fcaf780b | 441 | */ |
f4277422 | 442 | static void i7300_check_error(struct mem_ctl_info *mci) |
5de6e07e | 443 | { |
f4277422 MCC |
444 | i7300_process_error_global(mci); |
445 | i7300_process_fbd_error(mci); | |
5de6e07e | 446 | }; |
fcaf780b MCC |
447 | |
448 | /* | |
449 | * i7300_clear_error Retrieve any error from the hardware | |
450 | * but do NOT process that error. | |
451 | * Used for 'clearing' out of previous errors | |
452 | * Called by the Core module. | |
453 | */ | |
454 | static void i7300_clear_error(struct mem_ctl_info *mci) | |
455 | { | |
e4327605 MCC |
456 | struct i7300_pvt *pvt = mci->pvt_info; |
457 | u32 value; | |
458 | /* | |
459 | * All error values are RWC - we need to read and write 1 to the | |
460 | * bit that we want to cleanup | |
461 | */ | |
fcaf780b | 462 | |
e4327605 MCC |
463 | /* Clear global error registers */ |
464 | pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
465 | FERR_GLOBAL_HI, &value); | |
466 | pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
467 | FERR_GLOBAL_HI, value); | |
468 | ||
469 | pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
470 | FERR_GLOBAL_LO, &value); | |
471 | pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, | |
472 | FERR_GLOBAL_LO, value); | |
473 | ||
474 | /* Clear FBD error registers */ | |
475 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
476 | FERR_FAT_FBD, &value); | |
477 | pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
478 | FERR_FAT_FBD, value); | |
479 | ||
480 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
481 | FERR_NF_FBD, &value); | |
482 | pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
483 | FERR_NF_FBD, value); | |
fcaf780b MCC |
484 | } |
485 | ||
fcaf780b MCC |
486 | /* |
487 | * i7300_enable_error_reporting | |
488 | * Turn on the memory reporting features of the hardware | |
489 | */ | |
490 | static void i7300_enable_error_reporting(struct mem_ctl_info *mci) | |
491 | { | |
57021918 MCC |
492 | struct i7300_pvt *pvt = mci->pvt_info; |
493 | u32 fbd_error_mask; | |
494 | ||
495 | /* Read the FBD Error Mask Register */ | |
496 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
497 | EMASK_FBD, &fbd_error_mask); | |
498 | ||
499 | /* Enable with a '0' */ | |
500 | fbd_error_mask &= ~(EMASK_FBD_ERR_MASK); | |
501 | ||
502 | pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, | |
503 | EMASK_FBD, fbd_error_mask); | |
fcaf780b | 504 | } |
5de6e07e MCC |
505 | |
506 | /************************************************ | |
507 | * i7300 Functions related to memory enumberation | |
508 | ************************************************/ | |
fcaf780b MCC |
509 | |
510 | /* | |
511 | * determine_mtr(pvt, csrow, channel) | |
512 | * | |
513 | * return the proper MTR register as determine by the csrow and desired channel | |
514 | */ | |
515 | static int decode_mtr(struct i7300_pvt *pvt, | |
516 | int slot, int ch, int branch, | |
517 | struct i7300_dimm_info *dinfo, | |
518 | struct csrow_info *p_csrow) | |
519 | { | |
520 | int mtr, ans, addrBits, channel; | |
521 | ||
522 | channel = to_channel(ch, branch); | |
523 | ||
524 | mtr = pvt->mtr[slot][branch]; | |
525 | ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0; | |
526 | ||
527 | debugf2("\tMTR%d CH%d: DIMMs are %s (mtr)\n", | |
528 | slot, channel, | |
529 | ans ? "Present" : "NOT Present"); | |
530 | ||
531 | /* Determine if there is a DIMM present in this DIMM slot */ | |
532 | ||
533 | #if 0 | |
534 | if (!amb_present || !ans) | |
535 | return 0; | |
536 | #else | |
537 | if (!ans) | |
538 | return 0; | |
539 | #endif | |
540 | ||
541 | /* Start with the number of bits for a Bank | |
542 | * on the DRAM */ | |
543 | addrBits = MTR_DRAM_BANKS_ADDR_BITS; | |
544 | /* Add thenumber of ROW bits */ | |
545 | addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); | |
546 | /* add the number of COLUMN bits */ | |
547 | addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); | |
548 | /* add the number of RANK bits */ | |
549 | addrBits += MTR_DIMM_RANKS(mtr); | |
550 | ||
551 | addrBits += 6; /* add 64 bits per DIMM */ | |
552 | addrBits -= 20; /* divide by 2^^20 */ | |
553 | addrBits -= 3; /* 8 bits per bytes */ | |
554 | ||
555 | dinfo->megabytes = 1 << addrBits; | |
556 | ||
557 | debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); | |
558 | ||
559 | debugf2("\t\tELECTRICAL THROTTLING is %s\n", | |
560 | MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); | |
561 | ||
562 | debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); | |
563 | debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single"); | |
564 | debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]); | |
565 | debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]); | |
566 | debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes); | |
567 | ||
568 | p_csrow->grain = 8; | |
569 | p_csrow->nr_pages = dinfo->megabytes << 8; | |
570 | p_csrow->mtype = MEM_FB_DDR2; | |
116389ed MCC |
571 | |
572 | /* | |
15154c57 | 573 | * The type of error detection actually depends of the |
116389ed | 574 | * mode of operation. When it is just one single memory chip, at |
15154c57 MCC |
575 | * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code. |
576 | * In normal or mirrored mode, it uses Lockstep mode, | |
116389ed MCC |
577 | * with the possibility of using an extended algorithm for x8 memories |
578 | * See datasheet Sections 7.3.6 to 7.3.8 | |
579 | */ | |
15154c57 MCC |
580 | |
581 | if (IS_SINGLE_MODE(pvt->mc_settings_a)) { | |
582 | p_csrow->edac_mode = EDAC_SECDED; | |
3b330f67 | 583 | debugf2("\t\tECC code is 8-byte-over-32-byte SECDED+ code\n"); |
15154c57 | 584 | } else { |
3b330f67 | 585 | debugf2("\t\tECC code is on Lockstep mode\n"); |
15154c57 MCC |
586 | if (MTR_DRAM_WIDTH(mtr)) |
587 | p_csrow->edac_mode = EDAC_S8ECD8ED; | |
588 | else | |
589 | p_csrow->edac_mode = EDAC_S4ECD4ED; | |
590 | } | |
fcaf780b MCC |
591 | |
592 | /* ask what device type on this row */ | |
d7de2bdb | 593 | if (MTR_DRAM_WIDTH(mtr)) { |
3b330f67 | 594 | debugf2("\t\tScrub algorithm for x8 is on %s mode\n", |
d7de2bdb MCC |
595 | IS_SCRBALGO_ENHANCED(pvt->mc_settings) ? |
596 | "enhanced" : "normal"); | |
597 | ||
fcaf780b | 598 | p_csrow->dtype = DEV_X8; |
d7de2bdb | 599 | } else |
fcaf780b MCC |
600 | p_csrow->dtype = DEV_X4; |
601 | ||
602 | return mtr; | |
603 | } | |
604 | ||
605 | /* | |
606 | * print_dimm_size | |
607 | * | |
608 | * also will output a DIMM matrix map, if debug is enabled, for viewing | |
609 | * how the DIMMs are populated | |
610 | */ | |
611 | static void print_dimm_size(struct i7300_pvt *pvt) | |
612 | { | |
613 | struct i7300_dimm_info *dinfo; | |
614 | char *p, *mem_buffer; | |
615 | int space, n; | |
616 | int channel, slot; | |
617 | ||
618 | space = PAGE_SIZE; | |
619 | mem_buffer = p = kmalloc(space, GFP_KERNEL); | |
620 | if (p == NULL) { | |
621 | i7300_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n", | |
622 | __FILE__, __func__); | |
623 | return; | |
624 | } | |
625 | ||
626 | n = snprintf(p, space, " "); | |
627 | p += n; | |
628 | space -= n; | |
629 | for (channel = 0; channel < MAX_CHANNELS; channel++) { | |
630 | n = snprintf(p, space, "channel %d | ", channel); | |
631 | p += n; | |
632 | space -= n; | |
633 | } | |
634 | debugf2("%s\n", mem_buffer); | |
635 | p = mem_buffer; | |
636 | space = PAGE_SIZE; | |
637 | n = snprintf(p, space, "-------------------------------" | |
638 | "------------------------------"); | |
639 | p += n; | |
640 | space -= n; | |
641 | debugf2("%s\n", mem_buffer); | |
642 | p = mem_buffer; | |
643 | space = PAGE_SIZE; | |
644 | ||
645 | for (slot = 0; slot < MAX_SLOTS; slot++) { | |
646 | n = snprintf(p, space, "csrow/SLOT %d ", slot); | |
647 | p += n; | |
648 | space -= n; | |
649 | ||
650 | for (channel = 0; channel < MAX_CHANNELS; channel++) { | |
651 | dinfo = &pvt->dimm_info[slot][channel]; | |
652 | n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); | |
653 | p += n; | |
654 | space -= n; | |
655 | } | |
656 | ||
657 | debugf2("%s\n", mem_buffer); | |
658 | p = mem_buffer; | |
659 | space = PAGE_SIZE; | |
660 | } | |
661 | ||
662 | n = snprintf(p, space, "-------------------------------" | |
663 | "------------------------------"); | |
664 | p += n; | |
665 | space -= n; | |
666 | debugf2("%s\n", mem_buffer); | |
667 | p = mem_buffer; | |
668 | space = PAGE_SIZE; | |
669 | ||
670 | kfree(mem_buffer); | |
671 | } | |
672 | ||
673 | /* | |
674 | * i7300_init_csrows Initialize the 'csrows' table within | |
675 | * the mci control structure with the | |
676 | * addressing of memory. | |
677 | * | |
678 | * return: | |
679 | * 0 success | |
680 | * 1 no actual memory found on this MC | |
681 | */ | |
682 | static int i7300_init_csrows(struct mem_ctl_info *mci) | |
683 | { | |
684 | struct i7300_pvt *pvt; | |
685 | struct i7300_dimm_info *dinfo; | |
686 | struct csrow_info *p_csrow; | |
687 | int empty; | |
688 | int mtr; | |
689 | int ch, branch, slot, channel; | |
690 | ||
691 | pvt = mci->pvt_info; | |
692 | ||
693 | empty = 1; /* Assume NO memory */ | |
694 | ||
695 | debugf2("Memory Technology Registers:\n"); | |
696 | ||
697 | /* Get the AMB present registers for the four channels */ | |
698 | for (branch = 0; branch < MAX_BRANCHES; branch++) { | |
699 | /* Read and dump branch 0's MTRs */ | |
700 | channel = to_channel(0, branch); | |
3e57eef6 | 701 | pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_0, |
fcaf780b MCC |
702 | &pvt->ambpresent[channel]); |
703 | debugf2("\t\tAMB-present CH%d = 0x%x:\n", | |
704 | channel, pvt->ambpresent[channel]); | |
705 | ||
706 | channel = to_channel(1, branch); | |
3e57eef6 | 707 | pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_1, |
fcaf780b MCC |
708 | &pvt->ambpresent[channel]); |
709 | debugf2("\t\tAMB-present CH%d = 0x%x:\n", | |
710 | channel, pvt->ambpresent[channel]); | |
711 | } | |
712 | ||
713 | /* Get the set of MTR[0-7] regs by each branch */ | |
714 | for (slot = 0; slot < MAX_SLOTS; slot++) { | |
715 | int where = mtr_regs[slot]; | |
716 | for (branch = 0; branch < MAX_BRANCHES; branch++) { | |
3e57eef6 | 717 | pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], |
fcaf780b MCC |
718 | where, |
719 | &pvt->mtr[slot][branch]); | |
720 | for (ch = 0; ch < MAX_BRANCHES; ch++) { | |
721 | int channel = to_channel(ch, branch); | |
722 | ||
723 | dinfo = &pvt->dimm_info[slot][channel]; | |
724 | p_csrow = &mci->csrows[slot]; | |
725 | ||
726 | mtr = decode_mtr(pvt, slot, ch, branch, | |
727 | dinfo, p_csrow); | |
728 | /* if no DIMMS on this row, continue */ | |
729 | if (!MTR_DIMMS_PRESENT(mtr)) | |
730 | continue; | |
731 | ||
732 | p_csrow->csrow_idx = slot; | |
733 | ||
734 | /* FAKE OUT VALUES, FIXME */ | |
735 | p_csrow->first_page = 0 + slot * 20; | |
736 | p_csrow->last_page = 9 + slot * 20; | |
737 | p_csrow->page_mask = 0xfff; | |
738 | ||
739 | empty = 0; | |
740 | } | |
741 | } | |
742 | } | |
743 | ||
744 | return empty; | |
745 | } | |
746 | ||
747 | static void decode_mir(int mir_no, u16 mir[MAX_MIR]) | |
748 | { | |
749 | if (mir[mir_no] & 3) | |
750 | debugf2("MIR%d: limit= 0x%x Branch(es) that participate: %s %s\n", | |
751 | mir_no, | |
752 | (mir[mir_no] >> 4) & 0xfff, | |
753 | (mir[mir_no] & 1) ? "B0" : "", | |
754 | (mir[mir_no] & 2) ? "B1": ""); | |
755 | } | |
756 | ||
757 | /* | |
758 | * i7300_get_mc_regs read in the necessary registers and | |
759 | * cache locally | |
760 | * | |
761 | * Fills in the private data members | |
762 | */ | |
763 | static int i7300_get_mc_regs(struct mem_ctl_info *mci) | |
764 | { | |
765 | struct i7300_pvt *pvt; | |
766 | u32 actual_tolm; | |
767 | int i, rc; | |
768 | ||
769 | pvt = mci->pvt_info; | |
770 | ||
3e57eef6 | 771 | pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE, |
fcaf780b MCC |
772 | (u32 *) &pvt->ambase); |
773 | ||
774 | debugf2("AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase); | |
775 | ||
776 | /* Get the Branch Map regs */ | |
3e57eef6 | 777 | pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm); |
fcaf780b MCC |
778 | pvt->tolm >>= 12; |
779 | debugf2("TOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm, | |
780 | pvt->tolm); | |
781 | ||
782 | actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); | |
783 | debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n", | |
784 | actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); | |
785 | ||
af3d8831 | 786 | /* Get memory controller settings */ |
3e57eef6 | 787 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS, |
af3d8831 | 788 | &pvt->mc_settings); |
bb81a216 MCC |
789 | pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A, |
790 | &pvt->mc_settings_a); | |
d7de2bdb | 791 | |
bb81a216 MCC |
792 | if (IS_SINGLE_MODE(pvt->mc_settings_a)) |
793 | debugf0("Memory controller operating on single mode\n"); | |
794 | else | |
795 | debugf0("Memory controller operating on %s mode\n", | |
d7de2bdb | 796 | IS_MIRRORED(pvt->mc_settings) ? "mirrored" : "non-mirrored"); |
bb81a216 | 797 | |
af3d8831 | 798 | debugf0("Error detection is %s\n", |
d7de2bdb MCC |
799 | IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); |
800 | debugf0("Retry is %s\n", | |
801 | IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); | |
af3d8831 MCC |
802 | |
803 | /* Get Memory Interleave Range registers */ | |
3e57eef6 MCC |
804 | pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0, &pvt->mir[0]); |
805 | pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1, &pvt->mir[1]); | |
806 | pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2, &pvt->mir[2]); | |
fcaf780b MCC |
807 | |
808 | /* Decode the MIR regs */ | |
809 | for (i = 0; i < MAX_MIR; i++) | |
810 | decode_mir(i, pvt->mir); | |
811 | ||
812 | rc = i7300_init_csrows(mci); | |
813 | if (rc < 0) | |
814 | return rc; | |
815 | ||
816 | /* Go and determine the size of each DIMM and place in an | |
817 | * orderly matrix */ | |
818 | print_dimm_size(pvt); | |
819 | ||
820 | return 0; | |
821 | } | |
822 | ||
5de6e07e MCC |
823 | /************************************************* |
824 | * i7300 Functions related to device probe/release | |
825 | *************************************************/ | |
826 | ||
fcaf780b MCC |
827 | /* |
828 | * i7300_put_devices 'put' all the devices that we have | |
829 | * reserved via 'get' | |
830 | */ | |
831 | static void i7300_put_devices(struct mem_ctl_info *mci) | |
832 | { | |
833 | struct i7300_pvt *pvt; | |
834 | int branch; | |
835 | ||
836 | pvt = mci->pvt_info; | |
837 | ||
838 | /* Decrement usage count for devices */ | |
839 | for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++) | |
3e57eef6 MCC |
840 | pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]); |
841 | pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs); | |
842 | pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map); | |
fcaf780b MCC |
843 | } |
844 | ||
845 | /* | |
846 | * i7300_get_devices Find and perform 'get' operation on the MCH's | |
847 | * device/functions we want to reference for this driver | |
848 | * | |
849 | * Need to 'get' device 16 func 1 and func 2 | |
850 | */ | |
851 | static int i7300_get_devices(struct mem_ctl_info *mci, int dev_idx) | |
852 | { | |
853 | struct i7300_pvt *pvt; | |
854 | struct pci_dev *pdev; | |
855 | ||
856 | pvt = mci->pvt_info; | |
857 | ||
858 | /* Attempt to 'get' the MCH register we want */ | |
859 | pdev = NULL; | |
3e57eef6 | 860 | while (!pvt->pci_dev_16_1_fsb_addr_map || !pvt->pci_dev_16_2_fsb_err_regs) { |
fcaf780b MCC |
861 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
862 | PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev); | |
863 | if (!pdev) { | |
864 | /* End of list, leave */ | |
865 | i7300_printk(KERN_ERR, | |
866 | "'system address,Process Bus' " | |
867 | "device not found:" | |
868 | "vendor 0x%x device 0x%x ERR funcs " | |
869 | "(broken BIOS?)\n", | |
870 | PCI_VENDOR_ID_INTEL, | |
871 | PCI_DEVICE_ID_INTEL_I7300_MCH_ERR); | |
872 | goto error; | |
873 | } | |
874 | ||
875 | /* Store device 16 funcs 1 and 2 */ | |
876 | switch (PCI_FUNC(pdev->devfn)) { | |
877 | case 1: | |
3e57eef6 | 878 | pvt->pci_dev_16_1_fsb_addr_map = pdev; |
fcaf780b MCC |
879 | break; |
880 | case 2: | |
3e57eef6 | 881 | pvt->pci_dev_16_2_fsb_err_regs = pdev; |
fcaf780b MCC |
882 | break; |
883 | } | |
884 | } | |
885 | ||
886 | debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n", | |
3e57eef6 MCC |
887 | pci_name(pvt->pci_dev_16_0_fsb_ctlr), |
888 | pvt->pci_dev_16_0_fsb_ctlr->vendor, pvt->pci_dev_16_0_fsb_ctlr->device); | |
fcaf780b | 889 | debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", |
3e57eef6 MCC |
890 | pci_name(pvt->pci_dev_16_1_fsb_addr_map), |
891 | pvt->pci_dev_16_1_fsb_addr_map->vendor, pvt->pci_dev_16_1_fsb_addr_map->device); | |
fcaf780b | 892 | debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n", |
3e57eef6 MCC |
893 | pci_name(pvt->pci_dev_16_2_fsb_err_regs), |
894 | pvt->pci_dev_16_2_fsb_err_regs->vendor, pvt->pci_dev_16_2_fsb_err_regs->device); | |
fcaf780b | 895 | |
3e57eef6 | 896 | pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL, |
fcaf780b MCC |
897 | PCI_DEVICE_ID_INTEL_I7300_MCH_FB0, |
898 | NULL); | |
3e57eef6 | 899 | if (!pvt->pci_dev_2x_0_fbd_branch[0]) { |
fcaf780b MCC |
900 | i7300_printk(KERN_ERR, |
901 | "MC: 'BRANCH 0' device not found:" | |
902 | "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n", | |
903 | PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0); | |
904 | goto error; | |
905 | } | |
906 | ||
3e57eef6 | 907 | pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL, |
fcaf780b MCC |
908 | PCI_DEVICE_ID_INTEL_I7300_MCH_FB1, |
909 | NULL); | |
3e57eef6 | 910 | if (!pvt->pci_dev_2x_0_fbd_branch[1]) { |
fcaf780b MCC |
911 | i7300_printk(KERN_ERR, |
912 | "MC: 'BRANCH 1' device not found:" | |
913 | "vendor 0x%x device 0x%x Func 0 " | |
914 | "(broken BIOS?)\n", | |
915 | PCI_VENDOR_ID_INTEL, | |
916 | PCI_DEVICE_ID_INTEL_I7300_MCH_FB1); | |
917 | goto error; | |
918 | } | |
919 | ||
920 | return 0; | |
921 | ||
922 | error: | |
923 | i7300_put_devices(mci); | |
924 | return -ENODEV; | |
925 | } | |
926 | ||
927 | /* | |
928 | * i7300_probe1 Probe for ONE instance of device to see if it is | |
929 | * present. | |
930 | * return: | |
931 | * 0 for FOUND a device | |
932 | * < 0 for error code | |
933 | */ | |
934 | static int i7300_probe1(struct pci_dev *pdev, int dev_idx) | |
935 | { | |
936 | struct mem_ctl_info *mci; | |
937 | struct i7300_pvt *pvt; | |
938 | int num_channels; | |
939 | int num_dimms_per_channel; | |
940 | int num_csrows; | |
941 | ||
942 | if (dev_idx >= ARRAY_SIZE(i7300_devs)) | |
943 | return -EINVAL; | |
944 | ||
945 | debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n", | |
946 | __func__, | |
947 | pdev->bus->number, | |
948 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
949 | ||
950 | /* We only are looking for func 0 of the set */ | |
951 | if (PCI_FUNC(pdev->devfn) != 0) | |
952 | return -ENODEV; | |
953 | ||
954 | /* As we don't have a motherboard identification routine to determine | |
955 | * actual number of slots/dimms per channel, we thus utilize the | |
956 | * resource as specified by the chipset. Thus, we might have | |
957 | * have more DIMMs per channel than actually on the mobo, but this | |
958 | * allows the driver to support upto the chipset max, without | |
959 | * some fancy mobo determination. | |
960 | */ | |
961 | num_dimms_per_channel = MAX_SLOTS; | |
962 | num_channels = MAX_CHANNELS; | |
963 | num_csrows = MAX_SLOTS * MAX_CHANNELS; | |
964 | ||
965 | debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n", | |
966 | __func__, num_channels, num_dimms_per_channel, num_csrows); | |
967 | ||
968 | /* allocate a new MC control structure */ | |
969 | mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0); | |
970 | ||
971 | if (mci == NULL) | |
972 | return -ENOMEM; | |
973 | ||
974 | debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci); | |
975 | ||
976 | mci->dev = &pdev->dev; /* record ptr to the generic device */ | |
977 | ||
978 | pvt = mci->pvt_info; | |
3e57eef6 | 979 | pvt->pci_dev_16_0_fsb_ctlr = pdev; /* Record this device in our private */ |
fcaf780b MCC |
980 | |
981 | /* 'get' the pci devices we want to reserve for our use */ | |
982 | if (i7300_get_devices(mci, dev_idx)) | |
983 | goto fail0; | |
984 | ||
985 | mci->mc_idx = 0; | |
986 | mci->mtype_cap = MEM_FLAG_FB_DDR2; | |
987 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
988 | mci->edac_cap = EDAC_FLAG_NONE; | |
989 | mci->mod_name = "i7300_edac.c"; | |
990 | mci->mod_ver = I7300_REVISION; | |
991 | mci->ctl_name = i7300_devs[dev_idx].ctl_name; | |
992 | mci->dev_name = pci_name(pdev); | |
993 | mci->ctl_page_to_phys = NULL; | |
994 | ||
fcaf780b MCC |
995 | /* Set the function pointer to an actual operation function */ |
996 | mci->edac_check = i7300_check_error; | |
fcaf780b MCC |
997 | |
998 | /* initialize the MC control structure 'csrows' table | |
999 | * with the mapping and control information */ | |
1000 | if (i7300_get_mc_regs(mci)) { | |
1001 | debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n" | |
1002 | " because i7300_init_csrows() returned nonzero " | |
1003 | "value\n"); | |
1004 | mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */ | |
1005 | } else { | |
fcaf780b MCC |
1006 | debugf1("MC: Enable error reporting now\n"); |
1007 | i7300_enable_error_reporting(mci); | |
fcaf780b MCC |
1008 | } |
1009 | ||
1010 | /* add this new MC control structure to EDAC's list of MCs */ | |
1011 | if (edac_mc_add_mc(mci)) { | |
1012 | debugf0("MC: " __FILE__ | |
1013 | ": %s(): failed edac_mc_add_mc()\n", __func__); | |
1014 | /* FIXME: perhaps some code should go here that disables error | |
1015 | * reporting if we just enabled it | |
1016 | */ | |
1017 | goto fail1; | |
1018 | } | |
1019 | ||
fcaf780b | 1020 | i7300_clear_error(mci); |
fcaf780b MCC |
1021 | |
1022 | /* allocating generic PCI control info */ | |
1023 | i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); | |
1024 | if (!i7300_pci) { | |
1025 | printk(KERN_WARNING | |
1026 | "%s(): Unable to create PCI control\n", | |
1027 | __func__); | |
1028 | printk(KERN_WARNING | |
1029 | "%s(): PCI error report via EDAC not setup\n", | |
1030 | __func__); | |
1031 | } | |
1032 | ||
1033 | return 0; | |
1034 | ||
1035 | /* Error exit unwinding stack */ | |
1036 | fail1: | |
1037 | ||
1038 | i7300_put_devices(mci); | |
1039 | ||
1040 | fail0: | |
1041 | edac_mc_free(mci); | |
1042 | return -ENODEV; | |
1043 | } | |
1044 | ||
1045 | /* | |
1046 | * i7300_init_one constructor for one instance of device | |
1047 | * | |
1048 | * returns: | |
1049 | * negative on error | |
1050 | * count (>= 0) | |
1051 | */ | |
1052 | static int __devinit i7300_init_one(struct pci_dev *pdev, | |
1053 | const struct pci_device_id *id) | |
1054 | { | |
1055 | int rc; | |
1056 | ||
1057 | debugf0("MC: " __FILE__ ": %s()\n", __func__); | |
1058 | ||
1059 | /* wake up device */ | |
1060 | rc = pci_enable_device(pdev); | |
1061 | if (rc == -EIO) | |
1062 | return rc; | |
1063 | ||
1064 | /* now probe and enable the device */ | |
1065 | return i7300_probe1(pdev, id->driver_data); | |
1066 | } | |
1067 | ||
1068 | /* | |
1069 | * i7300_remove_one destructor for one instance of device | |
1070 | * | |
1071 | */ | |
1072 | static void __devexit i7300_remove_one(struct pci_dev *pdev) | |
1073 | { | |
1074 | struct mem_ctl_info *mci; | |
1075 | ||
1076 | debugf0(__FILE__ ": %s()\n", __func__); | |
1077 | ||
1078 | if (i7300_pci) | |
1079 | edac_pci_release_generic_ctl(i7300_pci); | |
1080 | ||
1081 | mci = edac_mc_del_mc(&pdev->dev); | |
1082 | if (!mci) | |
1083 | return; | |
1084 | ||
1085 | /* retrieve references to resources, and free those resources */ | |
1086 | i7300_put_devices(mci); | |
1087 | ||
1088 | edac_mc_free(mci); | |
1089 | } | |
1090 | ||
1091 | /* | |
1092 | * pci_device_id table for which devices we are looking for | |
1093 | * | |
1094 | * The "E500P" device is the first device supported. | |
1095 | */ | |
1096 | static const struct pci_device_id i7300_pci_tbl[] __devinitdata = { | |
1097 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)}, | |
1098 | {0,} /* 0 terminated list. */ | |
1099 | }; | |
1100 | ||
1101 | MODULE_DEVICE_TABLE(pci, i7300_pci_tbl); | |
1102 | ||
1103 | /* | |
1104 | * i7300_driver pci_driver structure for this module | |
1105 | * | |
1106 | */ | |
1107 | static struct pci_driver i7300_driver = { | |
1108 | .name = "i7300_edac", | |
1109 | .probe = i7300_init_one, | |
1110 | .remove = __devexit_p(i7300_remove_one), | |
1111 | .id_table = i7300_pci_tbl, | |
1112 | }; | |
1113 | ||
1114 | /* | |
1115 | * i7300_init Module entry function | |
1116 | * Try to initialize this module for its devices | |
1117 | */ | |
1118 | static int __init i7300_init(void) | |
1119 | { | |
1120 | int pci_rc; | |
1121 | ||
1122 | debugf2("MC: " __FILE__ ": %s()\n", __func__); | |
1123 | ||
1124 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | |
1125 | opstate_init(); | |
1126 | ||
1127 | pci_rc = pci_register_driver(&i7300_driver); | |
1128 | ||
1129 | return (pci_rc < 0) ? pci_rc : 0; | |
1130 | } | |
1131 | ||
1132 | /* | |
1133 | * i7300_exit() Module exit function | |
1134 | * Unregister the driver | |
1135 | */ | |
1136 | static void __exit i7300_exit(void) | |
1137 | { | |
1138 | debugf2("MC: " __FILE__ ": %s()\n", __func__); | |
1139 | pci_unregister_driver(&i7300_driver); | |
1140 | } | |
1141 | ||
1142 | module_init(i7300_init); | |
1143 | module_exit(i7300_exit); | |
1144 | ||
1145 | MODULE_LICENSE("GPL"); | |
1146 | MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); | |
1147 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); | |
1148 | MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - " | |
1149 | I7300_REVISION); | |
1150 | ||
1151 | module_param(edac_op_state, int, 0444); | |
1152 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |