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i7300_edac: Adds detection for enhanced scrub mode on x8
[deliverable/linux.git] / drivers / edac / i7300_edac.c
CommitLineData
fcaf780b
MCC		 1/*
2 * Intel 7300 class Memory Controllers kernel module (Clarksboro)
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License version 2 only.
6 *
7 * Copyright (c) 2010 by:
8 * Mauro Carvalho Chehab <mchehab@redhat.com>
9 *
10 * Red Hat Inc. http://www.redhat.com
11 *
12 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
13 * http://www.intel.com/Assets/PDF/datasheet/318082.pdf
14 *
15 * TODO: The chipset allow checking for PCI Express errors also. Currently,
16 * the driver covers only memory error errors
17 *
18 * This driver uses "csrows" EDAC attribute to represent DIMM slot#
19 */
20
21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/pci.h>
24#include <linux/pci_ids.h>
25#include <linux/slab.h>
26#include <linux/edac.h>
27#include <linux/mmzone.h>
28
29#include "edac_core.h"
30
31/*
32 * Alter this version for the I7300 module when modifications are made
33 */
34#define I7300_REVISION " Ver: 1.0.0 " __DATE__
35
36#define EDAC_MOD_STR "i7300_edac"
37
38#define i7300_printk(level, fmt, arg...) \
39 edac_printk(level, "i7300", fmt, ##arg)
40
41#define i7300_mc_printk(mci, level, fmt, arg...) \
42 edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg)
43
44/*
45 * Memory topology is organized as:
46 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
47 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
48 * Each channel can have to 8 DIMM sets (called as SLOTS)
49 * Slots should generally be filled in pairs
50 * Except on Single Channel mode of operation
51 * just slot 0/channel0 filled on this mode
52 * On normal operation mode, the two channels on a branch should be
c3af2eaf 53 * filled together for the same SLOT#
fcaf780b
MCC		 54 * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
55 * channels on both branches should be filled
56 */
57
58/* Limits for i7300 */
59#define MAX_SLOTS 8
60#define MAX_BRANCHES 2
61#define MAX_CH_PER_BRANCH 2
62#define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES)
63#define MAX_MIR 3
64
65#define to_channel(ch, branch) ((((branch)) << 1) | (ch))
66
67#define to_csrow(slot, ch, branch) \
68 (to_channel(ch, branch) | ((slot) << 2))
69
c3af2eaf
MCC		 70/*
71 * I7300 devices
fcaf780b
MCC		 72 * All 3 functions of Device 16 (0,1,2) share the SAME DID and
73 * uses PCI_DEVICE_ID_INTEL_I7300_MCH_ERR for device 16 (0,1,2),
74 * PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 and PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
75 * for device 21 (0,1).
c3af2eaf
MCC		 76 */
77
78/****************************************************
79 * i7300 Register definitions for memory enumberation
80 ****************************************************/
81
82/*
83 * Device 16,
84 * Function 0: System Address (not documented)
85 * Function 1: Memory Branch Map, Control, Errors Register
fcaf780b
MCC		 86 */
87
88 /* OFFSETS for Function 0 */
af3d8831
MCC		 89#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
90#define MAXCH 0x56 /* Max Channel Number */
91#define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */
fcaf780b
MCC		 92
93 /* OFFSETS for Function 1 */
af3d8831 94#define MC_SETTINGS 0x40
fcaf780b 95
d7de2bdb
MCC		 96#define IS_MIRRORED(mc) ((mc) & (1 << 16))
97#define IS_ECC_ENABLED(mc) ((mc) & (1 << 5))
98#define IS_RETRY_ENABLED(mc) ((mc) & (1 << 31))
99#define IS_SCRBALGO_ENHANCED(mc) ((mc) & (1 << 8))
100
101
af3d8831
MCC		 102#define TOLM 0x6C
103#define REDMEMB 0x7C
104
105#define MIR0 0x80
106#define MIR1 0x84
107#define MIR2 0x88
fcaf780b 108
fcaf780b
MCC		 109/*
110 * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
111 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
112 * seems that we cannot use this information directly for the same usage.
113 * Each memory slot may have up to 2 AMB interfaces, one for income and another
114 * for outcome interface to the next slot.
115 * For now, the driver just stores the AMB present registers, but rely only at
116 * the MTR info to detect memory.
117 * Datasheet is also not clear about how to map each AMBPRESENT registers to
118 * one of the 4 available channels.
119 */
120#define AMBPRESENT_0 0x64
121#define AMBPRESENT_1 0x66
122
123const static u16 mtr_regs [MAX_SLOTS] = {
124 0x80, 0x84, 0x88, 0x8c,
125 0x82, 0x86, 0x8a, 0x8e
126};
127
128/* Defines to extract the vaious fields from the
129 * MTRx - Memory Technology Registers
130 */
131#define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8))
132#define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7))
133#define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
134#define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4)
135#define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0)
136#define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
137#define MTR_DRAM_BANKS_ADDR_BITS 2
138#define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
139#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
140#define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
141
fcaf780b
MCC		 142#ifdef CONFIG_EDAC_DEBUG
143/* MTR NUMROW */
144static const char *numrow_toString[] = {
145 "8,192 - 13 rows",
146 "16,384 - 14 rows",
147 "32,768 - 15 rows",
148 "65,536 - 16 rows"
149};
150
151/* MTR NUMCOL */
152static const char *numcol_toString[] = {
153 "1,024 - 10 columns",
154 "2,048 - 11 columns",
155 "4,096 - 12 columns",
156 "reserved"
157};
158#endif
159
c3af2eaf
MCC		 160/************************************************
161 * i7300 Register definitions for error detection
162 ************************************************/
163/*
164 * Device 16.2: Global Error Registers
165 */
166
5de6e07e
MCC		 167#define FERR_GLOBAL_HI 0x48
168static const char *ferr_global_hi_name[] = {
169 [3] = "FSB 3 Fatal Error",
170 [2] = "FSB 2 Fatal Error",
171 [1] = "FSB 1 Fatal Error",
172 [0] = "FSB 0 Fatal Error",
173};
174#define ferr_global_hi_is_fatal(errno) 1
175
c3af2eaf 176#define FERR_GLOBAL_LO 0x40
5de6e07e 177static const char *ferr_global_lo_name[] = {
c3af2eaf
MCC		 178 [31] = "Internal MCH Fatal Error",
179 [30] = "Intel QuickData Technology Device Fatal Error",
180 [29] = "FSB1 Fatal Error",
181 [28] = "FSB0 Fatal Error",
182 [27] = "FBD Channel 3 Fatal Error",
183 [26] = "FBD Channel 2 Fatal Error",
184 [25] = "FBD Channel 1 Fatal Error",
185 [24] = "FBD Channel 0 Fatal Error",
186 [23] = "PCI Express Device 7Fatal Error",
187 [22] = "PCI Express Device 6 Fatal Error",
188 [21] = "PCI Express Device 5 Fatal Error",
189 [20] = "PCI Express Device 4 Fatal Error",
190 [19] = "PCI Express Device 3 Fatal Error",
191 [18] = "PCI Express Device 2 Fatal Error",
192 [17] = "PCI Express Device 1 Fatal Error",
193 [16] = "ESI Fatal Error",
194 [15] = "Internal MCH Non-Fatal Error",
195 [14] = "Intel QuickData Technology Device Non Fatal Error",
196 [13] = "FSB1 Non-Fatal Error",
197 [12] = "FSB 0 Non-Fatal Error",
198 [11] = "FBD Channel 3 Non-Fatal Error",
199 [10] = "FBD Channel 2 Non-Fatal Error",
200 [9] = "FBD Channel 1 Non-Fatal Error",
201 [8] = "FBD Channel 0 Non-Fatal Error",
202 [7] = "PCI Express Device 7 Non-Fatal Error",
203 [6] = "PCI Express Device 6 Non-Fatal Error",
204 [5] = "PCI Express Device 5 Non-Fatal Error",
205 [4] = "PCI Express Device 4 Non-Fatal Error",
206 [3] = "PCI Express Device 3 Non-Fatal Error",
207 [2] = "PCI Express Device 2 Non-Fatal Error",
208 [1] = "PCI Express Device 1 Non-Fatal Error",
209 [0] = "ESI Non-Fatal Error",
210};
5de6e07e 211#define ferr_global_lo_is_fatal(errno) ((errno < 16) ? 0 : 1)
fcaf780b
MCC		 212
213/* Device name and register DID (Device ID) */
214struct i7300_dev_info {
215 const char *ctl_name; /* name for this device */
216 u16 fsb_mapping_errors; /* DID for the branchmap,control */
217};
218
219/* Table of devices attributes supported by this driver */
220static const struct i7300_dev_info i7300_devs[] = {
221 {
222 .ctl_name = "I7300",
223 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR,
224 },
225};
226
227struct i7300_dimm_info {
228 int megabytes; /* size, 0 means not present */
229};
230
231/* driver private data structure */
232struct i7300_pvt {
3e57eef6
MCC		 233 struct pci_dev *pci_dev_16_0_fsb_ctlr; /* 16.0 */
234 struct pci_dev *pci_dev_16_1_fsb_addr_map; /* 16.1 */
235 struct pci_dev *pci_dev_16_2_fsb_err_regs; /* 16.2 */
236 struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES]; /* 21.0 and 22.0 */
fcaf780b
MCC		 237
238 u16 tolm; /* top of low memory */
239 u64 ambase; /* AMB BAR */
af3d8831 240 u32 mc_settings;
fcaf780b
MCC		 241
242 u16 mir[MAX_MIR];
243
244 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */
245 u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */
246
247 /* DIMM information matrix, allocating architecture maximums */
248 struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS];
249};
250
fcaf780b
MCC		 251/* FIXME: Why do we need to have this static? */
252static struct edac_pci_ctl_info *i7300_pci;
253
5de6e07e
MCC		 254/********************************************
255 * i7300 Functions related to error detection
256 ********************************************/
fcaf780b 257
5de6e07e
MCC		 258struct i7300_error_info {
259 int dummy; /* FIXME */
260};
261
262const char *get_err_from_table(const char *table[], int size, int pos)
fcaf780b 263{
5de6e07e
MCC		 264 if (pos >= size)
265 return "Reserved";
266
267 return table[pos];
fcaf780b
MCC		 268}
269
5de6e07e
MCC		 270#define GET_ERR_FROM_TABLE(table, pos) \
271 get_err_from_table(table, ARRAY_SIZE(table), pos)
272
fcaf780b
MCC		 273/*
274 * i7300_get_error_info Retrieve the hardware error information from
275 * the hardware and cache it in the 'info'
276 * structure
277 */
278static void i7300_get_error_info(struct mem_ctl_info *mci,
279 struct i7300_error_info *info)
280{
fcaf780b
MCC		 281}
282
283/*
5de6e07e
MCC		 284 * i7300_process_error_global Retrieve the hardware error information from
285 * the hardware and cache it in the 'info'
286 * structure
fcaf780b 287 */
5de6e07e
MCC		 288static void i7300_process_error_global(struct mem_ctl_info *mci,
289 struct i7300_error_info *info)
fcaf780b 290{
5de6e07e
MCC		 291 struct i7300_pvt *pvt;
292 u32 errnum, value;
293 unsigned long errors;
294 const char *specific;
295 bool is_fatal;
fcaf780b 296
5de6e07e 297 pvt = mci->pvt_info;
fcaf780b 298
5de6e07e
MCC		 299 /* read in the 1st FATAL error register */
300 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
301 FERR_GLOBAL_HI, &value);
302 if (unlikely(value)) {
303 errors = value;
304 errnum = find_first_bit(&errors,
305 ARRAY_SIZE(ferr_global_hi_name));
306 specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum);
307 is_fatal = ferr_global_hi_is_fatal(errnum);
86002324
MCC		 308
309 /* Clear the error bit */
310 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
311 FERR_GLOBAL_HI, value);
312
5de6e07e 313 goto error_global;
fcaf780b
MCC		 314 }
315
5de6e07e
MCC		 316 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
317 FERR_GLOBAL_LO, &value);
318 if (unlikely(value)) {
319 errors = value;
320 errnum = find_first_bit(&errors,
321 ARRAY_SIZE(ferr_global_lo_name));
322 specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum);
323 is_fatal = ferr_global_lo_is_fatal(errnum);
86002324
MCC		 324
325 /* Clear the error bit */
326 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
327 FERR_GLOBAL_LO, value);
328
5de6e07e
MCC		 329 goto error_global;
330 }
331 return;
fcaf780b 332
5de6e07e
MCC		 333error_global:
334 i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s\n",
335 is_fatal ? "Fatal" : "NOT fatal", specific);
fcaf780b
MCC		 336}
337
338/*
5de6e07e
MCC		 339 * i7300_process_error_info Retrieve the hardware error information from
340 * the hardware and cache it in the 'info'
341 * structure
fcaf780b
MCC		 342 */
343static void i7300_process_error_info(struct mem_ctl_info *mci,
5de6e07e
MCC		 344 struct i7300_error_info *info)
345{
346 i7300_process_error_global(mci, info);
347};
fcaf780b
MCC		 348
349/*
350 * i7300_clear_error Retrieve any error from the hardware
351 * but do NOT process that error.
352 * Used for 'clearing' out of previous errors
353 * Called by the Core module.
354 */
355static void i7300_clear_error(struct mem_ctl_info *mci)
356{
357 struct i7300_error_info info;
358
359 i7300_get_error_info(mci, &info);
360}
361
362/*
363 * i7300_check_error Retrieve and process errors reported by the
364 * hardware. Called by the Core module.
365 */
366static void i7300_check_error(struct mem_ctl_info *mci)
367{
368 struct i7300_error_info info;
369 debugf4("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
5de6e07e 370
fcaf780b
MCC		 371 i7300_get_error_info(mci, &info);
372 i7300_process_error_info(mci, &info);
373}
374
375/*
376 * i7300_enable_error_reporting
377 * Turn on the memory reporting features of the hardware
378 */
379static void i7300_enable_error_reporting(struct mem_ctl_info *mci)
380{
fcaf780b 381}
5de6e07e
MCC		 382
383/************************************************
384 * i7300 Functions related to memory enumberation
385 ************************************************/
fcaf780b
MCC		 386
387/*
388 * determine_mtr(pvt, csrow, channel)
389 *
390 * return the proper MTR register as determine by the csrow and desired channel
391 */
392static int decode_mtr(struct i7300_pvt *pvt,
393 int slot, int ch, int branch,
394 struct i7300_dimm_info *dinfo,
395 struct csrow_info *p_csrow)
396{
397 int mtr, ans, addrBits, channel;
398
399 channel = to_channel(ch, branch);
400
401 mtr = pvt->mtr[slot][branch];
402 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;
403
404 debugf2("\tMTR%d CH%d: DIMMs are %s (mtr)\n",
405 slot, channel,
406 ans ? "Present" : "NOT Present");
407
408 /* Determine if there is a DIMM present in this DIMM slot */
409
410#if 0
411 if (!amb_present || !ans)
412 return 0;
413#else
414 if (!ans)
415 return 0;
416#endif
417
418 /* Start with the number of bits for a Bank
419 * on the DRAM */
420 addrBits = MTR_DRAM_BANKS_ADDR_BITS;
421 /* Add thenumber of ROW bits */
422 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
423 /* add the number of COLUMN bits */
424 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
425 /* add the number of RANK bits */
426 addrBits += MTR_DIMM_RANKS(mtr);
427
428 addrBits += 6; /* add 64 bits per DIMM */
429 addrBits -= 20; /* divide by 2^^20 */
430 addrBits -= 3; /* 8 bits per bytes */
431
432 dinfo->megabytes = 1 << addrBits;
433
434 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
435
436 debugf2("\t\tELECTRICAL THROTTLING is %s\n",
437 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
438
439 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
440 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single");
441 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
442 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
443 debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes);
444
445 p_csrow->grain = 8;
446 p_csrow->nr_pages = dinfo->megabytes << 8;
447 p_csrow->mtype = MEM_FB_DDR2;
116389ed
MCC		 448
449 /*
450 * FIXME: the type of error detection actually depends of the
451 * mode of operation. When it is just one single memory chip, at
452 * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code.
453 * In normal or mirrored mode, it uses Single Device Data correction,
454 * with the possibility of using an extended algorithm for x8 memories
455 * See datasheet Sections 7.3.6 to 7.3.8
456 */
fcaf780b
MCC		 457 p_csrow->edac_mode = EDAC_S8ECD8ED;
458
459 /* ask what device type on this row */
d7de2bdb
MCC		 460 if (MTR_DRAM_WIDTH(mtr)) {
461 debugf0("Scrub algorithm for x8 is on %s mode\n",
462 IS_SCRBALGO_ENHANCED(pvt->mc_settings) ?
463 "enhanced" : "normal");
464
fcaf780b 465 p_csrow->dtype = DEV_X8;
d7de2bdb 466 } else
fcaf780b
MCC		 467 p_csrow->dtype = DEV_X4;
468
469 return mtr;
470}
471
472/*
473 * print_dimm_size
474 *
475 * also will output a DIMM matrix map, if debug is enabled, for viewing
476 * how the DIMMs are populated
477 */
478static void print_dimm_size(struct i7300_pvt *pvt)
479{
480 struct i7300_dimm_info *dinfo;
481 char *p, *mem_buffer;
482 int space, n;
483 int channel, slot;
484
485 space = PAGE_SIZE;
486 mem_buffer = p = kmalloc(space, GFP_KERNEL);
487 if (p == NULL) {
488 i7300_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
489 __FILE__, __func__);
490 return;
491 }
492
493 n = snprintf(p, space, " ");
494 p += n;
495 space -= n;
496 for (channel = 0; channel < MAX_CHANNELS; channel++) {
497 n = snprintf(p, space, "channel %d | ", channel);
498 p += n;
499 space -= n;
500 }
501 debugf2("%s\n", mem_buffer);
502 p = mem_buffer;
503 space = PAGE_SIZE;
504 n = snprintf(p, space, "-------------------------------"
505 "------------------------------");
506 p += n;
507 space -= n;
508 debugf2("%s\n", mem_buffer);
509 p = mem_buffer;
510 space = PAGE_SIZE;
511
512 for (slot = 0; slot < MAX_SLOTS; slot++) {
513 n = snprintf(p, space, "csrow/SLOT %d ", slot);
514 p += n;
515 space -= n;
516
517 for (channel = 0; channel < MAX_CHANNELS; channel++) {
518 dinfo = &pvt->dimm_info[slot][channel];
519 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
520 p += n;
521 space -= n;
522 }
523
524 debugf2("%s\n", mem_buffer);
525 p = mem_buffer;
526 space = PAGE_SIZE;
527 }
528
529 n = snprintf(p, space, "-------------------------------"
530 "------------------------------");
531 p += n;
532 space -= n;
533 debugf2("%s\n", mem_buffer);
534 p = mem_buffer;
535 space = PAGE_SIZE;
536
537 kfree(mem_buffer);
538}
539
540/*
541 * i7300_init_csrows Initialize the 'csrows' table within
542 * the mci control structure with the
543 * addressing of memory.
544 *
545 * return:
546 * 0 success
547 * 1 no actual memory found on this MC
548 */
549static int i7300_init_csrows(struct mem_ctl_info *mci)
550{
551 struct i7300_pvt *pvt;
552 struct i7300_dimm_info *dinfo;
553 struct csrow_info *p_csrow;
554 int empty;
555 int mtr;
556 int ch, branch, slot, channel;
557
558 pvt = mci->pvt_info;
559
560 empty = 1; /* Assume NO memory */
561
562 debugf2("Memory Technology Registers:\n");
563
564 /* Get the AMB present registers for the four channels */
565 for (branch = 0; branch < MAX_BRANCHES; branch++) {
566 /* Read and dump branch 0's MTRs */
567 channel = to_channel(0, branch);
3e57eef6 568 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_0,
fcaf780b
MCC		 569 &pvt->ambpresent[channel]);
570 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
571 channel, pvt->ambpresent[channel]);
572
573 channel = to_channel(1, branch);
3e57eef6 574 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], AMBPRESENT_1,
fcaf780b
MCC		 575 &pvt->ambpresent[channel]);
576 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
577 channel, pvt->ambpresent[channel]);
578 }
579
580 /* Get the set of MTR[0-7] regs by each branch */
581 for (slot = 0; slot < MAX_SLOTS; slot++) {
582 int where = mtr_regs[slot];
583 for (branch = 0; branch < MAX_BRANCHES; branch++) {
3e57eef6 584 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
fcaf780b
MCC		 585 where,
586 &pvt->mtr[slot][branch]);
587 for (ch = 0; ch < MAX_BRANCHES; ch++) {
588 int channel = to_channel(ch, branch);
589
590 dinfo = &pvt->dimm_info[slot][channel];
591 p_csrow = &mci->csrows[slot];
592
593 mtr = decode_mtr(pvt, slot, ch, branch,
594 dinfo, p_csrow);
595 /* if no DIMMS on this row, continue */
596 if (!MTR_DIMMS_PRESENT(mtr))
597 continue;
598
599 p_csrow->csrow_idx = slot;
600
601 /* FAKE OUT VALUES, FIXME */
602 p_csrow->first_page = 0 + slot * 20;
603 p_csrow->last_page = 9 + slot * 20;
604 p_csrow->page_mask = 0xfff;
605
606 empty = 0;
607 }
608 }
609 }
610
611 return empty;
612}
613
614static void decode_mir(int mir_no, u16 mir[MAX_MIR])
615{
616 if (mir[mir_no] & 3)
617 debugf2("MIR%d: limit= 0x%x Branch(es) that participate: %s %s\n",
618 mir_no,
619 (mir[mir_no] >> 4) & 0xfff,
620 (mir[mir_no] & 1) ? "B0" : "",
621 (mir[mir_no] & 2) ? "B1": "");
622}
623
624/*
625 * i7300_get_mc_regs read in the necessary registers and
626 * cache locally
627 *
628 * Fills in the private data members
629 */
630static int i7300_get_mc_regs(struct mem_ctl_info *mci)
631{
632 struct i7300_pvt *pvt;
633 u32 actual_tolm;
634 int i, rc;
635
636 pvt = mci->pvt_info;
637
3e57eef6 638 pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE,
fcaf780b
MCC		 639 (u32 *) &pvt->ambase);
640
641 debugf2("AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase);
642
643 /* Get the Branch Map regs */
3e57eef6 644 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm);
fcaf780b
MCC		 645 pvt->tolm >>= 12;
646 debugf2("TOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
647 pvt->tolm);
648
649 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
650 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
651 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
652
af3d8831 653 /* Get memory controller settings */
3e57eef6 654 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS,
af3d8831 655 &pvt->mc_settings);
d7de2bdb 656
af3d8831 657 debugf0("Memory controller operating on %s mode\n",
d7de2bdb 658 IS_MIRRORED(pvt->mc_settings) ? "mirrored" : "non-mirrored");
af3d8831 659 debugf0("Error detection is %s\n",
d7de2bdb
MCC		 660 IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
661 debugf0("Retry is %s\n",
662 IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
af3d8831
MCC		 663
664 /* Get Memory Interleave Range registers */
3e57eef6
MCC		 665 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0, &pvt->mir[0]);
666 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1, &pvt->mir[1]);
667 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2, &pvt->mir[2]);
fcaf780b
MCC		 668
669 /* Decode the MIR regs */
670 for (i = 0; i < MAX_MIR; i++)
671 decode_mir(i, pvt->mir);
672
673 rc = i7300_init_csrows(mci);
674 if (rc < 0)
675 return rc;
676
677 /* Go and determine the size of each DIMM and place in an
678 * orderly matrix */
679 print_dimm_size(pvt);
680
681 return 0;
682}
683
5de6e07e
MCC		 684/*************************************************
685 * i7300 Functions related to device probe/release
686 *************************************************/
687
fcaf780b
MCC		 688/*
689 * i7300_put_devices 'put' all the devices that we have
690 * reserved via 'get'
691 */
692static void i7300_put_devices(struct mem_ctl_info *mci)
693{
694 struct i7300_pvt *pvt;
695 int branch;
696
697 pvt = mci->pvt_info;
698
699 /* Decrement usage count for devices */
700 for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++)
3e57eef6
MCC		 701 pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]);
702 pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs);
703 pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map);
fcaf780b
MCC		 704}
705
706/*
707 * i7300_get_devices Find and perform 'get' operation on the MCH's
708 * device/functions we want to reference for this driver
709 *
710 * Need to 'get' device 16 func 1 and func 2
711 */
712static int i7300_get_devices(struct mem_ctl_info *mci, int dev_idx)
713{
714 struct i7300_pvt *pvt;
715 struct pci_dev *pdev;
716
717 pvt = mci->pvt_info;
718
719 /* Attempt to 'get' the MCH register we want */
720 pdev = NULL;
3e57eef6 721 while (!pvt->pci_dev_16_1_fsb_addr_map || !pvt->pci_dev_16_2_fsb_err_regs) {
fcaf780b
MCC		 722 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
723 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev);
724 if (!pdev) {
725 /* End of list, leave */
726 i7300_printk(KERN_ERR,
727 "'system address,Process Bus' "
728 "device not found:"
729 "vendor 0x%x device 0x%x ERR funcs "
730 "(broken BIOS?)\n",
731 PCI_VENDOR_ID_INTEL,
732 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR);
733 goto error;
734 }
735
736 /* Store device 16 funcs 1 and 2 */
737 switch (PCI_FUNC(pdev->devfn)) {
738 case 1:
3e57eef6 739 pvt->pci_dev_16_1_fsb_addr_map = pdev;
fcaf780b
MCC		 740 break;
741 case 2:
3e57eef6 742 pvt->pci_dev_16_2_fsb_err_regs = pdev;
fcaf780b
MCC		 743 break;
744 }
745 }
746
747 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
3e57eef6
MCC		 748 pci_name(pvt->pci_dev_16_0_fsb_ctlr),
749 pvt->pci_dev_16_0_fsb_ctlr->vendor, pvt->pci_dev_16_0_fsb_ctlr->device);
fcaf780b 750 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
3e57eef6
MCC		 751 pci_name(pvt->pci_dev_16_1_fsb_addr_map),
752 pvt->pci_dev_16_1_fsb_addr_map->vendor, pvt->pci_dev_16_1_fsb_addr_map->device);
fcaf780b 753 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
3e57eef6
MCC		 754 pci_name(pvt->pci_dev_16_2_fsb_err_regs),
755 pvt->pci_dev_16_2_fsb_err_regs->vendor, pvt->pci_dev_16_2_fsb_err_regs->device);
fcaf780b 756
3e57eef6 757 pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL,
fcaf780b
MCC		 758 PCI_DEVICE_ID_INTEL_I7300_MCH_FB0,
759 NULL);
3e57eef6 760 if (!pvt->pci_dev_2x_0_fbd_branch[0]) {
fcaf780b
MCC		 761 i7300_printk(KERN_ERR,
762 "MC: 'BRANCH 0' device not found:"
763 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
764 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0);
765 goto error;
766 }
767
3e57eef6 768 pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL,
fcaf780b
MCC		 769 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1,
770 NULL);
3e57eef6 771 if (!pvt->pci_dev_2x_0_fbd_branch[1]) {
fcaf780b
MCC		 772 i7300_printk(KERN_ERR,
773 "MC: 'BRANCH 1' device not found:"
774 "vendor 0x%x device 0x%x Func 0 "
775 "(broken BIOS?)\n",
776 PCI_VENDOR_ID_INTEL,
777 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1);
778 goto error;
779 }
780
781 return 0;
782
783error:
784 i7300_put_devices(mci);
785 return -ENODEV;
786}
787
788/*
789 * i7300_probe1 Probe for ONE instance of device to see if it is
790 * present.
791 * return:
792 * 0 for FOUND a device
793 * < 0 for error code
794 */
795static int i7300_probe1(struct pci_dev *pdev, int dev_idx)
796{
797 struct mem_ctl_info *mci;
798 struct i7300_pvt *pvt;
799 int num_channels;
800 int num_dimms_per_channel;
801 int num_csrows;
802
803 if (dev_idx >= ARRAY_SIZE(i7300_devs))
804 return -EINVAL;
805
806 debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
807 __func__,
808 pdev->bus->number,
809 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
810
811 /* We only are looking for func 0 of the set */
812 if (PCI_FUNC(pdev->devfn) != 0)
813 return -ENODEV;
814
815 /* As we don't have a motherboard identification routine to determine
816 * actual number of slots/dimms per channel, we thus utilize the
817 * resource as specified by the chipset. Thus, we might have
818 * have more DIMMs per channel than actually on the mobo, but this
819 * allows the driver to support upto the chipset max, without
820 * some fancy mobo determination.
821 */
822 num_dimms_per_channel = MAX_SLOTS;
823 num_channels = MAX_CHANNELS;
824 num_csrows = MAX_SLOTS * MAX_CHANNELS;
825
826 debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
827 __func__, num_channels, num_dimms_per_channel, num_csrows);
828
829 /* allocate a new MC control structure */
830 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
831
832 if (mci == NULL)
833 return -ENOMEM;
834
835 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
836
837 mci->dev = &pdev->dev; /* record ptr to the generic device */
838
839 pvt = mci->pvt_info;
3e57eef6 840 pvt->pci_dev_16_0_fsb_ctlr = pdev; /* Record this device in our private */
fcaf780b
MCC		 841
842 /* 'get' the pci devices we want to reserve for our use */
843 if (i7300_get_devices(mci, dev_idx))
844 goto fail0;
845
846 mci->mc_idx = 0;
847 mci->mtype_cap = MEM_FLAG_FB_DDR2;
848 mci->edac_ctl_cap = EDAC_FLAG_NONE;
849 mci->edac_cap = EDAC_FLAG_NONE;
850 mci->mod_name = "i7300_edac.c";
851 mci->mod_ver = I7300_REVISION;
852 mci->ctl_name = i7300_devs[dev_idx].ctl_name;
853 mci->dev_name = pci_name(pdev);
854 mci->ctl_page_to_phys = NULL;
855
fcaf780b
MCC		 856 /* Set the function pointer to an actual operation function */
857 mci->edac_check = i7300_check_error;
fcaf780b
MCC		 858
859 /* initialize the MC control structure 'csrows' table
860 * with the mapping and control information */
861 if (i7300_get_mc_regs(mci)) {
862 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
863 " because i7300_init_csrows() returned nonzero "
864 "value\n");
865 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
866 } else {
fcaf780b
MCC		 867 debugf1("MC: Enable error reporting now\n");
868 i7300_enable_error_reporting(mci);
fcaf780b
MCC		 869 }
870
871 /* add this new MC control structure to EDAC's list of MCs */
872 if (edac_mc_add_mc(mci)) {
873 debugf0("MC: " __FILE__
874 ": %s(): failed edac_mc_add_mc()\n", __func__);
875 /* FIXME: perhaps some code should go here that disables error
876 * reporting if we just enabled it
877 */
878 goto fail1;
879 }
880
fcaf780b 881 i7300_clear_error(mci);
fcaf780b
MCC		 882
883 /* allocating generic PCI control info */
884 i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
885 if (!i7300_pci) {
886 printk(KERN_WARNING
887 "%s(): Unable to create PCI control\n",
888 __func__);
889 printk(KERN_WARNING
890 "%s(): PCI error report via EDAC not setup\n",
891 __func__);
892 }
893
894 return 0;
895
896 /* Error exit unwinding stack */
897fail1:
898
899 i7300_put_devices(mci);
900
901fail0:
902 edac_mc_free(mci);
903 return -ENODEV;
904}
905
906/*
907 * i7300_init_one constructor for one instance of device
908 *
909 * returns:
910 * negative on error
911 * count (>= 0)
912 */
913static int __devinit i7300_init_one(struct pci_dev *pdev,
914 const struct pci_device_id *id)
915{
916 int rc;
917
918 debugf0("MC: " __FILE__ ": %s()\n", __func__);
919
920 /* wake up device */
921 rc = pci_enable_device(pdev);
922 if (rc == -EIO)
923 return rc;
924
925 /* now probe and enable the device */
926 return i7300_probe1(pdev, id->driver_data);
927}
928
929/*
930 * i7300_remove_one destructor for one instance of device
931 *
932 */
933static void __devexit i7300_remove_one(struct pci_dev *pdev)
934{
935 struct mem_ctl_info *mci;
936
937 debugf0(__FILE__ ": %s()\n", __func__);
938
939 if (i7300_pci)
940 edac_pci_release_generic_ctl(i7300_pci);
941
942 mci = edac_mc_del_mc(&pdev->dev);
943 if (!mci)
944 return;
945
946 /* retrieve references to resources, and free those resources */
947 i7300_put_devices(mci);
948
949 edac_mc_free(mci);
950}
951
952/*
953 * pci_device_id table for which devices we are looking for
954 *
955 * The "E500P" device is the first device supported.
956 */
957static const struct pci_device_id i7300_pci_tbl[] __devinitdata = {
958 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)},
959 {0,} /* 0 terminated list. */
960};
961
962MODULE_DEVICE_TABLE(pci, i7300_pci_tbl);
963
964/*
965 * i7300_driver pci_driver structure for this module
966 *
967 */
968static struct pci_driver i7300_driver = {
969 .name = "i7300_edac",
970 .probe = i7300_init_one,
971 .remove = __devexit_p(i7300_remove_one),
972 .id_table = i7300_pci_tbl,
973};
974
975/*
976 * i7300_init Module entry function
977 * Try to initialize this module for its devices
978 */
979static int __init i7300_init(void)
980{
981 int pci_rc;
982
983 debugf2("MC: " __FILE__ ": %s()\n", __func__);
984
985 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
986 opstate_init();
987
988 pci_rc = pci_register_driver(&i7300_driver);
989
990 return (pci_rc < 0) ? pci_rc : 0;
991}
992
993/*
994 * i7300_exit() Module exit function
995 * Unregister the driver
996 */
997static void __exit i7300_exit(void)
998{
999 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1000 pci_unregister_driver(&i7300_driver);
1001}
1002
1003module_init(i7300_init);
1004module_exit(i7300_exit);
1005
1006MODULE_LICENSE("GPL");
1007MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1008MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1009MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - "
1010 I7300_REVISION);
1011
1012module_param(edac_op_state, int, 0444);
1013MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Linux kernel - Deliverables
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