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i7300_edac: start a driver for i7300 chipset (Clarksboro)
[deliverable/linux.git] / drivers / edac / i7300_edac.c
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fcaf780b
MCC		 1/*
2 * Intel 7300 class Memory Controllers kernel module (Clarksboro)
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License version 2 only.
6 *
7 * Copyright (c) 2010 by:
8 * Mauro Carvalho Chehab <mchehab@redhat.com>
9 *
10 * Red Hat Inc. http://www.redhat.com
11 *
12 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
13 * http://www.intel.com/Assets/PDF/datasheet/318082.pdf
14 *
15 * TODO: The chipset allow checking for PCI Express errors also. Currently,
16 * the driver covers only memory error errors
17 *
18 * This driver uses "csrows" EDAC attribute to represent DIMM slot#
19 */
20
21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/pci.h>
24#include <linux/pci_ids.h>
25#include <linux/slab.h>
26#include <linux/edac.h>
27#include <linux/mmzone.h>
28
29#include "edac_core.h"
30
31/*
32 * Alter this version for the I7300 module when modifications are made
33 */
34#define I7300_REVISION " Ver: 1.0.0 " __DATE__
35
36#define EDAC_MOD_STR "i7300_edac"
37
38#define i7300_printk(level, fmt, arg...) \
39 edac_printk(level, "i7300", fmt, ##arg)
40
41#define i7300_mc_printk(mci, level, fmt, arg...) \
42 edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg)
43
44/*
45 * Memory topology is organized as:
46 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
47 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
48 * Each channel can have to 8 DIMM sets (called as SLOTS)
49 * Slots should generally be filled in pairs
50 * Except on Single Channel mode of operation
51 * just slot 0/channel0 filled on this mode
52 * On normal operation mode, the two channels on a branch should be
53 filled together for the same SLOT#
54 * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
55 * channels on both branches should be filled
56 */
57
58/* Limits for i7300 */
59#define MAX_SLOTS 8
60#define MAX_BRANCHES 2
61#define MAX_CH_PER_BRANCH 2
62#define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES)
63#define MAX_MIR 3
64
65#define to_channel(ch, branch) ((((branch)) << 1) | (ch))
66
67#define to_csrow(slot, ch, branch) \
68 (to_channel(ch, branch) | ((slot) << 2))
69
70
71/* Device 16,
72 * Function 0: System Address (not documented)
73 * Function 1: Memory Branch Map, Control, Errors Register
74 * Function 2: FSB Error Registers
75 *
76 * All 3 functions of Device 16 (0,1,2) share the SAME DID and
77 * uses PCI_DEVICE_ID_INTEL_I7300_MCH_ERR for device 16 (0,1,2),
78 * PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 and PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
79 * for device 21 (0,1).
80 */
81
82 /* OFFSETS for Function 0 */
83#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
84#define MAXCH 0x56 /* Max Channel Number */
85#define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */
86
87 /* OFFSETS for Function 1 */
88#define TOLM 0x6C
89#define REDMEMB 0x7C
90
91#define MIR0 0x80
92#define MIR1 0x84
93#define MIR2 0x88
94
95#if 0
96#define AMIR0 0x8c
97#define AMIR1 0x90
98#define AMIR2 0x94
99
100/*TODO: double check it */
101#define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */
102
103 /* Fatal error registers */
104#define FERR_FAT_FBD 0x98
105
106/*TODO: double check it */
107#define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
108
109#define NERR_FAT_FBD 0x9c
110#define FERR_NF_FBD 0xa0
111
112 /* Non-fatal error register */
113#define NERR_NF_FBD 0xa4
114
115 /* Enable error mask */
116#define EMASK_FBD 0xa8
117
118#define ERR0_FBD 0xac
119#define ERR1_FBD 0xb0
120#define ERR2_FBD 0xb4
121#define MCERR_FBD 0xb8
122
123#endif
124
125/* TODO: Dev 16 fn1 allows memory error injection - offsets 0x100-0x10b */
126
127 /* TODO: OFFSETS for Device 16 Function 2 */
128
129/*
130 * Device 21,
131 * Function 0: Memory Map Branch 0
132 *
133 * Device 22,
134 * Function 0: Memory Map Branch 1
135 */
136
137 /* OFFSETS for Function 0 */
138
139/*
140 * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
141 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
142 * seems that we cannot use this information directly for the same usage.
143 * Each memory slot may have up to 2 AMB interfaces, one for income and another
144 * for outcome interface to the next slot.
145 * For now, the driver just stores the AMB present registers, but rely only at
146 * the MTR info to detect memory.
147 * Datasheet is also not clear about how to map each AMBPRESENT registers to
148 * one of the 4 available channels.
149 */
150#define AMBPRESENT_0 0x64
151#define AMBPRESENT_1 0x66
152
153const static u16 mtr_regs [MAX_SLOTS] = {
154 0x80, 0x84, 0x88, 0x8c,
155 0x82, 0x86, 0x8a, 0x8e
156};
157
158/* Defines to extract the vaious fields from the
159 * MTRx - Memory Technology Registers
160 */
161#define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8))
162#define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7))
163#define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
164#define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4)
165#define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0)
166#define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
167#define MTR_DRAM_BANKS_ADDR_BITS 2
168#define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
169#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
170#define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
171
172#if 0
173 /* OFFSETS for Function 1 */
174
175/* TODO */
176#define NRECFGLOG 0x74
177#define RECFGLOG 0x78
178#define NRECMEMA 0xbe
179#define NRECMEMB 0xc0
180#define NRECFB_DIMMA 0xc4
181#define NRECFB_DIMMB 0xc8
182#define NRECFB_DIMMC 0xcc
183#define NRECFB_DIMMD 0xd0
184#define NRECFB_DIMME 0xd4
185#define NRECFB_DIMMF 0xd8
186#define REDMEMA 0xdC
187#define RECMEMA 0xf0
188#define RECMEMB 0xf4
189#define RECFB_DIMMA 0xf8
190#define RECFB_DIMMB 0xec
191#define RECFB_DIMMC 0xf0
192#define RECFB_DIMMD 0xf4
193#define RECFB_DIMME 0xf8
194#define RECFB_DIMMF 0xfC
195
196/* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */
197static inline int extract_fbdchan_indx(u32 x)
198{
199 return (x>>28) & 0x3;
200}
201#endif
202
203#ifdef CONFIG_EDAC_DEBUG
204/* MTR NUMROW */
205static const char *numrow_toString[] = {
206 "8,192 - 13 rows",
207 "16,384 - 14 rows",
208 "32,768 - 15 rows",
209 "65,536 - 16 rows"
210};
211
212/* MTR NUMCOL */
213static const char *numcol_toString[] = {
214 "1,024 - 10 columns",
215 "2,048 - 11 columns",
216 "4,096 - 12 columns",
217 "reserved"
218};
219#endif
220
221#if 0
222
223/*
224 * Error indicator bits and masks
225 * Error masks are according with Table 5-17 of i7300 datasheet
226 */
227
228enum error_mask {
229 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
230 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
231 EMASK_M3 = 1<<2, /* Reserved */
232 EMASK_M4 = 1<<3, /* Uncorrectable Data ECC on Replay */
233 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
234 EMASK_M6 = 1<<5, /* Unsupported on i7300 */
235 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
236 EMASK_M8 = 1<<7, /* Aliased Uncorrectable Patrol Data ECC */
237 EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */
238 EMASK_M10 = 1<<9, /* Unsupported on i7300 */
239 EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
240 EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */
241 EMASK_M13 = 1<<12, /* Memory Write error on first attempt */
242 EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */
243 EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */
244 EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */
245 EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */
246 EMASK_M18 = 1<<17, /* Unsupported on i7300 */
247 EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */
248 EMASK_M20 = 1<<19, /* Correctable Patrol Data ECC */
249 EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */
250 EMASK_M22 = 1<<21, /* SPD protocol Error */
251 EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */
252 EMASK_M24 = 1<<23, /* Refresh error */
253 EMASK_M25 = 1<<24, /* Memory Write error on redundant retry */
254 EMASK_M26 = 1<<25, /* Redundant Fast Reset Timeout */
255 EMASK_M27 = 1<<26, /* Correctable Counter Threshold Exceeded */
256 EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */
257 EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */
258};
259
260/*
261 * Names to translate bit error into something useful
262 */
263static const char *error_name[] = {
264 [0] = "Memory Write error on non-redundant retry",
265 [1] = "Memory or FB-DIMM configuration CRC read error",
266 /* Reserved */
267 [3] = "Uncorrectable Data ECC on Replay",
268 [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
269 /* M6 Unsupported on i7300 */
270 [6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
271 [7] = "Aliased Uncorrectable Patrol Data ECC",
272 [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
273 /* M10 Unsupported on i7300 */
274 [10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
275 [11] = "Non-Aliased Uncorrectable Patrol Data ECC",
276 [12] = "Memory Write error on first attempt",
277 [13] = "FB-DIMM Configuration Write error on first attempt",
278 [14] = "Memory or FB-DIMM configuration CRC read error",
279 [15] = "Channel Failed-Over Occurred",
280 [16] = "Correctable Non-Mirrored Demand Data ECC",
281 /* M18 Unsupported on i7300 */
282 [18] = "Correctable Resilver- or Spare-Copy Data ECC",
283 [19] = "Correctable Patrol Data ECC",
284 [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status",
285 [21] = "SPD protocol Error",
286 [22] = "Non-Redundant Fast Reset Timeout",
287 [23] = "Refresh error",
288 [24] = "Memory Write error on redundant retry",
289 [25] = "Redundant Fast Reset Timeout",
290 [26] = "Correctable Counter Threshold Exceeded",
291 [27] = "DIMM-Spare Copy Completed",
292 [28] = "DIMM-Isolation Completed",
293};
294
295/* Fatal errors */
296#define ERROR_FAT_MASK (EMASK_M1 | \
297 EMASK_M2 | \
298 EMASK_M23)
299
300/* Correctable errors */
301#define ERROR_NF_CORRECTABLE (EMASK_M27 | \
302 EMASK_M20 | \
303 EMASK_M19 | \
304 EMASK_M18 | \
305 EMASK_M17 | \
306 EMASK_M16)
307#define ERROR_NF_DIMM_SPARE (EMASK_M29 | \
308 EMASK_M28)
309#define ERROR_NF_SPD_PROTOCOL (EMASK_M22)
310#define ERROR_NF_NORTH_CRC (EMASK_M21)
311
312/* Recoverable errors */
313#define ERROR_NF_RECOVERABLE (EMASK_M26 | \
314 EMASK_M25 | \
315 EMASK_M24 | \
316 EMASK_M15 | \
317 EMASK_M14 | \
318 EMASK_M13 | \
319 EMASK_M12 | \
320 EMASK_M11 | \
321 EMASK_M9 | \
322 EMASK_M8 | \
323 EMASK_M7 | \
324 EMASK_M5)
325
326/* uncorrectable errors */
327#define ERROR_NF_UNCORRECTABLE (EMASK_M4)
328
329/* mask to all non-fatal errors */
330#define ERROR_NF_MASK (ERROR_NF_CORRECTABLE | \
331 ERROR_NF_UNCORRECTABLE | \
332 ERROR_NF_RECOVERABLE | \
333 ERROR_NF_DIMM_SPARE | \
334 ERROR_NF_SPD_PROTOCOL | \
335 ERROR_NF_NORTH_CRC)
336
337/*
338 * Define error masks for the several registers
339 */
340
341/* Enable all fatal and non fatal errors */
342#define ENABLE_EMASK_ALL (ERROR_FAT_MASK | ERROR_NF_MASK)
343
344/* mask for fatal error registers */
345#define FERR_FAT_MASK ERROR_FAT_MASK
346
347/* masks for non-fatal error register */
348static inline int to_nf_mask(unsigned int mask)
349{
350 return (mask & EMASK_M29) | (mask >> 3);
351};
352
353static inline int from_nf_ferr(unsigned int mask)
354{
355 return (mask & EMASK_M29) | /* Bit 28 */
356 (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */
357};
358
359#define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK)
360#define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE)
361#define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE)
362#define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL)
363#define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC)
364#define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE)
365#define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE)
366
367#endif
368
369/* Device name and register DID (Device ID) */
370struct i7300_dev_info {
371 const char *ctl_name; /* name for this device */
372 u16 fsb_mapping_errors; /* DID for the branchmap,control */
373};
374
375/* Table of devices attributes supported by this driver */
376static const struct i7300_dev_info i7300_devs[] = {
377 {
378 .ctl_name = "I7300",
379 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR,
380 },
381};
382
383struct i7300_dimm_info {
384 int megabytes; /* size, 0 means not present */
385};
386
387/* driver private data structure */
388struct i7300_pvt {
389 struct pci_dev *system_address; /* 16.0 */
390 struct pci_dev *branchmap_werrors; /* 16.1 */
391 struct pci_dev *fsb_error_regs; /* 16.2 */
392 struct pci_dev *branch_pci[MAX_BRANCHES]; /* 21.0 and 22.0 */
393
394 u16 tolm; /* top of low memory */
395 u64 ambase; /* AMB BAR */
396
397 u16 mir[MAX_MIR];
398
399 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */
400 u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */
401
402 /* DIMM information matrix, allocating architecture maximums */
403 struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS];
404};
405
406#if 0
407/* I7300 MCH error information retrieved from Hardware */
408struct i7300_error_info {
409 /* These registers are always read from the MC */
410 u32 ferr_fat_fbd; /* First Errors Fatal */
411 u32 nerr_fat_fbd; /* Next Errors Fatal */
412 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
413 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
414
415 /* These registers are input ONLY if there was a Recoverable Error */
416 u32 redmemb; /* Recoverable Mem Data Error log B */
417 u16 recmema; /* Recoverable Mem Error log A */
418 u32 recmemb; /* Recoverable Mem Error log B */
419
420 /* These registers are input ONLY if there was a Non-Rec Error */
421 u16 nrecmema; /* Non-Recoverable Mem log A */
422 u16 nrecmemb; /* Non-Recoverable Mem log B */
423
424};
425#endif
426
427/* FIXME: Why do we need to have this static? */
428static struct edac_pci_ctl_info *i7300_pci;
429
430
431#if 0
432/* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and
433 5400 better to use an inline function than a macro in this case */
434static inline int nrec_bank(struct i7300_error_info *info)
435{
436 return ((info->nrecmema) >> 12) & 0x7;
437}
438static inline int nrec_rank(struct i7300_error_info *info)
439{
440 return ((info->nrecmema) >> 8) & 0xf;
441}
442static inline int nrec_buf_id(struct i7300_error_info *info)
443{
444 return ((info->nrecmema)) & 0xff;
445}
446static inline int nrec_rdwr(struct i7300_error_info *info)
447{
448 return (info->nrecmemb) >> 31;
449}
450/* This applies to both NREC and REC string so it can be used with nrec_rdwr
451 and rec_rdwr */
452static inline const char *rdwr_str(int rdwr)
453{
454 return rdwr ? "Write" : "Read";
455}
456static inline int nrec_cas(struct i7300_error_info *info)
457{
458 return ((info->nrecmemb) >> 16) & 0x1fff;
459}
460static inline int nrec_ras(struct i7300_error_info *info)
461{
462 return (info->nrecmemb) & 0xffff;
463}
464static inline int rec_bank(struct i7300_error_info *info)
465{
466 return ((info->recmema) >> 12) & 0x7;
467}
468static inline int rec_rank(struct i7300_error_info *info)
469{
470 return ((info->recmema) >> 8) & 0xf;
471}
472static inline int rec_rdwr(struct i7300_error_info *info)
473{
474 return (info->recmemb) >> 31;
475}
476static inline int rec_cas(struct i7300_error_info *info)
477{
478 return ((info->recmemb) >> 16) & 0x1fff;
479}
480static inline int rec_ras(struct i7300_error_info *info)
481{
482 return (info->recmemb) & 0xffff;
483}
484
485/*
486 * i7300_get_error_info Retrieve the hardware error information from
487 * the hardware and cache it in the 'info'
488 * structure
489 */
490static void i7300_get_error_info(struct mem_ctl_info *mci,
491 struct i7300_error_info *info)
492{
493 struct i7300_pvt *pvt;
494 u32 value;
495
496 pvt = mci->pvt_info;
497
498 /* read in the 1st FATAL error register */
499 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
500
501 /* Mask only the bits that the doc says are valid
502 */
503 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
504
505 /* If there is an error, then read in the
506 NEXT FATAL error register and the Memory Error Log Register A
507 */
508 if (value & FERR_FAT_MASK) {
509 info->ferr_fat_fbd = value;
510
511 /* harvest the various error data we need */
512 pci_read_config_dword(pvt->branchmap_werrors,
513 NERR_FAT_FBD, &info->nerr_fat_fbd);
514 pci_read_config_word(pvt->branchmap_werrors,
515 NRECMEMA, &info->nrecmema);
516 pci_read_config_word(pvt->branchmap_werrors,
517 NRECMEMB, &info->nrecmemb);
518
519 /* Clear the error bits, by writing them back */
520 pci_write_config_dword(pvt->branchmap_werrors,
521 FERR_FAT_FBD, value);
522 } else {
523 info->ferr_fat_fbd = 0;
524 info->nerr_fat_fbd = 0;
525 info->nrecmema = 0;
526 info->nrecmemb = 0;
527 }
528
529 /* read in the 1st NON-FATAL error register */
530 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
531
532 /* If there is an error, then read in the 1st NON-FATAL error
533 * register as well */
534 if (value & FERR_NF_MASK) {
535 info->ferr_nf_fbd = value;
536
537 /* harvest the various error data we need */
538 pci_read_config_dword(pvt->branchmap_werrors,
539 NERR_NF_FBD, &info->nerr_nf_fbd);
540 pci_read_config_word(pvt->branchmap_werrors,
541 RECMEMA, &info->recmema);
542 pci_read_config_dword(pvt->branchmap_werrors,
543 RECMEMB, &info->recmemb);
544 pci_read_config_dword(pvt->branchmap_werrors,
545 REDMEMB, &info->redmemb);
546
547 /* Clear the error bits, by writing them back */
548 pci_write_config_dword(pvt->branchmap_werrors,
549 FERR_NF_FBD, value);
550 } else {
551 info->ferr_nf_fbd = 0;
552 info->nerr_nf_fbd = 0;
553 info->recmema = 0;
554 info->recmemb = 0;
555 info->redmemb = 0;
556 }
557}
558
559/*
560 * i7300_proccess_non_recoverable_info(struct mem_ctl_info *mci,
561 * struct i7300_error_info *info,
562 * int handle_errors);
563 *
564 * handle the Intel FATAL and unrecoverable errors, if any
565 */
566static void i7300_proccess_non_recoverable_info(struct mem_ctl_info *mci,
567 struct i7300_error_info *info,
568 unsigned long allErrors)
569{
570 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];
571 int branch;
572 int channel;
573 int bank;
574 int buf_id;
575 int rank;
576 int rdwr;
577 int ras, cas;
578 int errnum;
579 char *type = NULL;
580
581 if (!allErrors)
582 return; /* if no error, return now */
583
584 if (allErrors & ERROR_FAT_MASK)
585 type = "FATAL";
586 else if (allErrors & FERR_NF_UNCORRECTABLE)
587 type = "NON-FATAL uncorrected";
588 else
589 type = "NON-FATAL recoverable";
590
591 /* ONLY ONE of the possible error bits will be set, as per the docs */
592
593 branch = extract_fbdchan_indx(info->ferr_fat_fbd);
594 channel = branch;
595
596 /* Use the NON-Recoverable macros to extract data */
597 bank = nrec_bank(info);
598 rank = nrec_rank(info);
599 buf_id = nrec_buf_id(info);
600 rdwr = nrec_rdwr(info);
601 ras = nrec_ras(info);
602 cas = nrec_cas(info);
603
604 debugf0("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
605 "DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n",
606 rank, channel, channel + 1, branch >> 1, bank,
607 buf_id, rdwr_str(rdwr), ras, cas);
608
609 /* Only 1 bit will be on */
610 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
611
612 /* Form out message */
613 snprintf(msg, sizeof(msg),
614 "%s (Branch=%d DRAM-Bank=%d Buffer ID = %d RDWR=%s "
615 "RAS=%d CAS=%d %s Err=0x%lx (%s))",
616 type, branch >> 1, bank, buf_id, rdwr_str(rdwr), ras, cas,
617 type, allErrors, error_name[errnum]);
618
619 /* Call the helper to output message */
620 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
621}
622
623/*
624 * i7300_process_fatal_error_info(struct mem_ctl_info *mci,
625 * struct i7300_error_info *info,
626 * int handle_errors);
627 *
628 * handle the Intel NON-FATAL errors, if any
629 */
630static void i7300_process_nonfatal_error_info(struct mem_ctl_info *mci,
631 struct i7300_error_info *info)
632{
633 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80];
634 unsigned long allErrors;
635 int branch;
636 int channel;
637 int bank;
638 int rank;
639 int rdwr;
640 int ras, cas;
641 int errnum;
642
643 /* mask off the Error bits that are possible */
644 allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK);
645 if (!allErrors)
646 return; /* if no error, return now */
647
648 /* ONLY ONE of the possible error bits will be set, as per the docs */
649
650 if (allErrors & (ERROR_NF_UNCORRECTABLE | ERROR_NF_RECOVERABLE)) {
651 i7300_proccess_non_recoverable_info(mci, info, allErrors);
652 return;
653 }
654
655 /* Correctable errors */
656 if (allErrors & ERROR_NF_CORRECTABLE) {
657 debugf0("\tCorrected bits= 0x%lx\n", allErrors);
658
659 branch = extract_fbdchan_indx(info->ferr_nf_fbd);
660
661 channel = 0;
662 if (REC_ECC_LOCATOR_ODD(info->redmemb))
663 channel = 1;
664
665 /* Convert channel to be based from zero, instead of
666 * from branch base of 0 */
667 channel += branch;
668
669 bank = rec_bank(info);
670 rank = rec_rank(info);
671 rdwr = rec_rdwr(info);
672 ras = rec_ras(info);
673 cas = rec_cas(info);
674
675 /* Only 1 bit will be on */
676 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
677
678 debugf0("\t\tCSROW= %d Channel= %d (Branch %d "
679 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
680 rank, channel, branch >> 1, bank,
681 rdwr_str(rdwr), ras, cas);
682
683 /* Form out message */
684 snprintf(msg, sizeof(msg),
685 "Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s "
686 "RAS=%d CAS=%d, CE Err=0x%lx (%s))",
687 branch >> 1, bank, rdwr_str(rdwr), ras, cas,
688 allErrors, error_name[errnum]);
689
690 /* Call the helper to output message */
691 edac_mc_handle_fbd_ce(mci, rank, channel, msg);
692
693 return;
694 }
695
696 /* Miscelaneous errors */
697 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name));
698
699 branch = extract_fbdchan_indx(info->ferr_nf_fbd);
700
701 i7300_mc_printk(mci, KERN_EMERG,
702 "Non-Fatal misc error (Branch=%d Err=%#lx (%s))",
703 branch >> 1, allErrors, error_name[errnum]);
704}
705
706/*
707 * i7300_process_error_info Process the error info that is
708 * in the 'info' structure, previously retrieved from hardware
709 */
710static void i7300_process_error_info(struct mem_ctl_info *mci,
711 struct i7300_error_info *info)
712{ u32 allErrors;
713
714 /* First handle any fatal errors that occurred */
715 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
716 i7300_proccess_non_recoverable_info(mci, info, allErrors);
717
718 /* now handle any non-fatal errors that occurred */
719 i7300_process_nonfatal_error_info(mci, info);
720}
721
722/*
723 * i7300_clear_error Retrieve any error from the hardware
724 * but do NOT process that error.
725 * Used for 'clearing' out of previous errors
726 * Called by the Core module.
727 */
728static void i7300_clear_error(struct mem_ctl_info *mci)
729{
730 struct i7300_error_info info;
731
732 i7300_get_error_info(mci, &info);
733}
734
735/*
736 * i7300_check_error Retrieve and process errors reported by the
737 * hardware. Called by the Core module.
738 */
739static void i7300_check_error(struct mem_ctl_info *mci)
740{
741 struct i7300_error_info info;
742 debugf4("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
743 i7300_get_error_info(mci, &info);
744 i7300_process_error_info(mci, &info);
745}
746
747/*
748 * i7300_enable_error_reporting
749 * Turn on the memory reporting features of the hardware
750 */
751static void i7300_enable_error_reporting(struct mem_ctl_info *mci)
752{
753 struct i7300_pvt *pvt;
754 u32 fbd_error_mask;
755
756 pvt = mci->pvt_info;
757
758 /* Read the FBD Error Mask Register */
759 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
760 &fbd_error_mask);
761
762 /* Enable with a '0' */
763 fbd_error_mask &= ~(ENABLE_EMASK_ALL);
764
765 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
766 fbd_error_mask);
767}
768#endif
769
770/*
771 * determine_mtr(pvt, csrow, channel)
772 *
773 * return the proper MTR register as determine by the csrow and desired channel
774 */
775static int decode_mtr(struct i7300_pvt *pvt,
776 int slot, int ch, int branch,
777 struct i7300_dimm_info *dinfo,
778 struct csrow_info *p_csrow)
779{
780 int mtr, ans, addrBits, channel;
781
782 channel = to_channel(ch, branch);
783
784 mtr = pvt->mtr[slot][branch];
785 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;
786
787 debugf2("\tMTR%d CH%d: DIMMs are %s (mtr)\n",
788 slot, channel,
789 ans ? "Present" : "NOT Present");
790
791 /* Determine if there is a DIMM present in this DIMM slot */
792
793#if 0
794 if (!amb_present || !ans)
795 return 0;
796#else
797 if (!ans)
798 return 0;
799#endif
800
801 /* Start with the number of bits for a Bank
802 * on the DRAM */
803 addrBits = MTR_DRAM_BANKS_ADDR_BITS;
804 /* Add thenumber of ROW bits */
805 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
806 /* add the number of COLUMN bits */
807 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
808 /* add the number of RANK bits */
809 addrBits += MTR_DIMM_RANKS(mtr);
810
811 addrBits += 6; /* add 64 bits per DIMM */
812 addrBits -= 20; /* divide by 2^^20 */
813 addrBits -= 3; /* 8 bits per bytes */
814
815 dinfo->megabytes = 1 << addrBits;
816
817 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
818
819 debugf2("\t\tELECTRICAL THROTTLING is %s\n",
820 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
821
822 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
823 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single");
824 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
825 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
826 debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes);
827
828 p_csrow->grain = 8;
829 p_csrow->nr_pages = dinfo->megabytes << 8;
830 p_csrow->mtype = MEM_FB_DDR2;
831 p_csrow->edac_mode = EDAC_S8ECD8ED;
832
833 /* ask what device type on this row */
834 if (MTR_DRAM_WIDTH(mtr))
835 p_csrow->dtype = DEV_X8;
836 else
837 p_csrow->dtype = DEV_X4;
838
839 return mtr;
840}
841
842/*
843 * print_dimm_size
844 *
845 * also will output a DIMM matrix map, if debug is enabled, for viewing
846 * how the DIMMs are populated
847 */
848static void print_dimm_size(struct i7300_pvt *pvt)
849{
850 struct i7300_dimm_info *dinfo;
851 char *p, *mem_buffer;
852 int space, n;
853 int channel, slot;
854
855 space = PAGE_SIZE;
856 mem_buffer = p = kmalloc(space, GFP_KERNEL);
857 if (p == NULL) {
858 i7300_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
859 __FILE__, __func__);
860 return;
861 }
862
863 n = snprintf(p, space, " ");
864 p += n;
865 space -= n;
866 for (channel = 0; channel < MAX_CHANNELS; channel++) {
867 n = snprintf(p, space, "channel %d | ", channel);
868 p += n;
869 space -= n;
870 }
871 debugf2("%s\n", mem_buffer);
872 p = mem_buffer;
873 space = PAGE_SIZE;
874 n = snprintf(p, space, "-------------------------------"
875 "------------------------------");
876 p += n;
877 space -= n;
878 debugf2("%s\n", mem_buffer);
879 p = mem_buffer;
880 space = PAGE_SIZE;
881
882 for (slot = 0; slot < MAX_SLOTS; slot++) {
883 n = snprintf(p, space, "csrow/SLOT %d ", slot);
884 p += n;
885 space -= n;
886
887 for (channel = 0; channel < MAX_CHANNELS; channel++) {
888 dinfo = &pvt->dimm_info[slot][channel];
889 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
890 p += n;
891 space -= n;
892 }
893
894 debugf2("%s\n", mem_buffer);
895 p = mem_buffer;
896 space = PAGE_SIZE;
897 }
898
899 n = snprintf(p, space, "-------------------------------"
900 "------------------------------");
901 p += n;
902 space -= n;
903 debugf2("%s\n", mem_buffer);
904 p = mem_buffer;
905 space = PAGE_SIZE;
906
907 kfree(mem_buffer);
908}
909
910/*
911 * i7300_init_csrows Initialize the 'csrows' table within
912 * the mci control structure with the
913 * addressing of memory.
914 *
915 * return:
916 * 0 success
917 * 1 no actual memory found on this MC
918 */
919static int i7300_init_csrows(struct mem_ctl_info *mci)
920{
921 struct i7300_pvt *pvt;
922 struct i7300_dimm_info *dinfo;
923 struct csrow_info *p_csrow;
924 int empty;
925 int mtr;
926 int ch, branch, slot, channel;
927
928 pvt = mci->pvt_info;
929
930 empty = 1; /* Assume NO memory */
931
932 debugf2("Memory Technology Registers:\n");
933
934 /* Get the AMB present registers for the four channels */
935 for (branch = 0; branch < MAX_BRANCHES; branch++) {
936 /* Read and dump branch 0's MTRs */
937 channel = to_channel(0, branch);
938 pci_read_config_word(pvt->branch_pci[branch], AMBPRESENT_0,
939 &pvt->ambpresent[channel]);
940 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
941 channel, pvt->ambpresent[channel]);
942
943 channel = to_channel(1, branch);
944 pci_read_config_word(pvt->branch_pci[branch], AMBPRESENT_1,
945 &pvt->ambpresent[channel]);
946 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
947 channel, pvt->ambpresent[channel]);
948 }
949
950 /* Get the set of MTR[0-7] regs by each branch */
951 for (slot = 0; slot < MAX_SLOTS; slot++) {
952 int where = mtr_regs[slot];
953 for (branch = 0; branch < MAX_BRANCHES; branch++) {
954 pci_read_config_word(pvt->branch_pci[branch],
955 where,
956 &pvt->mtr[slot][branch]);
957 for (ch = 0; ch < MAX_BRANCHES; ch++) {
958 int channel = to_channel(ch, branch);
959
960 dinfo = &pvt->dimm_info[slot][channel];
961 p_csrow = &mci->csrows[slot];
962
963 mtr = decode_mtr(pvt, slot, ch, branch,
964 dinfo, p_csrow);
965 /* if no DIMMS on this row, continue */
966 if (!MTR_DIMMS_PRESENT(mtr))
967 continue;
968
969 p_csrow->csrow_idx = slot;
970
971 /* FAKE OUT VALUES, FIXME */
972 p_csrow->first_page = 0 + slot * 20;
973 p_csrow->last_page = 9 + slot * 20;
974 p_csrow->page_mask = 0xfff;
975
976 empty = 0;
977 }
978 }
979 }
980
981 return empty;
982}
983
984static void decode_mir(int mir_no, u16 mir[MAX_MIR])
985{
986 if (mir[mir_no] & 3)
987 debugf2("MIR%d: limit= 0x%x Branch(es) that participate: %s %s\n",
988 mir_no,
989 (mir[mir_no] >> 4) & 0xfff,
990 (mir[mir_no] & 1) ? "B0" : "",
991 (mir[mir_no] & 2) ? "B1": "");
992}
993
994/*
995 * i7300_get_mc_regs read in the necessary registers and
996 * cache locally
997 *
998 * Fills in the private data members
999 */
1000static int i7300_get_mc_regs(struct mem_ctl_info *mci)
1001{
1002 struct i7300_pvt *pvt;
1003 u32 actual_tolm;
1004 int i, rc;
1005
1006 pvt = mci->pvt_info;
1007
1008 pci_read_config_dword(pvt->system_address, AMBASE,
1009 (u32 *) &pvt->ambase);
1010
1011 debugf2("AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase);
1012
1013 /* Get the Branch Map regs */
1014 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1015 pvt->tolm >>= 12;
1016 debugf2("TOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1017 pvt->tolm);
1018
1019 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
1020 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
1021 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
1022
1023 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir[0]);
1024 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir[1]);
1025 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir[2]);
1026
1027 /* Decode the MIR regs */
1028 for (i = 0; i < MAX_MIR; i++)
1029 decode_mir(i, pvt->mir);
1030
1031 rc = i7300_init_csrows(mci);
1032 if (rc < 0)
1033 return rc;
1034
1035 /* Go and determine the size of each DIMM and place in an
1036 * orderly matrix */
1037 print_dimm_size(pvt);
1038
1039 return 0;
1040}
1041
1042/*
1043 * i7300_put_devices 'put' all the devices that we have
1044 * reserved via 'get'
1045 */
1046static void i7300_put_devices(struct mem_ctl_info *mci)
1047{
1048 struct i7300_pvt *pvt;
1049 int branch;
1050
1051 pvt = mci->pvt_info;
1052
1053 /* Decrement usage count for devices */
1054 for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++)
1055 pci_dev_put(pvt->branch_pci[branch]);
1056 pci_dev_put(pvt->fsb_error_regs);
1057 pci_dev_put(pvt->branchmap_werrors);
1058}
1059
1060/*
1061 * i7300_get_devices Find and perform 'get' operation on the MCH's
1062 * device/functions we want to reference for this driver
1063 *
1064 * Need to 'get' device 16 func 1 and func 2
1065 */
1066static int i7300_get_devices(struct mem_ctl_info *mci, int dev_idx)
1067{
1068 struct i7300_pvt *pvt;
1069 struct pci_dev *pdev;
1070
1071 pvt = mci->pvt_info;
1072
1073 /* Attempt to 'get' the MCH register we want */
1074 pdev = NULL;
1075 while (!pvt->branchmap_werrors || !pvt->fsb_error_regs) {
1076 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1077 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev);
1078 if (!pdev) {
1079 /* End of list, leave */
1080 i7300_printk(KERN_ERR,
1081 "'system address,Process Bus' "
1082 "device not found:"
1083 "vendor 0x%x device 0x%x ERR funcs "
1084 "(broken BIOS?)\n",
1085 PCI_VENDOR_ID_INTEL,
1086 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR);
1087 goto error;
1088 }
1089
1090 /* Store device 16 funcs 1 and 2 */
1091 switch (PCI_FUNC(pdev->devfn)) {
1092 case 1:
1093 pvt->branchmap_werrors = pdev;
1094 break;
1095 case 2:
1096 pvt->fsb_error_regs = pdev;
1097 break;
1098 }
1099 }
1100
1101 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
1102 pci_name(pvt->system_address),
1103 pvt->system_address->vendor, pvt->system_address->device);
1104 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
1105 pci_name(pvt->branchmap_werrors),
1106 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
1107 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
1108 pci_name(pvt->fsb_error_regs),
1109 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
1110
1111 pvt->branch_pci[0] = pci_get_device(PCI_VENDOR_ID_INTEL,
1112 PCI_DEVICE_ID_INTEL_I7300_MCH_FB0,
1113 NULL);
1114 if (!pvt->branch_pci[0]) {
1115 i7300_printk(KERN_ERR,
1116 "MC: 'BRANCH 0' device not found:"
1117 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
1118 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0);
1119 goto error;
1120 }
1121
1122 pvt->branch_pci[1] = pci_get_device(PCI_VENDOR_ID_INTEL,
1123 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1,
1124 NULL);
1125 if (!pvt->branch_pci[1]) {
1126 i7300_printk(KERN_ERR,
1127 "MC: 'BRANCH 1' device not found:"
1128 "vendor 0x%x device 0x%x Func 0 "
1129 "(broken BIOS?)\n",
1130 PCI_VENDOR_ID_INTEL,
1131 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1);
1132 goto error;
1133 }
1134
1135 return 0;
1136
1137error:
1138 i7300_put_devices(mci);
1139 return -ENODEV;
1140}
1141
1142/*
1143 * i7300_probe1 Probe for ONE instance of device to see if it is
1144 * present.
1145 * return:
1146 * 0 for FOUND a device
1147 * < 0 for error code
1148 */
1149static int i7300_probe1(struct pci_dev *pdev, int dev_idx)
1150{
1151 struct mem_ctl_info *mci;
1152 struct i7300_pvt *pvt;
1153 int num_channels;
1154 int num_dimms_per_channel;
1155 int num_csrows;
1156
1157 if (dev_idx >= ARRAY_SIZE(i7300_devs))
1158 return -EINVAL;
1159
1160 debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
1161 __func__,
1162 pdev->bus->number,
1163 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1164
1165 /* We only are looking for func 0 of the set */
1166 if (PCI_FUNC(pdev->devfn) != 0)
1167 return -ENODEV;
1168
1169 /* As we don't have a motherboard identification routine to determine
1170 * actual number of slots/dimms per channel, we thus utilize the
1171 * resource as specified by the chipset. Thus, we might have
1172 * have more DIMMs per channel than actually on the mobo, but this
1173 * allows the driver to support upto the chipset max, without
1174 * some fancy mobo determination.
1175 */
1176 num_dimms_per_channel = MAX_SLOTS;
1177 num_channels = MAX_CHANNELS;
1178 num_csrows = MAX_SLOTS * MAX_CHANNELS;
1179
1180 debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
1181 __func__, num_channels, num_dimms_per_channel, num_csrows);
1182
1183 /* allocate a new MC control structure */
1184 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
1185
1186 if (mci == NULL)
1187 return -ENOMEM;
1188
1189 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
1190
1191 mci->dev = &pdev->dev; /* record ptr to the generic device */
1192
1193 pvt = mci->pvt_info;
1194 pvt->system_address = pdev; /* Record this device in our private */
1195
1196 /* 'get' the pci devices we want to reserve for our use */
1197 if (i7300_get_devices(mci, dev_idx))
1198 goto fail0;
1199
1200 mci->mc_idx = 0;
1201 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1202 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1203 mci->edac_cap = EDAC_FLAG_NONE;
1204 mci->mod_name = "i7300_edac.c";
1205 mci->mod_ver = I7300_REVISION;
1206 mci->ctl_name = i7300_devs[dev_idx].ctl_name;
1207 mci->dev_name = pci_name(pdev);
1208 mci->ctl_page_to_phys = NULL;
1209
1210#if 0
1211 /* Set the function pointer to an actual operation function */
1212 mci->edac_check = i7300_check_error;
1213#endif
1214
1215 /* initialize the MC control structure 'csrows' table
1216 * with the mapping and control information */
1217 if (i7300_get_mc_regs(mci)) {
1218 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1219 " because i7300_init_csrows() returned nonzero "
1220 "value\n");
1221 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1222 } else {
1223#if 0
1224 debugf1("MC: Enable error reporting now\n");
1225 i7300_enable_error_reporting(mci);
1226#endif
1227 }
1228
1229 /* add this new MC control structure to EDAC's list of MCs */
1230 if (edac_mc_add_mc(mci)) {
1231 debugf0("MC: " __FILE__
1232 ": %s(): failed edac_mc_add_mc()\n", __func__);
1233 /* FIXME: perhaps some code should go here that disables error
1234 * reporting if we just enabled it
1235 */
1236 goto fail1;
1237 }
1238
1239#if 0
1240 i7300_clear_error(mci);
1241#endif
1242
1243 /* allocating generic PCI control info */
1244 i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1245 if (!i7300_pci) {
1246 printk(KERN_WARNING
1247 "%s(): Unable to create PCI control\n",
1248 __func__);
1249 printk(KERN_WARNING
1250 "%s(): PCI error report via EDAC not setup\n",
1251 __func__);
1252 }
1253
1254 return 0;
1255
1256 /* Error exit unwinding stack */
1257fail1:
1258
1259 i7300_put_devices(mci);
1260
1261fail0:
1262 edac_mc_free(mci);
1263 return -ENODEV;
1264}
1265
1266/*
1267 * i7300_init_one constructor for one instance of device
1268 *
1269 * returns:
1270 * negative on error
1271 * count (>= 0)
1272 */
1273static int __devinit i7300_init_one(struct pci_dev *pdev,
1274 const struct pci_device_id *id)
1275{
1276 int rc;
1277
1278 debugf0("MC: " __FILE__ ": %s()\n", __func__);
1279
1280 /* wake up device */
1281 rc = pci_enable_device(pdev);
1282 if (rc == -EIO)
1283 return rc;
1284
1285 /* now probe and enable the device */
1286 return i7300_probe1(pdev, id->driver_data);
1287}
1288
1289/*
1290 * i7300_remove_one destructor for one instance of device
1291 *
1292 */
1293static void __devexit i7300_remove_one(struct pci_dev *pdev)
1294{
1295 struct mem_ctl_info *mci;
1296
1297 debugf0(__FILE__ ": %s()\n", __func__);
1298
1299 if (i7300_pci)
1300 edac_pci_release_generic_ctl(i7300_pci);
1301
1302 mci = edac_mc_del_mc(&pdev->dev);
1303 if (!mci)
1304 return;
1305
1306 /* retrieve references to resources, and free those resources */
1307 i7300_put_devices(mci);
1308
1309 edac_mc_free(mci);
1310}
1311
1312/*
1313 * pci_device_id table for which devices we are looking for
1314 *
1315 * The "E500P" device is the first device supported.
1316 */
1317static const struct pci_device_id i7300_pci_tbl[] __devinitdata = {
1318 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)},
1319 {0,} /* 0 terminated list. */
1320};
1321
1322MODULE_DEVICE_TABLE(pci, i7300_pci_tbl);
1323
1324/*
1325 * i7300_driver pci_driver structure for this module
1326 *
1327 */
1328static struct pci_driver i7300_driver = {
1329 .name = "i7300_edac",
1330 .probe = i7300_init_one,
1331 .remove = __devexit_p(i7300_remove_one),
1332 .id_table = i7300_pci_tbl,
1333};
1334
1335/*
1336 * i7300_init Module entry function
1337 * Try to initialize this module for its devices
1338 */
1339static int __init i7300_init(void)
1340{
1341 int pci_rc;
1342
1343 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1344
1345 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1346 opstate_init();
1347
1348 pci_rc = pci_register_driver(&i7300_driver);
1349
1350 return (pci_rc < 0) ? pci_rc : 0;
1351}
1352
1353/*
1354 * i7300_exit() Module exit function
1355 * Unregister the driver
1356 */
1357static void __exit i7300_exit(void)
1358{
1359 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1360 pci_unregister_driver(&i7300_driver);
1361}
1362
1363module_init(i7300_init);
1364module_exit(i7300_exit);
1365
1366MODULE_LICENSE("GPL");
1367MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1368MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1369MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - "
1370 I7300_REVISION);
1371
1372module_param(edac_op_state, int, 0444);
1373MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Linux kernel - Deliverables
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