Commit | Line | Data |
---|---|---|
5a2c675c TS |
1 | /* |
2 | * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel | |
3 | * module (C) 2006 Tim Small | |
4 | * | |
5 | * This file may be distributed under the terms of the GNU General | |
6 | * Public License. | |
7 | * | |
8 | * Written by Tim Small <tim@buttersideup.com>, based on work by Linux | |
9 | * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and | |
10 | * others. | |
11 | * | |
12 | * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>. | |
13 | * | |
14 | * Written with reference to 82443BX Host Bridge Datasheet: | |
084a4fcc | 15 | * http://download.intel.com/design/chipsets/datashts/29063301.pdf |
5a2c675c TS |
16 | * references to this document given in []. |
17 | * | |
18 | * This module doesn't support the 440LX, but it may be possible to | |
19 | * make it do so (the 440LX's register definitions are different, but | |
20 | * not completely so - I haven't studied them in enough detail to know | |
21 | * how easy this would be). | |
22 | */ | |
23 | ||
24 | #include <linux/module.h> | |
25 | #include <linux/init.h> | |
26 | ||
27 | #include <linux/pci.h> | |
28 | #include <linux/pci_ids.h> | |
29 | ||
5a2c675c | 30 | |
c3c52bce | 31 | #include <linux/edac.h> |
20bcb7a8 | 32 | #include "edac_core.h" |
5a2c675c TS |
33 | |
34 | #define I82443_REVISION "0.1" | |
35 | ||
36 | #define EDAC_MOD_STR "i82443bxgx_edac" | |
37 | ||
5a2c675c TS |
38 | /* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory |
39 | * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory | |
40 | * rows" "The 82443BX supports multiple-bit error detection and | |
41 | * single-bit error correction when ECC mode is enabled and | |
42 | * single/multi-bit error detection when correction is disabled. | |
43 | * During writes to the DRAM, the 82443BX generates ECC for the data | |
44 | * on a QWord basis. Partial QWord writes require a read-modify-write | |
45 | * cycle when ECC is enabled." | |
46 | */ | |
47 | ||
48 | /* "Additionally, the 82443BX ensures that the data is corrected in | |
49 | * main memory so that accumulation of errors is prevented. Another | |
50 | * error within the same QWord would result in a double-bit error | |
51 | * which is unrecoverable. This is known as hardware scrubbing since | |
52 | * it requires no software intervention to correct the data in memory." | |
53 | */ | |
54 | ||
55 | /* [Also see page 100 (section 4.3), "DRAM Interface"] | |
56 | * [Also see page 112 (section 4.6.1.4), ECC] | |
57 | */ | |
58 | ||
59 | #define I82443BXGX_NR_CSROWS 8 | |
60 | #define I82443BXGX_NR_CHANS 1 | |
61 | #define I82443BXGX_NR_DIMMS 4 | |
62 | ||
5a2c675c | 63 | /* 82443 PCI Device 0 */ |
11116601 DT |
64 | #define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI |
65 | * config space offset */ | |
66 | #define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if | |
67 | * row is non-ECC */ | |
68 | #define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */ | |
69 | ||
70 | #define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */ | |
71 | #define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */ | |
72 | #define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */ | |
73 | #define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */ | |
74 | #define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */ | |
5a2c675c TS |
75 | |
76 | #define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6 | |
77 | ||
5a2c675c | 78 | /* 82443 PCI Device 0 */ |
11116601 DT |
79 | #define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI |
80 | * config space offset, Error Address | |
81 | * Pointer Register */ | |
82 | #define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */ | |
83 | #define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */ | |
84 | #define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */ | |
85 | ||
86 | #define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI | |
5a2c675c | 87 | * config space offset. */ |
11116601 DT |
88 | #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */ |
89 | #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */ | |
5a2c675c | 90 | |
11116601 | 91 | #define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI |
5a2c675c | 92 | * config space offset. */ |
11116601 DT |
93 | #define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */ |
94 | #define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */ | |
95 | #define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */ | |
96 | #define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */ | |
5a2c675c | 97 | |
11116601 DT |
98 | #define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI |
99 | * config space offset. */ | |
100 | #define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */ | |
101 | #define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */ | |
5a2c675c | 102 | #define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */ |
11116601 | 103 | #define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */ |
5a2c675c | 104 | |
11116601 DT |
105 | #define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI |
106 | * config space offset. */ | |
5a2c675c TS |
107 | |
108 | /* FIXME - don't poll when ECC disabled? */ | |
109 | ||
5a2c675c TS |
110 | struct i82443bxgx_edacmc_error_info { |
111 | u32 eap; | |
112 | }; | |
113 | ||
456a2f95 DJ |
114 | static struct edac_pci_ctl_info *i82443bxgx_pci; |
115 | ||
53a2fe58 VB |
116 | static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has |
117 | * already registered driver | |
118 | */ | |
119 | ||
120 | static int i82443bxgx_registered = 1; | |
121 | ||
11116601 | 122 | static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci, |
052dfb45 DT |
123 | struct i82443bxgx_edacmc_error_info |
124 | *info) | |
5a2c675c TS |
125 | { |
126 | struct pci_dev *pdev; | |
fd687502 | 127 | pdev = to_pci_dev(mci->pdev); |
5a2c675c TS |
128 | pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap); |
129 | if (info->eap & I82443BXGX_EAP_OFFSET_SBE) | |
130 | /* Clear error to allow next error to be reported [p.61] */ | |
131 | pci_write_bits32(pdev, I82443BXGX_EAP, | |
132 | I82443BXGX_EAP_OFFSET_SBE, | |
133 | I82443BXGX_EAP_OFFSET_SBE); | |
134 | ||
135 | if (info->eap & I82443BXGX_EAP_OFFSET_MBE) | |
136 | /* Clear error to allow next error to be reported [p.61] */ | |
137 | pci_write_bits32(pdev, I82443BXGX_EAP, | |
138 | I82443BXGX_EAP_OFFSET_MBE, | |
139 | I82443BXGX_EAP_OFFSET_MBE); | |
140 | } | |
141 | ||
11116601 DT |
142 | static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci, |
143 | struct | |
144 | i82443bxgx_edacmc_error_info | |
145 | *info, int handle_errors) | |
5a2c675c TS |
146 | { |
147 | int error_found = 0; | |
148 | u32 eapaddr, page, pageoffset; | |
149 | ||
150 | /* bits 30:12 hold the 4kb block in which the error occurred | |
151 | * [p.61] */ | |
152 | eapaddr = (info->eap & 0xfffff000); | |
153 | page = eapaddr >> PAGE_SHIFT; | |
154 | pageoffset = eapaddr - (page << PAGE_SHIFT); | |
155 | ||
11116601 | 156 | if (info->eap & I82443BXGX_EAP_OFFSET_SBE) { |
5a2c675c TS |
157 | error_found = 1; |
158 | if (handle_errors) | |
40f562b1 MCC |
159 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, |
160 | page, pageoffset, 0, | |
161 | edac_mc_find_csrow_by_page(mci, page), | |
162 | 0, -1, mci->ctl_name, "", NULL); | |
5a2c675c TS |
163 | } |
164 | ||
11116601 | 165 | if (info->eap & I82443BXGX_EAP_OFFSET_MBE) { |
5a2c675c TS |
166 | error_found = 1; |
167 | if (handle_errors) | |
40f562b1 MCC |
168 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, |
169 | page, pageoffset, 0, | |
170 | edac_mc_find_csrow_by_page(mci, page), | |
171 | 0, -1, mci->ctl_name, "", NULL); | |
5a2c675c TS |
172 | } |
173 | ||
174 | return error_found; | |
175 | } | |
176 | ||
5a2c675c TS |
177 | static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci) |
178 | { | |
179 | struct i82443bxgx_edacmc_error_info info; | |
180 | ||
63ae96be | 181 | debugf1("MC%d: %s: %s()\n", mci->mc_idx, __FILE__, __func__); |
5a2c675c TS |
182 | i82443bxgx_edacmc_get_error_info(mci, &info); |
183 | i82443bxgx_edacmc_process_error_info(mci, &info, 1); | |
184 | } | |
185 | ||
5a2c675c | 186 | static void i82443bxgx_init_csrows(struct mem_ctl_info *mci, |
052dfb45 DT |
187 | struct pci_dev *pdev, |
188 | enum edac_type edac_mode, | |
189 | enum mem_type mtype) | |
5a2c675c TS |
190 | { |
191 | struct csrow_info *csrow; | |
084a4fcc | 192 | struct dimm_info *dimm; |
5a2c675c TS |
193 | int index; |
194 | u8 drbar, dramc; | |
195 | u32 row_base, row_high_limit, row_high_limit_last; | |
196 | ||
197 | pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc); | |
198 | row_high_limit_last = 0; | |
199 | for (index = 0; index < mci->nr_csrows; index++) { | |
200 | csrow = &mci->csrows[index]; | |
084a4fcc MCC |
201 | dimm = csrow->channels[0].dimm; |
202 | ||
5a2c675c | 203 | pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar); |
63ae96be JP |
204 | debugf1("MC%d: %s: %s() Row=%d DRB = %#0x\n", |
205 | mci->mc_idx, __FILE__, __func__, index, drbar); | |
5a2c675c TS |
206 | row_high_limit = ((u32) drbar << 23); |
207 | /* find the DRAM Chip Select Base address and mask */ | |
63ae96be | 208 | debugf1("MC%d: %s: %s() Row=%d, " |
25985edc | 209 | "Boundary Address=%#0x, Last = %#0x\n", |
63ae96be | 210 | mci->mc_idx, __FILE__, __func__, index, row_high_limit, |
5a2c675c TS |
211 | row_high_limit_last); |
212 | ||
213 | /* 440GX goes to 2GB, represented with a DRB of 0. */ | |
214 | if (row_high_limit_last && !row_high_limit) | |
215 | row_high_limit = 1UL << 31; | |
216 | ||
217 | /* This row is empty [p.49] */ | |
218 | if (row_high_limit == row_high_limit_last) | |
219 | continue; | |
220 | row_base = row_high_limit_last; | |
221 | csrow->first_page = row_base >> PAGE_SHIFT; | |
222 | csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; | |
a895bf8b | 223 | dimm->nr_pages = csrow->last_page - csrow->first_page + 1; |
5a2c675c | 224 | /* EAP reports in 4kilobyte granularity [61] */ |
084a4fcc MCC |
225 | dimm->grain = 1 << 12; |
226 | dimm->mtype = mtype; | |
5a2c675c | 227 | /* I don't think 440BX can tell you device type? FIXME? */ |
084a4fcc | 228 | dimm->dtype = DEV_UNKNOWN; |
5a2c675c | 229 | /* Mode is global to all rows on 440BX */ |
084a4fcc | 230 | dimm->edac_mode = edac_mode; |
5a2c675c TS |
231 | row_high_limit_last = row_high_limit; |
232 | } | |
233 | } | |
234 | ||
11116601 | 235 | static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) |
5a2c675c TS |
236 | { |
237 | struct mem_ctl_info *mci; | |
40f562b1 | 238 | struct edac_mc_layer layers[2]; |
5a2c675c TS |
239 | u8 dramc; |
240 | u32 nbxcfg, ecc_mode; | |
241 | enum mem_type mtype; | |
242 | enum edac_type edac_mode; | |
243 | ||
63ae96be | 244 | debugf0("MC: %s: %s()\n", __FILE__, __func__); |
5a2c675c TS |
245 | |
246 | /* Something is really hosed if PCI config space reads from | |
052dfb45 DT |
247 | * the MC aren't working. |
248 | */ | |
5a2c675c TS |
249 | if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg)) |
250 | return -EIO; | |
251 | ||
40f562b1 MCC |
252 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
253 | layers[0].size = I82443BXGX_NR_CSROWS; | |
254 | layers[0].is_virt_csrow = true; | |
255 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
256 | layers[1].size = I82443BXGX_NR_CHANS; | |
257 | layers[1].is_virt_csrow = false; | |
ca0907b9 | 258 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); |
5a2c675c TS |
259 | if (mci == NULL) |
260 | return -ENOMEM; | |
261 | ||
63ae96be | 262 | debugf0("MC: %s: %s(): mci = %p\n", __FILE__, __func__, mci); |
fd687502 | 263 | mci->pdev = &pdev->dev; |
5a2c675c TS |
264 | mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR; |
265 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; | |
266 | pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc); | |
267 | switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) { | |
11116601 | 268 | case I82443BXGX_DRAMC_DRAM_IS_EDO: |
5a2c675c TS |
269 | mtype = MEM_EDO; |
270 | break; | |
271 | case I82443BXGX_DRAMC_DRAM_IS_SDRAM: | |
272 | mtype = MEM_SDR; | |
273 | break; | |
274 | case I82443BXGX_DRAMC_DRAM_IS_RSDRAM: | |
275 | mtype = MEM_RDR; | |
276 | break; | |
277 | default: | |
052dfb45 DT |
278 | debugf0("Unknown/reserved DRAM type value " |
279 | "in DRAMC register!\n"); | |
5a2c675c TS |
280 | mtype = -MEM_UNKNOWN; |
281 | } | |
282 | ||
283 | if ((mtype == MEM_SDR) || (mtype == MEM_RDR)) | |
284 | mci->edac_cap = mci->edac_ctl_cap; | |
285 | else | |
286 | mci->edac_cap = EDAC_FLAG_NONE; | |
287 | ||
288 | mci->scrub_cap = SCRUB_FLAG_HW_SRC; | |
289 | pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg); | |
290 | ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) & | |
052dfb45 | 291 | (BIT(0) | BIT(1))); |
5a2c675c TS |
292 | |
293 | mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB) | |
052dfb45 | 294 | ? SCRUB_HW_SRC : SCRUB_NONE; |
5a2c675c | 295 | |
11116601 | 296 | switch (ecc_mode) { |
5a2c675c TS |
297 | case I82443BXGX_NBXCFG_INTEGRITY_NONE: |
298 | edac_mode = EDAC_NONE; | |
299 | break; | |
300 | case I82443BXGX_NBXCFG_INTEGRITY_EC: | |
301 | edac_mode = EDAC_EC; | |
302 | break; | |
303 | case I82443BXGX_NBXCFG_INTEGRITY_ECC: | |
304 | case I82443BXGX_NBXCFG_INTEGRITY_SCRUB: | |
305 | edac_mode = EDAC_SECDED; | |
306 | break; | |
307 | default: | |
052dfb45 DT |
308 | debugf0("%s(): Unknown/reserved ECC state " |
309 | "in NBXCFG register!\n", __func__); | |
5a2c675c TS |
310 | edac_mode = EDAC_UNKNOWN; |
311 | break; | |
312 | } | |
313 | ||
314 | i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype); | |
315 | ||
316 | /* Many BIOSes don't clear error flags on boot, so do this | |
25985edc | 317 | * here, or we get "phantom" errors occurring at module-load |
5a2c675c TS |
318 | * time. */ |
319 | pci_write_bits32(pdev, I82443BXGX_EAP, | |
052dfb45 DT |
320 | (I82443BXGX_EAP_OFFSET_SBE | |
321 | I82443BXGX_EAP_OFFSET_MBE), | |
322 | (I82443BXGX_EAP_OFFSET_SBE | | |
323 | I82443BXGX_EAP_OFFSET_MBE)); | |
5a2c675c TS |
324 | |
325 | mci->mod_name = EDAC_MOD_STR; | |
326 | mci->mod_ver = I82443_REVISION; | |
327 | mci->ctl_name = "I82443BXGX"; | |
c4192705 | 328 | mci->dev_name = pci_name(pdev); |
5a2c675c TS |
329 | mci->edac_check = i82443bxgx_edacmc_check; |
330 | mci->ctl_page_to_phys = NULL; | |
331 | ||
b8f6f975 | 332 | if (edac_mc_add_mc(mci)) { |
5a2c675c TS |
333 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); |
334 | goto fail; | |
335 | } | |
336 | ||
456a2f95 DJ |
337 | /* allocating generic PCI control info */ |
338 | i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); | |
339 | if (!i82443bxgx_pci) { | |
340 | printk(KERN_WARNING | |
341 | "%s(): Unable to create PCI control\n", | |
342 | __func__); | |
343 | printk(KERN_WARNING | |
344 | "%s(): PCI error report via EDAC not setup\n", | |
345 | __func__); | |
346 | } | |
347 | ||
63ae96be | 348 | debugf3("MC: %s: %s(): success\n", __FILE__, __func__); |
5a2c675c TS |
349 | return 0; |
350 | ||
052dfb45 | 351 | fail: |
5a2c675c TS |
352 | edac_mc_free(mci); |
353 | return -ENODEV; | |
354 | } | |
11116601 | 355 | |
5a2c675c TS |
356 | EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_probe1); |
357 | ||
358 | /* returns count (>= 0), or negative on error */ | |
359 | static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev, | |
11116601 | 360 | const struct pci_device_id *ent) |
5a2c675c | 361 | { |
53a2fe58 VB |
362 | int rc; |
363 | ||
63ae96be | 364 | debugf0("MC: %s: %s()\n", __FILE__, __func__); |
5a2c675c | 365 | |
ee6583f6 | 366 | /* don't need to call pci_enable_device() */ |
53a2fe58 VB |
367 | rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data); |
368 | ||
369 | if (mci_pdev == NULL) | |
370 | mci_pdev = pci_dev_get(pdev); | |
371 | ||
372 | return rc; | |
5a2c675c TS |
373 | } |
374 | ||
5a2c675c TS |
375 | static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev) |
376 | { | |
377 | struct mem_ctl_info *mci; | |
378 | ||
63ae96be | 379 | debugf0("%s: %s()\n", __FILE__, __func__); |
5a2c675c | 380 | |
456a2f95 DJ |
381 | if (i82443bxgx_pci) |
382 | edac_pci_release_generic_ctl(i82443bxgx_pci); | |
383 | ||
11116601 | 384 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
5a2c675c TS |
385 | return; |
386 | ||
387 | edac_mc_free(mci); | |
388 | } | |
5a2c675c | 389 | |
11116601 | 390 | EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one); |
5a2c675c | 391 | |
36c46f31 | 392 | static DEFINE_PCI_DEVICE_TABLE(i82443bxgx_pci_tbl) = { |
5a2c675c TS |
393 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)}, |
394 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)}, | |
395 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)}, | |
396 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)}, | |
397 | {0,} /* 0 terminated list. */ | |
398 | }; | |
399 | ||
400 | MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl); | |
401 | ||
5a2c675c TS |
402 | static struct pci_driver i82443bxgx_edacmc_driver = { |
403 | .name = EDAC_MOD_STR, | |
404 | .probe = i82443bxgx_edacmc_init_one, | |
405 | .remove = __devexit_p(i82443bxgx_edacmc_remove_one), | |
406 | .id_table = i82443bxgx_pci_tbl, | |
407 | }; | |
408 | ||
5a2c675c TS |
409 | static int __init i82443bxgx_edacmc_init(void) |
410 | { | |
53a2fe58 | 411 | int pci_rc; |
c3c52bce HM |
412 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
413 | opstate_init(); | |
414 | ||
53a2fe58 VB |
415 | pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver); |
416 | if (pci_rc < 0) | |
417 | goto fail0; | |
418 | ||
419 | if (mci_pdev == NULL) { | |
420 | const struct pci_device_id *id = &i82443bxgx_pci_tbl[0]; | |
421 | int i = 0; | |
422 | i82443bxgx_registered = 0; | |
423 | ||
424 | while (mci_pdev == NULL && id->vendor != 0) { | |
425 | mci_pdev = pci_get_device(id->vendor, | |
426 | id->device, NULL); | |
427 | i++; | |
428 | id = &i82443bxgx_pci_tbl[i]; | |
429 | } | |
430 | if (!mci_pdev) { | |
431 | debugf0("i82443bxgx pci_get_device fail\n"); | |
432 | pci_rc = -ENODEV; | |
433 | goto fail1; | |
434 | } | |
435 | ||
436 | pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl); | |
437 | ||
438 | if (pci_rc < 0) { | |
439 | debugf0("i82443bxgx init fail\n"); | |
440 | pci_rc = -ENODEV; | |
441 | goto fail1; | |
442 | } | |
443 | } | |
444 | ||
445 | return 0; | |
446 | ||
447 | fail1: | |
448 | pci_unregister_driver(&i82443bxgx_edacmc_driver); | |
449 | ||
450 | fail0: | |
451 | if (mci_pdev != NULL) | |
452 | pci_dev_put(mci_pdev); | |
453 | ||
454 | return pci_rc; | |
5a2c675c TS |
455 | } |
456 | ||
5a2c675c TS |
457 | static void __exit i82443bxgx_edacmc_exit(void) |
458 | { | |
459 | pci_unregister_driver(&i82443bxgx_edacmc_driver); | |
53a2fe58 VB |
460 | |
461 | if (!i82443bxgx_registered) | |
462 | i82443bxgx_edacmc_remove_one(mci_pdev); | |
463 | ||
464 | if (mci_pdev) | |
465 | pci_dev_put(mci_pdev); | |
5a2c675c TS |
466 | } |
467 | ||
5a2c675c TS |
468 | module_init(i82443bxgx_edacmc_init); |
469 | module_exit(i82443bxgx_edacmc_exit); | |
470 | ||
5a2c675c TS |
471 | MODULE_LICENSE("GPL"); |
472 | MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD"); | |
473 | MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers"); | |
c3c52bce HM |
474 | |
475 | module_param(edac_op_state, int, 0444); | |
476 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |