Commit | Line | Data |
---|---|---|
0d88a10e AC |
1 | /* |
2 | * Intel D82875P Memory Controller kernel module | |
3 | * (C) 2003 Linux Networx (http://lnxi.com) | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Thayne Harbaugh | |
8 | * Contributors: | |
9 | * Wang Zhenyu at intel.com | |
10 | * | |
11 | * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $ | |
12 | * | |
13 | * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com | |
14 | */ | |
15 | ||
0d88a10e AC |
16 | #include <linux/module.h> |
17 | #include <linux/init.h> | |
0d88a10e AC |
18 | #include <linux/pci.h> |
19 | #include <linux/pci_ids.h> | |
c3c52bce | 20 | #include <linux/edac.h> |
20bcb7a8 | 21 | #include "edac_core.h" |
0d88a10e | 22 | |
152ba394 | 23 | #define I82875P_REVISION " Ver: 2.0.2" |
929a40ec | 24 | #define EDAC_MOD_STR "i82875p_edac" |
37f04581 | 25 | |
537fba28 | 26 | #define i82875p_printk(level, fmt, arg...) \ |
e7ecd891 | 27 | edac_printk(level, "i82875p", fmt, ##arg) |
537fba28 DP |
28 | |
29 | #define i82875p_mc_printk(mci, level, fmt, arg...) \ | |
e7ecd891 | 30 | edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg) |
537fba28 | 31 | |
0d88a10e AC |
32 | #ifndef PCI_DEVICE_ID_INTEL_82875_0 |
33 | #define PCI_DEVICE_ID_INTEL_82875_0 0x2578 | |
34 | #endif /* PCI_DEVICE_ID_INTEL_82875_0 */ | |
35 | ||
36 | #ifndef PCI_DEVICE_ID_INTEL_82875_6 | |
37 | #define PCI_DEVICE_ID_INTEL_82875_6 0x257e | |
38 | #endif /* PCI_DEVICE_ID_INTEL_82875_6 */ | |
39 | ||
0d88a10e | 40 | /* four csrows in dual channel, eight in single channel */ |
0a8a9ac9 MCC |
41 | #define I82875P_NR_DIMMS 8 |
42 | #define I82875P_NR_CSROWS(nr_chans) (I82875P_NR_DIMMS / (nr_chans)) | |
0d88a10e | 43 | |
0d88a10e AC |
44 | /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */ |
45 | #define I82875P_EAP 0x58 /* Error Address Pointer (32b) | |
46 | * | |
47 | * 31:12 block address | |
48 | * 11:0 reserved | |
49 | */ | |
50 | ||
51 | #define I82875P_DERRSYN 0x5c /* DRAM Error Syndrome (8b) | |
52 | * | |
53 | * 7:0 DRAM ECC Syndrome | |
54 | */ | |
55 | ||
56 | #define I82875P_DES 0x5d /* DRAM Error Status (8b) | |
57 | * | |
58 | * 7:1 reserved | |
59 | * 0 Error channel 0/1 | |
60 | */ | |
61 | ||
62 | #define I82875P_ERRSTS 0xc8 /* Error Status Register (16b) | |
63 | * | |
64 | * 15:10 reserved | |
65 | * 9 non-DRAM lock error (ndlock) | |
66 | * 8 Sftwr Generated SMI | |
67 | * 7 ECC UE | |
68 | * 6 reserved | |
69 | * 5 MCH detects unimplemented cycle | |
70 | * 4 AGP access outside GA | |
71 | * 3 Invalid AGP access | |
72 | * 2 Invalid GA translation table | |
73 | * 1 Unsupported AGP command | |
74 | * 0 ECC CE | |
75 | */ | |
76 | ||
77 | #define I82875P_ERRCMD 0xca /* Error Command (16b) | |
78 | * | |
79 | * 15:10 reserved | |
80 | * 9 SERR on non-DRAM lock | |
81 | * 8 SERR on ECC UE | |
82 | * 7 SERR on ECC CE | |
83 | * 6 target abort on high exception | |
84 | * 5 detect unimplemented cyc | |
85 | * 4 AGP access outside of GA | |
86 | * 3 SERR on invalid AGP access | |
87 | * 2 invalid translation table | |
88 | * 1 SERR on unsupported AGP command | |
89 | * 0 reserved | |
90 | */ | |
91 | ||
0d88a10e AC |
92 | /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */ |
93 | #define I82875P_PCICMD6 0x04 /* PCI Command Register (16b) | |
94 | * | |
95 | * 15:10 reserved | |
96 | * 9 fast back-to-back - ro 0 | |
97 | * 8 SERR enable - ro 0 | |
98 | * 7 addr/data stepping - ro 0 | |
99 | * 6 parity err enable - ro 0 | |
100 | * 5 VGA palette snoop - ro 0 | |
101 | * 4 mem wr & invalidate - ro 0 | |
102 | * 3 special cycle - ro 0 | |
103 | * 2 bus master - ro 0 | |
104 | * 1 mem access dev6 - 0(dis),1(en) | |
105 | * 0 IO access dev3 - 0(dis),1(en) | |
106 | */ | |
107 | ||
108 | #define I82875P_BAR6 0x10 /* Mem Delays Base ADDR Reg (32b) | |
109 | * | |
110 | * 31:12 mem base addr [31:12] | |
111 | * 11:4 address mask - ro 0 | |
112 | * 3 prefetchable - ro 0(non),1(pre) | |
113 | * 2:1 mem type - ro 0 | |
114 | * 0 mem space - ro 0 | |
115 | */ | |
116 | ||
117 | /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */ | |
118 | ||
119 | #define I82875P_DRB_SHIFT 26 /* 64MiB grain */ | |
120 | #define I82875P_DRB 0x00 /* DRAM Row Boundary (8b x 8) | |
121 | * | |
122 | * 7 reserved | |
123 | * 6:0 64MiB row boundary addr | |
124 | */ | |
125 | ||
126 | #define I82875P_DRA 0x10 /* DRAM Row Attribute (4b x 8) | |
127 | * | |
128 | * 7 reserved | |
129 | * 6:4 row attr row 1 | |
130 | * 3 reserved | |
131 | * 2:0 row attr row 0 | |
132 | * | |
133 | * 000 = 4KiB | |
134 | * 001 = 8KiB | |
135 | * 010 = 16KiB | |
136 | * 011 = 32KiB | |
137 | */ | |
138 | ||
139 | #define I82875P_DRC 0x68 /* DRAM Controller Mode (32b) | |
140 | * | |
141 | * 31:30 reserved | |
142 | * 29 init complete | |
143 | * 28:23 reserved | |
144 | * 22:21 nr chan 00=1,01=2 | |
145 | * 20 reserved | |
146 | * 19:18 Data Integ Mode 00=none,01=ecc | |
147 | * 17:11 reserved | |
148 | * 10:8 refresh mode | |
149 | * 7 reserved | |
150 | * 6:4 mode select | |
151 | * 3:2 reserved | |
152 | * 1:0 DRAM type 01=DDR | |
153 | */ | |
154 | ||
0d88a10e AC |
155 | enum i82875p_chips { |
156 | I82875P = 0, | |
157 | }; | |
158 | ||
0d88a10e AC |
159 | struct i82875p_pvt { |
160 | struct pci_dev *ovrfl_pdev; | |
6d57348d | 161 | void __iomem *ovrfl_window; |
0d88a10e AC |
162 | }; |
163 | ||
0d88a10e AC |
164 | struct i82875p_dev_info { |
165 | const char *ctl_name; | |
166 | }; | |
167 | ||
0d88a10e AC |
168 | struct i82875p_error_info { |
169 | u16 errsts; | |
170 | u32 eap; | |
171 | u8 des; | |
172 | u8 derrsyn; | |
173 | u16 errsts2; | |
174 | }; | |
175 | ||
0d88a10e AC |
176 | static const struct i82875p_dev_info i82875p_devs[] = { |
177 | [I82875P] = { | |
052dfb45 | 178 | .ctl_name = "i82875p"}, |
0d88a10e AC |
179 | }; |
180 | ||
f044091c | 181 | static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has |
e7ecd891 DP |
182 | * already registered driver |
183 | */ | |
184 | ||
456a2f95 DJ |
185 | static struct edac_pci_ctl_info *i82875p_pci; |
186 | ||
e7ecd891 | 187 | static void i82875p_get_error_info(struct mem_ctl_info *mci, |
052dfb45 | 188 | struct i82875p_error_info *info) |
0d88a10e | 189 | { |
37f04581 DT |
190 | struct pci_dev *pdev; |
191 | ||
fd687502 | 192 | pdev = to_pci_dev(mci->pdev); |
37f04581 | 193 | |
0d88a10e AC |
194 | /* |
195 | * This is a mess because there is no atomic way to read all the | |
196 | * registers at once and the registers can transition from CE being | |
197 | * overwritten by UE. | |
198 | */ | |
37f04581 | 199 | pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts); |
654ede20 JU |
200 | |
201 | if (!(info->errsts & 0x0081)) | |
202 | return; | |
203 | ||
37f04581 DT |
204 | pci_read_config_dword(pdev, I82875P_EAP, &info->eap); |
205 | pci_read_config_byte(pdev, I82875P_DES, &info->des); | |
206 | pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn); | |
207 | pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2); | |
0d88a10e | 208 | |
0d88a10e AC |
209 | /* |
210 | * If the error is the same then we can for both reads then | |
211 | * the first set of reads is valid. If there is a change then | |
212 | * there is a CE no info and the second set of reads is valid | |
213 | * and should be UE info. | |
214 | */ | |
0d88a10e | 215 | if ((info->errsts ^ info->errsts2) & 0x0081) { |
37f04581 DT |
216 | pci_read_config_dword(pdev, I82875P_EAP, &info->eap); |
217 | pci_read_config_byte(pdev, I82875P_DES, &info->des); | |
466b71d5 | 218 | pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn); |
0d88a10e | 219 | } |
654ede20 JU |
220 | |
221 | pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081); | |
0d88a10e AC |
222 | } |
223 | ||
e7ecd891 | 224 | static int i82875p_process_error_info(struct mem_ctl_info *mci, |
052dfb45 DT |
225 | struct i82875p_error_info *info, |
226 | int handle_errors) | |
0d88a10e AC |
227 | { |
228 | int row, multi_chan; | |
229 | ||
de3910eb | 230 | multi_chan = mci->csrows[0]->nr_channels - 1; |
0d88a10e | 231 | |
654ede20 | 232 | if (!(info->errsts & 0x0081)) |
0d88a10e AC |
233 | return 0; |
234 | ||
235 | if (!handle_errors) | |
236 | return 1; | |
237 | ||
238 | if ((info->errsts ^ info->errsts2) & 0x0081) { | |
9eb07a7f | 239 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, |
0a8a9ac9 | 240 | -1, -1, -1, |
03f7eae8 | 241 | "UE overwrote CE", ""); |
0d88a10e AC |
242 | info->errsts = info->errsts2; |
243 | } | |
244 | ||
245 | info->eap >>= PAGE_SHIFT; | |
246 | row = edac_mc_find_csrow_by_page(mci, info->eap); | |
247 | ||
248 | if (info->errsts & 0x0080) | |
9eb07a7f | 249 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
0a8a9ac9 MCC |
250 | info->eap, 0, 0, |
251 | row, -1, -1, | |
03f7eae8 | 252 | "i82875p UE", ""); |
0d88a10e | 253 | else |
9eb07a7f | 254 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, |
0a8a9ac9 MCC |
255 | info->eap, 0, info->derrsyn, |
256 | row, multi_chan ? (info->des & 0x1) : 0, | |
03f7eae8 | 257 | -1, "i82875p CE", ""); |
0d88a10e AC |
258 | |
259 | return 1; | |
260 | } | |
261 | ||
0d88a10e AC |
262 | static void i82875p_check(struct mem_ctl_info *mci) |
263 | { | |
264 | struct i82875p_error_info info; | |
265 | ||
956b9ba1 | 266 | edac_dbg(1, "MC%d\n", mci->mc_idx); |
0d88a10e AC |
267 | i82875p_get_error_info(mci, &info); |
268 | i82875p_process_error_info(mci, &info, 1); | |
269 | } | |
270 | ||
13189525 DT |
271 | /* Return 0 on success or 1 on failure. */ |
272 | static int i82875p_setup_overfl_dev(struct pci_dev *pdev, | |
052dfb45 DT |
273 | struct pci_dev **ovrfl_pdev, |
274 | void __iomem **ovrfl_window) | |
0d88a10e | 275 | { |
13189525 DT |
276 | struct pci_dev *dev; |
277 | void __iomem *window; | |
1c52152b | 278 | int err; |
0d88a10e | 279 | |
13189525 DT |
280 | *ovrfl_pdev = NULL; |
281 | *ovrfl_window = NULL; | |
282 | dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL); | |
0d88a10e | 283 | |
13189525 DT |
284 | if (dev == NULL) { |
285 | /* Intel tells BIOS developers to hide device 6 which | |
0d88a10e AC |
286 | * configures the overflow device access containing |
287 | * the DRBs - this is where we expose device 6. | |
288 | * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm | |
289 | */ | |
290 | pci_write_bits8(pdev, 0xf4, 0x2, 0x2); | |
13189525 | 291 | dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0)); |
e7ecd891 | 292 | |
13189525 DT |
293 | if (dev == NULL) |
294 | return 1; | |
62456726 | 295 | |
1c52152b DT |
296 | err = pci_bus_add_device(dev); |
297 | if (err) { | |
298 | i82875p_printk(KERN_ERR, | |
299 | "%s(): pci_bus_add_device() Failed\n", | |
300 | __func__); | |
301 | } | |
307d1144 | 302 | pci_bus_assign_resources(dev->bus); |
0d88a10e | 303 | } |
e7ecd891 | 304 | |
13189525 DT |
305 | *ovrfl_pdev = dev; |
306 | ||
13189525 DT |
307 | if (pci_enable_device(dev)) { |
308 | i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow " | |
052dfb45 | 309 | "device\n", __func__); |
13189525 | 310 | return 1; |
0d88a10e AC |
311 | } |
312 | ||
13189525 | 313 | if (pci_request_regions(dev, pci_name(dev))) { |
0d88a10e | 314 | #ifdef CORRECT_BIOS |
637beb69 | 315 | goto fail0; |
0d88a10e AC |
316 | #endif |
317 | } | |
e7ecd891 | 318 | |
0d88a10e | 319 | /* cache is irrelevant for PCI bus reads/writes */ |
1dca00bd | 320 | window = pci_ioremap_bar(dev, 0); |
13189525 | 321 | if (window == NULL) { |
537fba28 | 322 | i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n", |
052dfb45 | 323 | __func__); |
637beb69 | 324 | goto fail1; |
0d88a10e AC |
325 | } |
326 | ||
13189525 DT |
327 | *ovrfl_window = window; |
328 | return 0; | |
0d88a10e | 329 | |
052dfb45 | 330 | fail1: |
13189525 | 331 | pci_release_regions(dev); |
0d88a10e | 332 | |
13189525 | 333 | #ifdef CORRECT_BIOS |
052dfb45 | 334 | fail0: |
13189525 DT |
335 | pci_disable_device(dev); |
336 | #endif | |
337 | /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */ | |
338 | return 1; | |
339 | } | |
0d88a10e | 340 | |
13189525 DT |
341 | /* Return 1 if dual channel mode is active. Else return 0. */ |
342 | static inline int dual_channel_active(u32 drc) | |
343 | { | |
344 | return (drc >> 21) & 0x1; | |
345 | } | |
0d88a10e | 346 | |
13189525 | 347 | static void i82875p_init_csrows(struct mem_ctl_info *mci, |
466b71d5 DJ |
348 | struct pci_dev *pdev, |
349 | void __iomem * ovrfl_window, u32 drc) | |
13189525 DT |
350 | { |
351 | struct csrow_info *csrow; | |
084a4fcc MCC |
352 | struct dimm_info *dimm; |
353 | unsigned nr_chans = dual_channel_active(drc) + 1; | |
13189525 DT |
354 | unsigned long last_cumul_size; |
355 | u8 value; | |
466b71d5 | 356 | u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */ |
a895bf8b | 357 | u32 cumul_size, nr_pages; |
084a4fcc | 358 | int index, j; |
13189525 DT |
359 | |
360 | drc_ddim = (drc >> 18) & 0x1; | |
361 | last_cumul_size = 0; | |
362 | ||
363 | /* The dram row boundary (DRB) reg values are boundary address | |
0d88a10e AC |
364 | * for each DRAM row with a granularity of 32 or 64MB (single/dual |
365 | * channel operation). DRB regs are cumulative; therefore DRB7 will | |
366 | * contain the total memory contained in all eight rows. | |
367 | */ | |
13189525 DT |
368 | |
369 | for (index = 0; index < mci->nr_csrows; index++) { | |
de3910eb | 370 | csrow = mci->csrows[index]; |
0d88a10e AC |
371 | |
372 | value = readb(ovrfl_window + I82875P_DRB + index); | |
373 | cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT); | |
956b9ba1 | 374 | edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size); |
0d88a10e AC |
375 | if (cumul_size == last_cumul_size) |
376 | continue; /* not populated */ | |
377 | ||
378 | csrow->first_page = last_cumul_size; | |
379 | csrow->last_page = cumul_size - 1; | |
a895bf8b | 380 | nr_pages = cumul_size - last_cumul_size; |
0d88a10e | 381 | last_cumul_size = cumul_size; |
084a4fcc MCC |
382 | |
383 | for (j = 0; j < nr_chans; j++) { | |
de3910eb | 384 | dimm = csrow->channels[j]->dimm; |
084a4fcc | 385 | |
a895bf8b | 386 | dimm->nr_pages = nr_pages / nr_chans; |
084a4fcc MCC |
387 | dimm->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */ |
388 | dimm->mtype = MEM_DDR; | |
389 | dimm->dtype = DEV_UNKNOWN; | |
390 | dimm->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE; | |
391 | } | |
0d88a10e | 392 | } |
13189525 DT |
393 | } |
394 | ||
395 | static int i82875p_probe1(struct pci_dev *pdev, int dev_idx) | |
396 | { | |
397 | int rc = -ENODEV; | |
398 | struct mem_ctl_info *mci; | |
0a8a9ac9 | 399 | struct edac_mc_layer layers[2]; |
13189525 DT |
400 | struct i82875p_pvt *pvt; |
401 | struct pci_dev *ovrfl_pdev; | |
402 | void __iomem *ovrfl_window; | |
403 | u32 drc; | |
404 | u32 nr_chans; | |
405 | struct i82875p_error_info discard; | |
0d88a10e | 406 | |
956b9ba1 | 407 | edac_dbg(0, "\n"); |
c3c52bce | 408 | |
13189525 DT |
409 | ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL); |
410 | ||
411 | if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window)) | |
412 | return -ENODEV; | |
413 | drc = readl(ovrfl_window + I82875P_DRC); | |
414 | nr_chans = dual_channel_active(drc) + 1; | |
13189525 | 415 | |
0a8a9ac9 MCC |
416 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
417 | layers[0].size = I82875P_NR_CSROWS(nr_chans); | |
418 | layers[0].is_virt_csrow = true; | |
419 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
420 | layers[1].size = nr_chans; | |
421 | layers[1].is_virt_csrow = false; | |
ca0907b9 | 422 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); |
13189525 DT |
423 | if (!mci) { |
424 | rc = -ENOMEM; | |
425 | goto fail0; | |
426 | } | |
427 | ||
956b9ba1 | 428 | edac_dbg(3, "init mci\n"); |
fd687502 | 429 | mci->pdev = &pdev->dev; |
13189525 DT |
430 | mci->mtype_cap = MEM_FLAG_DDR; |
431 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
432 | mci->edac_cap = EDAC_FLAG_UNKNOWN; | |
433 | mci->mod_name = EDAC_MOD_STR; | |
434 | mci->mod_ver = I82875P_REVISION; | |
435 | mci->ctl_name = i82875p_devs[dev_idx].ctl_name; | |
c4192705 | 436 | mci->dev_name = pci_name(pdev); |
13189525 DT |
437 | mci->edac_check = i82875p_check; |
438 | mci->ctl_page_to_phys = NULL; | |
956b9ba1 | 439 | edac_dbg(3, "init pvt\n"); |
466b71d5 | 440 | pvt = (struct i82875p_pvt *)mci->pvt_info; |
13189525 DT |
441 | pvt->ovrfl_pdev = ovrfl_pdev; |
442 | pvt->ovrfl_window = ovrfl_window; | |
443 | i82875p_init_csrows(mci, pdev, ovrfl_window, drc); | |
466b71d5 | 444 | i82875p_get_error_info(mci, &discard); /* clear counters */ |
0d88a10e | 445 | |
2d7bbb91 DT |
446 | /* Here we assume that we will never see multiple instances of this |
447 | * type of memory controller. The ID is therefore hardcoded to 0. | |
448 | */ | |
b8f6f975 | 449 | if (edac_mc_add_mc(mci)) { |
956b9ba1 | 450 | edac_dbg(3, "failed edac_mc_add_mc()\n"); |
13189525 | 451 | goto fail1; |
0d88a10e AC |
452 | } |
453 | ||
456a2f95 DJ |
454 | /* allocating generic PCI control info */ |
455 | i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); | |
456 | if (!i82875p_pci) { | |
457 | printk(KERN_WARNING | |
458 | "%s(): Unable to create PCI control\n", | |
459 | __func__); | |
460 | printk(KERN_WARNING | |
461 | "%s(): PCI error report via EDAC not setup\n", | |
462 | __func__); | |
463 | } | |
464 | ||
0d88a10e | 465 | /* get this far and it's successful */ |
956b9ba1 | 466 | edac_dbg(3, "success\n"); |
0d88a10e AC |
467 | return 0; |
468 | ||
052dfb45 | 469 | fail1: |
637beb69 | 470 | edac_mc_free(mci); |
0d88a10e | 471 | |
052dfb45 | 472 | fail0: |
637beb69 | 473 | iounmap(ovrfl_window); |
637beb69 | 474 | pci_release_regions(ovrfl_pdev); |
0d88a10e | 475 | |
637beb69 | 476 | pci_disable_device(ovrfl_pdev); |
0d88a10e AC |
477 | /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */ |
478 | return rc; | |
479 | } | |
480 | ||
0d88a10e | 481 | /* returns count (>= 0), or negative on error */ |
9b3c6e85 GKH |
482 | static int i82875p_init_one(struct pci_dev *pdev, |
483 | const struct pci_device_id *ent) | |
0d88a10e AC |
484 | { |
485 | int rc; | |
486 | ||
956b9ba1 | 487 | edac_dbg(0, "\n"); |
537fba28 | 488 | i82875p_printk(KERN_INFO, "i82875p init one\n"); |
e7ecd891 DP |
489 | |
490 | if (pci_enable_device(pdev) < 0) | |
0d88a10e | 491 | return -EIO; |
e7ecd891 | 492 | |
0d88a10e | 493 | rc = i82875p_probe1(pdev, ent->driver_data); |
e7ecd891 | 494 | |
0d88a10e AC |
495 | if (mci_pdev == NULL) |
496 | mci_pdev = pci_dev_get(pdev); | |
e7ecd891 | 497 | |
0d88a10e AC |
498 | return rc; |
499 | } | |
500 | ||
9b3c6e85 | 501 | static void i82875p_remove_one(struct pci_dev *pdev) |
0d88a10e AC |
502 | { |
503 | struct mem_ctl_info *mci; | |
504 | struct i82875p_pvt *pvt = NULL; | |
505 | ||
956b9ba1 | 506 | edac_dbg(0, "\n"); |
0d88a10e | 507 | |
456a2f95 DJ |
508 | if (i82875p_pci) |
509 | edac_pci_release_generic_ctl(i82875p_pci); | |
510 | ||
37f04581 | 511 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
0d88a10e AC |
512 | return; |
513 | ||
466b71d5 | 514 | pvt = (struct i82875p_pvt *)mci->pvt_info; |
e7ecd891 | 515 | |
0d88a10e AC |
516 | if (pvt->ovrfl_window) |
517 | iounmap(pvt->ovrfl_window); | |
518 | ||
519 | if (pvt->ovrfl_pdev) { | |
520 | #ifdef CORRECT_BIOS | |
521 | pci_release_regions(pvt->ovrfl_pdev); | |
522 | #endif /*CORRECT_BIOS */ | |
523 | pci_disable_device(pvt->ovrfl_pdev); | |
524 | pci_dev_put(pvt->ovrfl_pdev); | |
525 | } | |
526 | ||
0d88a10e AC |
527 | edac_mc_free(mci); |
528 | } | |
529 | ||
36c46f31 | 530 | static DEFINE_PCI_DEVICE_TABLE(i82875p_pci_tbl) = { |
e7ecd891 | 531 | { |
466b71d5 DJ |
532 | PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
533 | I82875P}, | |
e7ecd891 | 534 | { |
466b71d5 DJ |
535 | 0, |
536 | } /* 0 terminated list. */ | |
0d88a10e AC |
537 | }; |
538 | ||
539 | MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl); | |
540 | ||
0d88a10e | 541 | static struct pci_driver i82875p_driver = { |
680cbbbb | 542 | .name = EDAC_MOD_STR, |
0d88a10e | 543 | .probe = i82875p_init_one, |
9b3c6e85 | 544 | .remove = i82875p_remove_one, |
0d88a10e AC |
545 | .id_table = i82875p_pci_tbl, |
546 | }; | |
547 | ||
da9bb1d2 | 548 | static int __init i82875p_init(void) |
0d88a10e AC |
549 | { |
550 | int pci_rc; | |
551 | ||
956b9ba1 | 552 | edac_dbg(3, "\n"); |
c3c52bce HM |
553 | |
554 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | |
555 | opstate_init(); | |
556 | ||
0d88a10e | 557 | pci_rc = pci_register_driver(&i82875p_driver); |
e7ecd891 | 558 | |
0d88a10e | 559 | if (pci_rc < 0) |
637beb69 | 560 | goto fail0; |
e7ecd891 | 561 | |
0d88a10e | 562 | if (mci_pdev == NULL) { |
e7ecd891 | 563 | mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
052dfb45 | 564 | PCI_DEVICE_ID_INTEL_82875_0, NULL); |
e7ecd891 | 565 | |
0d88a10e | 566 | if (!mci_pdev) { |
956b9ba1 | 567 | edac_dbg(0, "875p pci_get_device fail\n"); |
637beb69 DP |
568 | pci_rc = -ENODEV; |
569 | goto fail1; | |
0d88a10e | 570 | } |
e7ecd891 | 571 | |
0d88a10e | 572 | pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl); |
e7ecd891 | 573 | |
0d88a10e | 574 | if (pci_rc < 0) { |
956b9ba1 | 575 | edac_dbg(0, "875p init fail\n"); |
637beb69 DP |
576 | pci_rc = -ENODEV; |
577 | goto fail1; | |
0d88a10e AC |
578 | } |
579 | } | |
e7ecd891 | 580 | |
0d88a10e | 581 | return 0; |
637beb69 | 582 | |
052dfb45 | 583 | fail1: |
637beb69 DP |
584 | pci_unregister_driver(&i82875p_driver); |
585 | ||
052dfb45 | 586 | fail0: |
637beb69 DP |
587 | if (mci_pdev != NULL) |
588 | pci_dev_put(mci_pdev); | |
589 | ||
590 | return pci_rc; | |
0d88a10e AC |
591 | } |
592 | ||
0d88a10e AC |
593 | static void __exit i82875p_exit(void) |
594 | { | |
956b9ba1 | 595 | edac_dbg(3, "\n"); |
0d88a10e | 596 | |
09a81269 JL |
597 | i82875p_remove_one(mci_pdev); |
598 | pci_dev_put(mci_pdev); | |
599 | ||
0d88a10e | 600 | pci_unregister_driver(&i82875p_driver); |
e7ecd891 | 601 | |
0d88a10e AC |
602 | } |
603 | ||
0d88a10e AC |
604 | module_init(i82875p_init); |
605 | module_exit(i82875p_exit); | |
606 | ||
0d88a10e AC |
607 | MODULE_LICENSE("GPL"); |
608 | MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh"); | |
609 | MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers"); | |
c3c52bce HM |
610 | |
611 | module_param(edac_op_state, int, 0444); | |
612 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |