[deliverable/linux.git] / drivers / edac / i82875p_edac.c

/*
 * Intel D82875P Memory Controller kernel module
 * (C) 2003 Linux Networx (http://lnxi.com)
 * This file may be distributed under the terms of the
 * GNU General Public License.
 *
 * Written by Thayne Harbaugh
 * Contributors:
 *	Wang Zhenyu at intel.com
 *
 * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
 *
 * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/edac.h>
#include "edac_core.h"

#define I82875P_REVISION	" Ver: 2.0.2 " __DATE__
#define EDAC_MOD_STR		"i82875p_edac"

#define i82875p_printk(level, fmt, arg...) \
	edac_printk(level, "i82875p", fmt, ##arg)

#define i82875p_mc_printk(mci, level, fmt, arg...) \
	edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)

#ifndef PCI_DEVICE_ID_INTEL_82875_0
#define PCI_DEVICE_ID_INTEL_82875_0	0x2578
#endif				/* PCI_DEVICE_ID_INTEL_82875_0 */

#ifndef PCI_DEVICE_ID_INTEL_82875_6
#define PCI_DEVICE_ID_INTEL_82875_6	0x257e
#endif				/* PCI_DEVICE_ID_INTEL_82875_6 */

/* four csrows in dual channel, eight in single channel */
#define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))

/* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
#define I82875P_EAP		0x58	/* Error Address Pointer (32b)
					 *
					 * 31:12 block address
					 * 11:0  reserved
					 */

#define I82875P_DERRSYN		0x5c	/* DRAM Error Syndrome (8b)
					 *
					 *  7:0  DRAM ECC Syndrome
					 */

#define I82875P_DES		0x5d	/* DRAM Error Status (8b)
					 *
					 *  7:1  reserved
					 *  0    Error channel 0/1
					 */

#define I82875P_ERRSTS		0xc8	/* Error Status Register (16b)
					 *
					 * 15:10 reserved
					 *  9    non-DRAM lock error (ndlock)
					 *  8    Sftwr Generated SMI
					 *  7    ECC UE
					 *  6    reserved
					 *  5    MCH detects unimplemented cycle
					 *  4    AGP access outside GA
					 *  3    Invalid AGP access
					 *  2    Invalid GA translation table
					 *  1    Unsupported AGP command
					 *  0    ECC CE
					 */

#define I82875P_ERRCMD		0xca	/* Error Command (16b)
					 *
					 * 15:10 reserved
					 *  9    SERR on non-DRAM lock
					 *  8    SERR on ECC UE
					 *  7    SERR on ECC CE
					 *  6    target abort on high exception
					 *  5    detect unimplemented cyc
					 *  4    AGP access outside of GA
					 *  3    SERR on invalid AGP access
					 *  2    invalid translation table
					 *  1    SERR on unsupported AGP command
					 *  0    reserved
					 */

/* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
#define I82875P_PCICMD6		0x04	/* PCI Command Register (16b)
					 *
					 * 15:10 reserved
					 *  9    fast back-to-back - ro 0
					 *  8    SERR enable - ro 0
					 *  7    addr/data stepping - ro 0
					 *  6    parity err enable - ro 0
					 *  5    VGA palette snoop - ro 0
					 *  4    mem wr & invalidate - ro 0
					 *  3    special cycle - ro 0
					 *  2    bus master - ro 0
					 *  1    mem access dev6 - 0(dis),1(en)
					 *  0    IO access dev3 - 0(dis),1(en)
					 */

#define I82875P_BAR6		0x10	/* Mem Delays Base ADDR Reg (32b)
					 *
					 * 31:12 mem base addr [31:12]
					 * 11:4  address mask - ro 0
					 *  3    prefetchable - ro 0(non),1(pre)
					 *  2:1  mem type - ro 0
					 *  0    mem space - ro 0
					 */

/* Intel 82875p MMIO register space - device 0 function 0 - MMR space */

#define I82875P_DRB_SHIFT 26	/* 64MiB grain */
#define I82875P_DRB		0x00	/* DRAM Row Boundary (8b x 8)
					 *
					 *  7    reserved
					 *  6:0  64MiB row boundary addr
					 */

#define I82875P_DRA		0x10	/* DRAM Row Attribute (4b x 8)
					 *
					 *  7    reserved
					 *  6:4  row attr row 1
					 *  3    reserved
					 *  2:0  row attr row 0
					 *
					 * 000 =  4KiB
					 * 001 =  8KiB
					 * 010 = 16KiB
					 * 011 = 32KiB
					 */

#define I82875P_DRC		0x68	/* DRAM Controller Mode (32b)
					 *
					 * 31:30 reserved
					 * 29    init complete
					 * 28:23 reserved
					 * 22:21 nr chan 00=1,01=2
					 * 20    reserved
					 * 19:18 Data Integ Mode 00=none,01=ecc
					 * 17:11 reserved
					 * 10:8  refresh mode
					 *  7    reserved
					 *  6:4  mode select
					 *  3:2  reserved
					 *  1:0  DRAM type 01=DDR
					 */

enum i82875p_chips {
	I82875P = 0,
};

struct i82875p_pvt {
	struct pci_dev *ovrfl_pdev;
	void __iomem *ovrfl_window;
};

struct i82875p_dev_info {
	const char *ctl_name;
};

struct i82875p_error_info {
	u16 errsts;
	u32 eap;
	u8 des;
	u8 derrsyn;
	u16 errsts2;
};

static const struct i82875p_dev_info i82875p_devs[] = {
	[I82875P] = {
		.ctl_name = "i82875p"},
};

static struct pci_dev *mci_pdev;	/* init dev: in case that AGP code has
					 * already registered driver
					 */

static struct edac_pci_ctl_info *i82875p_pci;

static void i82875p_get_error_info(struct mem_ctl_info *mci,
				struct i82875p_error_info *info)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->dev);

	/*
	 * This is a mess because there is no atomic way to read all the
	 * registers at once and the registers can transition from CE being
	 * overwritten by UE.
	 */
	pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);

	if (!(info->errsts & 0x0081))
		return;

	pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
	pci_read_config_byte(pdev, I82875P_DES, &info->des);
	pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
	pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);

	/*
	 * If the error is the same then we can for both reads then
	 * the first set of reads is valid.  If there is a change then
	 * there is a CE no info and the second set of reads is valid
	 * and should be UE info.
	 */
	if ((info->errsts ^ info->errsts2) & 0x0081) {
		pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
		pci_read_config_byte(pdev, I82875P_DES, &info->des);
		pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
	}

	pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
}

static int i82875p_process_error_info(struct mem_ctl_info *mci,
				struct i82875p_error_info *info,
				int handle_errors)
{
	int row, multi_chan;

	multi_chan = mci->csrows[0].nr_channels - 1;

	if (!(info->errsts & 0x0081))
		return 0;

	if (!handle_errors)
		return 1;

	if ((info->errsts ^ info->errsts2) & 0x0081) {
		edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
		info->errsts = info->errsts2;
	}

	info->eap >>= PAGE_SHIFT;
	row = edac_mc_find_csrow_by_page(mci, info->eap);

	if (info->errsts & 0x0080)
		edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
	else
		edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
				multi_chan ? (info->des & 0x1) : 0,
				"i82875p CE");

	return 1;
}

static void i82875p_check(struct mem_ctl_info *mci)
{
	struct i82875p_error_info info;

	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
	i82875p_get_error_info(mci, &info);
	i82875p_process_error_info(mci, &info, 1);
}

/* Return 0 on success or 1 on failure. */
static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
				struct pci_dev **ovrfl_pdev,
				void __iomem **ovrfl_window)
{
	struct pci_dev *dev;
	void __iomem *window;
	int err;

	*ovrfl_pdev = NULL;
	*ovrfl_window = NULL;
	dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);

	if (dev == NULL) {
		/* Intel tells BIOS developers to hide device 6 which
		 * configures the overflow device access containing
		 * the DRBs - this is where we expose device 6.
		 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
		 */
		pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
		dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));

		if (dev == NULL)
			return 1;

		err = pci_bus_add_device(dev);
		if (err) {
			i82875p_printk(KERN_ERR,
				"%s(): pci_bus_add_device() Failed\n",
				__func__);
		}
		pci_bus_assign_resources(dev->bus);
	}

	*ovrfl_pdev = dev;

	if (pci_enable_device(dev)) {
		i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
			"device\n", __func__);
		return 1;
	}

	if (pci_request_regions(dev, pci_name(dev))) {
#ifdef CORRECT_BIOS
		goto fail0;
#endif
	}

	/* cache is irrelevant for PCI bus reads/writes */
	window = pci_ioremap_bar(dev, 0);
	if (window == NULL) {
		i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
			__func__);
		goto fail1;
	}

	*ovrfl_window = window;
	return 0;

fail1:
	pci_release_regions(dev);

#ifdef CORRECT_BIOS
fail0:
	pci_disable_device(dev);
#endif
	/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
	return 1;
}

/* Return 1 if dual channel mode is active.  Else return 0. */
static inline int dual_channel_active(u32 drc)
{
	return (drc >> 21) & 0x1;
}

static void i82875p_init_csrows(struct mem_ctl_info *mci,
				struct pci_dev *pdev,
				void __iomem * ovrfl_window, u32 drc)
{
	struct csrow_info *csrow;
	unsigned long last_cumul_size;
	u8 value;
	u32 drc_ddim;		/* DRAM Data Integrity Mode 0=none,2=edac */
	u32 cumul_size;
	int index;

	drc_ddim = (drc >> 18) & 0x1;
	last_cumul_size = 0;

	/* The dram row boundary (DRB) reg values are boundary address
	 * for each DRAM row with a granularity of 32 or 64MB (single/dual
	 * channel operation).  DRB regs are cumulative; therefore DRB7 will
	 * contain the total memory contained in all eight rows.
	 */

	for (index = 0; index < mci->nr_csrows; index++) {
		csrow = &mci->csrows[index];

		value = readb(ovrfl_window + I82875P_DRB + index);
		cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
		debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
			cumul_size);
		if (cumul_size == last_cumul_size)
			continue;	/* not populated */

		csrow->first_page = last_cumul_size;
		csrow->last_page = cumul_size - 1;
		csrow->nr_pages = cumul_size - last_cumul_size;
		last_cumul_size = cumul_size;
		csrow->grain = 1 << 12;	/* I82875P_EAP has 4KiB reolution */
		csrow->mtype = MEM_DDR;
		csrow->dtype = DEV_UNKNOWN;
		csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
	}
}

static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
{
	int rc = -ENODEV;
	struct mem_ctl_info *mci;
	struct i82875p_pvt *pvt;
	struct pci_dev *ovrfl_pdev;
	void __iomem *ovrfl_window;
	u32 drc;
	u32 nr_chans;
	struct i82875p_error_info discard;

	debugf0("%s()\n", __func__);

	ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);

	if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
		return -ENODEV;
	drc = readl(ovrfl_window + I82875P_DRC);
	nr_chans = dual_channel_active(drc) + 1;
	mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
			nr_chans, 0);

	if (!mci) {
		rc = -ENOMEM;
		goto fail0;
	}

	/* Keeps mci available after edac_mc_del_mc() till edac_mc_free() */
	kobject_get(&mci->edac_mci_kobj);

	debugf3("%s(): init mci\n", __func__);
	mci->dev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_DDR;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
	mci->edac_cap = EDAC_FLAG_UNKNOWN;
	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = I82875P_REVISION;
	mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
	mci->dev_name = pci_name(pdev);
	mci->edac_check = i82875p_check;
	mci->ctl_page_to_phys = NULL;
	debugf3("%s(): init pvt\n", __func__);
	pvt = (struct i82875p_pvt *)mci->pvt_info;
	pvt->ovrfl_pdev = ovrfl_pdev;
	pvt->ovrfl_window = ovrfl_window;
	i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
	i82875p_get_error_info(mci, &discard);	/* clear counters */

	/* Here we assume that we will never see multiple instances of this
	 * type of memory controller.  The ID is therefore hardcoded to 0.
	 */
	if (edac_mc_add_mc(mci)) {
		debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
		goto fail1;
	}

	/* allocating generic PCI control info */
	i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	if (!i82875p_pci) {
		printk(KERN_WARNING
			"%s(): Unable to create PCI control\n",
			__func__);
		printk(KERN_WARNING
			"%s(): PCI error report via EDAC not setup\n",
			__func__);
	}

	/* get this far and it's successful */
	debugf3("%s(): success\n", __func__);
	return 0;

fail1:
	kobject_put(&mci->edac_mci_kobj);
	edac_mc_free(mci);

fail0:
	iounmap(ovrfl_window);
	pci_release_regions(ovrfl_pdev);

	pci_disable_device(ovrfl_pdev);
	/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
	return rc;
}

/* returns count (>= 0), or negative on error */
static int __devinit i82875p_init_one(struct pci_dev *pdev,
				const struct pci_device_id *ent)
{
	int rc;

	debugf0("%s()\n", __func__);
	i82875p_printk(KERN_INFO, "i82875p init one\n");

	if (pci_enable_device(pdev) < 0)
		return -EIO;

	rc = i82875p_probe1(pdev, ent->driver_data);

	if (mci_pdev == NULL)
		mci_pdev = pci_dev_get(pdev);

	return rc;
}

static void __devexit i82875p_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;
	struct i82875p_pvt *pvt = NULL;

	debugf0("%s()\n", __func__);

	if (i82875p_pci)
		edac_pci_release_generic_ctl(i82875p_pci);

	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
		return;

	pvt = (struct i82875p_pvt *)mci->pvt_info;

	if (pvt->ovrfl_window)
		iounmap(pvt->ovrfl_window);

	if (pvt->ovrfl_pdev) {
#ifdef CORRECT_BIOS
		pci_release_regions(pvt->ovrfl_pdev);
#endif				/*CORRECT_BIOS */
		pci_disable_device(pvt->ovrfl_pdev);
		pci_dev_put(pvt->ovrfl_pdev);
	}

	edac_mc_free(mci);
}

static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
	{
	 PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 I82875P},
	{
	 0,
	 }			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);

static struct pci_driver i82875p_driver = {
	.name = EDAC_MOD_STR,
	.probe = i82875p_init_one,
	.remove = __devexit_p(i82875p_remove_one),
	.id_table = i82875p_pci_tbl,
};

static int __init i82875p_init(void)
{
	int pci_rc;

	debugf3("%s()\n", __func__);

       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
       opstate_init();

	pci_rc = pci_register_driver(&i82875p_driver);

	if (pci_rc < 0)
		goto fail0;

	if (mci_pdev == NULL) {
		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
					PCI_DEVICE_ID_INTEL_82875_0, NULL);

		if (!mci_pdev) {
			debugf0("875p pci_get_device fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}

		pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);

		if (pci_rc < 0) {
			debugf0("875p init fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}
	}

	return 0;

fail1:
	pci_unregister_driver(&i82875p_driver);

fail0:
	if (mci_pdev != NULL)
		pci_dev_put(mci_pdev);

	return pci_rc;
}

static void __exit i82875p_exit(void)
{
	debugf3("%s()\n", __func__);

	i82875p_remove_one(mci_pdev);
	pci_dev_put(mci_pdev);

	pci_unregister_driver(&i82875p_driver);

}

module_init(i82875p_init);
module_exit(i82875p_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
0d88a10e AC	1	/*
	2	* Intel D82875P Memory Controller kernel module
	3	* (C) 2003 Linux Networx (http://lnxi.com)
	4	* This file may be distributed under the terms of the
	5	* GNU General Public License.
	6	*
	7	* Written by Thayne Harbaugh
	8	* Contributors:
	9	* Wang Zhenyu at intel.com
	10	*
	11	* $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
	12	*
	13	* Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
	14	*/
	15
0d88a10e AC	16	#include <linux/module.h>
0d88a10e AC	17	#include <linux/init.h>
0d88a10e AC	18	#include <linux/pci.h>
0d88a10e AC	19	#include <linux/pci_ids.h>
0d88a10e	20	#include <linux/slab.h>
c3c52bce	21	#include <linux/edac.h>
20bcb7a8	22	#include "edac_core.h"
0d88a10e	23
20bcb7a8	24	#define I82875P_REVISION " Ver: 2.0.2 " __DATE__
929a40ec	25	#define EDAC_MOD_STR "i82875p_edac"
37f04581	26
537fba28	27	#define i82875p_printk(level, fmt, arg...) \
e7ecd891	28	edac_printk(level, "i82875p", fmt, ##arg)
537fba28 DP	29
537fba28 DP	30	#define i82875p_mc_printk(mci, level, fmt, arg...) \
e7ecd891	31	edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
537fba28	32
0d88a10e AC	33	#ifndef PCI_DEVICE_ID_INTEL_82875_0
	34	#define PCI_DEVICE_ID_INTEL_82875_0 0x2578
	35	#endif /* PCI_DEVICE_ID_INTEL_82875_0 */
	36
	37	#ifndef PCI_DEVICE_ID_INTEL_82875_6
	38	#define PCI_DEVICE_ID_INTEL_82875_6 0x257e
	39	#endif /* PCI_DEVICE_ID_INTEL_82875_6 */
	40
0d88a10e AC	41	/* four csrows in dual channel, eight in single channel */
	42	#define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
	43
0d88a10e AC	44	/* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
	45	#define I82875P_EAP 0x58 /* Error Address Pointer (32b)
	46	*
	47	* 31:12 block address
	48	* 11:0 reserved
	49	*/
	50
	51	#define I82875P_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
	52	*
	53	* 7:0 DRAM ECC Syndrome
	54	*/
	55
	56	#define I82875P_DES 0x5d /* DRAM Error Status (8b)
	57	*
	58	* 7:1 reserved
	59	* 0 Error channel 0/1
	60	*/
	61
	62	#define I82875P_ERRSTS 0xc8 /* Error Status Register (16b)
	63	*
	64	* 15:10 reserved
	65	* 9 non-DRAM lock error (ndlock)
	66	* 8 Sftwr Generated SMI
	67	* 7 ECC UE
	68	* 6 reserved
	69	* 5 MCH detects unimplemented cycle
	70	* 4 AGP access outside GA
	71	* 3 Invalid AGP access
	72	* 2 Invalid GA translation table
	73	* 1 Unsupported AGP command
	74	* 0 ECC CE
	75	*/
	76
	77	#define I82875P_ERRCMD 0xca /* Error Command (16b)
	78	*
	79	* 15:10 reserved
	80	* 9 SERR on non-DRAM lock
	81	* 8 SERR on ECC UE
	82	* 7 SERR on ECC CE
	83	* 6 target abort on high exception
	84	* 5 detect unimplemented cyc
	85	* 4 AGP access outside of GA
	86	* 3 SERR on invalid AGP access
	87	* 2 invalid translation table
	88	* 1 SERR on unsupported AGP command
	89	* 0 reserved
	90	*/
	91
0d88a10e AC	92	/* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
	93	#define I82875P_PCICMD6 0x04 /* PCI Command Register (16b)
	94	*
	95	* 15:10 reserved
	96	* 9 fast back-to-back - ro 0
	97	* 8 SERR enable - ro 0
	98	* 7 addr/data stepping - ro 0
	99	* 6 parity err enable - ro 0
	100	* 5 VGA palette snoop - ro 0
	101	* 4 mem wr & invalidate - ro 0
	102	* 3 special cycle - ro 0
	103	* 2 bus master - ro 0
	104	* 1 mem access dev6 - 0(dis),1(en)
	105	* 0 IO access dev3 - 0(dis),1(en)
	106	*/
	107
	108	#define I82875P_BAR6 0x10 /* Mem Delays Base ADDR Reg (32b)
	109	*
	110	* 31:12 mem base addr [31:12]
	111	* 11:4 address mask - ro 0
	112	* 3 prefetchable - ro 0(non),1(pre)
	113	* 2:1 mem type - ro 0
	114	* 0 mem space - ro 0
	115	*/
	116
	117	/* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
	118
	119	#define I82875P_DRB_SHIFT 26 /* 64MiB grain */
	120	#define I82875P_DRB 0x00 /* DRAM Row Boundary (8b x 8)
	121	*
	122	* 7 reserved
	123	* 6:0 64MiB row boundary addr
	124	*/
	125
	126	#define I82875P_DRA 0x10 /* DRAM Row Attribute (4b x 8)
	127	*
	128	* 7 reserved
	129	* 6:4 row attr row 1
	130	* 3 reserved
	131	* 2:0 row attr row 0
	132	*
	133	* 000 = 4KiB
	134	* 001 = 8KiB
	135	* 010 = 16KiB
	136	* 011 = 32KiB
	137	*/
	138
	139	#define I82875P_DRC 0x68 /* DRAM Controller Mode (32b)
	140	*
	141	* 31:30 reserved
	142	* 29 init complete
	143	* 28:23 reserved
	144	* 22:21 nr chan 00=1,01=2
	145	* 20 reserved
	146	* 19:18 Data Integ Mode 00=none,01=ecc
	147	* 17:11 reserved
	148	* 10:8 refresh mode
	149	* 7 reserved
	150	* 6:4 mode select
	151	* 3:2 reserved
	152	* 1:0 DRAM type 01=DDR
	153	*/
	154
0d88a10e AC	155	enum i82875p_chips {
	156	I82875P = 0,
	157	};
	158
0d88a10e AC	159	struct i82875p_pvt {
0d88a10e AC	160	struct pci_dev *ovrfl_pdev;
6d57348d	161	void __iomem *ovrfl_window;
0d88a10e AC	162	};
0d88a10e AC	163
0d88a10e AC	164	struct i82875p_dev_info {
	165	const char *ctl_name;
	166	};
	167
0d88a10e AC	168	struct i82875p_error_info {
	169	u16 errsts;
	170	u32 eap;
	171	u8 des;
	172	u8 derrsyn;
	173	u16 errsts2;
	174	};
	175
0d88a10e AC	176	static const struct i82875p_dev_info i82875p_devs[] = {
0d88a10e AC	177	[I82875P] = {
052dfb45	178	.ctl_name = "i82875p"},
0d88a10e AC	179	};
0d88a10e AC	180
f044091c	181	static struct pci_dev mci_pdev; / init dev: in case that AGP code has
e7ecd891 DP	182	* already registered driver
	183	*/
	184
456a2f95 DJ	185	static struct edac_pci_ctl_info *i82875p_pci;
456a2f95 DJ	186
e7ecd891	187	static void i82875p_get_error_info(struct mem_ctl_info *mci,
052dfb45	188	struct i82875p_error_info *info)
0d88a10e	189	{
37f04581 DT	190	struct pci_dev *pdev;
	191
	192	pdev = to_pci_dev(mci->dev);
	193
0d88a10e AC	194	/*
	195	* This is a mess because there is no atomic way to read all the
	196	* registers at once and the registers can transition from CE being
	197	* overwritten by UE.
	198	*/
37f04581	199	pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
654ede20 JU	200
	201	if (!(info->errsts & 0x0081))
	202	return;
	203
37f04581 DT	204	pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
	205	pci_read_config_byte(pdev, I82875P_DES, &info->des);
	206	pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
	207	pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
0d88a10e	208
0d88a10e AC	209	/*
	210	* If the error is the same then we can for both reads then
	211	* the first set of reads is valid. If there is a change then
	212	* there is a CE no info and the second set of reads is valid
	213	* and should be UE info.
	214	*/
0d88a10e	215	if ((info->errsts ^ info->errsts2) & 0x0081) {
37f04581 DT	216	pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
37f04581 DT	217	pci_read_config_byte(pdev, I82875P_DES, &info->des);
466b71d5	218	pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
0d88a10e	219	}
654ede20 JU	220
654ede20 JU	221	pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
0d88a10e AC	222	}
0d88a10e AC	223
e7ecd891	224	static int i82875p_process_error_info(struct mem_ctl_info *mci,
052dfb45 DT	225	struct i82875p_error_info *info,
052dfb45 DT	226	int handle_errors)
0d88a10e AC	227	{
	228	int row, multi_chan;
	229
	230	multi_chan = mci->csrows[0].nr_channels - 1;
	231
654ede20	232	if (!(info->errsts & 0x0081))
0d88a10e AC	233	return 0;
	234
	235	if (!handle_errors)
	236	return 1;
	237
	238	if ((info->errsts ^ info->errsts2) & 0x0081) {
	239	edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
	240	info->errsts = info->errsts2;
	241	}
	242
	243	info->eap >>= PAGE_SHIFT;
	244	row = edac_mc_find_csrow_by_page(mci, info->eap);
	245
	246	if (info->errsts & 0x0080)
	247	edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
	248	else
	249	edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
052dfb45 DT	250	multi_chan ? (info->des & 0x1) : 0,
052dfb45 DT	251	"i82875p CE");
0d88a10e AC	252
	253	return 1;
	254	}
	255
0d88a10e AC	256	static void i82875p_check(struct mem_ctl_info *mci)
	257	{
	258	struct i82875p_error_info info;
	259
537fba28	260	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
0d88a10e AC	261	i82875p_get_error_info(mci, &info);
	262	i82875p_process_error_info(mci, &info, 1);
	263	}
	264
13189525 DT	265	/* Return 0 on success or 1 on failure. */
13189525 DT	266	static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
052dfb45 DT	267	struct pci_dev **ovrfl_pdev,
052dfb45 DT	268	void __iomem **ovrfl_window)
0d88a10e	269	{
13189525 DT	270	struct pci_dev *dev;
13189525 DT	271	void __iomem *window;
1c52152b	272	int err;
0d88a10e	273
13189525 DT	274	*ovrfl_pdev = NULL;
	275	*ovrfl_window = NULL;
	276	dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
0d88a10e	277
13189525 DT	278	if (dev == NULL) {
13189525 DT	279	/* Intel tells BIOS developers to hide device 6 which
0d88a10e AC	280	* configures the overflow device access containing
	281	* the DRBs - this is where we expose device 6.
	282	* http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
	283	*/
	284	pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
13189525	285	dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
e7ecd891	286
13189525 DT	287	if (dev == NULL)
13189525 DT	288	return 1;
62456726	289
1c52152b DT	290	err = pci_bus_add_device(dev);
	291	if (err) {
	292	i82875p_printk(KERN_ERR,
	293	"%s(): pci_bus_add_device() Failed\n",
	294	__func__);
	295	}
307d1144	296	pci_bus_assign_resources(dev->bus);
0d88a10e	297	}
e7ecd891	298
13189525 DT	299	*ovrfl_pdev = dev;
13189525 DT	300
13189525 DT	301	if (pci_enable_device(dev)) {
13189525 DT	302	i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
052dfb45	303	"device\n", __func__);
13189525	304	return 1;
0d88a10e AC	305	}
0d88a10e AC	306
13189525	307	if (pci_request_regions(dev, pci_name(dev))) {
0d88a10e	308	#ifdef CORRECT_BIOS
637beb69	309	goto fail0;
0d88a10e AC	310	#endif
0d88a10e AC	311	}
e7ecd891	312
0d88a10e	313	/* cache is irrelevant for PCI bus reads/writes */
1dca00bd	314	window = pci_ioremap_bar(dev, 0);
13189525	315	if (window == NULL) {
537fba28	316	i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
052dfb45	317	__func__);
637beb69	318	goto fail1;
0d88a10e AC	319	}
0d88a10e AC	320
13189525 DT	321	*ovrfl_window = window;
13189525 DT	322	return 0;
0d88a10e	323
052dfb45	324	fail1:
13189525	325	pci_release_regions(dev);
0d88a10e	326
13189525	327	#ifdef CORRECT_BIOS
052dfb45	328	fail0:
13189525 DT	329	pci_disable_device(dev);
	330	#endif
	331	/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
	332	return 1;
	333	}
0d88a10e	334
13189525 DT	335	/* Return 1 if dual channel mode is active. Else return 0. */
	336	static inline int dual_channel_active(u32 drc)
	337	{
	338	return (drc >> 21) & 0x1;
	339	}
0d88a10e	340
13189525	341	static void i82875p_init_csrows(struct mem_ctl_info *mci,
466b71d5 DJ	342	struct pci_dev *pdev,
466b71d5 DJ	343	void __iomem * ovrfl_window, u32 drc)
13189525 DT	344	{
	345	struct csrow_info *csrow;
	346	unsigned long last_cumul_size;
	347	u8 value;
466b71d5	348	u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
13189525 DT	349	u32 cumul_size;
	350	int index;
	351
	352	drc_ddim = (drc >> 18) & 0x1;
	353	last_cumul_size = 0;
	354
	355	/* The dram row boundary (DRB) reg values are boundary address
0d88a10e AC	356	* for each DRAM row with a granularity of 32 or 64MB (single/dual
	357	* channel operation). DRB regs are cumulative; therefore DRB7 will
	358	* contain the total memory contained in all eight rows.
	359	*/
13189525 DT	360
	361	for (index = 0; index < mci->nr_csrows; index++) {
	362	csrow = &mci->csrows[index];
0d88a10e AC	363
	364	value = readb(ovrfl_window + I82875P_DRB + index);
	365	cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
537fba28 DP	366	debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
537fba28 DP	367	cumul_size);
0d88a10e AC	368	if (cumul_size == last_cumul_size)
	369	continue; /* not populated */
	370
	371	csrow->first_page = last_cumul_size;
	372	csrow->last_page = cumul_size - 1;
	373	csrow->nr_pages = cumul_size - last_cumul_size;
	374	last_cumul_size = cumul_size;
13189525	375	csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
0d88a10e AC	376	csrow->mtype = MEM_DDR;
	377	csrow->dtype = DEV_UNKNOWN;
	378	csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
	379	}
13189525 DT	380	}
	381
	382	static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
	383	{
	384	int rc = -ENODEV;
	385	struct mem_ctl_info *mci;
	386	struct i82875p_pvt *pvt;
	387	struct pci_dev *ovrfl_pdev;
	388	void __iomem *ovrfl_window;
	389	u32 drc;
	390	u32 nr_chans;
	391	struct i82875p_error_info discard;
0d88a10e	392
13189525	393	debugf0("%s()\n", __func__);
c3c52bce	394
13189525 DT	395	ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
	396
	397	if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
	398	return -ENODEV;
	399	drc = readl(ovrfl_window + I82875P_DRC);
	400	nr_chans = dual_channel_active(drc) + 1;
	401	mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
b8f6f975	402	nr_chans, 0);
13189525 DT	403
	404	if (!mci) {
	405	rc = -ENOMEM;
	406	goto fail0;
	407	}
	408
09a81269 JL	409	/* Keeps mci available after edac_mc_del_mc() till edac_mc_free() */
	410	kobject_get(&mci->edac_mci_kobj);
	411
13189525 DT	412	debugf3("%s(): init mci\n", __func__);
	413	mci->dev = &pdev->dev;
	414	mci->mtype_cap = MEM_FLAG_DDR;
	415	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
	416	mci->edac_cap = EDAC_FLAG_UNKNOWN;
	417	mci->mod_name = EDAC_MOD_STR;
	418	mci->mod_ver = I82875P_REVISION;
	419	mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
c4192705	420	mci->dev_name = pci_name(pdev);
13189525 DT	421	mci->edac_check = i82875p_check;
	422	mci->ctl_page_to_phys = NULL;
	423	debugf3("%s(): init pvt\n", __func__);
466b71d5	424	pvt = (struct i82875p_pvt *)mci->pvt_info;
13189525 DT	425	pvt->ovrfl_pdev = ovrfl_pdev;
	426	pvt->ovrfl_window = ovrfl_window;
	427	i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
466b71d5	428	i82875p_get_error_info(mci, &discard); /* clear counters */
0d88a10e	429
2d7bbb91 DT	430	/* Here we assume that we will never see multiple instances of this
	431	* type of memory controller. The ID is therefore hardcoded to 0.
	432	*/
b8f6f975	433	if (edac_mc_add_mc(mci)) {
537fba28	434	debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
13189525	435	goto fail1;
0d88a10e AC	436	}
0d88a10e AC	437
456a2f95 DJ	438	/* allocating generic PCI control info */
	439	i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	440	if (!i82875p_pci) {
	441	printk(KERN_WARNING
	442	"%s(): Unable to create PCI control\n",
	443	__func__);
	444	printk(KERN_WARNING
	445	"%s(): PCI error report via EDAC not setup\n",
	446	__func__);
	447	}
	448
0d88a10e	449	/* get this far and it's successful */
537fba28	450	debugf3("%s(): success\n", __func__);
0d88a10e AC	451	return 0;
0d88a10e AC	452
052dfb45	453	fail1:
09a81269	454	kobject_put(&mci->edac_mci_kobj);
637beb69	455	edac_mc_free(mci);
0d88a10e	456
052dfb45	457	fail0:
637beb69	458	iounmap(ovrfl_window);
637beb69	459	pci_release_regions(ovrfl_pdev);
0d88a10e	460
637beb69	461	pci_disable_device(ovrfl_pdev);
0d88a10e AC	462	/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
	463	return rc;
	464	}
	465
0d88a10e AC	466	/* returns count (>= 0), or negative on error */
0d88a10e AC	467	static int __devinit i82875p_init_one(struct pci_dev *pdev,
052dfb45	468	const struct pci_device_id *ent)
0d88a10e AC	469	{
	470	int rc;
	471
537fba28	472	debugf0("%s()\n", __func__);
537fba28	473	i82875p_printk(KERN_INFO, "i82875p init one\n");
e7ecd891 DP	474
e7ecd891 DP	475	if (pci_enable_device(pdev) < 0)
0d88a10e	476	return -EIO;
e7ecd891	477
0d88a10e	478	rc = i82875p_probe1(pdev, ent->driver_data);
e7ecd891	479
0d88a10e AC	480	if (mci_pdev == NULL)
0d88a10e AC	481	mci_pdev = pci_dev_get(pdev);
e7ecd891	482
0d88a10e AC	483	return rc;
	484	}
	485
0d88a10e AC	486	static void __devexit i82875p_remove_one(struct pci_dev *pdev)
	487	{
	488	struct mem_ctl_info *mci;
	489	struct i82875p_pvt *pvt = NULL;
	490
537fba28	491	debugf0("%s()\n", __func__);
0d88a10e	492
456a2f95 DJ	493	if (i82875p_pci)
	494	edac_pci_release_generic_ctl(i82875p_pci);
	495
37f04581	496	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
0d88a10e AC	497	return;
0d88a10e AC	498
466b71d5	499	pvt = (struct i82875p_pvt *)mci->pvt_info;
e7ecd891	500
0d88a10e AC	501	if (pvt->ovrfl_window)
	502	iounmap(pvt->ovrfl_window);
	503
	504	if (pvt->ovrfl_pdev) {
	505	#ifdef CORRECT_BIOS
	506	pci_release_regions(pvt->ovrfl_pdev);
	507	#endif /CORRECT_BIOS /
	508	pci_disable_device(pvt->ovrfl_pdev);
	509	pci_dev_put(pvt->ovrfl_pdev);
	510	}
	511
0d88a10e AC	512	edac_mc_free(mci);
	513	}
	514
0d88a10e	515	static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
e7ecd891	516	{
466b71d5 DJ	517	PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
466b71d5 DJ	518	I82875P},
e7ecd891	519	{
466b71d5 DJ	520	0,
466b71d5 DJ	521	} /* 0 terminated list. */
0d88a10e AC	522	};
	523
	524	MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
	525
0d88a10e	526	static struct pci_driver i82875p_driver = {
680cbbbb	527	.name = EDAC_MOD_STR,
0d88a10e AC	528	.probe = i82875p_init_one,
	529	.remove = __devexit_p(i82875p_remove_one),
	530	.id_table = i82875p_pci_tbl,
	531	};
	532
da9bb1d2	533	static int __init i82875p_init(void)
0d88a10e AC	534	{
	535	int pci_rc;
	536
537fba28	537	debugf3("%s()\n", __func__);
c3c52bce HM	538
	539	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	540	opstate_init();
	541
0d88a10e	542	pci_rc = pci_register_driver(&i82875p_driver);
e7ecd891	543
0d88a10e	544	if (pci_rc < 0)
637beb69	545	goto fail0;
e7ecd891	546
0d88a10e	547	if (mci_pdev == NULL) {
e7ecd891	548	mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45	549	PCI_DEVICE_ID_INTEL_82875_0, NULL);
e7ecd891	550
0d88a10e AC	551	if (!mci_pdev) {
0d88a10e AC	552	debugf0("875p pci_get_device fail\n");
637beb69 DP	553	pci_rc = -ENODEV;
637beb69 DP	554	goto fail1;
0d88a10e	555	}
e7ecd891	556
0d88a10e	557	pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
e7ecd891	558
0d88a10e AC	559	if (pci_rc < 0) {
0d88a10e AC	560	debugf0("875p init fail\n");
637beb69 DP	561	pci_rc = -ENODEV;
637beb69 DP	562	goto fail1;
0d88a10e AC	563	}
0d88a10e AC	564	}
e7ecd891	565
0d88a10e	566	return 0;
637beb69	567
052dfb45	568	fail1:
637beb69 DP	569	pci_unregister_driver(&i82875p_driver);
637beb69 DP	570
052dfb45	571	fail0:
637beb69 DP	572	if (mci_pdev != NULL)
	573	pci_dev_put(mci_pdev);
	574
	575	return pci_rc;
0d88a10e AC	576	}
0d88a10e AC	577
0d88a10e AC	578	static void __exit i82875p_exit(void)
0d88a10e AC	579	{
537fba28	580	debugf3("%s()\n", __func__);
0d88a10e	581
09a81269 JL	582	i82875p_remove_one(mci_pdev);
	583	pci_dev_put(mci_pdev);
	584
0d88a10e	585	pci_unregister_driver(&i82875p_driver);
e7ecd891	586
0d88a10e AC	587	}
0d88a10e AC	588
0d88a10e AC	589	module_init(i82875p_init);
	590	module_exit(i82875p_exit);
	591
0d88a10e AC	592	MODULE_LICENSE("GPL");
	593	MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
	594	MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");
c3c52bce HM	595
	596	module_param(edac_op_state, int, 0444);
	597	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");