Commit | Line | Data |
---|---|---|
b70ef010 | 1 | #include <linux/module.h> |
888ab8e6 BP |
2 | #include <linux/slab.h> |
3 | ||
47ca08a4 | 4 | #include "mce_amd.h" |
b52401ce | 5 | |
888ab8e6 BP |
6 | static struct amd_decoder_ops *fam_ops; |
7 | ||
2be64bfa | 8 | static u8 xec_mask = 0xf; |
5ce88f6e | 9 | |
549d042d | 10 | static bool report_gart_errors; |
b0b07a2b | 11 | static void (*nb_bus_decoder)(int node_id, struct mce *m); |
549d042d BP |
12 | |
13 | void amd_report_gart_errors(bool v) | |
14 | { | |
15 | report_gart_errors = v; | |
16 | } | |
17 | EXPORT_SYMBOL_GPL(amd_report_gart_errors); | |
18 | ||
b0b07a2b | 19 | void amd_register_ecc_decoder(void (*f)(int, struct mce *)) |
549d042d BP |
20 | { |
21 | nb_bus_decoder = f; | |
22 | } | |
23 | EXPORT_SYMBOL_GPL(amd_register_ecc_decoder); | |
24 | ||
b0b07a2b | 25 | void amd_unregister_ecc_decoder(void (*f)(int, struct mce *)) |
549d042d BP |
26 | { |
27 | if (nb_bus_decoder) { | |
28 | WARN_ON(nb_bus_decoder != f); | |
29 | ||
30 | nb_bus_decoder = NULL; | |
31 | } | |
32 | } | |
33 | EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder); | |
34 | ||
b52401ce DT |
35 | /* |
36 | * string representation for the different MCA reported error types, see F3x48 | |
37 | * or MSR0000_0411. | |
38 | */ | |
6337583d BP |
39 | |
40 | /* transaction type */ | |
0f08669e | 41 | static const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" }; |
b52401ce | 42 | |
6337583d | 43 | /* cache level */ |
0f08669e | 44 | static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" }; |
b52401ce | 45 | |
6337583d | 46 | /* memory transaction type */ |
0f08669e | 47 | static const char * const rrrr_msgs[] = { |
6337583d | 48 | "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP" |
b52401ce DT |
49 | }; |
50 | ||
6337583d | 51 | /* participating processor */ |
ebe2aea8 | 52 | const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" }; |
b70ef010 | 53 | EXPORT_SYMBOL_GPL(pp_msgs); |
b52401ce | 54 | |
6337583d | 55 | /* request timeout */ |
0f08669e | 56 | static const char * const to_msgs[] = { "no timeout", "timed out" }; |
b52401ce | 57 | |
6337583d | 58 | /* memory or i/o */ |
0f08669e | 59 | static const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" }; |
b52401ce | 60 | |
980eec8b | 61 | /* internal error type */ |
0f08669e | 62 | static const char * const uu_msgs[] = { "RESV", "RESV", "HWA", "RESV" }; |
980eec8b | 63 | |
f05c41a9 | 64 | static const char * const f15h_mc1_mce_desc[] = { |
86039cd4 BP |
65 | "UC during a demand linefill from L2", |
66 | "Parity error during data load from IC", | |
67 | "Parity error for IC valid bit", | |
68 | "Main tag parity error", | |
69 | "Parity error in prediction queue", | |
70 | "PFB data/address parity error", | |
71 | "Parity error in the branch status reg", | |
72 | "PFB promotion address error", | |
73 | "Tag error during probe/victimization", | |
74 | "Parity error for IC probe tag valid bit", | |
75 | "PFB non-cacheable bit parity error", | |
76 | "PFB valid bit parity error", /* xec = 0xd */ | |
6c1173a6 | 77 | "Microcode Patch Buffer", /* xec = 010 */ |
86039cd4 BP |
78 | "uop queue", |
79 | "insn buffer", | |
80 | "predecode buffer", | |
eba4bfb3 AG |
81 | "fetch address FIFO", |
82 | "dispatch uop queue" | |
86039cd4 BP |
83 | }; |
84 | ||
f05c41a9 | 85 | static const char * const f15h_mc2_mce_desc[] = { |
70fdb494 BP |
86 | "Fill ECC error on data fills", /* xec = 0x4 */ |
87 | "Fill parity error on insn fills", | |
88 | "Prefetcher request FIFO parity error", | |
89 | "PRQ address parity error", | |
90 | "PRQ data parity error", | |
91 | "WCC Tag ECC error", | |
92 | "WCC Data ECC error", | |
93 | "WCB Data parity error", | |
b64a99c1 | 94 | "VB Data ECC or parity error", |
70fdb494 BP |
95 | "L2 Tag ECC error", /* xec = 0x10 */ |
96 | "Hard L2 Tag ECC error", | |
97 | "Multiple hits on L2 tag", | |
98 | "XAB parity error", | |
99 | "PRB address parity error" | |
100 | }; | |
101 | ||
f05c41a9 | 102 | static const char * const mc4_mce_desc[] = { |
68782673 BP |
103 | "DRAM ECC error detected on the NB", |
104 | "CRC error detected on HT link", | |
105 | "Link-defined sync error packets detected on HT link", | |
106 | "HT Master abort", | |
107 | "HT Target abort", | |
108 | "Invalid GART PTE entry during GART table walk", | |
109 | "Unsupported atomic RMW received from an IO link", | |
110 | "Watchdog timeout due to lack of progress", | |
111 | "DRAM ECC error detected on the NB", | |
112 | "SVM DMA Exclusion Vector error", | |
113 | "HT data error detected on link", | |
114 | "Protocol error (link, L3, probe filter)", | |
115 | "NB internal arrays parity error", | |
116 | "DRAM addr/ctl signals parity error", | |
117 | "IO link transmission error", | |
118 | "L3 data cache ECC error", /* xec = 0x1c */ | |
119 | "L3 cache tag error", | |
120 | "L3 LRU parity bits error", | |
121 | "ECC Error in the Probe Filter directory" | |
122 | }; | |
123 | ||
f05c41a9 | 124 | static const char * const mc5_mce_desc[] = { |
8259a7e5 BP |
125 | "CPU Watchdog timer expire", |
126 | "Wakeup array dest tag", | |
127 | "AG payload array", | |
128 | "EX payload array", | |
129 | "IDRF array", | |
130 | "Retire dispatch queue", | |
131 | "Mapper checkpoint array", | |
132 | "Physical register file EX0 port", | |
133 | "Physical register file EX1 port", | |
134 | "Physical register file AG0 port", | |
135 | "Physical register file AG1 port", | |
136 | "Flag register file", | |
aad19e51 AG |
137 | "DE error occurred", |
138 | "Retire status queue" | |
8259a7e5 BP |
139 | }; |
140 | ||
bc4febe9 AG |
141 | static const char * const mc6_mce_desc[] = { |
142 | "Hardware Assertion", | |
143 | "Free List", | |
144 | "Physical Register File", | |
145 | "Retire Queue", | |
146 | "Scheduler table", | |
147 | "Status Register File", | |
148 | }; | |
149 | ||
f05c41a9 | 150 | static bool f12h_mc0_mce(u16 ec, u8 xec) |
51966241 | 151 | { |
888ab8e6 | 152 | bool ret = false; |
51966241 | 153 | |
888ab8e6 | 154 | if (MEM_ERROR(ec)) { |
62452882 | 155 | u8 ll = LL(ec); |
888ab8e6 | 156 | ret = true; |
51966241 | 157 | |
888ab8e6 BP |
158 | if (ll == LL_L2) |
159 | pr_cont("during L1 linefill from L2.\n"); | |
160 | else if (ll == LL_L1) | |
62452882 | 161 | pr_cont("Data/Tag %s error.\n", R4_MSG(ec)); |
888ab8e6 BP |
162 | else |
163 | ret = false; | |
164 | } | |
165 | return ret; | |
166 | } | |
51966241 | 167 | |
f05c41a9 | 168 | static bool f10h_mc0_mce(u16 ec, u8 xec) |
9be0bb10 | 169 | { |
62452882 | 170 | if (R4(ec) == R4_GEN && LL(ec) == LL_L1) { |
9be0bb10 BP |
171 | pr_cont("during data scrub.\n"); |
172 | return true; | |
173 | } | |
f05c41a9 | 174 | return f12h_mc0_mce(ec, xec); |
9be0bb10 BP |
175 | } |
176 | ||
f05c41a9 | 177 | static bool k8_mc0_mce(u16 ec, u8 xec) |
888ab8e6 BP |
178 | { |
179 | if (BUS_ERROR(ec)) { | |
180 | pr_cont("during system linefill.\n"); | |
181 | return true; | |
182 | } | |
51966241 | 183 | |
f05c41a9 | 184 | return f10h_mc0_mce(ec, xec); |
888ab8e6 BP |
185 | } |
186 | ||
980eec8b | 187 | static bool cat_mc0_mce(u16 ec, u8 xec) |
888ab8e6 | 188 | { |
62452882 | 189 | u8 r4 = R4(ec); |
888ab8e6 BP |
190 | bool ret = true; |
191 | ||
192 | if (MEM_ERROR(ec)) { | |
193 | ||
62452882 | 194 | if (TT(ec) != TT_DATA || LL(ec) != LL_L1) |
888ab8e6 BP |
195 | return false; |
196 | ||
197 | switch (r4) { | |
198 | case R4_DRD: | |
199 | case R4_DWR: | |
200 | pr_cont("Data/Tag parity error due to %s.\n", | |
201 | (r4 == R4_DRD ? "load/hw prf" : "store")); | |
202 | break; | |
203 | case R4_EVICT: | |
204 | pr_cont("Copyback parity error on a tag miss.\n"); | |
205 | break; | |
206 | case R4_SNOOP: | |
207 | pr_cont("Tag parity error during snoop.\n"); | |
208 | break; | |
209 | default: | |
210 | ret = false; | |
211 | } | |
212 | } else if (BUS_ERROR(ec)) { | |
213 | ||
62452882 | 214 | if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG) |
888ab8e6 BP |
215 | return false; |
216 | ||
217 | pr_cont("System read data error on a "); | |
218 | ||
219 | switch (r4) { | |
220 | case R4_RD: | |
221 | pr_cont("TLB reload.\n"); | |
222 | break; | |
223 | case R4_DWR: | |
224 | pr_cont("store.\n"); | |
225 | break; | |
226 | case R4_DRD: | |
227 | pr_cont("load.\n"); | |
228 | break; | |
229 | default: | |
230 | ret = false; | |
231 | } | |
232 | } else { | |
233 | ret = false; | |
234 | } | |
235 | ||
236 | return ret; | |
237 | } | |
238 | ||
f05c41a9 | 239 | static bool f15h_mc0_mce(u16 ec, u8 xec) |
25a4f8b0 BP |
240 | { |
241 | bool ret = true; | |
242 | ||
243 | if (MEM_ERROR(ec)) { | |
244 | ||
245 | switch (xec) { | |
246 | case 0x0: | |
247 | pr_cont("Data Array access error.\n"); | |
248 | break; | |
249 | ||
250 | case 0x1: | |
251 | pr_cont("UC error during a linefill from L2/NB.\n"); | |
252 | break; | |
253 | ||
254 | case 0x2: | |
255 | case 0x11: | |
256 | pr_cont("STQ access error.\n"); | |
257 | break; | |
258 | ||
259 | case 0x3: | |
260 | pr_cont("SCB access error.\n"); | |
261 | break; | |
262 | ||
263 | case 0x10: | |
264 | pr_cont("Tag error.\n"); | |
265 | break; | |
266 | ||
267 | case 0x12: | |
268 | pr_cont("LDQ access error.\n"); | |
269 | break; | |
270 | ||
271 | default: | |
272 | ret = false; | |
273 | } | |
274 | } else if (BUS_ERROR(ec)) { | |
275 | ||
276 | if (!xec) | |
344f0a06 | 277 | pr_cont("System Read Data Error.\n"); |
25a4f8b0 | 278 | else |
344f0a06 | 279 | pr_cont(" Internal error condition type %d.\n", xec); |
eba4bfb3 AG |
280 | } else if (INT_ERROR(ec)) { |
281 | if (xec <= 0x1f) | |
282 | pr_cont("Hardware Assert.\n"); | |
283 | else | |
284 | ret = false; | |
285 | ||
25a4f8b0 BP |
286 | } else |
287 | ret = false; | |
288 | ||
289 | return ret; | |
290 | } | |
291 | ||
f05c41a9 | 292 | static void decode_mc0_mce(struct mce *m) |
888ab8e6 | 293 | { |
62452882 BP |
294 | u16 ec = EC(m->status); |
295 | u8 xec = XEC(m->status, xec_mask); | |
888ab8e6 | 296 | |
f05c41a9 | 297 | pr_emerg(HW_ERR "MC0 Error: "); |
888ab8e6 BP |
298 | |
299 | /* TLB error signatures are the same across families */ | |
300 | if (TLB_ERROR(ec)) { | |
62452882 | 301 | if (TT(ec) == TT_DATA) { |
888ab8e6 | 302 | pr_cont("%s TLB %s.\n", LL_MSG(ec), |
25a4f8b0 BP |
303 | ((xec == 2) ? "locked miss" |
304 | : (xec ? "multimatch" : "parity"))); | |
888ab8e6 BP |
305 | return; |
306 | } | |
f05c41a9 | 307 | } else if (fam_ops->mc0_mce(ec, xec)) |
25a4f8b0 BP |
308 | ; |
309 | else | |
f05c41a9 | 310 | pr_emerg(HW_ERR "Corrupted MC0 MCE info?\n"); |
51966241 BP |
311 | } |
312 | ||
f05c41a9 | 313 | static bool k8_mc1_mce(u16 ec, u8 xec) |
ab5535e7 | 314 | { |
62452882 | 315 | u8 ll = LL(ec); |
dd53bce4 | 316 | bool ret = true; |
ab5535e7 | 317 | |
dd53bce4 BP |
318 | if (!MEM_ERROR(ec)) |
319 | return false; | |
ab5535e7 | 320 | |
dd53bce4 BP |
321 | if (ll == 0x2) |
322 | pr_cont("during a linefill from L2.\n"); | |
323 | else if (ll == 0x1) { | |
62452882 | 324 | switch (R4(ec)) { |
dd53bce4 BP |
325 | case R4_IRD: |
326 | pr_cont("Parity error during data load.\n"); | |
327 | break; | |
ab5535e7 | 328 | |
dd53bce4 BP |
329 | case R4_EVICT: |
330 | pr_cont("Copyback Parity/Victim error.\n"); | |
331 | break; | |
332 | ||
333 | case R4_SNOOP: | |
334 | pr_cont("Tag Snoop error.\n"); | |
335 | break; | |
336 | ||
337 | default: | |
338 | ret = false; | |
339 | break; | |
340 | } | |
ab5535e7 | 341 | } else |
dd53bce4 | 342 | ret = false; |
ab5535e7 | 343 | |
dd53bce4 BP |
344 | return ret; |
345 | } | |
346 | ||
980eec8b | 347 | static bool cat_mc1_mce(u16 ec, u8 xec) |
dd53bce4 | 348 | { |
62452882 | 349 | u8 r4 = R4(ec); |
dd53bce4 | 350 | bool ret = true; |
ab5535e7 | 351 | |
980eec8b JS |
352 | if (!MEM_ERROR(ec)) |
353 | return false; | |
354 | ||
355 | if (TT(ec) != TT_INSTR) | |
356 | return false; | |
357 | ||
358 | if (r4 == R4_IRD) | |
359 | pr_cont("Data/tag array parity error for a tag hit.\n"); | |
360 | else if (r4 == R4_SNOOP) | |
361 | pr_cont("Tag error during snoop/victimization.\n"); | |
362 | else if (xec == 0x0) | |
363 | pr_cont("Tag parity error from victim castout.\n"); | |
364 | else if (xec == 0x2) | |
365 | pr_cont("Microcode patch RAM parity error.\n"); | |
366 | else | |
367 | ret = false; | |
dd53bce4 | 368 | |
dd53bce4 BP |
369 | return ret; |
370 | } | |
371 | ||
f05c41a9 | 372 | static bool f15h_mc1_mce(u16 ec, u8 xec) |
86039cd4 BP |
373 | { |
374 | bool ret = true; | |
375 | ||
376 | if (!MEM_ERROR(ec)) | |
377 | return false; | |
378 | ||
379 | switch (xec) { | |
380 | case 0x0 ... 0xa: | |
f05c41a9 | 381 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec]); |
86039cd4 BP |
382 | break; |
383 | ||
384 | case 0xd: | |
f05c41a9 | 385 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]); |
86039cd4 BP |
386 | break; |
387 | ||
6c1173a6 | 388 | case 0x10: |
f05c41a9 | 389 | pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]); |
6c1173a6 BP |
390 | break; |
391 | ||
eba4bfb3 | 392 | case 0x11 ... 0x15: |
f05c41a9 | 393 | pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]); |
86039cd4 BP |
394 | break; |
395 | ||
396 | default: | |
397 | ret = false; | |
398 | } | |
399 | return ret; | |
400 | } | |
401 | ||
f05c41a9 | 402 | static void decode_mc1_mce(struct mce *m) |
dd53bce4 | 403 | { |
62452882 BP |
404 | u16 ec = EC(m->status); |
405 | u8 xec = XEC(m->status, xec_mask); | |
dd53bce4 | 406 | |
f05c41a9 | 407 | pr_emerg(HW_ERR "MC1 Error: "); |
dd53bce4 BP |
408 | |
409 | if (TLB_ERROR(ec)) | |
410 | pr_cont("%s TLB %s.\n", LL_MSG(ec), | |
411 | (xec ? "multimatch" : "parity error")); | |
412 | else if (BUS_ERROR(ec)) { | |
525906bc | 413 | bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58))); |
dd53bce4 BP |
414 | |
415 | pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read")); | |
eba4bfb3 AG |
416 | } else if (INT_ERROR(ec)) { |
417 | if (xec <= 0x3f) | |
418 | pr_cont("Hardware Assert.\n"); | |
419 | else | |
420 | goto wrong_mc1_mce; | |
f05c41a9 | 421 | } else if (fam_ops->mc1_mce(ec, xec)) |
dd53bce4 BP |
422 | ; |
423 | else | |
eba4bfb3 AG |
424 | goto wrong_mc1_mce; |
425 | ||
426 | return; | |
427 | ||
428 | wrong_mc1_mce: | |
429 | pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n"); | |
ab5535e7 BP |
430 | } |
431 | ||
4a73d3de | 432 | static bool k8_mc2_mce(u16 ec, u8 xec) |
56cad2d6 | 433 | { |
4a73d3de | 434 | bool ret = true; |
56cad2d6 BP |
435 | |
436 | if (xec == 0x1) | |
437 | pr_cont(" in the write data buffers.\n"); | |
438 | else if (xec == 0x3) | |
439 | pr_cont(" in the victim data buffers.\n"); | |
440 | else if (xec == 0x2 && MEM_ERROR(ec)) | |
62452882 | 441 | pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec)); |
56cad2d6 BP |
442 | else if (xec == 0x0) { |
443 | if (TLB_ERROR(ec)) | |
50872ccd BP |
444 | pr_cont("%s error in a Page Descriptor Cache or Guest TLB.\n", |
445 | TT_MSG(ec)); | |
56cad2d6 BP |
446 | else if (BUS_ERROR(ec)) |
447 | pr_cont(": %s/ECC error in data read from NB: %s.\n", | |
62452882 | 448 | R4_MSG(ec), PP_MSG(ec)); |
56cad2d6 | 449 | else if (MEM_ERROR(ec)) { |
62452882 | 450 | u8 r4 = R4(ec); |
56cad2d6 | 451 | |
62452882 | 452 | if (r4 >= 0x7) |
56cad2d6 | 453 | pr_cont(": %s error during data copyback.\n", |
62452882 BP |
454 | R4_MSG(ec)); |
455 | else if (r4 <= 0x1) | |
56cad2d6 | 456 | pr_cont(": %s parity/ECC error during data " |
62452882 | 457 | "access from L2.\n", R4_MSG(ec)); |
56cad2d6 | 458 | else |
4a73d3de | 459 | ret = false; |
56cad2d6 | 460 | } else |
4a73d3de | 461 | ret = false; |
56cad2d6 | 462 | } else |
4a73d3de | 463 | ret = false; |
56cad2d6 | 464 | |
4a73d3de | 465 | return ret; |
56cad2d6 BP |
466 | } |
467 | ||
4a73d3de | 468 | static bool f15h_mc2_mce(u16 ec, u8 xec) |
70fdb494 | 469 | { |
4a73d3de | 470 | bool ret = true; |
70fdb494 BP |
471 | |
472 | if (TLB_ERROR(ec)) { | |
473 | if (xec == 0x0) | |
474 | pr_cont("Data parity TLB read error.\n"); | |
475 | else if (xec == 0x1) | |
476 | pr_cont("Poison data provided for TLB fill.\n"); | |
477 | else | |
4a73d3de | 478 | ret = false; |
70fdb494 BP |
479 | } else if (BUS_ERROR(ec)) { |
480 | if (xec > 2) | |
4a73d3de | 481 | ret = false; |
70fdb494 BP |
482 | |
483 | pr_cont("Error during attempted NB data read.\n"); | |
484 | } else if (MEM_ERROR(ec)) { | |
485 | switch (xec) { | |
486 | case 0x4 ... 0xc: | |
f05c41a9 | 487 | pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]); |
70fdb494 BP |
488 | break; |
489 | ||
490 | case 0x10 ... 0x14: | |
f05c41a9 | 491 | pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]); |
70fdb494 BP |
492 | break; |
493 | ||
494 | default: | |
4a73d3de | 495 | ret = false; |
70fdb494 | 496 | } |
eba4bfb3 AG |
497 | } else if (INT_ERROR(ec)) { |
498 | if (xec <= 0x3f) | |
499 | pr_cont("Hardware Assert.\n"); | |
500 | else | |
501 | ret = false; | |
70fdb494 BP |
502 | } |
503 | ||
4a73d3de JS |
504 | return ret; |
505 | } | |
506 | ||
980eec8b JS |
507 | static bool f16h_mc2_mce(u16 ec, u8 xec) |
508 | { | |
509 | u8 r4 = R4(ec); | |
510 | ||
511 | if (!MEM_ERROR(ec)) | |
512 | return false; | |
513 | ||
514 | switch (xec) { | |
515 | case 0x04 ... 0x05: | |
516 | pr_cont("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O'); | |
517 | break; | |
518 | ||
519 | case 0x09 ... 0x0b: | |
520 | case 0x0d ... 0x0f: | |
521 | pr_cont("ECC error in L2 tag (%s).\n", | |
522 | ((r4 == R4_GEN) ? "BankReq" : | |
523 | ((r4 == R4_SNOOP) ? "Prb" : "Fill"))); | |
524 | break; | |
525 | ||
526 | case 0x10 ... 0x19: | |
527 | case 0x1b: | |
528 | pr_cont("ECC error in L2 data array (%s).\n", | |
529 | (((r4 == R4_RD) && !(xec & 0x3)) ? "Hit" : | |
530 | ((r4 == R4_GEN) ? "Attr" : | |
531 | ((r4 == R4_EVICT) ? "Vict" : "Fill")))); | |
532 | break; | |
533 | ||
534 | case 0x1c ... 0x1d: | |
535 | case 0x1f: | |
536 | pr_cont("Parity error in L2 attribute bits (%s).\n", | |
537 | ((r4 == R4_RD) ? "Hit" : | |
538 | ((r4 == R4_GEN) ? "Attr" : "Fill"))); | |
539 | break; | |
540 | ||
541 | default: | |
542 | return false; | |
543 | } | |
544 | ||
545 | return true; | |
546 | } | |
547 | ||
4a73d3de JS |
548 | static void decode_mc2_mce(struct mce *m) |
549 | { | |
550 | u16 ec = EC(m->status); | |
551 | u8 xec = XEC(m->status, xec_mask); | |
70fdb494 | 552 | |
4a73d3de JS |
553 | pr_emerg(HW_ERR "MC2 Error: "); |
554 | ||
555 | if (!fam_ops->mc2_mce(ec, xec)) | |
556 | pr_cont(HW_ERR "Corrupted MC2 MCE info?\n"); | |
70fdb494 BP |
557 | } |
558 | ||
f05c41a9 | 559 | static void decode_mc3_mce(struct mce *m) |
f9350efd | 560 | { |
62452882 BP |
561 | u16 ec = EC(m->status); |
562 | u8 xec = XEC(m->status, xec_mask); | |
ded50623 | 563 | |
b18434ca | 564 | if (boot_cpu_data.x86 >= 0x14) { |
f05c41a9 | 565 | pr_emerg("You shouldn't be seeing MC3 MCE on this cpu family," |
ded50623 BP |
566 | " please report on LKML.\n"); |
567 | return; | |
568 | } | |
f9350efd | 569 | |
f05c41a9 | 570 | pr_emerg(HW_ERR "MC3 Error"); |
f9350efd BP |
571 | |
572 | if (xec == 0x0) { | |
62452882 | 573 | u8 r4 = R4(ec); |
f9350efd | 574 | |
ded50623 | 575 | if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR)) |
f05c41a9 | 576 | goto wrong_mc3_mce; |
f9350efd | 577 | |
62452882 | 578 | pr_cont(" during %s.\n", R4_MSG(ec)); |
ded50623 | 579 | } else |
f05c41a9 | 580 | goto wrong_mc3_mce; |
ded50623 | 581 | |
f9350efd BP |
582 | return; |
583 | ||
f05c41a9 BP |
584 | wrong_mc3_mce: |
585 | pr_emerg(HW_ERR "Corrupted MC3 MCE info?\n"); | |
f9350efd BP |
586 | } |
587 | ||
f05c41a9 | 588 | static void decode_mc4_mce(struct mce *m) |
5ce88f6e | 589 | { |
68782673 BP |
590 | struct cpuinfo_x86 *c = &boot_cpu_data; |
591 | int node_id = amd_get_nb_id(m->extcpu); | |
592 | u16 ec = EC(m->status); | |
593 | u8 xec = XEC(m->status, 0x1f); | |
594 | u8 offset = 0; | |
5ce88f6e | 595 | |
f05c41a9 | 596 | pr_emerg(HW_ERR "MC4 Error (node %d): ", node_id); |
5ce88f6e | 597 | |
68782673 BP |
598 | switch (xec) { |
599 | case 0x0 ... 0xe: | |
5ce88f6e | 600 | |
68782673 BP |
601 | /* special handling for DRAM ECCs */ |
602 | if (xec == 0x0 || xec == 0x8) { | |
603 | /* no ECCs on F11h */ | |
604 | if (c->x86 == 0x11) | |
f05c41a9 | 605 | goto wrong_mc4_mce; |
5ce88f6e | 606 | |
f05c41a9 | 607 | pr_cont("%s.\n", mc4_mce_desc[xec]); |
5ce88f6e | 608 | |
68782673 BP |
609 | if (nb_bus_decoder) |
610 | nb_bus_decoder(node_id, m); | |
611 | return; | |
612 | } | |
5ce88f6e BP |
613 | break; |
614 | ||
615 | case 0xf: | |
616 | if (TLB_ERROR(ec)) | |
617 | pr_cont("GART Table Walk data error.\n"); | |
618 | else if (BUS_ERROR(ec)) | |
619 | pr_cont("DMA Exclusion Vector Table Walk error.\n"); | |
620 | else | |
f05c41a9 | 621 | goto wrong_mc4_mce; |
68782673 | 622 | return; |
5ce88f6e | 623 | |
05cd667d | 624 | case 0x19: |
980eec8b | 625 | if (boot_cpu_data.x86 == 0x15 || boot_cpu_data.x86 == 0x16) |
05cd667d BP |
626 | pr_cont("Compute Unit Data Error.\n"); |
627 | else | |
f05c41a9 | 628 | goto wrong_mc4_mce; |
68782673 | 629 | return; |
05cd667d | 630 | |
5ce88f6e | 631 | case 0x1c ... 0x1f: |
68782673 | 632 | offset = 13; |
5ce88f6e BP |
633 | break; |
634 | ||
635 | default: | |
f05c41a9 | 636 | goto wrong_mc4_mce; |
68782673 | 637 | } |
5ce88f6e | 638 | |
f05c41a9 | 639 | pr_cont("%s.\n", mc4_mce_desc[xec - offset]); |
5ce88f6e BP |
640 | return; |
641 | ||
f05c41a9 BP |
642 | wrong_mc4_mce: |
643 | pr_emerg(HW_ERR "Corrupted MC4 MCE info?\n"); | |
d93cc222 | 644 | } |
d93cc222 | 645 | |
f05c41a9 | 646 | static void decode_mc5_mce(struct mce *m) |
53bd5fed | 647 | { |
8259a7e5 | 648 | struct cpuinfo_x86 *c = &boot_cpu_data; |
eba4bfb3 | 649 | u16 ec = EC(m->status); |
62452882 | 650 | u8 xec = XEC(m->status, xec_mask); |
8259a7e5 BP |
651 | |
652 | if (c->x86 == 0xf || c->x86 == 0x11) | |
f05c41a9 | 653 | goto wrong_mc5_mce; |
fe4ea262 | 654 | |
f05c41a9 | 655 | pr_emerg(HW_ERR "MC5 Error: "); |
8259a7e5 | 656 | |
eba4bfb3 AG |
657 | if (INT_ERROR(ec)) { |
658 | if (xec <= 0x1f) { | |
659 | pr_cont("Hardware Assert.\n"); | |
660 | return; | |
661 | } else | |
662 | goto wrong_mc5_mce; | |
663 | } | |
664 | ||
8259a7e5 | 665 | if (xec == 0x0 || xec == 0xc) |
f05c41a9 | 666 | pr_cont("%s.\n", mc5_mce_desc[xec]); |
aad19e51 | 667 | else if (xec <= 0xd) |
f05c41a9 | 668 | pr_cont("%s parity error.\n", mc5_mce_desc[xec]); |
8259a7e5 | 669 | else |
f05c41a9 | 670 | goto wrong_mc5_mce; |
8259a7e5 BP |
671 | |
672 | return; | |
fe4ea262 | 673 | |
f05c41a9 BP |
674 | wrong_mc5_mce: |
675 | pr_emerg(HW_ERR "Corrupted MC5 MCE info?\n"); | |
53bd5fed BP |
676 | } |
677 | ||
f05c41a9 | 678 | static void decode_mc6_mce(struct mce *m) |
b8f85c47 | 679 | { |
62452882 | 680 | u8 xec = XEC(m->status, xec_mask); |
b8f85c47 | 681 | |
f05c41a9 | 682 | pr_emerg(HW_ERR "MC6 Error: "); |
b8f85c47 | 683 | |
bc4febe9 | 684 | if (xec > 0x5) |
f05c41a9 | 685 | goto wrong_mc6_mce; |
b8f85c47 | 686 | |
bc4febe9 | 687 | pr_cont("%s parity error.\n", mc6_mce_desc[xec]); |
b8f85c47 BP |
688 | return; |
689 | ||
f05c41a9 BP |
690 | wrong_mc6_mce: |
691 | pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n"); | |
b8f85c47 BP |
692 | } |
693 | ||
6337583d | 694 | static inline void amd_decode_err_code(u16 ec) |
d93cc222 | 695 | { |
980eec8b JS |
696 | if (INT_ERROR(ec)) { |
697 | pr_emerg(HW_ERR "internal: %s\n", UU_MSG(ec)); | |
698 | return; | |
699 | } | |
fa7ae8cc BP |
700 | |
701 | pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec)); | |
702 | ||
703 | if (BUS_ERROR(ec)) | |
704 | pr_cont(", mem/io: %s", II_MSG(ec)); | |
705 | else | |
706 | pr_cont(", tx: %s", TT_MSG(ec)); | |
707 | ||
708 | if (MEM_ERROR(ec) || BUS_ERROR(ec)) { | |
709 | pr_cont(", mem-tx: %s", R4_MSG(ec)); | |
710 | ||
711 | if (BUS_ERROR(ec)) | |
712 | pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec)); | |
713 | } | |
714 | ||
715 | pr_cont("\n"); | |
549d042d | 716 | } |
549d042d | 717 | |
5ce88f6e BP |
718 | /* |
719 | * Filter out unwanted MCE signatures here. | |
720 | */ | |
721 | static bool amd_filter_mce(struct mce *m) | |
722 | { | |
723 | u8 xec = (m->status >> 16) & 0x1f; | |
724 | ||
725 | /* | |
726 | * NB GART TLB error reporting is disabled by default. | |
727 | */ | |
728 | if (m->bank == 4 && xec == 0x5 && !report_gart_errors) | |
729 | return true; | |
730 | ||
731 | return false; | |
732 | } | |
733 | ||
d5c6770d BP |
734 | static const char *decode_error_status(struct mce *m) |
735 | { | |
736 | if (m->status & MCI_STATUS_UC) { | |
737 | if (m->status & MCI_STATUS_PCC) | |
738 | return "System Fatal error."; | |
739 | if (m->mcgstatus & MCG_STATUS_RIPV) | |
740 | return "Uncorrected, software restartable error."; | |
741 | return "Uncorrected, software containable error."; | |
742 | } | |
743 | ||
744 | if (m->status & MCI_STATUS_DEFERRED) | |
745 | return "Deferred error."; | |
746 | ||
747 | return "Corrected error, no action required."; | |
748 | } | |
749 | ||
9cdeb404 | 750 | int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data) |
549d042d | 751 | { |
fb253195 | 752 | struct mce *m = (struct mce *)data; |
f89f8388 | 753 | struct cpuinfo_x86 *c = &cpu_data(m->extcpu); |
b0b07a2b | 754 | int ecc; |
549d042d | 755 | |
5ce88f6e BP |
756 | if (amd_filter_mce(m)) |
757 | return NOTIFY_STOP; | |
758 | ||
fd0f5fff BP |
759 | pr_emerg(HW_ERR "%s\n", decode_error_status(m)); |
760 | ||
761 | pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s", | |
762 | m->extcpu, | |
763 | c->x86, c->x86_model, c->x86_mask, | |
764 | m->bank, | |
765 | ((m->status & MCI_STATUS_OVER) ? "Over" : "-"), | |
99e1dfb7 AG |
766 | ((m->status & MCI_STATUS_UC) ? "UE" : |
767 | (m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"), | |
fd0f5fff BP |
768 | ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"), |
769 | ((m->status & MCI_STATUS_PCC) ? "PCC" : "-"), | |
770 | ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-")); | |
771 | ||
772 | if (c->x86 == 0x15 || c->x86 == 0x16) | |
773 | pr_cont("|%s|%s", | |
774 | ((m->status & MCI_STATUS_DEFERRED) ? "Deferred" : "-"), | |
775 | ((m->status & MCI_STATUS_POISON) ? "Poison" : "-")); | |
776 | ||
777 | /* do the two bits[14:13] together */ | |
778 | ecc = (m->status >> 45) & 0x3; | |
779 | if (ecc) | |
780 | pr_cont("|%sECC", ((ecc == 2) ? "C" : "U")); | |
781 | ||
782 | pr_cont("]: 0x%016llx\n", m->status); | |
783 | ||
784 | if (m->status & MCI_STATUS_ADDRV) | |
50872ccd | 785 | pr_emerg(HW_ERR "MC%d Error Address: 0x%016llx\n", m->bank, m->addr); |
fd0f5fff BP |
786 | |
787 | if (!fam_ops) | |
788 | goto err_code; | |
789 | ||
51966241 BP |
790 | switch (m->bank) { |
791 | case 0: | |
f05c41a9 | 792 | decode_mc0_mce(m); |
51966241 | 793 | break; |
d93cc222 | 794 | |
ab5535e7 | 795 | case 1: |
f05c41a9 | 796 | decode_mc1_mce(m); |
ab5535e7 BP |
797 | break; |
798 | ||
56cad2d6 | 799 | case 2: |
4a73d3de | 800 | decode_mc2_mce(m); |
56cad2d6 BP |
801 | break; |
802 | ||
f9350efd | 803 | case 3: |
f05c41a9 | 804 | decode_mc3_mce(m); |
f9350efd BP |
805 | break; |
806 | ||
51966241 | 807 | case 4: |
f05c41a9 | 808 | decode_mc4_mce(m); |
51966241 BP |
809 | break; |
810 | ||
53bd5fed | 811 | case 5: |
f05c41a9 | 812 | decode_mc5_mce(m); |
53bd5fed BP |
813 | break; |
814 | ||
b8f85c47 | 815 | case 6: |
f05c41a9 | 816 | decode_mc6_mce(m); |
b8f85c47 BP |
817 | break; |
818 | ||
51966241 BP |
819 | default: |
820 | break; | |
b69b29de | 821 | } |
51966241 | 822 | |
fd0f5fff | 823 | err_code: |
51966241 | 824 | amd_decode_err_code(m->status & 0xffff); |
fb253195 BP |
825 | |
826 | return NOTIFY_STOP; | |
549d042d | 827 | } |
9cdeb404 | 828 | EXPORT_SYMBOL_GPL(amd_decode_mce); |
f436f8bb | 829 | |
fb253195 BP |
830 | static struct notifier_block amd_mce_dec_nb = { |
831 | .notifier_call = amd_decode_mce, | |
832 | }; | |
833 | ||
f436f8bb IM |
834 | static int __init mce_amd_init(void) |
835 | { | |
bad11e03 BP |
836 | struct cpuinfo_x86 *c = &boot_cpu_data; |
837 | ||
838 | if (c->x86_vendor != X86_VENDOR_AMD) | |
fd0f5fff | 839 | return -ENODEV; |
e045c291 | 840 | |
888ab8e6 BP |
841 | fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL); |
842 | if (!fam_ops) | |
843 | return -ENOMEM; | |
844 | ||
bad11e03 | 845 | switch (c->x86) { |
888ab8e6 | 846 | case 0xf: |
f05c41a9 BP |
847 | fam_ops->mc0_mce = k8_mc0_mce; |
848 | fam_ops->mc1_mce = k8_mc1_mce; | |
4a73d3de | 849 | fam_ops->mc2_mce = k8_mc2_mce; |
888ab8e6 BP |
850 | break; |
851 | ||
852 | case 0x10: | |
f05c41a9 BP |
853 | fam_ops->mc0_mce = f10h_mc0_mce; |
854 | fam_ops->mc1_mce = k8_mc1_mce; | |
4a73d3de | 855 | fam_ops->mc2_mce = k8_mc2_mce; |
888ab8e6 BP |
856 | break; |
857 | ||
f0157b3a | 858 | case 0x11: |
f05c41a9 BP |
859 | fam_ops->mc0_mce = k8_mc0_mce; |
860 | fam_ops->mc1_mce = k8_mc1_mce; | |
4a73d3de | 861 | fam_ops->mc2_mce = k8_mc2_mce; |
f0157b3a BP |
862 | break; |
863 | ||
9be0bb10 | 864 | case 0x12: |
f05c41a9 BP |
865 | fam_ops->mc0_mce = f12h_mc0_mce; |
866 | fam_ops->mc1_mce = k8_mc1_mce; | |
4a73d3de | 867 | fam_ops->mc2_mce = k8_mc2_mce; |
9be0bb10 BP |
868 | break; |
869 | ||
888ab8e6 | 870 | case 0x14: |
980eec8b JS |
871 | fam_ops->mc0_mce = cat_mc0_mce; |
872 | fam_ops->mc1_mce = cat_mc1_mce; | |
4a73d3de | 873 | fam_ops->mc2_mce = k8_mc2_mce; |
888ab8e6 BP |
874 | break; |
875 | ||
2be64bfa | 876 | case 0x15: |
eba4bfb3 AG |
877 | xec_mask = c->x86_model == 0x60 ? 0x3f : 0x1f; |
878 | ||
f05c41a9 BP |
879 | fam_ops->mc0_mce = f15h_mc0_mce; |
880 | fam_ops->mc1_mce = f15h_mc1_mce; | |
4a73d3de | 881 | fam_ops->mc2_mce = f15h_mc2_mce; |
2be64bfa BP |
882 | break; |
883 | ||
980eec8b JS |
884 | case 0x16: |
885 | xec_mask = 0x1f; | |
886 | fam_ops->mc0_mce = cat_mc0_mce; | |
887 | fam_ops->mc1_mce = cat_mc1_mce; | |
888 | fam_ops->mc2_mce = f16h_mc2_mce; | |
889 | break; | |
890 | ||
888ab8e6 | 891 | default: |
ec3e82d6 | 892 | printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86); |
888ab8e6 | 893 | kfree(fam_ops); |
fd0f5fff | 894 | fam_ops = NULL; |
888ab8e6 BP |
895 | } |
896 | ||
9530d608 BP |
897 | pr_info("MCE: In-kernel MCE decoding enabled.\n"); |
898 | ||
3653ada5 | 899 | mce_register_decode_chain(&amd_mce_dec_nb); |
f436f8bb IM |
900 | |
901 | return 0; | |
902 | } | |
903 | early_initcall(mce_amd_init); | |
0d18b2e3 BP |
904 | |
905 | #ifdef MODULE | |
906 | static void __exit mce_amd_exit(void) | |
907 | { | |
3653ada5 | 908 | mce_unregister_decode_chain(&amd_mce_dec_nb); |
888ab8e6 | 909 | kfree(fam_ops); |
0d18b2e3 BP |
910 | } |
911 | ||
912 | MODULE_DESCRIPTION("AMD MCE decoder"); | |
913 | MODULE_ALIAS("edac-mce-amd"); | |
914 | MODULE_LICENSE("GPL"); | |
915 | module_exit(mce_amd_exit); | |
916 | #endif |