[deliverable/linux.git] / drivers / edac / mce_amd.c

#include <linux/module.h>
#include <linux/slab.h>

#include "mce_amd.h"

static struct amd_decoder_ops *fam_ops;

static bool report_gart_errors;
static void (*nb_bus_decoder)(int node_id, struct mce *m, u32 nbcfg);

void amd_report_gart_errors(bool v)
{
	report_gart_errors = v;
}
EXPORT_SYMBOL_GPL(amd_report_gart_errors);

void amd_register_ecc_decoder(void (*f)(int, struct mce *, u32))
{
	nb_bus_decoder = f;
}
EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);

void amd_unregister_ecc_decoder(void (*f)(int, struct mce *, u32))
{
	if (nb_bus_decoder) {
		WARN_ON(nb_bus_decoder != f);

		nb_bus_decoder = NULL;
	}
}
EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);

/*
 * string representation for the different MCA reported error types, see F3x48
 * or MSR0000_0411.
 */

/* transaction type */
const char *tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
EXPORT_SYMBOL_GPL(tt_msgs);

/* cache level */
const char *ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
EXPORT_SYMBOL_GPL(ll_msgs);

/* memory transaction type */
const char *rrrr_msgs[] = {
       "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
};
EXPORT_SYMBOL_GPL(rrrr_msgs);

/* participating processor */
const char *pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
EXPORT_SYMBOL_GPL(pp_msgs);

/* request timeout */
const char *to_msgs[] = { "no timeout",	"timed out" };
EXPORT_SYMBOL_GPL(to_msgs);

/* memory or i/o */
const char *ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
EXPORT_SYMBOL_GPL(ii_msgs);

/*
 * Map the 4 or 5 (family-specific) bits of Extended Error code to the
 * string table.
 */
const char *ext_msgs[] = {
	"K8 ECC error",					/* 0_0000b */
	"CRC error on link",				/* 0_0001b */
	"Sync error packets on link",			/* 0_0010b */
	"Master Abort during link operation",		/* 0_0011b */
	"Target Abort during link operation",		/* 0_0100b */
	"Invalid GART PTE entry during table walk",	/* 0_0101b */
	"Unsupported atomic RMW command received",	/* 0_0110b */
	"WDT error: NB transaction timeout",		/* 0_0111b */
	"ECC/ChipKill ECC error",			/* 0_1000b */
	"SVM DEV Error",				/* 0_1001b */
	"Link Data error",				/* 0_1010b */
	"Link/L3/Probe Filter Protocol error",		/* 0_1011b */
	"NB Internal Arrays Parity error",		/* 0_1100b */
	"DRAM Address/Control Parity error",		/* 0_1101b */
	"Link Transmission error",			/* 0_1110b */
	"GART/DEV Table Walk Data error"		/* 0_1111b */
	"Res 0x100 error",				/* 1_0000b */
	"Res 0x101 error",				/* 1_0001b */
	"Res 0x102 error",				/* 1_0010b */
	"Res 0x103 error",				/* 1_0011b */
	"Res 0x104 error",				/* 1_0100b */
	"Res 0x105 error",				/* 1_0101b */
	"Res 0x106 error",				/* 1_0110b */
	"Res 0x107 error",				/* 1_0111b */
	"Res 0x108 error",				/* 1_1000b */
	"Res 0x109 error",				/* 1_1001b */
	"Res 0x10A error",				/* 1_1010b */
	"Res 0x10B error",				/* 1_1011b */
	"ECC error in L3 Cache Data",			/* 1_1100b */
	"L3 Cache Tag error",				/* 1_1101b */
	"L3 Cache LRU Parity error",			/* 1_1110b */
	"Probe Filter error"				/* 1_1111b */
};
EXPORT_SYMBOL_GPL(ext_msgs);

static bool f10h_dc_mce(u16 ec)
{
	u8 r4  = (ec >> 4) & 0xf;
	bool ret = false;

	if (r4 == R4_GEN) {
		pr_cont("during data scrub.\n");
		return true;
	}

	if (MEM_ERROR(ec)) {
		u8 ll = ec & 0x3;
		ret = true;

		if (ll == LL_L2)
			pr_cont("during L1 linefill from L2.\n");
		else if (ll == LL_L1)
			pr_cont("Data/Tag %s error.\n", RRRR_MSG(ec));
		else
			ret = false;
	}
	return ret;
}

static bool k8_dc_mce(u16 ec)
{
	if (BUS_ERROR(ec)) {
		pr_cont("during system linefill.\n");
		return true;
	}

	return f10h_dc_mce(ec);
}

static bool f14h_dc_mce(u16 ec)
{
	u8 r4	 = (ec >> 4) & 0xf;
	u8 ll	 = ec & 0x3;
	u8 tt	 = (ec >> 2) & 0x3;
	u8 ii	 = tt;
	bool ret = true;

	if (MEM_ERROR(ec)) {

		if (tt != TT_DATA || ll != LL_L1)
			return false;

		switch (r4) {
		case R4_DRD:
		case R4_DWR:
			pr_cont("Data/Tag parity error due to %s.\n",
				(r4 == R4_DRD ? "load/hw prf" : "store"));
			break;
		case R4_EVICT:
			pr_cont("Copyback parity error on a tag miss.\n");
			break;
		case R4_SNOOP:
			pr_cont("Tag parity error during snoop.\n");
			break;
		default:
			ret = false;
		}
	} else if (BUS_ERROR(ec)) {

		if ((ii != II_MEM && ii != II_IO) || ll != LL_LG)
			return false;

		pr_cont("System read data error on a ");

		switch (r4) {
		case R4_RD:
			pr_cont("TLB reload.\n");
			break;
		case R4_DWR:
			pr_cont("store.\n");
			break;
		case R4_DRD:
			pr_cont("load.\n");
			break;
		default:
			ret = false;
		}
	} else {
		ret = false;
	}

	return ret;
}

static void amd_decode_dc_mce(struct mce *m)
{
	u16 ec = m->status & 0xffff;
	u8 xec = (m->status >> 16) & 0xf;

	pr_emerg(HW_ERR "Data Cache Error: ");

	/* TLB error signatures are the same across families */
	if (TLB_ERROR(ec)) {
		u8 tt = (ec >> 2) & 0x3;

		if (tt == TT_DATA) {
			pr_cont("%s TLB %s.\n", LL_MSG(ec),
				(xec ? "multimatch" : "parity error"));
			return;
		}
		else
			goto wrong_dc_mce;
	}

	if (!fam_ops->dc_mce(ec))
		goto wrong_dc_mce;

	return;

wrong_dc_mce:
	pr_emerg(HW_ERR "Corrupted DC MCE info?\n");
}

static bool k8_ic_mce(u16 ec)
{
	u8 ll	 = ec & 0x3;
	u8 r4	 = (ec >> 4) & 0xf;
	bool ret = true;

	if (!MEM_ERROR(ec))
		return false;

	if (ll == 0x2)
		pr_cont("during a linefill from L2.\n");
	else if (ll == 0x1) {
		switch (r4) {
		case R4_IRD:
			pr_cont("Parity error during data load.\n");
			break;

		case R4_EVICT:
			pr_cont("Copyback Parity/Victim error.\n");
			break;

		case R4_SNOOP:
			pr_cont("Tag Snoop error.\n");
			break;

		default:
			ret = false;
			break;
		}
	} else
		ret = false;

	return ret;
}

static bool f14h_ic_mce(u16 ec)
{
	u8 ll    = ec & 0x3;
	u8 tt    = (ec >> 2) & 0x3;
	u8 r4  = (ec >> 4) & 0xf;
	bool ret = true;

	if (MEM_ERROR(ec)) {
		if (tt != 0 || ll != 1)
			ret = false;

		if (r4 == R4_IRD)
			pr_cont("Data/tag array parity error for a tag hit.\n");
		else if (r4 == R4_SNOOP)
			pr_cont("Tag error during snoop/victimization.\n");
		else
			ret = false;
	}
	return ret;
}

static void amd_decode_ic_mce(struct mce *m)
{
	u16 ec = m->status & 0xffff;
	u8 xec = (m->status >> 16) & 0xf;

	pr_emerg(HW_ERR "Instruction Cache Error: ");

	if (TLB_ERROR(ec))
		pr_cont("%s TLB %s.\n", LL_MSG(ec),
			(xec ? "multimatch" : "parity error"));
	else if (BUS_ERROR(ec)) {
		bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT(58)));

		pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
	} else if (fam_ops->ic_mce(ec))
		;
	else
		pr_emerg(HW_ERR "Corrupted IC MCE info?\n");
}

static void amd_decode_bu_mce(struct mce *m)
{
	u32 ec = m->status & 0xffff;
	u32 xec = (m->status >> 16) & 0xf;

	pr_emerg(HW_ERR "Bus Unit Error");

	if (xec == 0x1)
		pr_cont(" in the write data buffers.\n");
	else if (xec == 0x3)
		pr_cont(" in the victim data buffers.\n");
	else if (xec == 0x2 && MEM_ERROR(ec))
		pr_cont(": %s error in the L2 cache tags.\n", RRRR_MSG(ec));
	else if (xec == 0x0) {
		if (TLB_ERROR(ec))
			pr_cont(": %s error in a Page Descriptor Cache or "
				"Guest TLB.\n", TT_MSG(ec));
		else if (BUS_ERROR(ec))
			pr_cont(": %s/ECC error in data read from NB: %s.\n",
				RRRR_MSG(ec), PP_MSG(ec));
		else if (MEM_ERROR(ec)) {
			u8 rrrr = (ec >> 4) & 0xf;

			if (rrrr >= 0x7)
				pr_cont(": %s error during data copyback.\n",
					RRRR_MSG(ec));
			else if (rrrr <= 0x1)
				pr_cont(": %s parity/ECC error during data "
					"access from L2.\n", RRRR_MSG(ec));
			else
				goto wrong_bu_mce;
		} else
			goto wrong_bu_mce;
	} else
		goto wrong_bu_mce;

	return;

wrong_bu_mce:
	pr_emerg(HW_ERR "Corrupted BU MCE info?\n");
}

static void amd_decode_ls_mce(struct mce *m)
{
	u32 ec  = m->status & 0xffff;
	u32 xec = (m->status >> 16) & 0xf;

	pr_emerg(HW_ERR "Load Store Error");

	if (xec == 0x0) {
		u8 rrrr = (ec >> 4) & 0xf;

		if (!BUS_ERROR(ec) || (rrrr != 0x3 && rrrr != 0x4))
			goto wrong_ls_mce;

		pr_cont(" during %s.\n", RRRR_MSG(ec));
	}
	return;

wrong_ls_mce:
	pr_emerg(HW_ERR "Corrupted LS MCE info?\n");
}

void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
{
	u32 ec   = m->status & 0xffff;
	u32 nbsh = (u32)(m->status >> 32);
	u32 nbsl = (u32)m->status;

	/*
	 * GART TLB error reporting is disabled by default. Bail out early.
	 */
	if (TLB_ERROR(ec) && !report_gart_errors)
		return;

	pr_emerg(HW_ERR "Northbridge Error, node %d", node_id);

	/*
	 * F10h, revD can disable ErrCpu[3:0] so check that first and also the
	 * value encoding has changed so interpret those differently
	 */
	if ((boot_cpu_data.x86 == 0x10) &&
	    (boot_cpu_data.x86_model > 7)) {
		if (nbsh & K8_NBSH_ERR_CPU_VAL)
			pr_cont(", core: %u\n", (u8)(nbsh & 0xf));
	} else {
		u8 assoc_cpus = nbsh & 0xf;

		if (assoc_cpus > 0)
			pr_cont(", core: %d", fls(assoc_cpus) - 1);

		pr_cont("\n");
	}

	pr_emerg(HW_ERR "%s.\n", EXT_ERR_MSG(nbsl));

	if (BUS_ERROR(ec) && nb_bus_decoder)
		nb_bus_decoder(node_id, m, nbcfg);
}
EXPORT_SYMBOL_GPL(amd_decode_nb_mce);

static void amd_decode_fr_mce(struct mce *m)
{
	/* we have only one error signature so match all fields at once. */
	if ((m->status & 0xffff) == 0x0f0f)
		pr_emerg(HW_ERR " FR Error: CPU Watchdog timer expire.\n");
	else
		pr_emerg(HW_ERR "Corrupted FR MCE info?\n");
}

static inline void amd_decode_err_code(u16 ec)
{
	if (TLB_ERROR(ec)) {
		pr_emerg(HW_ERR "Transaction: %s, Cache Level: %s\n",
			 TT_MSG(ec), LL_MSG(ec));
	} else if (MEM_ERROR(ec)) {
		pr_emerg(HW_ERR "Transaction: %s, Type: %s, Cache Level: %s\n",
			 RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
	} else if (BUS_ERROR(ec)) {
		pr_emerg(HW_ERR "Transaction: %s (%s), %s, Cache Level: %s, "
			 "Participating Processor: %s\n",
			  RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
			  PP_MSG(ec));
	} else
		pr_emerg(HW_ERR "Huh? Unknown MCE error 0x%x\n", ec);
}

int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
{
	struct mce *m = (struct mce *)data;
	int node, ecc;

	pr_emerg(HW_ERR "MC%d_STATUS: ", m->bank);

	pr_cont("%sorrected error, other errors lost: %s, "
		 "CPU context corrupt: %s",
		 ((m->status & MCI_STATUS_UC) ? "Unc"  : "C"),
		 ((m->status & MCI_STATUS_OVER) ? "yes"  : "no"),
		 ((m->status & MCI_STATUS_PCC) ? "yes" : "no"));

	/* do the two bits[14:13] together */
	ecc = (m->status >> 45) & 0x3;
	if (ecc)
		pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));

	pr_cont("\n");

	switch (m->bank) {
	case 0:
		amd_decode_dc_mce(m);
		break;

	case 1:
		amd_decode_ic_mce(m);
		break;

	case 2:
		amd_decode_bu_mce(m);
		break;

	case 3:
		amd_decode_ls_mce(m);
		break;

	case 4:
		node = amd_get_nb_id(m->extcpu);
		amd_decode_nb_mce(node, m, 0);
		break;

	case 5:
		amd_decode_fr_mce(m);
		break;

	default:
		break;
	}

	amd_decode_err_code(m->status & 0xffff);

	return NOTIFY_STOP;
}
EXPORT_SYMBOL_GPL(amd_decode_mce);

static struct notifier_block amd_mce_dec_nb = {
	.notifier_call	= amd_decode_mce,
};

static int __init mce_amd_init(void)
{
	/*
	 * We can decode MCEs for K8, F10h and F11h CPUs:
	 */
	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
		return 0;

	if (boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11)
		return 0;

	fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
	if (!fam_ops)
		return -ENOMEM;

	switch (boot_cpu_data.x86) {
	case 0xf:
		fam_ops->dc_mce = k8_dc_mce;
		fam_ops->ic_mce = k8_ic_mce;
		break;

	case 0x10:
		fam_ops->dc_mce = f10h_dc_mce;
		fam_ops->ic_mce = k8_ic_mce;
		break;

	case 0x14:
		fam_ops->dc_mce = f14h_dc_mce;
		fam_ops->ic_mce = f14h_ic_mce;
		break;

	default:
		printk(KERN_WARNING "Huh? What family is that: %d?!\n",
				    boot_cpu_data.x86);
		kfree(fam_ops);
		return -EINVAL;
	}

	atomic_notifier_chain_register(&x86_mce_decoder_chain, &amd_mce_dec_nb);

	return 0;
}
early_initcall(mce_amd_init);

#ifdef MODULE
static void __exit mce_amd_exit(void)
{
	atomic_notifier_chain_unregister(&x86_mce_decoder_chain, &amd_mce_dec_nb);
	kfree(fam_ops);
}

MODULE_DESCRIPTION("AMD MCE decoder");
MODULE_ALIAS("edac-mce-amd");
MODULE_LICENSE("GPL");
module_exit(mce_amd_exit);
#endif
Commit	Line	Data
b70ef010	1	#include <linux/module.h>
888ab8e6 BP	2	#include <linux/slab.h>
888ab8e6 BP	3
47ca08a4	4	#include "mce_amd.h"
b52401ce	5
888ab8e6 BP	6	static struct amd_decoder_ops *fam_ops;
888ab8e6 BP	7
549d042d	8	static bool report_gart_errors;
7cfd4a87	9	static void (nb_bus_decoder)(int node_id, struct mce m, u32 nbcfg);
549d042d BP	10
	11	void amd_report_gart_errors(bool v)
	12	{
	13	report_gart_errors = v;
	14	}
	15	EXPORT_SYMBOL_GPL(amd_report_gart_errors);
	16
7cfd4a87	17	void amd_register_ecc_decoder(void (f)(int, struct mce , u32))
549d042d BP	18	{
	19	nb_bus_decoder = f;
	20	}
	21	EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
	22
7cfd4a87	23	void amd_unregister_ecc_decoder(void (f)(int, struct mce , u32))
549d042d BP	24	{
	25	if (nb_bus_decoder) {
	26	WARN_ON(nb_bus_decoder != f);
	27
	28	nb_bus_decoder = NULL;
	29	}
	30	}
	31	EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
	32
b52401ce DT	33	/*
	34	* string representation for the different MCA reported error types, see F3x48
	35	* or MSR0000_0411.
	36	*/
6337583d BP	37
	38	/* transaction type */
	39	const char *tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
b70ef010	40	EXPORT_SYMBOL_GPL(tt_msgs);
b52401ce	41
6337583d BP	42	/* cache level */
6337583d BP	43	const char *ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
b70ef010	44	EXPORT_SYMBOL_GPL(ll_msgs);
b52401ce	45
6337583d	46	/* memory transaction type */
b52401ce	47	const char *rrrr_msgs[] = {
6337583d	48	"GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
b52401ce	49	};
b70ef010	50	EXPORT_SYMBOL_GPL(rrrr_msgs);
b52401ce	51
6337583d BP	52	/* participating processor */
6337583d BP	53	const char *pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
b70ef010	54	EXPORT_SYMBOL_GPL(pp_msgs);
b52401ce	55
6337583d BP	56	/* request timeout */
6337583d BP	57	const char *to_msgs[] = { "no timeout", "timed out" };
b70ef010	58	EXPORT_SYMBOL_GPL(to_msgs);
b52401ce	59
6337583d BP	60	/* memory or i/o */
6337583d BP	61	const char *ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
b70ef010	62	EXPORT_SYMBOL_GPL(ii_msgs);
b52401ce	63
1c43f2e2 BP	64	/*
	65	* Map the 4 or 5 (family-specific) bits of Extended Error code to the
	66	* string table.
	67	*/
	68	const char *ext_msgs[] = {
	69	"K8 ECC error", /* 0_0000b */
	70	"CRC error on link", /* 0_0001b */
	71	"Sync error packets on link", /* 0_0010b */
	72	"Master Abort during link operation", /* 0_0011b */
	73	"Target Abort during link operation", /* 0_0100b */
	74	"Invalid GART PTE entry during table walk", /* 0_0101b */
	75	"Unsupported atomic RMW command received", /* 0_0110b */
	76	"WDT error: NB transaction timeout", /* 0_0111b */
	77	"ECC/ChipKill ECC error", /* 0_1000b */
	78	"SVM DEV Error", /* 0_1001b */
	79	"Link Data error", /* 0_1010b */
	80	"Link/L3/Probe Filter Protocol error", /* 0_1011b */
	81	"NB Internal Arrays Parity error", /* 0_1100b */
	82	"DRAM Address/Control Parity error", /* 0_1101b */
	83	"Link Transmission error", /* 0_1110b */
	84	"GART/DEV Table Walk Data error" /* 0_1111b */
	85	"Res 0x100 error", /* 1_0000b */
	86	"Res 0x101 error", /* 1_0001b */
	87	"Res 0x102 error", /* 1_0010b */
	88	"Res 0x103 error", /* 1_0011b */
	89	"Res 0x104 error", /* 1_0100b */
	90	"Res 0x105 error", /* 1_0101b */
	91	"Res 0x106 error", /* 1_0110b */
	92	"Res 0x107 error", /* 1_0111b */
	93	"Res 0x108 error", /* 1_1000b */
	94	"Res 0x109 error", /* 1_1001b */
	95	"Res 0x10A error", /* 1_1010b */
	96	"Res 0x10B error", /* 1_1011b */
	97	"ECC error in L3 Cache Data", /* 1_1100b */
	98	"L3 Cache Tag error", /* 1_1101b */
	99	"L3 Cache LRU Parity error", /* 1_1110b */
	100	"Probe Filter error" /* 1_1111b */
b52401ce	101	};
b70ef010	102	EXPORT_SYMBOL_GPL(ext_msgs);
549d042d	103
888ab8e6	104	static bool f10h_dc_mce(u16 ec)
51966241	105	{
888ab8e6 BP	106	u8 r4 = (ec >> 4) & 0xf;
888ab8e6 BP	107	bool ret = false;
51966241	108
888ab8e6 BP	109	if (r4 == R4_GEN) {
	110	pr_cont("during data scrub.\n");
	111	return true;
	112	}
51966241	113
888ab8e6 BP	114	if (MEM_ERROR(ec)) {
	115	u8 ll = ec & 0x3;
	116	ret = true;
51966241	117
888ab8e6 BP	118	if (ll == LL_L2)
	119	pr_cont("during L1 linefill from L2.\n");
	120	else if (ll == LL_L1)
	121	pr_cont("Data/Tag %s error.\n", RRRR_MSG(ec));
	122	else
	123	ret = false;
	124	}
	125	return ret;
	126	}
51966241	127
888ab8e6 BP	128	static bool k8_dc_mce(u16 ec)
	129	{
	130	if (BUS_ERROR(ec)) {
	131	pr_cont("during system linefill.\n");
	132	return true;
	133	}
51966241	134
888ab8e6 BP	135	return f10h_dc_mce(ec);
	136	}
	137
	138	static bool f14h_dc_mce(u16 ec)
	139	{
	140	u8 r4 = (ec >> 4) & 0xf;
	141	u8 ll = ec & 0x3;
	142	u8 tt = (ec >> 2) & 0x3;
	143	u8 ii = tt;
	144	bool ret = true;
	145
	146	if (MEM_ERROR(ec)) {
	147
	148	if (tt != TT_DATA \|\| ll != LL_L1)
	149	return false;
	150
	151	switch (r4) {
	152	case R4_DRD:
	153	case R4_DWR:
	154	pr_cont("Data/Tag parity error due to %s.\n",
	155	(r4 == R4_DRD ? "load/hw prf" : "store"));
	156	break;
	157	case R4_EVICT:
	158	pr_cont("Copyback parity error on a tag miss.\n");
	159	break;
	160	case R4_SNOOP:
	161	pr_cont("Tag parity error during snoop.\n");
	162	break;
	163	default:
	164	ret = false;
	165	}
	166	} else if (BUS_ERROR(ec)) {
	167
	168	if ((ii != II_MEM && ii != II_IO) \|\| ll != LL_LG)
	169	return false;
	170
	171	pr_cont("System read data error on a ");
	172
	173	switch (r4) {
	174	case R4_RD:
	175	pr_cont("TLB reload.\n");
	176	break;
	177	case R4_DWR:
	178	pr_cont("store.\n");
	179	break;
	180	case R4_DRD:
	181	pr_cont("load.\n");
	182	break;
	183	default:
	184	ret = false;
	185	}
	186	} else {
	187	ret = false;
	188	}
	189
	190	return ret;
	191	}
	192
	193	static void amd_decode_dc_mce(struct mce *m)
	194	{
	195	u16 ec = m->status & 0xffff;
	196	u8 xec = (m->status >> 16) & 0xf;
	197
	198	pr_emerg(HW_ERR "Data Cache Error: ");
199
200	/* TLB error signatures are the same across families */
201	if (TLB_ERROR(ec)) {
202	u8 tt = (ec >> 2) & 0x3;
203
204	if (tt == TT_DATA) {
205	pr_cont("%s TLB %s.\n", LL_MSG(ec),
206	(xec ? "multimatch" : "parity error"));
207	return;
208	}
51966241 BP	209	else
51966241 BP	210	goto wrong_dc_mce;
888ab8e6 BP	211	}
	212
	213	if (!fam_ops->dc_mce(ec))
51966241 BP	214	goto wrong_dc_mce;
	215
	216	return;
	217
	218	wrong_dc_mce:
c9f281fd	219	pr_emerg(HW_ERR "Corrupted DC MCE info?\n");
51966241 BP	220	}
51966241 BP	221
dd53bce4	222	static bool k8_ic_mce(u16 ec)
ab5535e7	223	{
dd53bce4 BP	224	u8 ll = ec & 0x3;
	225	u8 r4 = (ec >> 4) & 0xf;
	226	bool ret = true;
ab5535e7	227
dd53bce4 BP	228	if (!MEM_ERROR(ec))
dd53bce4 BP	229	return false;
ab5535e7	230
dd53bce4 BP	231	if (ll == 0x2)
	232	pr_cont("during a linefill from L2.\n");
	233	else if (ll == 0x1) {
	234	switch (r4) {
	235	case R4_IRD:
	236	pr_cont("Parity error during data load.\n");
	237	break;
ab5535e7	238
dd53bce4 BP	239	case R4_EVICT:
	240	pr_cont("Copyback Parity/Victim error.\n");
	241	break;
	242
	243	case R4_SNOOP:
	244	pr_cont("Tag Snoop error.\n");
	245	break;
	246
	247	default:
	248	ret = false;
	249	break;
	250	}
ab5535e7	251	} else
dd53bce4	252	ret = false;
ab5535e7	253
dd53bce4 BP	254	return ret;
	255	}
	256
	257	static bool f14h_ic_mce(u16 ec)
	258	{
	259	u8 ll = ec & 0x3;
	260	u8 tt = (ec >> 2) & 0x3;
	261	u8 r4 = (ec >> 4) & 0xf;
	262	bool ret = true;
ab5535e7	263
dd53bce4 BP	264	if (MEM_ERROR(ec)) {
	265	if (tt != 0 \|\| ll != 1)
	266	ret = false;
	267
	268	if (r4 == R4_IRD)
	269	pr_cont("Data/tag array parity error for a tag hit.\n");
	270	else if (r4 == R4_SNOOP)
	271	pr_cont("Tag error during snoop/victimization.\n");
	272	else
	273	ret = false;
	274	}
	275	return ret;
	276	}
	277
	278	static void amd_decode_ic_mce(struct mce *m)
	279	{
	280	u16 ec = m->status & 0xffff;
	281	u8 xec = (m->status >> 16) & 0xf;
	282
	283	pr_emerg(HW_ERR "Instruction Cache Error: ");
	284
	285	if (TLB_ERROR(ec))
	286	pr_cont("%s TLB %s.\n", LL_MSG(ec),
	287	(xec ? "multimatch" : "parity error"));
	288	else if (BUS_ERROR(ec)) {
	289	bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT(58)));
	290
	291	pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
	292	} else if (fam_ops->ic_mce(ec))
	293	;
	294	else
	295	pr_emerg(HW_ERR "Corrupted IC MCE info?\n");
ab5535e7 BP	296	}
ab5535e7 BP	297
7cfd4a87	298	static void amd_decode_bu_mce(struct mce *m)
56cad2d6	299	{
7cfd4a87 BP	300	u32 ec = m->status & 0xffff;
7cfd4a87 BP	301	u32 xec = (m->status >> 16) & 0xf;
56cad2d6	302
c9f281fd	303	pr_emerg(HW_ERR "Bus Unit Error");
56cad2d6 BP	304
	305	if (xec == 0x1)
	306	pr_cont(" in the write data buffers.\n");
	307	else if (xec == 0x3)
	308	pr_cont(" in the victim data buffers.\n");
	309	else if (xec == 0x2 && MEM_ERROR(ec))
	310	pr_cont(": %s error in the L2 cache tags.\n", RRRR_MSG(ec));
	311	else if (xec == 0x0) {
	312	if (TLB_ERROR(ec))
	313	pr_cont(": %s error in a Page Descriptor Cache or "
	314	"Guest TLB.\n", TT_MSG(ec));
	315	else if (BUS_ERROR(ec))
	316	pr_cont(": %s/ECC error in data read from NB: %s.\n",
	317	RRRR_MSG(ec), PP_MSG(ec));
	318	else if (MEM_ERROR(ec)) {
	319	u8 rrrr = (ec >> 4) & 0xf;
	320
	321	if (rrrr >= 0x7)
	322	pr_cont(": %s error during data copyback.\n",
	323	RRRR_MSG(ec));
	324	else if (rrrr <= 0x1)
	325	pr_cont(": %s parity/ECC error during data "
	326	"access from L2.\n", RRRR_MSG(ec));
	327	else
	328	goto wrong_bu_mce;
	329	} else
	330	goto wrong_bu_mce;
	331	} else
	332	goto wrong_bu_mce;
	333
	334	return;
	335
	336	wrong_bu_mce:
c9f281fd	337	pr_emerg(HW_ERR "Corrupted BU MCE info?\n");
56cad2d6 BP	338	}
56cad2d6 BP	339
7cfd4a87	340	static void amd_decode_ls_mce(struct mce *m)
f9350efd	341	{
7cfd4a87 BP	342	u32 ec = m->status & 0xffff;
7cfd4a87 BP	343	u32 xec = (m->status >> 16) & 0xf;
f9350efd	344
c9f281fd	345	pr_emerg(HW_ERR "Load Store Error");
f9350efd BP	346
	347	if (xec == 0x0) {
	348	u8 rrrr = (ec >> 4) & 0xf;
	349
	350	if (!BUS_ERROR(ec) \|\| (rrrr != 0x3 && rrrr != 0x4))
	351	goto wrong_ls_mce;
	352
	353	pr_cont(" during %s.\n", RRRR_MSG(ec));
	354	}
	355	return;
	356
	357	wrong_ls_mce:
c9f281fd	358	pr_emerg(HW_ERR "Corrupted LS MCE info?\n");
f9350efd BP	359	}
f9350efd BP	360
7cfd4a87	361	void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg)
549d042d	362	{
7cfd4a87 BP	363	u32 ec = m->status & 0xffff;
	364	u32 nbsh = (u32)(m->status >> 32);
	365	u32 nbsl = (u32)m->status;
549d042d	366
256f7276 BP	367	/*
	368	* GART TLB error reporting is disabled by default. Bail out early.
	369	*/
	370	if (TLB_ERROR(ec) && !report_gart_errors)
	371	return;
	372
c9f281fd	373	pr_emerg(HW_ERR "Northbridge Error, node %d", node_id);
549d042d BP	374
	375	/*
	376	* F10h, revD can disable ErrCpu[3:0] so check that first and also the
	377	* value encoding has changed so interpret those differently
	378	*/
	379	if ((boot_cpu_data.x86 == 0x10) &&
cec7924f	380	(boot_cpu_data.x86_model > 7)) {
7cfd4a87 BP	381	if (nbsh & K8_NBSH_ERR_CPU_VAL)
7cfd4a87 BP	382	pr_cont(", core: %u\n", (u8)(nbsh & 0xf));
549d042d	383	} else {
7cfd4a87	384	u8 assoc_cpus = nbsh & 0xf;
5b89d2f9 BP	385
	386	if (assoc_cpus > 0)
	387	pr_cont(", core: %d", fls(assoc_cpus) - 1);
	388
	389	pr_cont("\n");
549d042d BP	390	}
549d042d BP	391
7cfd4a87	392	pr_emerg(HW_ERR "%s.\n", EXT_ERR_MSG(nbsl));
d93cc222 BP	393
d93cc222 BP	394	if (BUS_ERROR(ec) && nb_bus_decoder)
7cfd4a87	395	nb_bus_decoder(node_id, m, nbcfg);
d93cc222 BP	396	}
	397	EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
	398
7cfd4a87	399	static void amd_decode_fr_mce(struct mce *m)
53bd5fed BP	400	{
53bd5fed BP	401	/* we have only one error signature so match all fields at once. */
7cfd4a87	402	if ((m->status & 0xffff) == 0x0f0f)
c9f281fd	403	pr_emerg(HW_ERR " FR Error: CPU Watchdog timer expire.\n");
53bd5fed	404	else
c9f281fd	405	pr_emerg(HW_ERR "Corrupted FR MCE info?\n");
53bd5fed BP	406	}
53bd5fed BP	407
6337583d	408	static inline void amd_decode_err_code(u16 ec)
d93cc222	409	{
549d042d	410	if (TLB_ERROR(ec)) {
c9f281fd	411	pr_emerg(HW_ERR "Transaction: %s, Cache Level: %s\n",
549d042d BP	412	TT_MSG(ec), LL_MSG(ec));
549d042d BP	413	} else if (MEM_ERROR(ec)) {
6337583d	414	pr_emerg(HW_ERR "Transaction: %s, Type: %s, Cache Level: %s\n",
549d042d BP	415	RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
549d042d BP	416	} else if (BUS_ERROR(ec)) {
6337583d	417	pr_emerg(HW_ERR "Transaction: %s (%s), %s, Cache Level: %s, "
d93cc222 BP	418	"Participating Processor: %s\n",
	419	RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
	420	PP_MSG(ec));
	421	} else
c9f281fd	422	pr_emerg(HW_ERR "Huh? Unknown MCE error 0x%x\n", ec);
549d042d	423	}
549d042d	424
9cdeb404	425	int amd_decode_mce(struct notifier_block nb, unsigned long val, void data)
549d042d	426	{
fb253195	427	struct mce m = (struct mce )data;
b69b29de	428	int node, ecc;
549d042d	429
c9f281fd	430	pr_emerg(HW_ERR "MC%d_STATUS: ", m->bank);
549d042d	431
37b7370a	432	pr_cont("%sorrected error, other errors lost: %s, "
b69b29de BP	433	"CPU context corrupt: %s",
b69b29de BP	434	((m->status & MCI_STATUS_UC) ? "Unc" : "C"),
37b7370a	435	((m->status & MCI_STATUS_OVER) ? "yes" : "no"),
b69b29de	436	((m->status & MCI_STATUS_PCC) ? "yes" : "no"));
549d042d	437
b69b29de	438	/* do the two bits[14:13] together */
35d824b2	439	ecc = (m->status >> 45) & 0x3;
b69b29de BP	440	if (ecc)
	441	pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));
	442
	443	pr_cont("\n");
	444
51966241 BP	445	switch (m->bank) {
51966241 BP	446	case 0:
7cfd4a87	447	amd_decode_dc_mce(m);
51966241	448	break;
d93cc222	449
ab5535e7	450	case 1:
7cfd4a87	451	amd_decode_ic_mce(m);
ab5535e7 BP	452	break;
ab5535e7 BP	453
56cad2d6	454	case 2:
7cfd4a87	455	amd_decode_bu_mce(m);
56cad2d6 BP	456	break;
56cad2d6 BP	457
f9350efd	458	case 3:
7cfd4a87	459	amd_decode_ls_mce(m);
f9350efd BP	460	break;
f9350efd BP	461
51966241	462	case 4:
7cfd4a87 BP	463	node = amd_get_nb_id(m->extcpu);
7cfd4a87 BP	464	amd_decode_nb_mce(node, m, 0);
51966241 BP	465	break;
51966241 BP	466
53bd5fed	467	case 5:
7cfd4a87	468	amd_decode_fr_mce(m);
53bd5fed BP	469	break;
53bd5fed BP	470
51966241 BP	471	default:
51966241 BP	472	break;
b69b29de	473	}
51966241 BP	474
51966241 BP	475	amd_decode_err_code(m->status & 0xffff);
fb253195 BP	476
fb253195 BP	477	return NOTIFY_STOP;
549d042d	478	}
9cdeb404	479	EXPORT_SYMBOL_GPL(amd_decode_mce);
f436f8bb	480
fb253195 BP	481	static struct notifier_block amd_mce_dec_nb = {
	482	.notifier_call = amd_decode_mce,
	483	};
	484
f436f8bb IM	485	static int __init mce_amd_init(void)
	486	{
	487	/*
e045c291	488	* We can decode MCEs for K8, F10h and F11h CPUs:
f436f8bb	489	*/
e045c291 BP	490	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
	491	return 0;
	492
	493	if (boot_cpu_data.x86 < 0xf \|\| boot_cpu_data.x86 > 0x11)
	494	return 0;
	495
888ab8e6 BP	496	fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
	497	if (!fam_ops)
	498	return -ENOMEM;
	499
	500	switch (boot_cpu_data.x86) {
	501	case 0xf:
	502	fam_ops->dc_mce = k8_dc_mce;
dd53bce4	503	fam_ops->ic_mce = k8_ic_mce;
888ab8e6 BP	504	break;
	505
	506	case 0x10:
	507	fam_ops->dc_mce = f10h_dc_mce;
dd53bce4	508	fam_ops->ic_mce = k8_ic_mce;
888ab8e6 BP	509	break;
	510
	511	case 0x14:
	512	fam_ops->dc_mce = f14h_dc_mce;
dd53bce4	513	fam_ops->ic_mce = f14h_ic_mce;
888ab8e6 BP	514	break;
	515
	516	default:
	517	printk(KERN_WARNING "Huh? What family is that: %d?!\n",
	518	boot_cpu_data.x86);
	519	kfree(fam_ops);
	520	return -EINVAL;
	521	}
	522
e045c291	523	atomic_notifier_chain_register(&x86_mce_decoder_chain, &amd_mce_dec_nb);
f436f8bb IM	524
	525	return 0;
	526	}
	527	early_initcall(mce_amd_init);
0d18b2e3 BP	528
	529	#ifdef MODULE
	530	static void __exit mce_amd_exit(void)
	531	{
fb253195	532	atomic_notifier_chain_unregister(&x86_mce_decoder_chain, &amd_mce_dec_nb);
888ab8e6	533	kfree(fam_ops);
0d18b2e3 BP	534	}
	535
	536	MODULE_DESCRIPTION("AMD MCE decoder");
	537	MODULE_ALIAS("edac-mce-amd");
	538	MODULE_LICENSE("GPL");
	539	module_exit(mce_amd_exit);
	540	#endif