MCE, AMD: Dump CPU f/m/s triple with the error
[deliverable/linux.git] / drivers / edac / mce_amd.c
CommitLineData
b70ef010 1#include <linux/module.h>
888ab8e6
BP
2#include <linux/slab.h>
3
47ca08a4 4#include "mce_amd.h"
b52401ce 5
888ab8e6
BP
6static struct amd_decoder_ops *fam_ops;
7
2be64bfa 8static u8 xec_mask = 0xf;
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BP
9static u8 nb_err_cpumask = 0xf;
10
549d042d 11static bool report_gart_errors;
b0b07a2b 12static void (*nb_bus_decoder)(int node_id, struct mce *m);
549d042d
BP
13
14void amd_report_gart_errors(bool v)
15{
16 report_gart_errors = v;
17}
18EXPORT_SYMBOL_GPL(amd_report_gart_errors);
19
b0b07a2b 20void amd_register_ecc_decoder(void (*f)(int, struct mce *))
549d042d
BP
21{
22 nb_bus_decoder = f;
23}
24EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
25
b0b07a2b 26void amd_unregister_ecc_decoder(void (*f)(int, struct mce *))
549d042d
BP
27{
28 if (nb_bus_decoder) {
29 WARN_ON(nb_bus_decoder != f);
30
31 nb_bus_decoder = NULL;
32 }
33}
34EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
35
b52401ce
DT
36/*
37 * string representation for the different MCA reported error types, see F3x48
38 * or MSR0000_0411.
39 */
6337583d
BP
40
41/* transaction type */
ebe2aea8 42const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
b70ef010 43EXPORT_SYMBOL_GPL(tt_msgs);
b52401ce 44
6337583d 45/* cache level */
ebe2aea8 46const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
b70ef010 47EXPORT_SYMBOL_GPL(ll_msgs);
b52401ce 48
6337583d 49/* memory transaction type */
ebe2aea8 50const char * const rrrr_msgs[] = {
6337583d 51 "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
b52401ce 52};
b70ef010 53EXPORT_SYMBOL_GPL(rrrr_msgs);
b52401ce 54
6337583d 55/* participating processor */
ebe2aea8 56const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
b70ef010 57EXPORT_SYMBOL_GPL(pp_msgs);
b52401ce 58
6337583d 59/* request timeout */
ebe2aea8 60const char * const to_msgs[] = { "no timeout", "timed out" };
b70ef010 61EXPORT_SYMBOL_GPL(to_msgs);
b52401ce 62
6337583d 63/* memory or i/o */
ebe2aea8 64const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
b70ef010 65EXPORT_SYMBOL_GPL(ii_msgs);
b52401ce 66
f05c41a9 67static const char * const f15h_mc1_mce_desc[] = {
86039cd4
BP
68 "UC during a demand linefill from L2",
69 "Parity error during data load from IC",
70 "Parity error for IC valid bit",
71 "Main tag parity error",
72 "Parity error in prediction queue",
73 "PFB data/address parity error",
74 "Parity error in the branch status reg",
75 "PFB promotion address error",
76 "Tag error during probe/victimization",
77 "Parity error for IC probe tag valid bit",
78 "PFB non-cacheable bit parity error",
79 "PFB valid bit parity error", /* xec = 0xd */
6c1173a6 80 "Microcode Patch Buffer", /* xec = 010 */
86039cd4
BP
81 "uop queue",
82 "insn buffer",
83 "predecode buffer",
84 "fetch address FIFO"
85};
86
f05c41a9 87static const char * const f15h_mc2_mce_desc[] = {
70fdb494
BP
88 "Fill ECC error on data fills", /* xec = 0x4 */
89 "Fill parity error on insn fills",
90 "Prefetcher request FIFO parity error",
91 "PRQ address parity error",
92 "PRQ data parity error",
93 "WCC Tag ECC error",
94 "WCC Data ECC error",
95 "WCB Data parity error",
b64a99c1 96 "VB Data ECC or parity error",
70fdb494
BP
97 "L2 Tag ECC error", /* xec = 0x10 */
98 "Hard L2 Tag ECC error",
99 "Multiple hits on L2 tag",
100 "XAB parity error",
101 "PRB address parity error"
102};
103
f05c41a9 104static const char * const mc4_mce_desc[] = {
68782673
BP
105 "DRAM ECC error detected on the NB",
106 "CRC error detected on HT link",
107 "Link-defined sync error packets detected on HT link",
108 "HT Master abort",
109 "HT Target abort",
110 "Invalid GART PTE entry during GART table walk",
111 "Unsupported atomic RMW received from an IO link",
112 "Watchdog timeout due to lack of progress",
113 "DRAM ECC error detected on the NB",
114 "SVM DMA Exclusion Vector error",
115 "HT data error detected on link",
116 "Protocol error (link, L3, probe filter)",
117 "NB internal arrays parity error",
118 "DRAM addr/ctl signals parity error",
119 "IO link transmission error",
120 "L3 data cache ECC error", /* xec = 0x1c */
121 "L3 cache tag error",
122 "L3 LRU parity bits error",
123 "ECC Error in the Probe Filter directory"
124};
125
f05c41a9 126static const char * const mc5_mce_desc[] = {
8259a7e5
BP
127 "CPU Watchdog timer expire",
128 "Wakeup array dest tag",
129 "AG payload array",
130 "EX payload array",
131 "IDRF array",
132 "Retire dispatch queue",
133 "Mapper checkpoint array",
134 "Physical register file EX0 port",
135 "Physical register file EX1 port",
136 "Physical register file AG0 port",
137 "Physical register file AG1 port",
138 "Flag register file",
ae615b4b 139 "DE error occurred"
8259a7e5
BP
140};
141
f05c41a9 142static bool f12h_mc0_mce(u16 ec, u8 xec)
51966241 143{
888ab8e6 144 bool ret = false;
51966241 145
888ab8e6 146 if (MEM_ERROR(ec)) {
62452882 147 u8 ll = LL(ec);
888ab8e6 148 ret = true;
51966241 149
888ab8e6
BP
150 if (ll == LL_L2)
151 pr_cont("during L1 linefill from L2.\n");
152 else if (ll == LL_L1)
62452882 153 pr_cont("Data/Tag %s error.\n", R4_MSG(ec));
888ab8e6
BP
154 else
155 ret = false;
156 }
157 return ret;
158}
51966241 159
f05c41a9 160static bool f10h_mc0_mce(u16 ec, u8 xec)
9be0bb10 161{
62452882 162 if (R4(ec) == R4_GEN && LL(ec) == LL_L1) {
9be0bb10
BP
163 pr_cont("during data scrub.\n");
164 return true;
165 }
f05c41a9 166 return f12h_mc0_mce(ec, xec);
9be0bb10
BP
167}
168
f05c41a9 169static bool k8_mc0_mce(u16 ec, u8 xec)
888ab8e6
BP
170{
171 if (BUS_ERROR(ec)) {
172 pr_cont("during system linefill.\n");
173 return true;
174 }
51966241 175
f05c41a9 176 return f10h_mc0_mce(ec, xec);
888ab8e6
BP
177}
178
f05c41a9 179static bool f14h_mc0_mce(u16 ec, u8 xec)
888ab8e6 180{
62452882 181 u8 r4 = R4(ec);
888ab8e6
BP
182 bool ret = true;
183
184 if (MEM_ERROR(ec)) {
185
62452882 186 if (TT(ec) != TT_DATA || LL(ec) != LL_L1)
888ab8e6
BP
187 return false;
188
189 switch (r4) {
190 case R4_DRD:
191 case R4_DWR:
192 pr_cont("Data/Tag parity error due to %s.\n",
193 (r4 == R4_DRD ? "load/hw prf" : "store"));
194 break;
195 case R4_EVICT:
196 pr_cont("Copyback parity error on a tag miss.\n");
197 break;
198 case R4_SNOOP:
199 pr_cont("Tag parity error during snoop.\n");
200 break;
201 default:
202 ret = false;
203 }
204 } else if (BUS_ERROR(ec)) {
205
62452882 206 if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG)
888ab8e6
BP
207 return false;
208
209 pr_cont("System read data error on a ");
210
211 switch (r4) {
212 case R4_RD:
213 pr_cont("TLB reload.\n");
214 break;
215 case R4_DWR:
216 pr_cont("store.\n");
217 break;
218 case R4_DRD:
219 pr_cont("load.\n");
220 break;
221 default:
222 ret = false;
223 }
224 } else {
225 ret = false;
226 }
227
228 return ret;
229}
230
f05c41a9 231static bool f15h_mc0_mce(u16 ec, u8 xec)
25a4f8b0
BP
232{
233 bool ret = true;
234
235 if (MEM_ERROR(ec)) {
236
237 switch (xec) {
238 case 0x0:
239 pr_cont("Data Array access error.\n");
240 break;
241
242 case 0x1:
243 pr_cont("UC error during a linefill from L2/NB.\n");
244 break;
245
246 case 0x2:
247 case 0x11:
248 pr_cont("STQ access error.\n");
249 break;
250
251 case 0x3:
252 pr_cont("SCB access error.\n");
253 break;
254
255 case 0x10:
256 pr_cont("Tag error.\n");
257 break;
258
259 case 0x12:
260 pr_cont("LDQ access error.\n");
261 break;
262
263 default:
264 ret = false;
265 }
266 } else if (BUS_ERROR(ec)) {
267
268 if (!xec)
344f0a06 269 pr_cont("System Read Data Error.\n");
25a4f8b0 270 else
344f0a06 271 pr_cont(" Internal error condition type %d.\n", xec);
25a4f8b0
BP
272 } else
273 ret = false;
274
275 return ret;
276}
277
f05c41a9 278static void decode_mc0_mce(struct mce *m)
888ab8e6 279{
62452882
BP
280 u16 ec = EC(m->status);
281 u8 xec = XEC(m->status, xec_mask);
888ab8e6 282
f05c41a9 283 pr_emerg(HW_ERR "MC0 Error: ");
888ab8e6
BP
284
285 /* TLB error signatures are the same across families */
286 if (TLB_ERROR(ec)) {
62452882 287 if (TT(ec) == TT_DATA) {
888ab8e6 288 pr_cont("%s TLB %s.\n", LL_MSG(ec),
25a4f8b0
BP
289 ((xec == 2) ? "locked miss"
290 : (xec ? "multimatch" : "parity")));
888ab8e6
BP
291 return;
292 }
f05c41a9 293 } else if (fam_ops->mc0_mce(ec, xec))
25a4f8b0
BP
294 ;
295 else
f05c41a9 296 pr_emerg(HW_ERR "Corrupted MC0 MCE info?\n");
51966241
BP
297}
298
f05c41a9 299static bool k8_mc1_mce(u16 ec, u8 xec)
ab5535e7 300{
62452882 301 u8 ll = LL(ec);
dd53bce4 302 bool ret = true;
ab5535e7 303
dd53bce4
BP
304 if (!MEM_ERROR(ec))
305 return false;
ab5535e7 306
dd53bce4
BP
307 if (ll == 0x2)
308 pr_cont("during a linefill from L2.\n");
309 else if (ll == 0x1) {
62452882 310 switch (R4(ec)) {
dd53bce4
BP
311 case R4_IRD:
312 pr_cont("Parity error during data load.\n");
313 break;
ab5535e7 314
dd53bce4
BP
315 case R4_EVICT:
316 pr_cont("Copyback Parity/Victim error.\n");
317 break;
318
319 case R4_SNOOP:
320 pr_cont("Tag Snoop error.\n");
321 break;
322
323 default:
324 ret = false;
325 break;
326 }
ab5535e7 327 } else
dd53bce4 328 ret = false;
ab5535e7 329
dd53bce4
BP
330 return ret;
331}
332
f05c41a9 333static bool f14h_mc1_mce(u16 ec, u8 xec)
dd53bce4 334{
62452882 335 u8 r4 = R4(ec);
dd53bce4 336 bool ret = true;
ab5535e7 337
dd53bce4 338 if (MEM_ERROR(ec)) {
62452882 339 if (TT(ec) != 0 || LL(ec) != 1)
dd53bce4
BP
340 ret = false;
341
342 if (r4 == R4_IRD)
343 pr_cont("Data/tag array parity error for a tag hit.\n");
344 else if (r4 == R4_SNOOP)
345 pr_cont("Tag error during snoop/victimization.\n");
346 else
347 ret = false;
348 }
349 return ret;
350}
351
f05c41a9 352static bool f15h_mc1_mce(u16 ec, u8 xec)
86039cd4
BP
353{
354 bool ret = true;
355
356 if (!MEM_ERROR(ec))
357 return false;
358
359 switch (xec) {
360 case 0x0 ... 0xa:
f05c41a9 361 pr_cont("%s.\n", f15h_mc1_mce_desc[xec]);
86039cd4
BP
362 break;
363
364 case 0xd:
f05c41a9 365 pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]);
86039cd4
BP
366 break;
367
6c1173a6 368 case 0x10:
f05c41a9 369 pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]);
6c1173a6
BP
370 break;
371
372 case 0x11 ... 0x14:
f05c41a9 373 pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]);
86039cd4
BP
374 break;
375
376 default:
377 ret = false;
378 }
379 return ret;
380}
381
f05c41a9 382static void decode_mc1_mce(struct mce *m)
dd53bce4 383{
62452882
BP
384 u16 ec = EC(m->status);
385 u8 xec = XEC(m->status, xec_mask);
dd53bce4 386
f05c41a9 387 pr_emerg(HW_ERR "MC1 Error: ");
dd53bce4
BP
388
389 if (TLB_ERROR(ec))
390 pr_cont("%s TLB %s.\n", LL_MSG(ec),
391 (xec ? "multimatch" : "parity error"));
392 else if (BUS_ERROR(ec)) {
525906bc 393 bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));
dd53bce4
BP
394
395 pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
f05c41a9 396 } else if (fam_ops->mc1_mce(ec, xec))
dd53bce4
BP
397 ;
398 else
f05c41a9 399 pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n");
ab5535e7
BP
400}
401
f05c41a9 402static void decode_mc2_mce(struct mce *m)
56cad2d6 403{
62452882
BP
404 u16 ec = EC(m->status);
405 u8 xec = XEC(m->status, xec_mask);
56cad2d6 406
f05c41a9 407 pr_emerg(HW_ERR "MC2 Error");
56cad2d6
BP
408
409 if (xec == 0x1)
410 pr_cont(" in the write data buffers.\n");
411 else if (xec == 0x3)
412 pr_cont(" in the victim data buffers.\n");
413 else if (xec == 0x2 && MEM_ERROR(ec))
62452882 414 pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec));
56cad2d6
BP
415 else if (xec == 0x0) {
416 if (TLB_ERROR(ec))
417 pr_cont(": %s error in a Page Descriptor Cache or "
418 "Guest TLB.\n", TT_MSG(ec));
419 else if (BUS_ERROR(ec))
420 pr_cont(": %s/ECC error in data read from NB: %s.\n",
62452882 421 R4_MSG(ec), PP_MSG(ec));
56cad2d6 422 else if (MEM_ERROR(ec)) {
62452882 423 u8 r4 = R4(ec);
56cad2d6 424
62452882 425 if (r4 >= 0x7)
56cad2d6 426 pr_cont(": %s error during data copyback.\n",
62452882
BP
427 R4_MSG(ec));
428 else if (r4 <= 0x1)
56cad2d6 429 pr_cont(": %s parity/ECC error during data "
62452882 430 "access from L2.\n", R4_MSG(ec));
56cad2d6 431 else
f05c41a9 432 goto wrong_mc2_mce;
56cad2d6 433 } else
f05c41a9 434 goto wrong_mc2_mce;
56cad2d6 435 } else
f05c41a9 436 goto wrong_mc2_mce;
56cad2d6
BP
437
438 return;
439
f05c41a9
BP
440 wrong_mc2_mce:
441 pr_emerg(HW_ERR "Corrupted MC2 MCE info?\n");
56cad2d6
BP
442}
443
f05c41a9 444static void decode_f15_mc2_mce(struct mce *m)
70fdb494 445{
62452882
BP
446 u16 ec = EC(m->status);
447 u8 xec = XEC(m->status, xec_mask);
70fdb494 448
f05c41a9 449 pr_emerg(HW_ERR "MC2 Error: ");
70fdb494
BP
450
451 if (TLB_ERROR(ec)) {
452 if (xec == 0x0)
453 pr_cont("Data parity TLB read error.\n");
454 else if (xec == 0x1)
455 pr_cont("Poison data provided for TLB fill.\n");
456 else
f05c41a9 457 goto wrong_f15_mc2_mce;
70fdb494
BP
458 } else if (BUS_ERROR(ec)) {
459 if (xec > 2)
f05c41a9 460 goto wrong_f15_mc2_mce;
70fdb494
BP
461
462 pr_cont("Error during attempted NB data read.\n");
463 } else if (MEM_ERROR(ec)) {
464 switch (xec) {
465 case 0x4 ... 0xc:
f05c41a9 466 pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]);
70fdb494
BP
467 break;
468
469 case 0x10 ... 0x14:
f05c41a9 470 pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]);
70fdb494
BP
471 break;
472
473 default:
f05c41a9 474 goto wrong_f15_mc2_mce;
70fdb494
BP
475 }
476 }
477
478 return;
479
f05c41a9
BP
480 wrong_f15_mc2_mce:
481 pr_emerg(HW_ERR "Corrupted MC2 MCE info?\n");
70fdb494
BP
482}
483
f05c41a9 484static void decode_mc3_mce(struct mce *m)
f9350efd 485{
62452882
BP
486 u16 ec = EC(m->status);
487 u8 xec = XEC(m->status, xec_mask);
ded50623 488
b18434ca 489 if (boot_cpu_data.x86 >= 0x14) {
f05c41a9 490 pr_emerg("You shouldn't be seeing MC3 MCE on this cpu family,"
ded50623
BP
491 " please report on LKML.\n");
492 return;
493 }
f9350efd 494
f05c41a9 495 pr_emerg(HW_ERR "MC3 Error");
f9350efd
BP
496
497 if (xec == 0x0) {
62452882 498 u8 r4 = R4(ec);
f9350efd 499
ded50623 500 if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
f05c41a9 501 goto wrong_mc3_mce;
f9350efd 502
62452882 503 pr_cont(" during %s.\n", R4_MSG(ec));
ded50623 504 } else
f05c41a9 505 goto wrong_mc3_mce;
ded50623 506
f9350efd
BP
507 return;
508
f05c41a9
BP
509 wrong_mc3_mce:
510 pr_emerg(HW_ERR "Corrupted MC3 MCE info?\n");
f9350efd
BP
511}
512
f05c41a9 513static void decode_mc4_mce(struct mce *m)
5ce88f6e 514{
68782673
BP
515 struct cpuinfo_x86 *c = &boot_cpu_data;
516 int node_id = amd_get_nb_id(m->extcpu);
517 u16 ec = EC(m->status);
518 u8 xec = XEC(m->status, 0x1f);
519 u8 offset = 0;
5ce88f6e 520
f05c41a9 521 pr_emerg(HW_ERR "MC4 Error (node %d): ", node_id);
5ce88f6e 522
68782673
BP
523 switch (xec) {
524 case 0x0 ... 0xe:
5ce88f6e 525
68782673
BP
526 /* special handling for DRAM ECCs */
527 if (xec == 0x0 || xec == 0x8) {
528 /* no ECCs on F11h */
529 if (c->x86 == 0x11)
f05c41a9 530 goto wrong_mc4_mce;
5ce88f6e 531
f05c41a9 532 pr_cont("%s.\n", mc4_mce_desc[xec]);
5ce88f6e 533
68782673
BP
534 if (nb_bus_decoder)
535 nb_bus_decoder(node_id, m);
536 return;
537 }
5ce88f6e
BP
538 break;
539
540 case 0xf:
541 if (TLB_ERROR(ec))
542 pr_cont("GART Table Walk data error.\n");
543 else if (BUS_ERROR(ec))
544 pr_cont("DMA Exclusion Vector Table Walk error.\n");
545 else
f05c41a9 546 goto wrong_mc4_mce;
68782673 547 return;
5ce88f6e 548
05cd667d
BP
549 case 0x19:
550 if (boot_cpu_data.x86 == 0x15)
551 pr_cont("Compute Unit Data Error.\n");
552 else
f05c41a9 553 goto wrong_mc4_mce;
68782673 554 return;
05cd667d 555
5ce88f6e 556 case 0x1c ... 0x1f:
68782673 557 offset = 13;
5ce88f6e
BP
558 break;
559
560 default:
f05c41a9 561 goto wrong_mc4_mce;
68782673 562 }
5ce88f6e 563
f05c41a9 564 pr_cont("%s.\n", mc4_mce_desc[xec - offset]);
5ce88f6e
BP
565 return;
566
f05c41a9
BP
567 wrong_mc4_mce:
568 pr_emerg(HW_ERR "Corrupted MC4 MCE info?\n");
d93cc222 569}
d93cc222 570
f05c41a9 571static void decode_mc5_mce(struct mce *m)
53bd5fed 572{
8259a7e5 573 struct cpuinfo_x86 *c = &boot_cpu_data;
62452882 574 u8 xec = XEC(m->status, xec_mask);
8259a7e5
BP
575
576 if (c->x86 == 0xf || c->x86 == 0x11)
f05c41a9 577 goto wrong_mc5_mce;
fe4ea262 578
f05c41a9 579 pr_emerg(HW_ERR "MC5 Error: ");
8259a7e5
BP
580
581 if (xec == 0x0 || xec == 0xc)
f05c41a9 582 pr_cont("%s.\n", mc5_mce_desc[xec]);
8259a7e5 583 else if (xec < 0xd)
f05c41a9 584 pr_cont("%s parity error.\n", mc5_mce_desc[xec]);
8259a7e5 585 else
f05c41a9 586 goto wrong_mc5_mce;
8259a7e5
BP
587
588 return;
fe4ea262 589
f05c41a9
BP
590 wrong_mc5_mce:
591 pr_emerg(HW_ERR "Corrupted MC5 MCE info?\n");
53bd5fed
BP
592}
593
f05c41a9 594static void decode_mc6_mce(struct mce *m)
b8f85c47 595{
62452882 596 u8 xec = XEC(m->status, xec_mask);
b8f85c47 597
f05c41a9 598 pr_emerg(HW_ERR "MC6 Error: ");
b8f85c47
BP
599
600 switch (xec) {
601 case 0x1:
602 pr_cont("Free List");
603 break;
604
605 case 0x2:
606 pr_cont("Physical Register File");
607 break;
608
609 case 0x3:
610 pr_cont("Retire Queue");
611 break;
612
613 case 0x4:
614 pr_cont("Scheduler table");
615 break;
616
617 case 0x5:
618 pr_cont("Status Register File");
619 break;
620
621 default:
f05c41a9 622 goto wrong_mc6_mce;
b8f85c47
BP
623 break;
624 }
625
626 pr_cont(" parity error.\n");
627
628 return;
629
f05c41a9
BP
630 wrong_mc6_mce:
631 pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n");
b8f85c47
BP
632}
633
6337583d 634static inline void amd_decode_err_code(u16 ec)
d93cc222 635{
fa7ae8cc
BP
636
637 pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec));
638
639 if (BUS_ERROR(ec))
640 pr_cont(", mem/io: %s", II_MSG(ec));
641 else
642 pr_cont(", tx: %s", TT_MSG(ec));
643
644 if (MEM_ERROR(ec) || BUS_ERROR(ec)) {
645 pr_cont(", mem-tx: %s", R4_MSG(ec));
646
647 if (BUS_ERROR(ec))
648 pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));
649 }
650
651 pr_cont("\n");
549d042d 652}
549d042d 653
5ce88f6e
BP
654/*
655 * Filter out unwanted MCE signatures here.
656 */
657static bool amd_filter_mce(struct mce *m)
658{
659 u8 xec = (m->status >> 16) & 0x1f;
660
661 /*
662 * NB GART TLB error reporting is disabled by default.
663 */
664 if (m->bank == 4 && xec == 0x5 && !report_gart_errors)
665 return true;
666
667 return false;
668}
669
9cdeb404 670int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
549d042d 671{
fb253195 672 struct mce *m = (struct mce *)data;
f89f8388 673 struct cpuinfo_x86 *c = &cpu_data(m->extcpu);
b0b07a2b 674 int ecc;
549d042d 675
5ce88f6e
BP
676 if (amd_filter_mce(m))
677 return NOTIFY_STOP;
678
f89f8388
BP
679 pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s",
680 m->extcpu,
681 c->x86, c->x86_model, c->x86_mask,
682 m->bank,
fa7ae8cc
BP
683 ((m->status & MCI_STATUS_OVER) ? "Over" : "-"),
684 ((m->status & MCI_STATUS_UC) ? "UE" : "CE"),
685 ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"),
686 ((m->status & MCI_STATUS_PCC) ? "PCC" : "-"),
687 ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"));
549d042d 688
fa7ae8cc
BP
689 if (c->x86 == 0x15)
690 pr_cont("|%s|%s",
50adbbd8
RD
691 ((m->status & BIT_64(44)) ? "Deferred" : "-"),
692 ((m->status & BIT_64(43)) ? "Poison" : "-"));
549d042d 693
b69b29de 694 /* do the two bits[14:13] together */
35d824b2 695 ecc = (m->status >> 45) & 0x3;
b69b29de 696 if (ecc)
fa7ae8cc
BP
697 pr_cont("|%sECC", ((ecc == 2) ? "C" : "U"));
698
699 pr_cont("]: 0x%016llx\n", m->status);
b69b29de 700
086be786 701 if (m->status & MCI_STATUS_ADDRV)
f89f8388 702 pr_emerg(HW_ERR "MC%d_ADDR: 0x%016llx\n", m->bank, m->addr);
b69b29de 703
51966241
BP
704 switch (m->bank) {
705 case 0:
f05c41a9 706 decode_mc0_mce(m);
51966241 707 break;
d93cc222 708
ab5535e7 709 case 1:
f05c41a9 710 decode_mc1_mce(m);
ab5535e7
BP
711 break;
712
56cad2d6 713 case 2:
fa7ae8cc 714 if (c->x86 == 0x15)
f05c41a9 715 decode_f15_mc2_mce(m);
70fdb494 716 else
f05c41a9 717 decode_mc2_mce(m);
56cad2d6
BP
718 break;
719
f9350efd 720 case 3:
f05c41a9 721 decode_mc3_mce(m);
f9350efd
BP
722 break;
723
51966241 724 case 4:
f05c41a9 725 decode_mc4_mce(m);
51966241
BP
726 break;
727
53bd5fed 728 case 5:
f05c41a9 729 decode_mc5_mce(m);
53bd5fed
BP
730 break;
731
b8f85c47 732 case 6:
f05c41a9 733 decode_mc6_mce(m);
b8f85c47
BP
734 break;
735
51966241
BP
736 default:
737 break;
b69b29de 738 }
51966241
BP
739
740 amd_decode_err_code(m->status & 0xffff);
fb253195
BP
741
742 return NOTIFY_STOP;
549d042d 743}
9cdeb404 744EXPORT_SYMBOL_GPL(amd_decode_mce);
f436f8bb 745
fb253195
BP
746static struct notifier_block amd_mce_dec_nb = {
747 .notifier_call = amd_decode_mce,
748};
749
f436f8bb
IM
750static int __init mce_amd_init(void)
751{
bad11e03
BP
752 struct cpuinfo_x86 *c = &boot_cpu_data;
753
754 if (c->x86_vendor != X86_VENDOR_AMD)
e045c291
BP
755 return 0;
756
ec3e82d6 757 if (c->x86 < 0xf || c->x86 > 0x15)
e045c291
BP
758 return 0;
759
888ab8e6
BP
760 fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
761 if (!fam_ops)
762 return -ENOMEM;
763
bad11e03 764 switch (c->x86) {
888ab8e6 765 case 0xf:
f05c41a9
BP
766 fam_ops->mc0_mce = k8_mc0_mce;
767 fam_ops->mc1_mce = k8_mc1_mce;
888ab8e6
BP
768 break;
769
770 case 0x10:
f05c41a9
BP
771 fam_ops->mc0_mce = f10h_mc0_mce;
772 fam_ops->mc1_mce = k8_mc1_mce;
888ab8e6
BP
773 break;
774
f0157b3a 775 case 0x11:
f05c41a9
BP
776 fam_ops->mc0_mce = k8_mc0_mce;
777 fam_ops->mc1_mce = k8_mc1_mce;
f0157b3a
BP
778 break;
779
9be0bb10 780 case 0x12:
f05c41a9
BP
781 fam_ops->mc0_mce = f12h_mc0_mce;
782 fam_ops->mc1_mce = k8_mc1_mce;
9be0bb10
BP
783 break;
784
888ab8e6 785 case 0x14:
5ce88f6e 786 nb_err_cpumask = 0x3;
f05c41a9
BP
787 fam_ops->mc0_mce = f14h_mc0_mce;
788 fam_ops->mc1_mce = f14h_mc1_mce;
888ab8e6
BP
789 break;
790
2be64bfa
BP
791 case 0x15:
792 xec_mask = 0x1f;
f05c41a9
BP
793 fam_ops->mc0_mce = f15h_mc0_mce;
794 fam_ops->mc1_mce = f15h_mc1_mce;
2be64bfa
BP
795 break;
796
888ab8e6 797 default:
ec3e82d6 798 printk(KERN_WARNING "Huh? What family is it: 0x%x?!\n", c->x86);
888ab8e6
BP
799 kfree(fam_ops);
800 return -EINVAL;
801 }
802
9530d608
BP
803 pr_info("MCE: In-kernel MCE decoding enabled.\n");
804
3653ada5 805 mce_register_decode_chain(&amd_mce_dec_nb);
f436f8bb
IM
806
807 return 0;
808}
809early_initcall(mce_amd_init);
0d18b2e3
BP
810
811#ifdef MODULE
812static void __exit mce_amd_exit(void)
813{
3653ada5 814 mce_unregister_decode_chain(&amd_mce_dec_nb);
888ab8e6 815 kfree(fam_ops);
0d18b2e3
BP
816}
817
818MODULE_DESCRIPTION("AMD MCE decoder");
819MODULE_ALIAS("edac-mce-amd");
820MODULE_LICENSE("GPL");
821module_exit(mce_amd_exit);
822#endif
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