[deliverable/linux.git] / drivers / edac / mce_amd.h

#ifndef _EDAC_MCE_AMD_H
#define _EDAC_MCE_AMD_H

#include <linux/notifier.h>

#include <asm/mce.h>

#define EC(x)				((x) & 0xffff)
#define XEC(x, mask)			(((x) >> 16) & mask)

#define LOW_SYNDROME(x)			(((x) >> 15) & 0xff)
#define HIGH_SYNDROME(x)		(((x) >> 24) & 0xff)

#define TLB_ERROR(x)			(((x) & 0xFFF0) == 0x0010)
#define MEM_ERROR(x)			(((x) & 0xFF00) == 0x0100)
#define BUS_ERROR(x)			(((x) & 0xF800) == 0x0800)
#define INT_ERROR(x)			(((x) & 0xF4FF) == 0x0400)

#define TT(x)				(((x) >> 2) & 0x3)
#define TT_MSG(x)			tt_msgs[TT(x)]
#define II(x)				(((x) >> 2) & 0x3)
#define II_MSG(x)			ii_msgs[II(x)]
#define LL(x)				((x) & 0x3)
#define LL_MSG(x)			ll_msgs[LL(x)]
#define TO(x)				(((x) >> 8) & 0x1)
#define TO_MSG(x)			to_msgs[TO(x)]
#define PP(x)				(((x) >> 9) & 0x3)
#define PP_MSG(x)			pp_msgs[PP(x)]
#define UU(x)				(((x) >> 8) & 0x3)
#define UU_MSG(x)			uu_msgs[UU(x)]

#define R4(x)				(((x) >> 4) & 0xf)
#define R4_MSG(x)			((R4(x) < 9) ?  rrrr_msgs[R4(x)] : "Wrong R4!")

extern const char * const pp_msgs[];

enum tt_ids {
	TT_INSTR = 0,
	TT_DATA,
	TT_GEN,
	TT_RESV,
};

enum ll_ids {
	LL_RESV = 0,
	LL_L1,
	LL_L2,
	LL_LG,
};

enum ii_ids {
	II_MEM = 0,
	II_RESV,
	II_IO,
	II_GEN,
};

enum rrrr_ids {
	R4_GEN	= 0,
	R4_RD,
	R4_WR,
	R4_DRD,
	R4_DWR,
	R4_IRD,
	R4_PREF,
	R4_EVICT,
	R4_SNOOP,
};

/*
 * per-family decoder ops
 */
struct amd_decoder_ops {
	bool (*mc0_mce)(u16, u8);
	bool (*mc1_mce)(u16, u8);
	bool (*mc2_mce)(u16, u8);
};

void amd_report_gart_errors(bool);
void amd_register_ecc_decoder(void (*f)(int, struct mce *));
void amd_unregister_ecc_decoder(void (*f)(int, struct mce *));
int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data);

#endif /* _EDAC_MCE_AMD_H */
Commit	Line	Data
549d042d BP	1	#ifndef _EDAC_MCE_AMD_H
	2	#define _EDAC_MCE_AMD_H
	3
9cdeb404 BP	4	#include <linux/notifier.h>
9cdeb404 BP	5
549d042d BP	6	#include <asm/mce.h>
549d042d BP	7
62452882 BP	8	#define EC(x) ((x) & 0xffff)
62452882 BP	9	#define XEC(x, mask) (((x) >> 16) & mask)
5110dbde	10
b70ef010 BP	11	#define LOW_SYNDROME(x) (((x) >> 15) & 0xff)
	12	#define HIGH_SYNDROME(x) (((x) >> 24) & 0xff)
	13
	14	#define TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010)
	15	#define MEM_ERROR(x) (((x) & 0xFF00) == 0x0100)
	16	#define BUS_ERROR(x) (((x) & 0xF800) == 0x0800)
980eec8b	17	#define INT_ERROR(x) (((x) & 0xF4FF) == 0x0400)
b70ef010 BP	18
	19	#define TT(x) (((x) >> 2) & 0x3)
	20	#define TT_MSG(x) tt_msgs[TT(x)]
	21	#define II(x) (((x) >> 2) & 0x3)
	22	#define II_MSG(x) ii_msgs[II(x)]
62452882	23	#define LL(x) ((x) & 0x3)
b70ef010	24	#define LL_MSG(x) ll_msgs[LL(x)]
b70ef010 BP	25	#define TO(x) (((x) >> 8) & 0x1)
	26	#define TO_MSG(x) to_msgs[TO(x)]
	27	#define PP(x) (((x) >> 9) & 0x3)
	28	#define PP_MSG(x) pp_msgs[PP(x)]
980eec8b JS	29	#define UU(x) (((x) >> 8) & 0x3)
980eec8b JS	30	#define UU_MSG(x) uu_msgs[UU(x)]
b70ef010	31
62452882 BP	32	#define R4(x) (((x) >> 4) & 0xf)
62452882 BP	33	#define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!")
6337583d	34
0f08669e BP	35	extern const char * const pp_msgs[];
0f08669e BP	36
888ab8e6 BP	37	enum tt_ids {
	38	TT_INSTR = 0,
	39	TT_DATA,
	40	TT_GEN,
	41	TT_RESV,
	42	};
	43
	44	enum ll_ids {
	45	LL_RESV = 0,
	46	LL_L1,
	47	LL_L2,
	48	LL_LG,
	49	};
	50
	51	enum ii_ids {
	52	II_MEM = 0,
	53	II_RESV,
	54	II_IO,
	55	II_GEN,
	56	};
	57
	58	enum rrrr_ids {
	59	R4_GEN = 0,
	60	R4_RD,
	61	R4_WR,
	62	R4_DRD,
	63	R4_DWR,
	64	R4_IRD,
	65	R4_PREF,
	66	R4_EVICT,
	67	R4_SNOOP,
	68	};
	69
888ab8e6 BP	70	/*
	71	* per-family decoder ops
	72	*/
	73	struct amd_decoder_ops {
f05c41a9 BP	74	bool (*mc0_mce)(u16, u8);
f05c41a9 BP	75	bool (*mc1_mce)(u16, u8);
4a73d3de	76	bool (*mc2_mce)(u16, u8);
888ab8e6 BP	77	};
888ab8e6 BP	78
549d042d	79	void amd_report_gart_errors(bool);
b0b07a2b BP	80	void amd_register_ecc_decoder(void (f)(int, struct mce ));
b0b07a2b BP	81	void amd_unregister_ecc_decoder(void (f)(int, struct mce ));
9cdeb404	82	int amd_decode_mce(struct notifier_block nb, unsigned long val, void data);
549d042d BP	83
549d042d BP	84	#endif /* _EDAC_MCE_AMD_H */