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a9a753d5 DJ |
1 | /* |
2 | * Freescale MPC85xx Memory Controller kenel module | |
3 | * | |
4 | * Author: Dave Jiang <djiang@mvista.com> | |
5 | * | |
6 | * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | * | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/ctype.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/mod_devicetable.h> | |
19 | #include <linux/edac.h> | |
20 | ||
21 | #include <linux/of_platform.h> | |
22 | #include <linux/of_device.h> | |
a9a753d5 DJ |
23 | #include "edac_module.h" |
24 | #include "edac_core.h" | |
25 | #include "mpc85xx_edac.h" | |
26 | ||
27 | static int edac_dev_idx; | |
28 | static int edac_pci_idx; | |
29 | static int edac_mc_idx; | |
30 | ||
31 | static u32 orig_ddr_err_disable; | |
32 | static u32 orig_ddr_err_sbe; | |
33 | ||
34 | /* | |
35 | * PCI Err defines | |
36 | */ | |
37 | #ifdef CONFIG_PCI | |
38 | static u32 orig_pci_err_cap_dr; | |
39 | static u32 orig_pci_err_en; | |
40 | #endif | |
41 | ||
42 | static u32 orig_l2_err_disable; | |
43 | static u32 orig_hid1; | |
44 | ||
a9a753d5 DJ |
45 | /************************ MC SYSFS parts ***********************************/ |
46 | ||
47 | static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci, | |
48 | char *data) | |
49 | { | |
50 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
51 | return sprintf(data, "0x%08x", | |
52 | in_be32(pdata->mc_vbase + | |
53 | MPC85XX_MC_DATA_ERR_INJECT_HI)); | |
54 | } | |
55 | ||
56 | static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci, | |
57 | char *data) | |
58 | { | |
59 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
60 | return sprintf(data, "0x%08x", | |
61 | in_be32(pdata->mc_vbase + | |
62 | MPC85XX_MC_DATA_ERR_INJECT_LO)); | |
63 | } | |
64 | ||
65 | static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data) | |
66 | { | |
67 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
68 | return sprintf(data, "0x%08x", | |
69 | in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); | |
70 | } | |
71 | ||
72 | static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci, | |
73 | const char *data, size_t count) | |
74 | { | |
75 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
76 | if (isdigit(*data)) { | |
77 | out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, | |
78 | simple_strtoul(data, NULL, 0)); | |
79 | return count; | |
80 | } | |
81 | return 0; | |
82 | } | |
83 | ||
84 | static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci, | |
85 | const char *data, size_t count) | |
86 | { | |
87 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
88 | if (isdigit(*data)) { | |
89 | out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO, | |
90 | simple_strtoul(data, NULL, 0)); | |
91 | return count; | |
92 | } | |
93 | return 0; | |
94 | } | |
95 | ||
96 | static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci, | |
97 | const char *data, size_t count) | |
98 | { | |
99 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
100 | if (isdigit(*data)) { | |
101 | out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT, | |
102 | simple_strtoul(data, NULL, 0)); | |
103 | return count; | |
104 | } | |
105 | return 0; | |
106 | } | |
107 | ||
108 | static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = { | |
109 | { | |
110 | .attr = { | |
111 | .name = "inject_data_hi", | |
112 | .mode = (S_IRUGO | S_IWUSR) | |
113 | }, | |
114 | .show = mpc85xx_mc_inject_data_hi_show, | |
115 | .store = mpc85xx_mc_inject_data_hi_store}, | |
116 | { | |
117 | .attr = { | |
118 | .name = "inject_data_lo", | |
119 | .mode = (S_IRUGO | S_IWUSR) | |
120 | }, | |
121 | .show = mpc85xx_mc_inject_data_lo_show, | |
122 | .store = mpc85xx_mc_inject_data_lo_store}, | |
123 | { | |
124 | .attr = { | |
125 | .name = "inject_ctrl", | |
126 | .mode = (S_IRUGO | S_IWUSR) | |
127 | }, | |
128 | .show = mpc85xx_mc_inject_ctrl_show, | |
129 | .store = mpc85xx_mc_inject_ctrl_store}, | |
130 | ||
131 | /* End of list */ | |
132 | { | |
133 | .attr = {.name = NULL} | |
134 | } | |
135 | }; | |
136 | ||
137 | static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci) | |
138 | { | |
139 | mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes; | |
140 | } | |
141 | ||
142 | /**************************** PCI Err device ***************************/ | |
143 | #ifdef CONFIG_PCI | |
144 | ||
145 | static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) | |
146 | { | |
147 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; | |
148 | u32 err_detect; | |
149 | ||
150 | err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); | |
151 | ||
152 | /* master aborts can happen during PCI config cycles */ | |
153 | if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { | |
154 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); | |
155 | return; | |
156 | } | |
157 | ||
158 | printk(KERN_ERR "PCI error(s) detected\n"); | |
159 | printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect); | |
160 | ||
161 | printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n", | |
162 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); | |
163 | printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n", | |
164 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); | |
165 | printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n", | |
166 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); | |
167 | printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n", | |
168 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); | |
169 | printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n", | |
170 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); | |
171 | ||
172 | /* clear error bits */ | |
173 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); | |
174 | ||
175 | if (err_detect & PCI_EDE_PERR_MASK) | |
176 | edac_pci_handle_pe(pci, pci->ctl_name); | |
177 | ||
178 | if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) | |
179 | edac_pci_handle_npe(pci, pci->ctl_name); | |
180 | } | |
181 | ||
182 | static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) | |
183 | { | |
184 | struct edac_pci_ctl_info *pci = dev_id; | |
185 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; | |
186 | u32 err_detect; | |
187 | ||
188 | err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); | |
189 | ||
190 | if (!err_detect) | |
191 | return IRQ_NONE; | |
192 | ||
193 | mpc85xx_pci_check(pci); | |
194 | ||
195 | return IRQ_HANDLED; | |
196 | } | |
197 | ||
f87bd330 DJ |
198 | static int __devinit mpc85xx_pci_err_probe(struct of_device *op, |
199 | const struct of_device_id *match) | |
a9a753d5 DJ |
200 | { |
201 | struct edac_pci_ctl_info *pci; | |
202 | struct mpc85xx_pci_pdata *pdata; | |
f87bd330 | 203 | struct resource r; |
a9a753d5 DJ |
204 | int res = 0; |
205 | ||
f87bd330 | 206 | if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) |
a9a753d5 DJ |
207 | return -ENOMEM; |
208 | ||
209 | pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err"); | |
210 | if (!pci) | |
211 | return -ENOMEM; | |
212 | ||
213 | pdata = pci->pvt_info; | |
214 | pdata->name = "mpc85xx_pci_err"; | |
215 | pdata->irq = NO_IRQ; | |
f87bd330 DJ |
216 | dev_set_drvdata(&op->dev, pci); |
217 | pci->dev = &op->dev; | |
a9a753d5 DJ |
218 | pci->mod_name = EDAC_MOD_STR; |
219 | pci->ctl_name = pdata->name; | |
f87bd330 | 220 | pci->dev_name = op->dev.bus_id; |
a9a753d5 DJ |
221 | |
222 | if (edac_op_state == EDAC_OPSTATE_POLL) | |
223 | pci->edac_check = mpc85xx_pci_check; | |
224 | ||
225 | pdata->edac_idx = edac_pci_idx++; | |
226 | ||
f87bd330 DJ |
227 | res = of_address_to_resource(op->node, 0, &r); |
228 | if (res) { | |
a9a753d5 DJ |
229 | printk(KERN_ERR "%s: Unable to get resource for " |
230 | "PCI err regs\n", __func__); | |
231 | goto err; | |
232 | } | |
233 | ||
f87bd330 DJ |
234 | /* we only need the error registers */ |
235 | r.start += 0xe00; | |
236 | ||
237 | if (!devm_request_mem_region(&op->dev, r.start, | |
238 | r.end - r.start + 1, pdata->name)) { | |
a9a753d5 DJ |
239 | printk(KERN_ERR "%s: Error while requesting mem region\n", |
240 | __func__); | |
241 | res = -EBUSY; | |
242 | goto err; | |
243 | } | |
244 | ||
f87bd330 DJ |
245 | pdata->pci_vbase = devm_ioremap(&op->dev, r.start, |
246 | r.end - r.start + 1); | |
a9a753d5 DJ |
247 | if (!pdata->pci_vbase) { |
248 | printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__); | |
249 | res = -ENOMEM; | |
250 | goto err; | |
251 | } | |
252 | ||
253 | orig_pci_err_cap_dr = | |
254 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); | |
255 | ||
256 | /* PCI master abort is expected during config cycles */ | |
257 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); | |
258 | ||
259 | orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); | |
260 | ||
261 | /* disable master abort reporting */ | |
262 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); | |
263 | ||
264 | /* clear error bits */ | |
265 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); | |
266 | ||
267 | if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { | |
268 | debugf3("%s(): failed edac_pci_add_device()\n", __func__); | |
269 | goto err; | |
270 | } | |
271 | ||
272 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
f87bd330 DJ |
273 | pdata->irq = irq_of_parse_and_map(op->node, 0); |
274 | res = devm_request_irq(&op->dev, pdata->irq, | |
a9a753d5 DJ |
275 | mpc85xx_pci_isr, IRQF_DISABLED, |
276 | "[EDAC] PCI err", pci); | |
277 | if (res < 0) { | |
278 | printk(KERN_ERR | |
279 | "%s: Unable to requiest irq %d for " | |
280 | "MPC85xx PCI err\n", __func__, pdata->irq); | |
f87bd330 | 281 | irq_dispose_mapping(pdata->irq); |
a9a753d5 DJ |
282 | res = -ENODEV; |
283 | goto err2; | |
284 | } | |
285 | ||
286 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n", | |
287 | pdata->irq); | |
288 | } | |
289 | ||
f87bd330 | 290 | devres_remove_group(&op->dev, mpc85xx_pci_err_probe); |
a9a753d5 DJ |
291 | debugf3("%s(): success\n", __func__); |
292 | printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n"); | |
293 | ||
294 | return 0; | |
295 | ||
296 | err2: | |
f87bd330 | 297 | edac_pci_del_device(&op->dev); |
a9a753d5 DJ |
298 | err: |
299 | edac_pci_free_ctl_info(pci); | |
f87bd330 | 300 | devres_release_group(&op->dev, mpc85xx_pci_err_probe); |
a9a753d5 DJ |
301 | return res; |
302 | } | |
303 | ||
f87bd330 | 304 | static int mpc85xx_pci_err_remove(struct of_device *op) |
a9a753d5 | 305 | { |
f87bd330 | 306 | struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev); |
a9a753d5 DJ |
307 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; |
308 | ||
309 | debugf0("%s()\n", __func__); | |
310 | ||
311 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, | |
312 | orig_pci_err_cap_dr); | |
313 | ||
314 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en); | |
315 | ||
316 | edac_pci_del_device(pci->dev); | |
317 | ||
318 | if (edac_op_state == EDAC_OPSTATE_INT) | |
319 | irq_dispose_mapping(pdata->irq); | |
320 | ||
321 | edac_pci_free_ctl_info(pci); | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
f87bd330 DJ |
326 | static struct of_device_id mpc85xx_pci_err_of_match[] = { |
327 | { | |
328 | .compatible = "fsl,mpc8540-pcix", | |
329 | }, | |
330 | { | |
331 | .compatible = "fsl,mpc8540-pci", | |
332 | }, | |
333 | {}, | |
334 | }; | |
335 | ||
336 | static struct of_platform_driver mpc85xx_pci_err_driver = { | |
337 | .owner = THIS_MODULE, | |
338 | .name = "mpc85xx_pci_err", | |
339 | .match_table = mpc85xx_pci_err_of_match, | |
a9a753d5 DJ |
340 | .probe = mpc85xx_pci_err_probe, |
341 | .remove = __devexit_p(mpc85xx_pci_err_remove), | |
342 | .driver = { | |
f87bd330 DJ |
343 | .name = "mpc85xx_pci_err", |
344 | .owner = THIS_MODULE, | |
345 | }, | |
a9a753d5 DJ |
346 | }; |
347 | ||
348 | #endif /* CONFIG_PCI */ | |
349 | ||
350 | /**************************** L2 Err device ***************************/ | |
351 | ||
352 | /************************ L2 SYSFS parts ***********************************/ | |
353 | ||
354 | static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info | |
355 | *edac_dev, char *data) | |
356 | { | |
357 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
358 | return sprintf(data, "0x%08x", | |
359 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI)); | |
360 | } | |
361 | ||
362 | static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info | |
363 | *edac_dev, char *data) | |
364 | { | |
365 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
366 | return sprintf(data, "0x%08x", | |
367 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO)); | |
368 | } | |
369 | ||
370 | static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info | |
371 | *edac_dev, char *data) | |
372 | { | |
373 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
374 | return sprintf(data, "0x%08x", | |
375 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL)); | |
376 | } | |
377 | ||
378 | static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info | |
379 | *edac_dev, const char *data, | |
380 | size_t count) | |
381 | { | |
382 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
383 | if (isdigit(*data)) { | |
384 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI, | |
385 | simple_strtoul(data, NULL, 0)); | |
386 | return count; | |
387 | } | |
388 | return 0; | |
389 | } | |
390 | ||
391 | static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info | |
392 | *edac_dev, const char *data, | |
393 | size_t count) | |
394 | { | |
395 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
396 | if (isdigit(*data)) { | |
397 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO, | |
398 | simple_strtoul(data, NULL, 0)); | |
399 | return count; | |
400 | } | |
401 | return 0; | |
402 | } | |
403 | ||
404 | static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info | |
405 | *edac_dev, const char *data, | |
406 | size_t count) | |
407 | { | |
408 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
409 | if (isdigit(*data)) { | |
410 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL, | |
411 | simple_strtoul(data, NULL, 0)); | |
412 | return count; | |
413 | } | |
414 | return 0; | |
415 | } | |
416 | ||
417 | static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = { | |
418 | { | |
419 | .attr = { | |
420 | .name = "inject_data_hi", | |
421 | .mode = (S_IRUGO | S_IWUSR) | |
422 | }, | |
423 | .show = mpc85xx_l2_inject_data_hi_show, | |
424 | .store = mpc85xx_l2_inject_data_hi_store}, | |
425 | { | |
426 | .attr = { | |
427 | .name = "inject_data_lo", | |
428 | .mode = (S_IRUGO | S_IWUSR) | |
429 | }, | |
430 | .show = mpc85xx_l2_inject_data_lo_show, | |
431 | .store = mpc85xx_l2_inject_data_lo_store}, | |
432 | { | |
433 | .attr = { | |
434 | .name = "inject_ctrl", | |
435 | .mode = (S_IRUGO | S_IWUSR) | |
436 | }, | |
437 | .show = mpc85xx_l2_inject_ctrl_show, | |
438 | .store = mpc85xx_l2_inject_ctrl_store}, | |
439 | ||
440 | /* End of list */ | |
441 | { | |
442 | .attr = {.name = NULL} | |
443 | } | |
444 | }; | |
445 | ||
446 | static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info | |
447 | *edac_dev) | |
448 | { | |
449 | edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes; | |
450 | } | |
451 | ||
452 | /***************************** L2 ops ***********************************/ | |
453 | ||
454 | static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev) | |
455 | { | |
456 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
457 | u32 err_detect; | |
458 | ||
459 | err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); | |
460 | ||
461 | if (!(err_detect & L2_EDE_MASK)) | |
462 | return; | |
463 | ||
464 | printk(KERN_ERR "ECC Error in CPU L2 cache\n"); | |
465 | printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect); | |
466 | printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n", | |
467 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI)); | |
468 | printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n", | |
469 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO)); | |
470 | printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n", | |
471 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC)); | |
472 | printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n", | |
473 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR)); | |
474 | printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n", | |
475 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR)); | |
476 | ||
477 | /* clear error detect register */ | |
478 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect); | |
479 | ||
480 | if (err_detect & L2_EDE_CE_MASK) | |
481 | edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); | |
482 | ||
483 | if (err_detect & L2_EDE_UE_MASK) | |
484 | edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); | |
485 | } | |
486 | ||
487 | static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id) | |
488 | { | |
489 | struct edac_device_ctl_info *edac_dev = dev_id; | |
490 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
491 | u32 err_detect; | |
492 | ||
493 | err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); | |
494 | ||
495 | if (!(err_detect & L2_EDE_MASK)) | |
496 | return IRQ_NONE; | |
497 | ||
498 | mpc85xx_l2_check(edac_dev); | |
499 | ||
500 | return IRQ_HANDLED; | |
501 | } | |
502 | ||
503 | static int __devinit mpc85xx_l2_err_probe(struct of_device *op, | |
504 | const struct of_device_id *match) | |
505 | { | |
506 | struct edac_device_ctl_info *edac_dev; | |
507 | struct mpc85xx_l2_pdata *pdata; | |
508 | struct resource r; | |
509 | int res; | |
510 | ||
511 | if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL)) | |
512 | return -ENOMEM; | |
513 | ||
514 | edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), | |
515 | "cpu", 1, "L", 1, 2, NULL, 0, | |
516 | edac_dev_idx); | |
517 | if (!edac_dev) { | |
518 | devres_release_group(&op->dev, mpc85xx_l2_err_probe); | |
519 | return -ENOMEM; | |
520 | } | |
521 | ||
522 | pdata = edac_dev->pvt_info; | |
523 | pdata->name = "mpc85xx_l2_err"; | |
524 | pdata->irq = NO_IRQ; | |
525 | edac_dev->dev = &op->dev; | |
526 | dev_set_drvdata(edac_dev->dev, edac_dev); | |
527 | edac_dev->ctl_name = pdata->name; | |
528 | edac_dev->dev_name = pdata->name; | |
529 | ||
530 | res = of_address_to_resource(op->node, 0, &r); | |
531 | if (res) { | |
532 | printk(KERN_ERR "%s: Unable to get resource for " | |
533 | "L2 err regs\n", __func__); | |
534 | goto err; | |
535 | } | |
536 | ||
537 | /* we only need the error registers */ | |
538 | r.start += 0xe00; | |
539 | ||
540 | if (!devm_request_mem_region(&op->dev, r.start, | |
541 | r.end - r.start + 1, pdata->name)) { | |
542 | printk(KERN_ERR "%s: Error while requesting mem region\n", | |
543 | __func__); | |
544 | res = -EBUSY; | |
545 | goto err; | |
546 | } | |
547 | ||
548 | pdata->l2_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1); | |
549 | if (!pdata->l2_vbase) { | |
550 | printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__); | |
551 | res = -ENOMEM; | |
552 | goto err; | |
553 | } | |
554 | ||
555 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0); | |
556 | ||
557 | orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS); | |
558 | ||
559 | /* clear the err_dis */ | |
560 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0); | |
561 | ||
562 | edac_dev->mod_name = EDAC_MOD_STR; | |
563 | ||
564 | if (edac_op_state == EDAC_OPSTATE_POLL) | |
565 | edac_dev->edac_check = mpc85xx_l2_check; | |
566 | ||
567 | mpc85xx_set_l2_sysfs_attributes(edac_dev); | |
568 | ||
569 | pdata->edac_idx = edac_dev_idx++; | |
570 | ||
571 | if (edac_device_add_device(edac_dev) > 0) { | |
572 | debugf3("%s(): failed edac_device_add_device()\n", __func__); | |
573 | goto err; | |
574 | } | |
575 | ||
576 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
577 | pdata->irq = irq_of_parse_and_map(op->node, 0); | |
578 | res = devm_request_irq(&op->dev, pdata->irq, | |
579 | mpc85xx_l2_isr, IRQF_DISABLED, | |
580 | "[EDAC] L2 err", edac_dev); | |
581 | if (res < 0) { | |
582 | printk(KERN_ERR | |
583 | "%s: Unable to requiest irq %d for " | |
584 | "MPC85xx L2 err\n", __func__, pdata->irq); | |
585 | irq_dispose_mapping(pdata->irq); | |
586 | res = -ENODEV; | |
587 | goto err2; | |
588 | } | |
589 | ||
590 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n", | |
591 | pdata->irq); | |
592 | ||
593 | edac_dev->op_state = OP_RUNNING_INTERRUPT; | |
594 | ||
595 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK); | |
596 | } | |
597 | ||
598 | devres_remove_group(&op->dev, mpc85xx_l2_err_probe); | |
599 | ||
600 | debugf3("%s(): success\n", __func__); | |
601 | printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n"); | |
602 | ||
603 | return 0; | |
604 | ||
605 | err2: | |
606 | edac_device_del_device(&op->dev); | |
607 | err: | |
608 | devres_release_group(&op->dev, mpc85xx_l2_err_probe); | |
609 | edac_device_free_ctl_info(edac_dev); | |
610 | return res; | |
611 | } | |
612 | ||
613 | static int mpc85xx_l2_err_remove(struct of_device *op) | |
614 | { | |
615 | struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev); | |
616 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
617 | ||
618 | debugf0("%s()\n", __func__); | |
619 | ||
620 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
621 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0); | |
622 | irq_dispose_mapping(pdata->irq); | |
623 | } | |
624 | ||
625 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable); | |
626 | edac_device_del_device(&op->dev); | |
627 | edac_device_free_ctl_info(edac_dev); | |
628 | return 0; | |
629 | } | |
630 | ||
631 | static struct of_device_id mpc85xx_l2_err_of_match[] = { | |
632 | { | |
633 | .compatible = "fsl,8540-l2-cache-controller", | |
634 | }, | |
635 | { | |
636 | .compatible = "fsl,8541-l2-cache-controller", | |
637 | }, | |
638 | { | |
639 | .compatible = "fsl,8544-l2-cache-controller", | |
640 | }, | |
641 | { | |
642 | .compatible = "fsl,8548-l2-cache-controller", | |
643 | }, | |
644 | { | |
645 | .compatible = "fsl,8555-l2-cache-controller", | |
646 | }, | |
647 | { | |
648 | .compatible = "fsl,8568-l2-cache-controller", | |
649 | }, | |
650 | {}, | |
651 | }; | |
652 | ||
653 | static struct of_platform_driver mpc85xx_l2_err_driver = { | |
654 | .owner = THIS_MODULE, | |
655 | .name = "mpc85xx_l2_err", | |
656 | .match_table = mpc85xx_l2_err_of_match, | |
657 | .probe = mpc85xx_l2_err_probe, | |
658 | .remove = mpc85xx_l2_err_remove, | |
659 | .driver = { | |
660 | .name = "mpc85xx_l2_err", | |
661 | .owner = THIS_MODULE, | |
662 | }, | |
663 | }; | |
664 | ||
665 | /**************************** MC Err device ***************************/ | |
666 | ||
667 | static void mpc85xx_mc_check(struct mem_ctl_info *mci) | |
668 | { | |
669 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
670 | struct csrow_info *csrow; | |
671 | u32 err_detect; | |
672 | u32 syndrome; | |
673 | u32 err_addr; | |
674 | u32 pfn; | |
675 | int row_index; | |
676 | ||
677 | err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); | |
678 | if (err_detect) | |
679 | return; | |
680 | ||
681 | mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n", | |
682 | err_detect); | |
683 | ||
684 | /* no more processing if not ECC bit errors */ | |
685 | if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { | |
686 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); | |
687 | return; | |
688 | } | |
689 | ||
690 | syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC); | |
691 | err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS); | |
692 | pfn = err_addr >> PAGE_SHIFT; | |
693 | ||
694 | for (row_index = 0; row_index < mci->nr_csrows; row_index++) { | |
695 | csrow = &mci->csrows[row_index]; | |
696 | if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page)) | |
697 | break; | |
698 | } | |
699 | ||
700 | mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data High: %#8.8x\n", | |
701 | in_be32(pdata->mc_vbase + | |
702 | MPC85XX_MC_CAPTURE_DATA_HI)); | |
703 | mpc85xx_mc_printk(mci, KERN_ERR, "Capture Data Low: %#8.8x\n", | |
704 | in_be32(pdata->mc_vbase + | |
705 | MPC85XX_MC_CAPTURE_DATA_LO)); | |
706 | mpc85xx_mc_printk(mci, KERN_ERR, "syndrome: %#8.8x\n", syndrome); | |
707 | mpc85xx_mc_printk(mci, KERN_ERR, "err addr: %#8.8x\n", err_addr); | |
708 | mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn); | |
709 | ||
710 | /* we are out of range */ | |
711 | if (row_index == mci->nr_csrows) | |
712 | mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n"); | |
713 | ||
714 | if (err_detect & DDR_EDE_SBE) | |
715 | edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK, | |
716 | syndrome, row_index, 0, mci->ctl_name); | |
717 | ||
718 | if (err_detect & DDR_EDE_MBE) | |
719 | edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK, | |
720 | row_index, mci->ctl_name); | |
721 | ||
722 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); | |
723 | } | |
724 | ||
725 | static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id) | |
726 | { | |
727 | struct mem_ctl_info *mci = dev_id; | |
728 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
729 | u32 err_detect; | |
730 | ||
731 | err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); | |
732 | if (!err_detect) | |
733 | return IRQ_NONE; | |
734 | ||
735 | mpc85xx_mc_check(mci); | |
736 | ||
737 | return IRQ_HANDLED; | |
738 | } | |
739 | ||
740 | static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci) | |
741 | { | |
742 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
743 | struct csrow_info *csrow; | |
744 | u32 sdram_ctl; | |
745 | u32 sdtype; | |
746 | enum mem_type mtype; | |
747 | u32 cs_bnds; | |
748 | int index; | |
749 | ||
750 | sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); | |
751 | ||
752 | sdtype = sdram_ctl & DSC_SDTYPE_MASK; | |
753 | if (sdram_ctl & DSC_RD_EN) { | |
754 | switch (sdtype) { | |
755 | case DSC_SDTYPE_DDR: | |
756 | mtype = MEM_RDDR; | |
757 | break; | |
758 | case DSC_SDTYPE_DDR2: | |
759 | mtype = MEM_RDDR2; | |
760 | break; | |
761 | default: | |
762 | mtype = MEM_UNKNOWN; | |
763 | break; | |
764 | } | |
765 | } else { | |
766 | switch (sdtype) { | |
767 | case DSC_SDTYPE_DDR: | |
768 | mtype = MEM_DDR; | |
769 | break; | |
770 | case DSC_SDTYPE_DDR2: | |
771 | mtype = MEM_DDR2; | |
772 | break; | |
773 | default: | |
774 | mtype = MEM_UNKNOWN; | |
775 | break; | |
776 | } | |
777 | } | |
778 | ||
779 | for (index = 0; index < mci->nr_csrows; index++) { | |
780 | u32 start; | |
781 | u32 end; | |
782 | ||
783 | csrow = &mci->csrows[index]; | |
784 | cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 + | |
785 | (index * MPC85XX_MC_CS_BNDS_OFS)); | |
786 | start = (cs_bnds & 0xfff0000) << 4; | |
787 | end = ((cs_bnds & 0xfff) << 20); | |
788 | if (start) | |
789 | start |= 0xfffff; | |
790 | if (end) | |
791 | end |= 0xfffff; | |
792 | ||
793 | if (start == end) | |
794 | continue; /* not populated */ | |
795 | ||
796 | csrow->first_page = start >> PAGE_SHIFT; | |
797 | csrow->last_page = end >> PAGE_SHIFT; | |
798 | csrow->nr_pages = csrow->last_page + 1 - csrow->first_page; | |
799 | csrow->grain = 8; | |
800 | csrow->mtype = mtype; | |
801 | csrow->dtype = DEV_UNKNOWN; | |
802 | if (sdram_ctl & DSC_X32_EN) | |
803 | csrow->dtype = DEV_X32; | |
804 | csrow->edac_mode = EDAC_SECDED; | |
805 | } | |
806 | } | |
807 | ||
808 | static int __devinit mpc85xx_mc_err_probe(struct of_device *op, | |
809 | const struct of_device_id *match) | |
810 | { | |
811 | struct mem_ctl_info *mci; | |
812 | struct mpc85xx_mc_pdata *pdata; | |
813 | struct resource r; | |
814 | u32 sdram_ctl; | |
815 | int res; | |
816 | ||
817 | if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL)) | |
818 | return -ENOMEM; | |
819 | ||
820 | mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx); | |
821 | if (!mci) { | |
822 | devres_release_group(&op->dev, mpc85xx_mc_err_probe); | |
823 | return -ENOMEM; | |
824 | } | |
825 | ||
826 | pdata = mci->pvt_info; | |
827 | pdata->name = "mpc85xx_mc_err"; | |
828 | pdata->irq = NO_IRQ; | |
829 | mci->dev = &op->dev; | |
830 | pdata->edac_idx = edac_mc_idx++; | |
831 | dev_set_drvdata(mci->dev, mci); | |
832 | mci->ctl_name = pdata->name; | |
833 | mci->dev_name = pdata->name; | |
834 | ||
835 | res = of_address_to_resource(op->node, 0, &r); | |
836 | if (res) { | |
837 | printk(KERN_ERR "%s: Unable to get resource for MC err regs\n", | |
838 | __func__); | |
839 | goto err; | |
840 | } | |
841 | ||
842 | if (!devm_request_mem_region(&op->dev, r.start, | |
843 | r.end - r.start + 1, pdata->name)) { | |
844 | printk(KERN_ERR "%s: Error while requesting mem region\n", | |
845 | __func__); | |
846 | res = -EBUSY; | |
847 | goto err; | |
848 | } | |
849 | ||
850 | pdata->mc_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1); | |
851 | if (!pdata->mc_vbase) { | |
852 | printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__); | |
853 | res = -ENOMEM; | |
854 | goto err; | |
855 | } | |
856 | ||
857 | sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); | |
858 | if (!(sdram_ctl & DSC_ECC_EN)) { | |
859 | /* no ECC */ | |
860 | printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__); | |
861 | res = -ENODEV; | |
862 | goto err; | |
863 | } | |
864 | ||
865 | debugf3("%s(): init mci\n", __func__); | |
866 | mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | | |
867 | MEM_FLAG_DDR | MEM_FLAG_DDR2; | |
868 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
869 | mci->edac_cap = EDAC_FLAG_SECDED; | |
870 | mci->mod_name = EDAC_MOD_STR; | |
871 | mci->mod_ver = MPC85XX_REVISION; | |
872 | ||
873 | if (edac_op_state == EDAC_OPSTATE_POLL) | |
874 | mci->edac_check = mpc85xx_mc_check; | |
875 | ||
876 | mci->ctl_page_to_phys = NULL; | |
877 | ||
878 | mci->scrub_mode = SCRUB_SW_SRC; | |
879 | ||
880 | mpc85xx_set_mc_sysfs_attributes(mci); | |
881 | ||
882 | mpc85xx_init_csrows(mci); | |
883 | ||
884 | #ifdef CONFIG_EDAC_DEBUG | |
885 | edac_mc_register_mcidev_debug((struct attribute **)debug_attr); | |
886 | #endif | |
887 | ||
888 | /* store the original error disable bits */ | |
889 | orig_ddr_err_disable = | |
890 | in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE); | |
891 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0); | |
892 | ||
893 | /* clear all error bits */ | |
894 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0); | |
895 | ||
896 | if (edac_mc_add_mc(mci)) { | |
897 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); | |
898 | goto err; | |
899 | } | |
900 | ||
901 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
902 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, | |
903 | DDR_EIE_MBEE | DDR_EIE_SBEE); | |
904 | ||
905 | /* store the original error management threshold */ | |
906 | orig_ddr_err_sbe = in_be32(pdata->mc_vbase + | |
907 | MPC85XX_MC_ERR_SBE) & 0xff0000; | |
908 | ||
909 | /* set threshold to 1 error per interrupt */ | |
910 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000); | |
911 | ||
912 | /* register interrupts */ | |
913 | pdata->irq = irq_of_parse_and_map(op->node, 0); | |
914 | res = devm_request_irq(&op->dev, pdata->irq, | |
915 | mpc85xx_mc_isr, IRQF_DISABLED, | |
916 | "[EDAC] MC err", mci); | |
917 | if (res < 0) { | |
918 | printk(KERN_ERR "%s: Unable to request irq %d for " | |
919 | "MPC85xx DRAM ERR\n", __func__, pdata->irq); | |
920 | irq_dispose_mapping(pdata->irq); | |
921 | res = -ENODEV; | |
922 | goto err2; | |
923 | } | |
924 | ||
925 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n", | |
926 | pdata->irq); | |
927 | } | |
928 | ||
929 | devres_remove_group(&op->dev, mpc85xx_mc_err_probe); | |
930 | debugf3("%s(): success\n", __func__); | |
931 | printk(KERN_INFO EDAC_MOD_STR " MC err registered\n"); | |
932 | ||
933 | return 0; | |
934 | ||
935 | err2: | |
936 | edac_mc_del_mc(&op->dev); | |
937 | err: | |
938 | devres_release_group(&op->dev, mpc85xx_mc_err_probe); | |
939 | edac_mc_free(mci); | |
940 | return res; | |
941 | } | |
942 | ||
943 | static int mpc85xx_mc_err_remove(struct of_device *op) | |
944 | { | |
945 | struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); | |
946 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
947 | ||
948 | debugf0("%s()\n", __func__); | |
949 | ||
950 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
951 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0); | |
952 | irq_dispose_mapping(pdata->irq); | |
953 | } | |
954 | ||
955 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, | |
956 | orig_ddr_err_disable); | |
957 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe); | |
958 | ||
959 | edac_mc_del_mc(&op->dev); | |
960 | edac_mc_free(mci); | |
961 | return 0; | |
962 | } | |
963 | ||
964 | static struct of_device_id mpc85xx_mc_err_of_match[] = { | |
965 | { | |
966 | .compatible = "fsl,8540-memory-controller", | |
967 | }, | |
968 | { | |
969 | .compatible = "fsl,8541-memory-controller", | |
970 | }, | |
971 | { | |
972 | .compatible = "fsl,8544-memory-controller", | |
973 | }, | |
974 | { | |
975 | .compatible = "fsl,8548-memory-controller", | |
976 | }, | |
977 | { | |
978 | .compatible = "fsl,8555-memory-controller", | |
979 | }, | |
980 | { | |
981 | .compatible = "fsl,8568-memory-controller", | |
982 | }, | |
983 | {}, | |
984 | }; | |
985 | ||
986 | static struct of_platform_driver mpc85xx_mc_err_driver = { | |
987 | .owner = THIS_MODULE, | |
988 | .name = "mpc85xx_mc_err", | |
989 | .match_table = mpc85xx_mc_err_of_match, | |
990 | .probe = mpc85xx_mc_err_probe, | |
991 | .remove = mpc85xx_mc_err_remove, | |
992 | .driver = { | |
993 | .name = "mpc85xx_mc_err", | |
994 | .owner = THIS_MODULE, | |
995 | }, | |
996 | }; | |
997 | ||
998 | static int __init mpc85xx_mc_init(void) | |
999 | { | |
1000 | int res = 0; | |
1001 | ||
1002 | printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, " | |
1003 | "(C) 2006 Montavista Software\n"); | |
1004 | ||
1005 | /* make sure error reporting method is sane */ | |
1006 | switch (edac_op_state) { | |
1007 | case EDAC_OPSTATE_POLL: | |
1008 | case EDAC_OPSTATE_INT: | |
1009 | break; | |
1010 | default: | |
1011 | edac_op_state = EDAC_OPSTATE_INT; | |
1012 | break; | |
1013 | } | |
1014 | ||
1015 | res = of_register_platform_driver(&mpc85xx_mc_err_driver); | |
1016 | if (res) | |
1017 | printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n"); | |
1018 | ||
1019 | res = of_register_platform_driver(&mpc85xx_l2_err_driver); | |
1020 | if (res) | |
1021 | printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n"); | |
1022 | ||
1023 | #ifdef CONFIG_PCI | |
f87bd330 | 1024 | res = of_register_platform_driver(&mpc85xx_pci_err_driver); |
a9a753d5 DJ |
1025 | if (res) |
1026 | printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n"); | |
1027 | #endif | |
1028 | ||
1029 | /* | |
1030 | * need to clear HID1[RFXE] to disable machine check int | |
1031 | * so we can catch it | |
1032 | */ | |
1033 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
1034 | orig_hid1 = mfspr(SPRN_HID1); | |
1035 | mtspr(SPRN_HID1, (orig_hid1 & ~0x20000)); | |
1036 | } | |
1037 | ||
1038 | return 0; | |
1039 | } | |
1040 | ||
1041 | module_init(mpc85xx_mc_init); | |
1042 | ||
1043 | static void __exit mpc85xx_mc_exit(void) | |
1044 | { | |
1045 | mtspr(SPRN_HID1, orig_hid1); | |
1046 | #ifdef CONFIG_PCI | |
f87bd330 | 1047 | of_unregister_platform_driver(&mpc85xx_pci_err_driver); |
a9a753d5 DJ |
1048 | #endif |
1049 | of_unregister_platform_driver(&mpc85xx_l2_err_driver); | |
1050 | of_unregister_platform_driver(&mpc85xx_mc_err_driver); | |
1051 | } | |
1052 | ||
1053 | module_exit(mpc85xx_mc_exit); | |
1054 | ||
1055 | MODULE_LICENSE("GPL"); | |
1056 | MODULE_AUTHOR("Montavista Software, Inc."); | |
1057 | module_param(edac_op_state, int, 0444); | |
1058 | MODULE_PARM_DESC(edac_op_state, | |
1059 | "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); |