Commit | Line | Data |
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f65aad41 RB |
1 | /* |
2 | * LMC Registers, see chapter 2.5 | |
3 | * | |
4 | * These are RSL Type registers and are accessed indirectly across the | |
5 | * I/O bus, so accesses are slowish. Not that it matters. Any size load is | |
6 | * ok but stores must be 64-bit. | |
7 | */ | |
8 | #define LMC_BASE 0x0001180088000000 | |
9 | #define LMC_SIZE 0xb8 | |
10 | ||
11 | #define LMC_MEM_CFG0 0x0000000000000000 | |
12 | #define LMC_MEM_CFG1 0x0000000000000008 | |
13 | #define LMC_CTL 0x0000000000000010 | |
14 | #define LMC_DDR2_CTL 0x0000000000000018 | |
15 | #define LMC_FADR 0x0000000000000020 | |
16 | #define LMC_FADR_FDIMM | |
17 | #define LMC_FADR_FBUNK | |
18 | #define LMC_FADR_FBANK | |
19 | #define LMC_FADR_FROW | |
20 | #define LMC_FADR_FCOL | |
21 | #define LMC_COMP_CTL 0x0000000000000028 | |
22 | #define LMC_WODT_CTL 0x0000000000000030 | |
23 | #define LMC_ECC_SYND 0x0000000000000038 | |
24 | #define LMC_IFB_CNT_LO 0x0000000000000048 | |
25 | #define LMC_IFB_CNT_HI 0x0000000000000050 | |
26 | #define LMC_OPS_CNT_LO 0x0000000000000058 | |
27 | #define LMC_OPS_CNT_HI 0x0000000000000060 | |
28 | #define LMC_DCLK_CNT_LO 0x0000000000000068 | |
29 | #define LMC_DCLK_CNT_HI 0x0000000000000070 | |
30 | #define LMC_DELAY_CFG 0x0000000000000088 | |
31 | #define LMC_CTL1 0x0000000000000090 | |
32 | #define LMC_DUAL_MEM_CONFIG 0x0000000000000098 | |
33 | #define LMC_RODT_COMP_CTL 0x00000000000000A0 | |
34 | #define LMC_PLL_CTL 0x00000000000000A8 | |
35 | #define LMC_PLL_STATUS 0x00000000000000B0 | |
36 | ||
37 | union lmc_mem_cfg0 { | |
38 | uint64_t u64; | |
39 | struct { | |
40 | uint64_t reserved_32_63:32; | |
41 | uint64_t reset:1; | |
42 | uint64_t silo_qc:1; | |
43 | uint64_t bunk_ena:1; | |
44 | uint64_t ded_err:4; | |
45 | uint64_t sec_err:4; | |
46 | uint64_t intr_ded_ena:1; | |
47 | uint64_t intr_sec_ena:1; | |
48 | uint64_t reserved_15_18:4; | |
49 | uint64_t ref_int:5; | |
50 | uint64_t pbank_lsb:4; | |
51 | uint64_t row_lsb:3; | |
52 | uint64_t ecc_ena:1; | |
53 | uint64_t init_start:1; | |
54 | }; | |
55 | }; | |
56 | ||
57 | union lmc_fadr { | |
58 | uint64_t u64; | |
59 | struct { | |
60 | uint64_t reserved_32_63:32; | |
61 | uint64_t fdimm:2; | |
62 | uint64_t fbunk:1; | |
63 | uint64_t fbank:3; | |
64 | uint64_t frow:14; | |
65 | uint64_t fcol:12; | |
66 | }; | |
67 | }; | |
68 | ||
69 | union lmc_ecc_synd { | |
70 | uint64_t u64; | |
71 | struct { | |
72 | uint64_t reserved_32_63:32; | |
73 | uint64_t mrdsyn3:8; | |
74 | uint64_t mrdsyn2:8; | |
75 | uint64_t mrdsyn1:8; | |
76 | uint64_t mrdsyn0:8; | |
77 | }; | |
78 | }; |