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eebf11a0 MCC |
1 | /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module |
2 | * | |
3 | * This driver supports the memory controllers found on the Intel | |
4 | * processor family Sandy Bridge. | |
5 | * | |
6 | * This file may be distributed under the terms of the | |
7 | * GNU General Public License version 2 only. | |
8 | * | |
9 | * Copyright (c) 2011 by: | |
10 | * Mauro Carvalho Chehab <mchehab@redhat.com> | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/pci_ids.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/edac.h> | |
20 | #include <linux/mmzone.h> | |
eebf11a0 MCC |
21 | #include <linux/smp.h> |
22 | #include <linux/bitmap.h> | |
5b889e37 | 23 | #include <linux/math64.h> |
eebf11a0 | 24 | #include <asm/processor.h> |
3d78c9af | 25 | #include <asm/mce.h> |
eebf11a0 MCC |
26 | |
27 | #include "edac_core.h" | |
28 | ||
29 | /* Static vars */ | |
30 | static LIST_HEAD(sbridge_edac_list); | |
31 | static DEFINE_MUTEX(sbridge_edac_lock); | |
32 | static int probed; | |
33 | ||
34 | /* | |
35 | * Alter this version for the module when modifications are made | |
36 | */ | |
37 | #define SBRIDGE_REVISION " Ver: 1.0.0 " | |
38 | #define EDAC_MOD_STR "sbridge_edac" | |
39 | ||
40 | /* | |
41 | * Debug macros | |
42 | */ | |
43 | #define sbridge_printk(level, fmt, arg...) \ | |
44 | edac_printk(level, "sbridge", fmt, ##arg) | |
45 | ||
46 | #define sbridge_mc_printk(mci, level, fmt, arg...) \ | |
47 | edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg) | |
48 | ||
49 | /* | |
50 | * Get a bit field at register value <v>, from bit <lo> to bit <hi> | |
51 | */ | |
52 | #define GET_BITFIELD(v, lo, hi) \ | |
53 | (((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo)) | |
54 | ||
55 | /* | |
56 | * sbridge Memory Controller Registers | |
57 | */ | |
58 | ||
59 | /* | |
60 | * FIXME: For now, let's order by device function, as it makes | |
15ed103a | 61 | * easier for driver's development process. This table should be |
eebf11a0 MCC |
62 | * moved to pci_id.h when submitted upstream |
63 | */ | |
64 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */ | |
65 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */ | |
66 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */ | |
67 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */ | |
68 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */ | |
69 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */ | |
70 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */ | |
71 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */ | |
72 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */ | |
73 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */ | |
74 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */ | |
75 | ||
76 | /* | |
77 | * Currently, unused, but will be needed in the future | |
78 | * implementations, as they hold the error counters | |
79 | */ | |
80 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */ | |
81 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */ | |
82 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */ | |
83 | #define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */ | |
84 | ||
85 | /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ | |
464f1d82 | 86 | static const u32 sbridge_dram_rule[] = { |
eebf11a0 MCC |
87 | 0x80, 0x88, 0x90, 0x98, 0xa0, |
88 | 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, | |
89 | }; | |
eebf11a0 MCC |
90 | |
91 | #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff) | |
92 | #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3) | |
93 | #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1) | |
94 | #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) | |
95 | ||
96 | static char *get_dram_attr(u32 reg) | |
97 | { | |
98 | switch(DRAM_ATTR(reg)) { | |
99 | case 0: | |
100 | return "DRAM"; | |
101 | case 1: | |
102 | return "MMCFG"; | |
103 | case 2: | |
104 | return "NXM"; | |
105 | default: | |
106 | return "unknown"; | |
107 | } | |
108 | } | |
109 | ||
ef1ce51e | 110 | static const u32 sbridge_interleave_list[] = { |
eebf11a0 MCC |
111 | 0x84, 0x8c, 0x94, 0x9c, 0xa4, |
112 | 0xac, 0xb4, 0xbc, 0xc4, 0xcc, | |
113 | }; | |
eebf11a0 | 114 | |
cc311991 AR |
115 | struct interleave_pkg { |
116 | unsigned char start; | |
117 | unsigned char end; | |
118 | }; | |
119 | ||
120 | static const struct interleave_pkg sbridge_interleave_pkg[] = { | |
121 | { 0, 2 }, | |
122 | { 3, 5 }, | |
123 | { 8, 10 }, | |
124 | { 11, 13 }, | |
125 | { 16, 18 }, | |
126 | { 19, 21 }, | |
127 | { 24, 26 }, | |
128 | { 27, 29 }, | |
129 | }; | |
130 | ||
131 | static inline int sad_pkg(const struct interleave_pkg *table, u32 reg, | |
132 | int interleave) | |
eebf11a0 | 133 | { |
cc311991 AR |
134 | return GET_BITFIELD(reg, table[interleave].start, |
135 | table[interleave].end); | |
eebf11a0 MCC |
136 | } |
137 | ||
138 | /* Devices 12 Function 7 */ | |
139 | ||
140 | #define TOLM 0x80 | |
141 | #define TOHM 0x84 | |
142 | ||
143 | #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) | |
144 | #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) | |
145 | ||
146 | /* Device 13 Function 6 */ | |
147 | ||
148 | #define SAD_TARGET 0xf0 | |
149 | ||
150 | #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) | |
151 | ||
152 | #define SAD_CONTROL 0xf4 | |
153 | ||
154 | #define NODE_ID(reg) GET_BITFIELD(reg, 0, 2) | |
155 | ||
156 | /* Device 14 function 0 */ | |
157 | ||
158 | static const u32 tad_dram_rule[] = { | |
159 | 0x40, 0x44, 0x48, 0x4c, | |
160 | 0x50, 0x54, 0x58, 0x5c, | |
161 | 0x60, 0x64, 0x68, 0x6c, | |
162 | }; | |
163 | #define MAX_TAD ARRAY_SIZE(tad_dram_rule) | |
164 | ||
165 | #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) | |
166 | #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) | |
167 | #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) | |
168 | #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) | |
169 | #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) | |
170 | #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) | |
171 | #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) | |
172 | ||
173 | /* Device 15, function 0 */ | |
174 | ||
175 | #define MCMTR 0x7c | |
176 | ||
177 | #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) | |
178 | #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) | |
179 | #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) | |
180 | ||
181 | /* Device 15, function 1 */ | |
182 | ||
183 | #define RASENABLES 0xac | |
184 | #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) | |
185 | ||
186 | /* Device 15, functions 2-5 */ | |
187 | ||
188 | static const int mtr_regs[] = { | |
189 | 0x80, 0x84, 0x88, | |
190 | }; | |
191 | ||
192 | #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) | |
193 | #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) | |
194 | #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) | |
195 | #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) | |
196 | #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) | |
197 | ||
198 | static const u32 tad_ch_nilv_offset[] = { | |
199 | 0x90, 0x94, 0x98, 0x9c, | |
200 | 0xa0, 0xa4, 0xa8, 0xac, | |
201 | 0xb0, 0xb4, 0xb8, 0xbc, | |
202 | }; | |
203 | #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) | |
204 | #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) | |
205 | ||
206 | static const u32 rir_way_limit[] = { | |
207 | 0x108, 0x10c, 0x110, 0x114, 0x118, | |
208 | }; | |
209 | #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit) | |
210 | ||
211 | #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) | |
212 | #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) | |
213 | #define RIR_LIMIT(reg) ((GET_BITFIELD(reg, 1, 10) << 29)| 0x1fffffff) | |
214 | ||
215 | #define MAX_RIR_WAY 8 | |
216 | ||
217 | static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { | |
218 | { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c }, | |
219 | { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c }, | |
220 | { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c }, | |
221 | { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c }, | |
222 | { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, | |
223 | }; | |
224 | ||
225 | #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19) | |
226 | #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14) | |
227 | ||
228 | /* Device 16, functions 2-7 */ | |
229 | ||
230 | /* | |
231 | * FIXME: Implement the error count reads directly | |
232 | */ | |
233 | ||
234 | static const u32 correrrcnt[] = { | |
235 | 0x104, 0x108, 0x10c, 0x110, | |
236 | }; | |
237 | ||
238 | #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) | |
239 | #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) | |
240 | #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) | |
241 | #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) | |
242 | ||
243 | static const u32 correrrthrsld[] = { | |
244 | 0x11c, 0x120, 0x124, 0x128, | |
245 | }; | |
246 | ||
247 | #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) | |
248 | #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) | |
249 | ||
250 | ||
251 | /* Device 17, function 0 */ | |
252 | ||
ef1e8d03 | 253 | #define SB_RANK_CFG_A 0x0328 |
eebf11a0 MCC |
254 | |
255 | #define IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11) | |
256 | ||
257 | /* | |
258 | * sbridge structs | |
259 | */ | |
260 | ||
261 | #define NUM_CHANNELS 4 | |
262 | #define MAX_DIMMS 3 /* Max DIMMS per channel */ | |
263 | ||
fb79a509 | 264 | struct sbridge_pvt; |
eebf11a0 | 265 | struct sbridge_info { |
464f1d82 AR |
266 | u32 mcmtr; |
267 | u32 rankcfgr; | |
268 | u64 (*get_tolm)(struct sbridge_pvt *pvt); | |
269 | u64 (*get_tohm)(struct sbridge_pvt *pvt); | |
270 | const u32 *dram_rule; | |
ef1ce51e | 271 | const u32 *interleave_list; |
cc311991 | 272 | const struct interleave_pkg *interleave_pkg; |
464f1d82 | 273 | u8 max_sad; |
ef1ce51e | 274 | u8 max_interleave; |
eebf11a0 MCC |
275 | }; |
276 | ||
277 | struct sbridge_channel { | |
278 | u32 ranks; | |
279 | u32 dimms; | |
280 | }; | |
281 | ||
282 | struct pci_id_descr { | |
283 | int dev; | |
284 | int func; | |
285 | int dev_id; | |
286 | int optional; | |
287 | }; | |
288 | ||
289 | struct pci_id_table { | |
290 | const struct pci_id_descr *descr; | |
291 | int n_devs; | |
292 | }; | |
293 | ||
294 | struct sbridge_dev { | |
295 | struct list_head list; | |
296 | u8 bus, mc; | |
297 | u8 node_id, source_id; | |
298 | struct pci_dev **pdev; | |
299 | int n_devs; | |
300 | struct mem_ctl_info *mci; | |
301 | }; | |
302 | ||
303 | struct sbridge_pvt { | |
304 | struct pci_dev *pci_ta, *pci_ddrio, *pci_ras; | |
305 | struct pci_dev *pci_sad0, *pci_sad1, *pci_ha0; | |
5f8a1b8a | 306 | struct pci_dev *pci_br0; |
eebf11a0 MCC |
307 | struct pci_dev *pci_tad[NUM_CHANNELS]; |
308 | ||
309 | struct sbridge_dev *sbridge_dev; | |
310 | ||
311 | struct sbridge_info info; | |
312 | struct sbridge_channel channel[NUM_CHANNELS]; | |
313 | ||
eebf11a0 MCC |
314 | /* Memory type detection */ |
315 | bool is_mirrored, is_lockstep, is_close_pg; | |
316 | ||
eebf11a0 MCC |
317 | /* Fifo double buffers */ |
318 | struct mce mce_entry[MCE_LOG_LEN]; | |
319 | struct mce mce_outentry[MCE_LOG_LEN]; | |
320 | ||
321 | /* Fifo in/out counters */ | |
322 | unsigned mce_in, mce_out; | |
323 | ||
324 | /* Count indicator to show errors not got */ | |
325 | unsigned mce_overrun; | |
326 | ||
327 | /* Memory description */ | |
328 | u64 tolm, tohm; | |
329 | }; | |
330 | ||
de4772c6 LT |
331 | #define PCI_DESCR(device, function, device_id, opt) \ |
332 | .dev = (device), \ | |
333 | .func = (function), \ | |
334 | .dev_id = (device_id), \ | |
335 | .optional = opt | |
eebf11a0 MCC |
336 | |
337 | static const struct pci_id_descr pci_dev_descr_sbridge[] = { | |
338 | /* Processor Home Agent */ | |
de4772c6 | 339 | { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) }, |
eebf11a0 MCC |
340 | |
341 | /* Memory controller */ | |
de4772c6 LT |
342 | { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) }, |
343 | { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) }, | |
344 | { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) }, | |
345 | { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) }, | |
346 | { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) }, | |
347 | { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) }, | |
348 | { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) }, | |
eebf11a0 MCC |
349 | |
350 | /* System Address Decoder */ | |
de4772c6 LT |
351 | { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) }, |
352 | { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) }, | |
eebf11a0 MCC |
353 | |
354 | /* Broadcast Registers */ | |
de4772c6 | 355 | { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) }, |
eebf11a0 MCC |
356 | }; |
357 | ||
358 | #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) } | |
359 | static const struct pci_id_table pci_dev_descr_sbridge_table[] = { | |
360 | PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge), | |
361 | {0,} /* 0 terminated list. */ | |
362 | }; | |
363 | ||
364 | /* | |
365 | * pci_device_id table for which devices we are looking for | |
366 | */ | |
36c46f31 | 367 | static DEFINE_PCI_DEVICE_TABLE(sbridge_pci_tbl) = { |
eebf11a0 MCC |
368 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)}, |
369 | {0,} /* 0 terminated list. */ | |
370 | }; | |
371 | ||
372 | ||
373 | /**************************************************************************** | |
15ed103a | 374 | Ancillary status routines |
eebf11a0 MCC |
375 | ****************************************************************************/ |
376 | ||
377 | static inline int numrank(u32 mtr) | |
378 | { | |
379 | int ranks = (1 << RANK_CNT_BITS(mtr)); | |
380 | ||
381 | if (ranks > 4) { | |
956b9ba1 JP |
382 | edac_dbg(0, "Invalid number of ranks: %d (max = 4) raw value = %x (%04x)\n", |
383 | ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr); | |
eebf11a0 MCC |
384 | return -EINVAL; |
385 | } | |
386 | ||
387 | return ranks; | |
388 | } | |
389 | ||
390 | static inline int numrow(u32 mtr) | |
391 | { | |
392 | int rows = (RANK_WIDTH_BITS(mtr) + 12); | |
393 | ||
394 | if (rows < 13 || rows > 18) { | |
956b9ba1 JP |
395 | edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n", |
396 | rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); | |
eebf11a0 MCC |
397 | return -EINVAL; |
398 | } | |
399 | ||
400 | return 1 << rows; | |
401 | } | |
402 | ||
403 | static inline int numcol(u32 mtr) | |
404 | { | |
405 | int cols = (COL_WIDTH_BITS(mtr) + 10); | |
406 | ||
407 | if (cols > 12) { | |
956b9ba1 JP |
408 | edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n", |
409 | cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); | |
eebf11a0 MCC |
410 | return -EINVAL; |
411 | } | |
412 | ||
413 | return 1 << cols; | |
414 | } | |
415 | ||
416 | static struct sbridge_dev *get_sbridge_dev(u8 bus) | |
417 | { | |
418 | struct sbridge_dev *sbridge_dev; | |
419 | ||
420 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
421 | if (sbridge_dev->bus == bus) | |
422 | return sbridge_dev; | |
423 | } | |
424 | ||
425 | return NULL; | |
426 | } | |
427 | ||
428 | static struct sbridge_dev *alloc_sbridge_dev(u8 bus, | |
429 | const struct pci_id_table *table) | |
430 | { | |
431 | struct sbridge_dev *sbridge_dev; | |
432 | ||
433 | sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL); | |
434 | if (!sbridge_dev) | |
435 | return NULL; | |
436 | ||
437 | sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs, | |
438 | GFP_KERNEL); | |
439 | if (!sbridge_dev->pdev) { | |
440 | kfree(sbridge_dev); | |
441 | return NULL; | |
442 | } | |
443 | ||
444 | sbridge_dev->bus = bus; | |
445 | sbridge_dev->n_devs = table->n_devs; | |
446 | list_add_tail(&sbridge_dev->list, &sbridge_edac_list); | |
447 | ||
448 | return sbridge_dev; | |
449 | } | |
450 | ||
451 | static void free_sbridge_dev(struct sbridge_dev *sbridge_dev) | |
452 | { | |
453 | list_del(&sbridge_dev->list); | |
454 | kfree(sbridge_dev->pdev); | |
455 | kfree(sbridge_dev); | |
456 | } | |
457 | ||
fb79a509 AR |
458 | static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) |
459 | { | |
460 | u32 reg; | |
461 | ||
462 | /* Address range is 32:28 */ | |
463 | pci_read_config_dword(pvt->pci_sad1, TOLM, ®); | |
464 | return GET_TOLM(reg); | |
465 | } | |
466 | ||
8fd6a43a AR |
467 | static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) |
468 | { | |
469 | u32 reg; | |
470 | ||
471 | pci_read_config_dword(pvt->pci_sad1, TOHM, ®); | |
472 | return GET_TOHM(reg); | |
473 | } | |
474 | ||
eebf11a0 MCC |
475 | /**************************************************************************** |
476 | Memory check routines | |
477 | ****************************************************************************/ | |
478 | static struct pci_dev *get_pdev_slot_func(u8 bus, unsigned slot, | |
479 | unsigned func) | |
480 | { | |
481 | struct sbridge_dev *sbridge_dev = get_sbridge_dev(bus); | |
482 | int i; | |
483 | ||
484 | if (!sbridge_dev) | |
485 | return NULL; | |
486 | ||
487 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
488 | if (!sbridge_dev->pdev[i]) | |
489 | continue; | |
490 | ||
491 | if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot && | |
492 | PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) { | |
956b9ba1 JP |
493 | edac_dbg(1, "Associated %02x.%02x.%d with %p\n", |
494 | bus, slot, func, sbridge_dev->pdev[i]); | |
eebf11a0 MCC |
495 | return sbridge_dev->pdev[i]; |
496 | } | |
497 | } | |
498 | ||
499 | return NULL; | |
500 | } | |
501 | ||
502 | /** | |
c36e3e77 | 503 | * check_if_ecc_is_active() - Checks if ECC is active |
eebf11a0 | 504 | * bus: Device bus |
eebf11a0 | 505 | */ |
c36e3e77 | 506 | static int check_if_ecc_is_active(const u8 bus) |
eebf11a0 MCC |
507 | { |
508 | struct pci_dev *pdev = NULL; | |
eebf11a0 MCC |
509 | u32 mcmtr; |
510 | ||
eebf11a0 MCC |
511 | pdev = get_pdev_slot_func(bus, 15, 0); |
512 | if (!pdev) { | |
513 | sbridge_printk(KERN_ERR, "Couldn't find PCI device " | |
514 | "%2x.%02d.%d!!!\n", | |
515 | bus, 15, 0); | |
516 | return -ENODEV; | |
517 | } | |
518 | ||
519 | pci_read_config_dword(pdev, MCMTR, &mcmtr); | |
520 | if (!IS_ECC_ENABLED(mcmtr)) { | |
521 | sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n"); | |
522 | return -ENODEV; | |
523 | } | |
eebf11a0 MCC |
524 | return 0; |
525 | } | |
526 | ||
084a4fcc | 527 | static int get_dimm_config(struct mem_ctl_info *mci) |
eebf11a0 MCC |
528 | { |
529 | struct sbridge_pvt *pvt = mci->pvt_info; | |
c36e3e77 | 530 | struct dimm_info *dimm; |
deb09dda MCC |
531 | unsigned i, j, banks, ranks, rows, cols, npages; |
532 | u64 size; | |
eebf11a0 MCC |
533 | u32 reg; |
534 | enum edac_type mode; | |
c6e13b52 | 535 | enum mem_type mtype; |
eebf11a0 | 536 | |
ef1e8d03 AR |
537 | pvt->info.rankcfgr = SB_RANK_CFG_A; |
538 | ||
5f8a1b8a | 539 | pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); |
eebf11a0 MCC |
540 | pvt->sbridge_dev->source_id = SOURCE_ID(reg); |
541 | ||
5f8a1b8a | 542 | pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); |
eebf11a0 | 543 | pvt->sbridge_dev->node_id = NODE_ID(reg); |
956b9ba1 JP |
544 | edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n", |
545 | pvt->sbridge_dev->mc, | |
546 | pvt->sbridge_dev->node_id, | |
547 | pvt->sbridge_dev->source_id); | |
eebf11a0 MCC |
548 | |
549 | pci_read_config_dword(pvt->pci_ras, RASENABLES, ®); | |
550 | if (IS_MIRROR_ENABLED(reg)) { | |
956b9ba1 | 551 | edac_dbg(0, "Memory mirror is enabled\n"); |
eebf11a0 MCC |
552 | pvt->is_mirrored = true; |
553 | } else { | |
956b9ba1 | 554 | edac_dbg(0, "Memory mirror is disabled\n"); |
eebf11a0 MCC |
555 | pvt->is_mirrored = false; |
556 | } | |
557 | ||
558 | pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr); | |
559 | if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { | |
956b9ba1 | 560 | edac_dbg(0, "Lockstep is enabled\n"); |
eebf11a0 MCC |
561 | mode = EDAC_S8ECD8ED; |
562 | pvt->is_lockstep = true; | |
563 | } else { | |
956b9ba1 | 564 | edac_dbg(0, "Lockstep is disabled\n"); |
eebf11a0 MCC |
565 | mode = EDAC_S4ECD4ED; |
566 | pvt->is_lockstep = false; | |
567 | } | |
568 | if (IS_CLOSE_PG(pvt->info.mcmtr)) { | |
956b9ba1 | 569 | edac_dbg(0, "address map is on closed page mode\n"); |
eebf11a0 MCC |
570 | pvt->is_close_pg = true; |
571 | } else { | |
956b9ba1 | 572 | edac_dbg(0, "address map is on open page mode\n"); |
eebf11a0 MCC |
573 | pvt->is_close_pg = false; |
574 | } | |
575 | ||
de4772c6 | 576 | if (pvt->pci_ddrio) { |
ef1e8d03 AR |
577 | pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, |
578 | ®); | |
de4772c6 LT |
579 | if (IS_RDIMM_ENABLED(reg)) { |
580 | /* FIXME: Can also be LRDIMM */ | |
581 | edac_dbg(0, "Memory is registered\n"); | |
582 | mtype = MEM_RDDR3; | |
583 | } else { | |
584 | edac_dbg(0, "Memory is unregistered\n"); | |
585 | mtype = MEM_DDR3; | |
586 | } | |
eebf11a0 | 587 | } else { |
de4772c6 LT |
588 | edac_dbg(0, "Cannot determine memory type\n"); |
589 | mtype = MEM_UNKNOWN; | |
eebf11a0 MCC |
590 | } |
591 | ||
592 | /* On all supported DDR3 DIMM types, there are 8 banks available */ | |
593 | banks = 8; | |
594 | ||
595 | for (i = 0; i < NUM_CHANNELS; i++) { | |
596 | u32 mtr; | |
597 | ||
598 | for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) { | |
c36e3e77 MCC |
599 | dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, |
600 | i, j, 0); | |
eebf11a0 MCC |
601 | pci_read_config_dword(pvt->pci_tad[i], |
602 | mtr_regs[j], &mtr); | |
956b9ba1 | 603 | edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); |
eebf11a0 MCC |
604 | if (IS_DIMM_PRESENT(mtr)) { |
605 | pvt->channel[i].dimms++; | |
606 | ||
607 | ranks = numrank(mtr); | |
608 | rows = numrow(mtr); | |
609 | cols = numcol(mtr); | |
610 | ||
611 | /* DDR3 has 8 I/O banks */ | |
deb09dda | 612 | size = ((u64)rows * cols * banks * ranks) >> (20 - 3); |
eebf11a0 MCC |
613 | npages = MiB_TO_PAGES(size); |
614 | ||
deb09dda | 615 | edac_dbg(0, "mc#%d: channel %d, dimm %d, %Ld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", |
956b9ba1 JP |
616 | pvt->sbridge_dev->mc, i, j, |
617 | size, npages, | |
618 | banks, ranks, rows, cols); | |
eebf11a0 | 619 | |
a895bf8b | 620 | dimm->nr_pages = npages; |
084a4fcc MCC |
621 | dimm->grain = 32; |
622 | dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4; | |
623 | dimm->mtype = mtype; | |
624 | dimm->edac_mode = mode; | |
625 | snprintf(dimm->label, sizeof(dimm->label), | |
eebf11a0 MCC |
626 | "CPU_SrcID#%u_Channel#%u_DIMM#%u", |
627 | pvt->sbridge_dev->source_id, i, j); | |
eebf11a0 MCC |
628 | } |
629 | } | |
630 | } | |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
635 | static void get_memory_layout(const struct mem_ctl_info *mci) | |
636 | { | |
637 | struct sbridge_pvt *pvt = mci->pvt_info; | |
638 | int i, j, k, n_sads, n_tads, sad_interl; | |
639 | u32 reg; | |
640 | u64 limit, prv = 0; | |
641 | u64 tmp_mb; | |
5b889e37 | 642 | u32 mb, kb; |
eebf11a0 MCC |
643 | u32 rir_way; |
644 | ||
645 | /* | |
646 | * Step 1) Get TOLM/TOHM ranges | |
647 | */ | |
648 | ||
fb79a509 | 649 | pvt->tolm = pvt->info.get_tolm(pvt); |
eebf11a0 MCC |
650 | tmp_mb = (1 + pvt->tolm) >> 20; |
651 | ||
5b889e37 | 652 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
956b9ba1 | 653 | edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tolm); |
eebf11a0 MCC |
654 | |
655 | /* Address range is already 45:25 */ | |
8fd6a43a | 656 | pvt->tohm = pvt->info.get_tohm(pvt); |
eebf11a0 MCC |
657 | tmp_mb = (1 + pvt->tohm) >> 20; |
658 | ||
5b889e37 | 659 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
da14d93d | 660 | edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", mb, kb, (u64)pvt->tohm); |
eebf11a0 MCC |
661 | |
662 | /* | |
663 | * Step 2) Get SAD range and SAD Interleave list | |
664 | * TAD registers contain the interleave wayness. However, it | |
665 | * seems simpler to just discover it indirectly, with the | |
666 | * algorithm bellow. | |
667 | */ | |
668 | prv = 0; | |
464f1d82 | 669 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
eebf11a0 | 670 | /* SAD_LIMIT Address range is 45:26 */ |
464f1d82 | 671 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], |
eebf11a0 MCC |
672 | ®); |
673 | limit = SAD_LIMIT(reg); | |
674 | ||
675 | if (!DRAM_RULE_ENABLE(reg)) | |
676 | continue; | |
677 | ||
678 | if (limit <= prv) | |
679 | break; | |
680 | ||
681 | tmp_mb = (limit + 1) >> 20; | |
5b889e37 | 682 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
956b9ba1 JP |
683 | edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", |
684 | n_sads, | |
685 | get_dram_attr(reg), | |
686 | mb, kb, | |
687 | ((u64)tmp_mb) << 20L, | |
688 | INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]", | |
689 | reg); | |
eebf11a0 MCC |
690 | prv = limit; |
691 | ||
ef1ce51e | 692 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
eebf11a0 | 693 | ®); |
cc311991 | 694 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); |
eebf11a0 | 695 | for (j = 0; j < 8; j++) { |
cc311991 AR |
696 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); |
697 | if (j > 0 && sad_interl == pkg) | |
eebf11a0 MCC |
698 | break; |
699 | ||
956b9ba1 | 700 | edac_dbg(0, "SAD#%d, interleave #%d: %d\n", |
cc311991 | 701 | n_sads, j, pkg); |
eebf11a0 MCC |
702 | } |
703 | } | |
704 | ||
705 | /* | |
706 | * Step 3) Get TAD range | |
707 | */ | |
708 | prv = 0; | |
709 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { | |
710 | pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads], | |
711 | ®); | |
712 | limit = TAD_LIMIT(reg); | |
713 | if (limit <= prv) | |
714 | break; | |
715 | tmp_mb = (limit + 1) >> 20; | |
716 | ||
5b889e37 | 717 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
956b9ba1 JP |
718 | edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", |
719 | n_tads, mb, kb, | |
720 | ((u64)tmp_mb) << 20L, | |
721 | (u32)TAD_SOCK(reg), | |
722 | (u32)TAD_CH(reg), | |
723 | (u32)TAD_TGT0(reg), | |
724 | (u32)TAD_TGT1(reg), | |
725 | (u32)TAD_TGT2(reg), | |
726 | (u32)TAD_TGT3(reg), | |
727 | reg); | |
7fae0db4 | 728 | prv = limit; |
eebf11a0 MCC |
729 | } |
730 | ||
731 | /* | |
732 | * Step 4) Get TAD offsets, per each channel | |
733 | */ | |
734 | for (i = 0; i < NUM_CHANNELS; i++) { | |
735 | if (!pvt->channel[i].dimms) | |
736 | continue; | |
737 | for (j = 0; j < n_tads; j++) { | |
738 | pci_read_config_dword(pvt->pci_tad[i], | |
739 | tad_ch_nilv_offset[j], | |
740 | ®); | |
741 | tmp_mb = TAD_OFFSET(reg) >> 20; | |
5b889e37 | 742 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
956b9ba1 JP |
743 | edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", |
744 | i, j, | |
745 | mb, kb, | |
746 | ((u64)tmp_mb) << 20L, | |
747 | reg); | |
eebf11a0 MCC |
748 | } |
749 | } | |
750 | ||
751 | /* | |
752 | * Step 6) Get RIR Wayness/Limit, per each channel | |
753 | */ | |
754 | for (i = 0; i < NUM_CHANNELS; i++) { | |
755 | if (!pvt->channel[i].dimms) | |
756 | continue; | |
757 | for (j = 0; j < MAX_RIR_RANGES; j++) { | |
758 | pci_read_config_dword(pvt->pci_tad[i], | |
759 | rir_way_limit[j], | |
760 | ®); | |
761 | ||
762 | if (!IS_RIR_VALID(reg)) | |
763 | continue; | |
764 | ||
765 | tmp_mb = RIR_LIMIT(reg) >> 20; | |
766 | rir_way = 1 << RIR_WAY(reg); | |
5b889e37 | 767 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
956b9ba1 JP |
768 | edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", |
769 | i, j, | |
770 | mb, kb, | |
771 | ((u64)tmp_mb) << 20L, | |
772 | rir_way, | |
773 | reg); | |
eebf11a0 MCC |
774 | |
775 | for (k = 0; k < rir_way; k++) { | |
776 | pci_read_config_dword(pvt->pci_tad[i], | |
777 | rir_offset[j][k], | |
778 | ®); | |
779 | tmp_mb = RIR_OFFSET(reg) << 6; | |
780 | ||
5b889e37 | 781 | mb = div_u64_rem(tmp_mb, 1000, &kb); |
956b9ba1 JP |
782 | edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", |
783 | i, j, k, | |
784 | mb, kb, | |
785 | ((u64)tmp_mb) << 20L, | |
786 | (u32)RIR_RNK_TGT(reg), | |
787 | reg); | |
eebf11a0 MCC |
788 | } |
789 | } | |
790 | } | |
791 | } | |
792 | ||
793 | struct mem_ctl_info *get_mci_for_node_id(u8 node_id) | |
794 | { | |
795 | struct sbridge_dev *sbridge_dev; | |
796 | ||
797 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
798 | if (sbridge_dev->node_id == node_id) | |
799 | return sbridge_dev->mci; | |
800 | } | |
801 | return NULL; | |
802 | } | |
803 | ||
804 | static int get_memory_error_data(struct mem_ctl_info *mci, | |
805 | u64 addr, | |
806 | u8 *socket, | |
807 | long *channel_mask, | |
808 | u8 *rank, | |
e17a2f42 | 809 | char **area_type, char *msg) |
eebf11a0 MCC |
810 | { |
811 | struct mem_ctl_info *new_mci; | |
812 | struct sbridge_pvt *pvt = mci->pvt_info; | |
eebf11a0 MCC |
813 | int n_rir, n_sads, n_tads, sad_way, sck_xch; |
814 | int sad_interl, idx, base_ch; | |
815 | int interleave_mode; | |
ef1ce51e | 816 | unsigned sad_interleave[pvt->info.max_interleave]; |
eebf11a0 MCC |
817 | u32 reg; |
818 | u8 ch_way,sck_way; | |
819 | u32 tad_offset; | |
820 | u32 rir_way; | |
5b889e37 | 821 | u32 mb, kb; |
eebf11a0 MCC |
822 | u64 ch_addr, offset, limit, prv = 0; |
823 | ||
824 | ||
825 | /* | |
826 | * Step 0) Check if the address is at special memory ranges | |
827 | * The check bellow is probably enough to fill all cases where | |
828 | * the error is not inside a memory, except for the legacy | |
829 | * range (e. g. VGA addresses). It is unlikely, however, that the | |
830 | * memory controller would generate an error on that range. | |
831 | */ | |
5b889e37 | 832 | if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { |
eebf11a0 | 833 | sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr); |
eebf11a0 MCC |
834 | return -EINVAL; |
835 | } | |
836 | if (addr >= (u64)pvt->tohm) { | |
837 | sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr); | |
eebf11a0 MCC |
838 | return -EINVAL; |
839 | } | |
840 | ||
841 | /* | |
842 | * Step 1) Get socket | |
843 | */ | |
464f1d82 AR |
844 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
845 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], | |
eebf11a0 MCC |
846 | ®); |
847 | ||
848 | if (!DRAM_RULE_ENABLE(reg)) | |
849 | continue; | |
850 | ||
851 | limit = SAD_LIMIT(reg); | |
852 | if (limit <= prv) { | |
853 | sprintf(msg, "Can't discover the memory socket"); | |
eebf11a0 MCC |
854 | return -EINVAL; |
855 | } | |
856 | if (addr <= limit) | |
857 | break; | |
858 | prv = limit; | |
859 | } | |
464f1d82 | 860 | if (n_sads == pvt->info.max_sad) { |
eebf11a0 | 861 | sprintf(msg, "Can't discover the memory socket"); |
eebf11a0 MCC |
862 | return -EINVAL; |
863 | } | |
e17a2f42 | 864 | *area_type = get_dram_attr(reg); |
eebf11a0 MCC |
865 | interleave_mode = INTERLEAVE_MODE(reg); |
866 | ||
ef1ce51e | 867 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
eebf11a0 | 868 | ®); |
cc311991 | 869 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); |
eebf11a0 | 870 | for (sad_way = 0; sad_way < 8; sad_way++) { |
cc311991 AR |
871 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); |
872 | if (sad_way > 0 && sad_interl == pkg) | |
eebf11a0 | 873 | break; |
cc311991 | 874 | sad_interleave[sad_way] = pkg; |
956b9ba1 JP |
875 | edac_dbg(0, "SAD interleave #%d: %d\n", |
876 | sad_way, sad_interleave[sad_way]); | |
eebf11a0 | 877 | } |
956b9ba1 JP |
878 | edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", |
879 | pvt->sbridge_dev->mc, | |
880 | n_sads, | |
881 | addr, | |
882 | limit, | |
883 | sad_way + 7, | |
884 | interleave_mode ? "" : "XOR[18:16]"); | |
eebf11a0 MCC |
885 | if (interleave_mode) |
886 | idx = ((addr >> 6) ^ (addr >> 16)) & 7; | |
887 | else | |
888 | idx = (addr >> 6) & 7; | |
889 | switch (sad_way) { | |
890 | case 1: | |
891 | idx = 0; | |
892 | break; | |
893 | case 2: | |
894 | idx = idx & 1; | |
895 | break; | |
896 | case 4: | |
897 | idx = idx & 3; | |
898 | break; | |
899 | case 8: | |
900 | break; | |
901 | default: | |
902 | sprintf(msg, "Can't discover socket interleave"); | |
eebf11a0 MCC |
903 | return -EINVAL; |
904 | } | |
905 | *socket = sad_interleave[idx]; | |
956b9ba1 JP |
906 | edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", |
907 | idx, sad_way, *socket); | |
eebf11a0 MCC |
908 | |
909 | /* | |
910 | * Move to the proper node structure, in order to access the | |
911 | * right PCI registers | |
912 | */ | |
913 | new_mci = get_mci_for_node_id(*socket); | |
914 | if (!new_mci) { | |
915 | sprintf(msg, "Struct for socket #%u wasn't initialized", | |
916 | *socket); | |
eebf11a0 MCC |
917 | return -EINVAL; |
918 | } | |
919 | mci = new_mci; | |
920 | pvt = mci->pvt_info; | |
921 | ||
922 | /* | |
923 | * Step 2) Get memory channel | |
924 | */ | |
925 | prv = 0; | |
926 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { | |
927 | pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads], | |
928 | ®); | |
929 | limit = TAD_LIMIT(reg); | |
930 | if (limit <= prv) { | |
931 | sprintf(msg, "Can't discover the memory channel"); | |
eebf11a0 MCC |
932 | return -EINVAL; |
933 | } | |
934 | if (addr <= limit) | |
935 | break; | |
936 | prv = limit; | |
937 | } | |
938 | ch_way = TAD_CH(reg) + 1; | |
939 | sck_way = TAD_SOCK(reg) + 1; | |
940 | /* | |
941 | * FIXME: Is it right to always use channel 0 for offsets? | |
942 | */ | |
943 | pci_read_config_dword(pvt->pci_tad[0], | |
944 | tad_ch_nilv_offset[n_tads], | |
945 | &tad_offset); | |
946 | ||
947 | if (ch_way == 3) | |
948 | idx = addr >> 6; | |
949 | else | |
950 | idx = addr >> (6 + sck_way); | |
951 | idx = idx % ch_way; | |
952 | ||
953 | /* | |
954 | * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ??? | |
955 | */ | |
956 | switch (idx) { | |
957 | case 0: | |
958 | base_ch = TAD_TGT0(reg); | |
959 | break; | |
960 | case 1: | |
961 | base_ch = TAD_TGT1(reg); | |
962 | break; | |
963 | case 2: | |
964 | base_ch = TAD_TGT2(reg); | |
965 | break; | |
966 | case 3: | |
967 | base_ch = TAD_TGT3(reg); | |
968 | break; | |
969 | default: | |
970 | sprintf(msg, "Can't discover the TAD target"); | |
eebf11a0 MCC |
971 | return -EINVAL; |
972 | } | |
973 | *channel_mask = 1 << base_ch; | |
974 | ||
975 | if (pvt->is_mirrored) { | |
976 | *channel_mask |= 1 << ((base_ch + 2) % 4); | |
977 | switch(ch_way) { | |
978 | case 2: | |
979 | case 4: | |
980 | sck_xch = 1 << sck_way * (ch_way >> 1); | |
981 | break; | |
982 | default: | |
983 | sprintf(msg, "Invalid mirror set. Can't decode addr"); | |
eebf11a0 MCC |
984 | return -EINVAL; |
985 | } | |
986 | } else | |
987 | sck_xch = (1 << sck_way) * ch_way; | |
988 | ||
989 | if (pvt->is_lockstep) | |
990 | *channel_mask |= 1 << ((base_ch + 1) % 4); | |
991 | ||
992 | offset = TAD_OFFSET(tad_offset); | |
993 | ||
956b9ba1 JP |
994 | edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", |
995 | n_tads, | |
996 | addr, | |
997 | limit, | |
998 | (u32)TAD_SOCK(reg), | |
999 | ch_way, | |
1000 | offset, | |
1001 | idx, | |
1002 | base_ch, | |
1003 | *channel_mask); | |
eebf11a0 MCC |
1004 | |
1005 | /* Calculate channel address */ | |
1006 | /* Remove the TAD offset */ | |
1007 | ||
1008 | if (offset > addr) { | |
1009 | sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!", | |
1010 | offset, addr); | |
eebf11a0 MCC |
1011 | return -EINVAL; |
1012 | } | |
1013 | addr -= offset; | |
1014 | /* Store the low bits [0:6] of the addr */ | |
1015 | ch_addr = addr & 0x7f; | |
1016 | /* Remove socket wayness and remove 6 bits */ | |
1017 | addr >>= 6; | |
5b889e37 | 1018 | addr = div_u64(addr, sck_xch); |
eebf11a0 MCC |
1019 | #if 0 |
1020 | /* Divide by channel way */ | |
1021 | addr = addr / ch_way; | |
1022 | #endif | |
1023 | /* Recover the last 6 bits */ | |
1024 | ch_addr |= addr << 6; | |
1025 | ||
1026 | /* | |
1027 | * Step 3) Decode rank | |
1028 | */ | |
1029 | for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) { | |
1030 | pci_read_config_dword(pvt->pci_tad[base_ch], | |
1031 | rir_way_limit[n_rir], | |
1032 | ®); | |
1033 | ||
1034 | if (!IS_RIR_VALID(reg)) | |
1035 | continue; | |
1036 | ||
1037 | limit = RIR_LIMIT(reg); | |
5b889e37 | 1038 | mb = div_u64_rem(limit >> 20, 1000, &kb); |
956b9ba1 JP |
1039 | edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", |
1040 | n_rir, | |
1041 | mb, kb, | |
1042 | limit, | |
1043 | 1 << RIR_WAY(reg)); | |
eebf11a0 MCC |
1044 | if (ch_addr <= limit) |
1045 | break; | |
1046 | } | |
1047 | if (n_rir == MAX_RIR_RANGES) { | |
1048 | sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx", | |
1049 | ch_addr); | |
eebf11a0 MCC |
1050 | return -EINVAL; |
1051 | } | |
1052 | rir_way = RIR_WAY(reg); | |
1053 | if (pvt->is_close_pg) | |
1054 | idx = (ch_addr >> 6); | |
1055 | else | |
1056 | idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */ | |
1057 | idx %= 1 << rir_way; | |
1058 | ||
1059 | pci_read_config_dword(pvt->pci_tad[base_ch], | |
1060 | rir_offset[n_rir][idx], | |
1061 | ®); | |
1062 | *rank = RIR_RNK_TGT(reg); | |
1063 | ||
956b9ba1 JP |
1064 | edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", |
1065 | n_rir, | |
1066 | ch_addr, | |
1067 | limit, | |
1068 | rir_way, | |
1069 | idx); | |
eebf11a0 MCC |
1070 | |
1071 | return 0; | |
1072 | } | |
1073 | ||
1074 | /**************************************************************************** | |
1075 | Device initialization routines: put/get, init/exit | |
1076 | ****************************************************************************/ | |
1077 | ||
1078 | /* | |
1079 | * sbridge_put_all_devices 'put' all the devices that we have | |
1080 | * reserved via 'get' | |
1081 | */ | |
1082 | static void sbridge_put_devices(struct sbridge_dev *sbridge_dev) | |
1083 | { | |
1084 | int i; | |
1085 | ||
956b9ba1 | 1086 | edac_dbg(0, "\n"); |
eebf11a0 MCC |
1087 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
1088 | struct pci_dev *pdev = sbridge_dev->pdev[i]; | |
1089 | if (!pdev) | |
1090 | continue; | |
956b9ba1 JP |
1091 | edac_dbg(0, "Removing dev %02x:%02x.%d\n", |
1092 | pdev->bus->number, | |
1093 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
eebf11a0 MCC |
1094 | pci_dev_put(pdev); |
1095 | } | |
1096 | } | |
1097 | ||
1098 | static void sbridge_put_all_devices(void) | |
1099 | { | |
1100 | struct sbridge_dev *sbridge_dev, *tmp; | |
1101 | ||
1102 | list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) { | |
1103 | sbridge_put_devices(sbridge_dev); | |
1104 | free_sbridge_dev(sbridge_dev); | |
1105 | } | |
1106 | } | |
1107 | ||
eebf11a0 MCC |
1108 | static int sbridge_get_onedevice(struct pci_dev **prev, |
1109 | u8 *num_mc, | |
1110 | const struct pci_id_table *table, | |
1111 | const unsigned devno) | |
1112 | { | |
1113 | struct sbridge_dev *sbridge_dev; | |
1114 | const struct pci_id_descr *dev_descr = &table->descr[devno]; | |
1115 | ||
1116 | struct pci_dev *pdev = NULL; | |
1117 | u8 bus = 0; | |
1118 | ||
1119 | sbridge_printk(KERN_INFO, | |
1120 | "Seeking for: dev %02x.%d PCI ID %04x:%04x\n", | |
1121 | dev_descr->dev, dev_descr->func, | |
1122 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
1123 | ||
1124 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1125 | dev_descr->dev_id, *prev); | |
1126 | ||
1127 | if (!pdev) { | |
1128 | if (*prev) { | |
1129 | *prev = pdev; | |
1130 | return 0; | |
1131 | } | |
1132 | ||
1133 | if (dev_descr->optional) | |
1134 | return 0; | |
1135 | ||
1136 | if (devno == 0) | |
1137 | return -ENODEV; | |
1138 | ||
1139 | sbridge_printk(KERN_INFO, | |
1140 | "Device not found: dev %02x.%d PCI ID %04x:%04x\n", | |
1141 | dev_descr->dev, dev_descr->func, | |
1142 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
1143 | ||
1144 | /* End of list, leave */ | |
1145 | return -ENODEV; | |
1146 | } | |
1147 | bus = pdev->bus->number; | |
1148 | ||
1149 | sbridge_dev = get_sbridge_dev(bus); | |
1150 | if (!sbridge_dev) { | |
1151 | sbridge_dev = alloc_sbridge_dev(bus, table); | |
1152 | if (!sbridge_dev) { | |
1153 | pci_dev_put(pdev); | |
1154 | return -ENOMEM; | |
1155 | } | |
1156 | (*num_mc)++; | |
1157 | } | |
1158 | ||
1159 | if (sbridge_dev->pdev[devno]) { | |
1160 | sbridge_printk(KERN_ERR, | |
1161 | "Duplicated device for " | |
1162 | "dev %02x:%d.%d PCI ID %04x:%04x\n", | |
1163 | bus, dev_descr->dev, dev_descr->func, | |
1164 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
1165 | pci_dev_put(pdev); | |
1166 | return -ENODEV; | |
1167 | } | |
1168 | ||
1169 | sbridge_dev->pdev[devno] = pdev; | |
1170 | ||
1171 | /* Sanity check */ | |
1172 | if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev || | |
1173 | PCI_FUNC(pdev->devfn) != dev_descr->func)) { | |
1174 | sbridge_printk(KERN_ERR, | |
1175 | "Device PCI ID %04x:%04x " | |
1176 | "has dev %02x:%d.%d instead of dev %02x:%02x.%d\n", | |
1177 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id, | |
1178 | bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
1179 | bus, dev_descr->dev, dev_descr->func); | |
1180 | return -ENODEV; | |
1181 | } | |
1182 | ||
1183 | /* Be sure that the device is enabled */ | |
1184 | if (unlikely(pci_enable_device(pdev) < 0)) { | |
1185 | sbridge_printk(KERN_ERR, | |
1186 | "Couldn't enable " | |
1187 | "dev %02x:%d.%d PCI ID %04x:%04x\n", | |
1188 | bus, dev_descr->dev, dev_descr->func, | |
1189 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
1190 | return -ENODEV; | |
1191 | } | |
1192 | ||
956b9ba1 JP |
1193 | edac_dbg(0, "Detected dev %02x:%d.%d PCI ID %04x:%04x\n", |
1194 | bus, dev_descr->dev, dev_descr->func, | |
1195 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
eebf11a0 MCC |
1196 | |
1197 | /* | |
1198 | * As stated on drivers/pci/search.c, the reference count for | |
1199 | * @from is always decremented if it is not %NULL. So, as we need | |
1200 | * to get all devices up to null, we need to do a get for the device | |
1201 | */ | |
1202 | pci_dev_get(pdev); | |
1203 | ||
1204 | *prev = pdev; | |
1205 | ||
1206 | return 0; | |
1207 | } | |
1208 | ||
5153a0f9 AR |
1209 | /* |
1210 | * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's | |
1211 | * device/functions we want to reference for this driver. | |
1212 | * Need to 'get' device 16 func 1 and func 2. | |
1213 | * @num_mc: pointer to the memory controllers count, to be incremented in case | |
1214 | * of success. | |
1215 | * @table: model specific table | |
1216 | * | |
1217 | * returns 0 in case of success or error code | |
1218 | */ | |
1219 | static int sbridge_get_all_devices(u8 *num_mc, | |
1220 | const struct pci_id_table *table) | |
eebf11a0 MCC |
1221 | { |
1222 | int i, rc; | |
1223 | struct pci_dev *pdev = NULL; | |
eebf11a0 MCC |
1224 | |
1225 | while (table && table->descr) { | |
1226 | for (i = 0; i < table->n_devs; i++) { | |
1227 | pdev = NULL; | |
1228 | do { | |
1229 | rc = sbridge_get_onedevice(&pdev, num_mc, | |
1230 | table, i); | |
1231 | if (rc < 0) { | |
1232 | if (i == 0) { | |
1233 | i = table->n_devs; | |
1234 | break; | |
1235 | } | |
1236 | sbridge_put_all_devices(); | |
1237 | return -ENODEV; | |
1238 | } | |
1239 | } while (pdev); | |
1240 | } | |
1241 | table++; | |
1242 | } | |
1243 | ||
1244 | return 0; | |
1245 | } | |
1246 | ||
1247 | static int mci_bind_devs(struct mem_ctl_info *mci, | |
1248 | struct sbridge_dev *sbridge_dev) | |
1249 | { | |
1250 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1251 | struct pci_dev *pdev; | |
1252 | int i, func, slot; | |
1253 | ||
1254 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
1255 | pdev = sbridge_dev->pdev[i]; | |
1256 | if (!pdev) | |
1257 | continue; | |
1258 | slot = PCI_SLOT(pdev->devfn); | |
1259 | func = PCI_FUNC(pdev->devfn); | |
1260 | switch (slot) { | |
1261 | case 12: | |
1262 | switch (func) { | |
1263 | case 6: | |
1264 | pvt->pci_sad0 = pdev; | |
1265 | break; | |
1266 | case 7: | |
1267 | pvt->pci_sad1 = pdev; | |
1268 | break; | |
1269 | default: | |
1270 | goto error; | |
1271 | } | |
1272 | break; | |
1273 | case 13: | |
1274 | switch (func) { | |
1275 | case 6: | |
5f8a1b8a | 1276 | pvt->pci_br0 = pdev; |
eebf11a0 MCC |
1277 | break; |
1278 | default: | |
1279 | goto error; | |
1280 | } | |
1281 | break; | |
1282 | case 14: | |
1283 | switch (func) { | |
1284 | case 0: | |
1285 | pvt->pci_ha0 = pdev; | |
1286 | break; | |
1287 | default: | |
1288 | goto error; | |
1289 | } | |
1290 | break; | |
1291 | case 15: | |
1292 | switch (func) { | |
1293 | case 0: | |
1294 | pvt->pci_ta = pdev; | |
1295 | break; | |
1296 | case 1: | |
1297 | pvt->pci_ras = pdev; | |
1298 | break; | |
1299 | case 2: | |
1300 | case 3: | |
1301 | case 4: | |
1302 | case 5: | |
1303 | pvt->pci_tad[func - 2] = pdev; | |
1304 | break; | |
1305 | default: | |
1306 | goto error; | |
1307 | } | |
1308 | break; | |
1309 | case 17: | |
1310 | switch (func) { | |
1311 | case 0: | |
1312 | pvt->pci_ddrio = pdev; | |
1313 | break; | |
1314 | default: | |
1315 | goto error; | |
1316 | } | |
1317 | break; | |
1318 | default: | |
1319 | goto error; | |
1320 | } | |
1321 | ||
956b9ba1 JP |
1322 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", |
1323 | sbridge_dev->bus, | |
1324 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
1325 | pdev); | |
eebf11a0 MCC |
1326 | } |
1327 | ||
1328 | /* Check if everything were registered */ | |
1329 | if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 || | |
de4772c6 | 1330 | !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta) |
eebf11a0 MCC |
1331 | goto enodev; |
1332 | ||
1333 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1334 | if (!pvt->pci_tad[i]) | |
1335 | goto enodev; | |
1336 | } | |
1337 | return 0; | |
1338 | ||
1339 | enodev: | |
1340 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
1341 | return -ENODEV; | |
1342 | ||
1343 | error: | |
1344 | sbridge_printk(KERN_ERR, "Device %d, function %d " | |
1345 | "is out of the expected range\n", | |
1346 | slot, func); | |
1347 | return -EINVAL; | |
1348 | } | |
1349 | ||
1350 | /**************************************************************************** | |
1351 | Error check routines | |
1352 | ****************************************************************************/ | |
1353 | ||
1354 | /* | |
1355 | * While Sandy Bridge has error count registers, SMI BIOS read values from | |
1356 | * and resets the counters. So, they are not reliable for the OS to read | |
1357 | * from them. So, we have no option but to just trust on whatever MCE is | |
1358 | * telling us about the errors. | |
1359 | */ | |
1360 | static void sbridge_mce_output_error(struct mem_ctl_info *mci, | |
1361 | const struct mce *m) | |
1362 | { | |
1363 | struct mem_ctl_info *new_mci; | |
1364 | struct sbridge_pvt *pvt = mci->pvt_info; | |
c36e3e77 | 1365 | enum hw_event_mc_err_type tp_event; |
e17a2f42 | 1366 | char *type, *optype, msg[256]; |
eebf11a0 MCC |
1367 | bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); |
1368 | bool overflow = GET_BITFIELD(m->status, 62, 62); | |
1369 | bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); | |
1370 | bool recoverable = GET_BITFIELD(m->status, 56, 56); | |
1371 | u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); | |
1372 | u32 mscod = GET_BITFIELD(m->status, 16, 31); | |
1373 | u32 errcode = GET_BITFIELD(m->status, 0, 15); | |
1374 | u32 channel = GET_BITFIELD(m->status, 0, 3); | |
1375 | u32 optypenum = GET_BITFIELD(m->status, 4, 6); | |
1376 | long channel_mask, first_channel; | |
1377 | u8 rank, socket; | |
c36e3e77 | 1378 | int rc, dimm; |
e17a2f42 | 1379 | char *area_type = NULL; |
eebf11a0 | 1380 | |
c36e3e77 MCC |
1381 | if (uncorrected_error) { |
1382 | if (ripv) { | |
1383 | type = "FATAL"; | |
1384 | tp_event = HW_EVENT_ERR_FATAL; | |
1385 | } else { | |
1386 | type = "NON_FATAL"; | |
1387 | tp_event = HW_EVENT_ERR_UNCORRECTED; | |
1388 | } | |
1389 | } else { | |
1390 | type = "CORRECTED"; | |
1391 | tp_event = HW_EVENT_ERR_CORRECTED; | |
1392 | } | |
eebf11a0 MCC |
1393 | |
1394 | /* | |
15ed103a | 1395 | * According with Table 15-9 of the Intel Architecture spec vol 3A, |
eebf11a0 MCC |
1396 | * memory errors should fit in this mask: |
1397 | * 000f 0000 1mmm cccc (binary) | |
1398 | * where: | |
1399 | * f = Correction Report Filtering Bit. If 1, subsequent errors | |
1400 | * won't be shown | |
1401 | * mmm = error type | |
1402 | * cccc = channel | |
1403 | * If the mask doesn't match, report an error to the parsing logic | |
1404 | */ | |
1405 | if (! ((errcode & 0xef80) == 0x80)) { | |
1406 | optype = "Can't parse: it is not a mem"; | |
1407 | } else { | |
1408 | switch (optypenum) { | |
1409 | case 0: | |
c36e3e77 | 1410 | optype = "generic undef request error"; |
eebf11a0 MCC |
1411 | break; |
1412 | case 1: | |
c36e3e77 | 1413 | optype = "memory read error"; |
eebf11a0 MCC |
1414 | break; |
1415 | case 2: | |
c36e3e77 | 1416 | optype = "memory write error"; |
eebf11a0 MCC |
1417 | break; |
1418 | case 3: | |
c36e3e77 | 1419 | optype = "addr/cmd error"; |
eebf11a0 MCC |
1420 | break; |
1421 | case 4: | |
c36e3e77 | 1422 | optype = "memory scrubbing error"; |
eebf11a0 MCC |
1423 | break; |
1424 | default: | |
1425 | optype = "reserved"; | |
1426 | break; | |
1427 | } | |
1428 | } | |
1429 | ||
1430 | rc = get_memory_error_data(mci, m->addr, &socket, | |
e17a2f42 | 1431 | &channel_mask, &rank, &area_type, msg); |
eebf11a0 | 1432 | if (rc < 0) |
c36e3e77 | 1433 | goto err_parsing; |
eebf11a0 MCC |
1434 | new_mci = get_mci_for_node_id(socket); |
1435 | if (!new_mci) { | |
c36e3e77 MCC |
1436 | strcpy(msg, "Error: socket got corrupted!"); |
1437 | goto err_parsing; | |
eebf11a0 MCC |
1438 | } |
1439 | mci = new_mci; | |
1440 | pvt = mci->pvt_info; | |
1441 | ||
1442 | first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); | |
1443 | ||
1444 | if (rank < 4) | |
1445 | dimm = 0; | |
1446 | else if (rank < 8) | |
1447 | dimm = 1; | |
1448 | else | |
1449 | dimm = 2; | |
1450 | ||
eebf11a0 MCC |
1451 | |
1452 | /* | |
e17a2f42 MCC |
1453 | * FIXME: On some memory configurations (mirror, lockstep), the |
1454 | * Memory Controller can't point the error to a single DIMM. The | |
1455 | * EDAC core should be handling the channel mask, in order to point | |
1456 | * to the group of dimm's where the error may be happening. | |
eebf11a0 | 1457 | */ |
c36e3e77 | 1458 | snprintf(msg, sizeof(msg), |
c1053839 | 1459 | "%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d", |
e17a2f42 MCC |
1460 | overflow ? " OVERFLOW" : "", |
1461 | (uncorrected_error && recoverable) ? " recoverable" : "", | |
1462 | area_type, | |
1463 | mscod, errcode, | |
1464 | socket, | |
1465 | channel_mask, | |
1466 | rank); | |
eebf11a0 | 1467 | |
956b9ba1 | 1468 | edac_dbg(0, "%s\n", msg); |
eebf11a0 | 1469 | |
c36e3e77 MCC |
1470 | /* FIXME: need support for channel mask */ |
1471 | ||
eebf11a0 | 1472 | /* Call the helper to output message */ |
c1053839 | 1473 | edac_mc_handle_error(tp_event, mci, core_err_cnt, |
c36e3e77 MCC |
1474 | m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, |
1475 | channel, dimm, -1, | |
03f7eae8 | 1476 | optype, msg); |
c36e3e77 MCC |
1477 | return; |
1478 | err_parsing: | |
c1053839 | 1479 | edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, |
c36e3e77 | 1480 | -1, -1, -1, |
03f7eae8 | 1481 | msg, ""); |
eebf11a0 | 1482 | |
eebf11a0 MCC |
1483 | } |
1484 | ||
1485 | /* | |
1486 | * sbridge_check_error Retrieve and process errors reported by the | |
1487 | * hardware. Called by the Core module. | |
1488 | */ | |
1489 | static void sbridge_check_error(struct mem_ctl_info *mci) | |
1490 | { | |
1491 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1492 | int i; | |
1493 | unsigned count = 0; | |
1494 | struct mce *m; | |
1495 | ||
1496 | /* | |
1497 | * MCE first step: Copy all mce errors into a temporary buffer | |
1498 | * We use a double buffering here, to reduce the risk of | |
1499 | * loosing an error. | |
1500 | */ | |
1501 | smp_rmb(); | |
1502 | count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in) | |
1503 | % MCE_LOG_LEN; | |
1504 | if (!count) | |
1505 | return; | |
1506 | ||
1507 | m = pvt->mce_outentry; | |
1508 | if (pvt->mce_in + count > MCE_LOG_LEN) { | |
1509 | unsigned l = MCE_LOG_LEN - pvt->mce_in; | |
1510 | ||
1511 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l); | |
1512 | smp_wmb(); | |
1513 | pvt->mce_in = 0; | |
1514 | count -= l; | |
1515 | m += l; | |
1516 | } | |
1517 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count); | |
1518 | smp_wmb(); | |
1519 | pvt->mce_in += count; | |
1520 | ||
1521 | smp_rmb(); | |
1522 | if (pvt->mce_overrun) { | |
1523 | sbridge_printk(KERN_ERR, "Lost %d memory errors\n", | |
1524 | pvt->mce_overrun); | |
1525 | smp_wmb(); | |
1526 | pvt->mce_overrun = 0; | |
1527 | } | |
1528 | ||
1529 | /* | |
1530 | * MCE second step: parse errors and display | |
1531 | */ | |
1532 | for (i = 0; i < count; i++) | |
1533 | sbridge_mce_output_error(mci, &pvt->mce_outentry[i]); | |
1534 | } | |
1535 | ||
1536 | /* | |
1537 | * sbridge_mce_check_error Replicates mcelog routine to get errors | |
1538 | * This routine simply queues mcelog errors, and | |
1539 | * return. The error itself should be handled later | |
1540 | * by sbridge_check_error. | |
1541 | * WARNING: As this routine should be called at NMI time, extra care should | |
1542 | * be taken to avoid deadlocks, and to be as fast as possible. | |
1543 | */ | |
3d78c9af MCC |
1544 | static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, |
1545 | void *data) | |
eebf11a0 | 1546 | { |
3d78c9af MCC |
1547 | struct mce *mce = (struct mce *)data; |
1548 | struct mem_ctl_info *mci; | |
1549 | struct sbridge_pvt *pvt; | |
1550 | ||
1551 | mci = get_mci_for_node_id(mce->socketid); | |
1552 | if (!mci) | |
1553 | return NOTIFY_BAD; | |
1554 | pvt = mci->pvt_info; | |
eebf11a0 MCC |
1555 | |
1556 | /* | |
1557 | * Just let mcelog handle it if the error is | |
1558 | * outside the memory controller. A memory error | |
1559 | * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. | |
1560 | * bit 12 has an special meaning. | |
1561 | */ | |
1562 | if ((mce->status & 0xefff) >> 7 != 1) | |
3d78c9af | 1563 | return NOTIFY_DONE; |
eebf11a0 MCC |
1564 | |
1565 | printk("sbridge: HANDLING MCE MEMORY ERROR\n"); | |
1566 | ||
1567 | printk("CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", | |
1568 | mce->extcpu, mce->mcgstatus, mce->bank, mce->status); | |
1569 | printk("TSC %llx ", mce->tsc); | |
1570 | printk("ADDR %llx ", mce->addr); | |
1571 | printk("MISC %llx ", mce->misc); | |
1572 | ||
1573 | printk("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", | |
1574 | mce->cpuvendor, mce->cpuid, mce->time, | |
1575 | mce->socketid, mce->apicid); | |
1576 | ||
eebf11a0 MCC |
1577 | /* Only handle if it is the right mc controller */ |
1578 | if (cpu_data(mce->cpu).phys_proc_id != pvt->sbridge_dev->mc) | |
3d78c9af | 1579 | return NOTIFY_DONE; |
eebf11a0 MCC |
1580 | |
1581 | smp_rmb(); | |
1582 | if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { | |
1583 | smp_wmb(); | |
1584 | pvt->mce_overrun++; | |
3d78c9af | 1585 | return NOTIFY_DONE; |
eebf11a0 MCC |
1586 | } |
1587 | ||
1588 | /* Copy memory error at the ringbuffer */ | |
1589 | memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce)); | |
1590 | smp_wmb(); | |
1591 | pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN; | |
1592 | ||
1593 | /* Handle fatal errors immediately */ | |
1594 | if (mce->mcgstatus & 1) | |
1595 | sbridge_check_error(mci); | |
1596 | ||
1597 | /* Advice mcelog that the error were handled */ | |
3d78c9af | 1598 | return NOTIFY_STOP; |
eebf11a0 MCC |
1599 | } |
1600 | ||
3d78c9af MCC |
1601 | static struct notifier_block sbridge_mce_dec = { |
1602 | .notifier_call = sbridge_mce_check_error, | |
1603 | }; | |
1604 | ||
eebf11a0 MCC |
1605 | /**************************************************************************** |
1606 | EDAC register/unregister logic | |
1607 | ****************************************************************************/ | |
1608 | ||
1609 | static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) | |
1610 | { | |
1611 | struct mem_ctl_info *mci = sbridge_dev->mci; | |
1612 | struct sbridge_pvt *pvt; | |
1613 | ||
1614 | if (unlikely(!mci || !mci->pvt_info)) { | |
956b9ba1 | 1615 | edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); |
eebf11a0 MCC |
1616 | |
1617 | sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); | |
1618 | return; | |
1619 | } | |
1620 | ||
1621 | pvt = mci->pvt_info; | |
1622 | ||
956b9ba1 JP |
1623 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
1624 | mci, &sbridge_dev->pdev[0]->dev); | |
eebf11a0 | 1625 | |
eebf11a0 | 1626 | /* Remove MC sysfs nodes */ |
fd687502 | 1627 | edac_mc_del_mc(mci->pdev); |
eebf11a0 | 1628 | |
956b9ba1 | 1629 | edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); |
eebf11a0 MCC |
1630 | kfree(mci->ctl_name); |
1631 | edac_mc_free(mci); | |
1632 | sbridge_dev->mci = NULL; | |
1633 | } | |
1634 | ||
1635 | static int sbridge_register_mci(struct sbridge_dev *sbridge_dev) | |
1636 | { | |
1637 | struct mem_ctl_info *mci; | |
c36e3e77 | 1638 | struct edac_mc_layer layers[2]; |
eebf11a0 | 1639 | struct sbridge_pvt *pvt; |
c36e3e77 | 1640 | int rc; |
eebf11a0 MCC |
1641 | |
1642 | /* Check the number of active and not disabled channels */ | |
c36e3e77 | 1643 | rc = check_if_ecc_is_active(sbridge_dev->bus); |
eebf11a0 MCC |
1644 | if (unlikely(rc < 0)) |
1645 | return rc; | |
1646 | ||
1647 | /* allocate a new MC control structure */ | |
c36e3e77 MCC |
1648 | layers[0].type = EDAC_MC_LAYER_CHANNEL; |
1649 | layers[0].size = NUM_CHANNELS; | |
1650 | layers[0].is_virt_csrow = false; | |
1651 | layers[1].type = EDAC_MC_LAYER_SLOT; | |
1652 | layers[1].size = MAX_DIMMS; | |
1653 | layers[1].is_virt_csrow = true; | |
ca0907b9 | 1654 | mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, |
c36e3e77 MCC |
1655 | sizeof(*pvt)); |
1656 | ||
eebf11a0 MCC |
1657 | if (unlikely(!mci)) |
1658 | return -ENOMEM; | |
1659 | ||
956b9ba1 JP |
1660 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
1661 | mci, &sbridge_dev->pdev[0]->dev); | |
eebf11a0 MCC |
1662 | |
1663 | pvt = mci->pvt_info; | |
1664 | memset(pvt, 0, sizeof(*pvt)); | |
1665 | ||
1666 | /* Associate sbridge_dev and mci for future usage */ | |
1667 | pvt->sbridge_dev = sbridge_dev; | |
1668 | sbridge_dev->mci = mci; | |
1669 | ||
1670 | mci->mtype_cap = MEM_FLAG_DDR3; | |
1671 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
1672 | mci->edac_cap = EDAC_FLAG_NONE; | |
1673 | mci->mod_name = "sbridge_edac.c"; | |
1674 | mci->mod_ver = SBRIDGE_REVISION; | |
1675 | mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx); | |
1676 | mci->dev_name = pci_name(sbridge_dev->pdev[0]); | |
1677 | mci->ctl_page_to_phys = NULL; | |
fb79a509 | 1678 | pvt->info.get_tolm = sbridge_get_tolm; |
8fd6a43a | 1679 | pvt->info.get_tohm = sbridge_get_tohm; |
464f1d82 AR |
1680 | pvt->info.dram_rule = sbridge_dram_rule; |
1681 | pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); | |
ef1ce51e AR |
1682 | pvt->info.interleave_list = sbridge_interleave_list; |
1683 | pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list); | |
cc311991 | 1684 | pvt->info.interleave_pkg = sbridge_interleave_pkg; |
eebf11a0 MCC |
1685 | |
1686 | /* Set the function pointer to an actual operation function */ | |
1687 | mci->edac_check = sbridge_check_error; | |
1688 | ||
1689 | /* Store pci devices at mci for faster access */ | |
1690 | rc = mci_bind_devs(mci, sbridge_dev); | |
1691 | if (unlikely(rc < 0)) | |
1692 | goto fail0; | |
1693 | ||
1694 | /* Get dimm basic config and the memory layout */ | |
1695 | get_dimm_config(mci); | |
1696 | get_memory_layout(mci); | |
1697 | ||
1698 | /* record ptr to the generic device */ | |
fd687502 | 1699 | mci->pdev = &sbridge_dev->pdev[0]->dev; |
eebf11a0 MCC |
1700 | |
1701 | /* add this new MC control structure to EDAC's list of MCs */ | |
1702 | if (unlikely(edac_mc_add_mc(mci))) { | |
956b9ba1 | 1703 | edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); |
eebf11a0 MCC |
1704 | rc = -EINVAL; |
1705 | goto fail0; | |
1706 | } | |
1707 | ||
eebf11a0 | 1708 | return 0; |
eebf11a0 MCC |
1709 | |
1710 | fail0: | |
1711 | kfree(mci->ctl_name); | |
1712 | edac_mc_free(mci); | |
1713 | sbridge_dev->mci = NULL; | |
1714 | return rc; | |
1715 | } | |
1716 | ||
1717 | /* | |
1718 | * sbridge_probe Probe for ONE instance of device to see if it is | |
1719 | * present. | |
1720 | * return: | |
1721 | * 0 for FOUND a device | |
1722 | * < 0 for error code | |
1723 | */ | |
1724 | ||
9b3c6e85 | 1725 | static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
eebf11a0 MCC |
1726 | { |
1727 | int rc; | |
1728 | u8 mc, num_mc = 0; | |
1729 | struct sbridge_dev *sbridge_dev; | |
1730 | ||
1731 | /* get the pci devices we want to reserve for our use */ | |
1732 | mutex_lock(&sbridge_edac_lock); | |
1733 | ||
1734 | /* | |
1735 | * All memory controllers are allocated at the first pass. | |
1736 | */ | |
1737 | if (unlikely(probed >= 1)) { | |
1738 | mutex_unlock(&sbridge_edac_lock); | |
1739 | return -ENODEV; | |
1740 | } | |
1741 | probed++; | |
1742 | ||
5153a0f9 | 1743 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table); |
eebf11a0 MCC |
1744 | if (unlikely(rc < 0)) |
1745 | goto fail0; | |
1746 | mc = 0; | |
1747 | ||
1748 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
956b9ba1 JP |
1749 | edac_dbg(0, "Registering MC#%d (%d of %d)\n", |
1750 | mc, mc + 1, num_mc); | |
eebf11a0 MCC |
1751 | sbridge_dev->mc = mc++; |
1752 | rc = sbridge_register_mci(sbridge_dev); | |
1753 | if (unlikely(rc < 0)) | |
1754 | goto fail1; | |
1755 | } | |
1756 | ||
1757 | sbridge_printk(KERN_INFO, "Driver loaded.\n"); | |
1758 | ||
1759 | mutex_unlock(&sbridge_edac_lock); | |
1760 | return 0; | |
1761 | ||
1762 | fail1: | |
1763 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) | |
1764 | sbridge_unregister_mci(sbridge_dev); | |
1765 | ||
1766 | sbridge_put_all_devices(); | |
1767 | fail0: | |
1768 | mutex_unlock(&sbridge_edac_lock); | |
1769 | return rc; | |
1770 | } | |
1771 | ||
1772 | /* | |
1773 | * sbridge_remove destructor for one instance of device | |
1774 | * | |
1775 | */ | |
9b3c6e85 | 1776 | static void sbridge_remove(struct pci_dev *pdev) |
eebf11a0 MCC |
1777 | { |
1778 | struct sbridge_dev *sbridge_dev; | |
1779 | ||
956b9ba1 | 1780 | edac_dbg(0, "\n"); |
eebf11a0 MCC |
1781 | |
1782 | /* | |
1783 | * we have a trouble here: pdev value for removal will be wrong, since | |
1784 | * it will point to the X58 register used to detect that the machine | |
1785 | * is a Nehalem or upper design. However, due to the way several PCI | |
1786 | * devices are grouped together to provide MC functionality, we need | |
1787 | * to use a different method for releasing the devices | |
1788 | */ | |
1789 | ||
1790 | mutex_lock(&sbridge_edac_lock); | |
1791 | ||
1792 | if (unlikely(!probed)) { | |
1793 | mutex_unlock(&sbridge_edac_lock); | |
1794 | return; | |
1795 | } | |
1796 | ||
1797 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) | |
1798 | sbridge_unregister_mci(sbridge_dev); | |
1799 | ||
1800 | /* Release PCI resources */ | |
1801 | sbridge_put_all_devices(); | |
1802 | ||
1803 | probed--; | |
1804 | ||
1805 | mutex_unlock(&sbridge_edac_lock); | |
1806 | } | |
1807 | ||
1808 | MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl); | |
1809 | ||
1810 | /* | |
1811 | * sbridge_driver pci_driver structure for this module | |
1812 | * | |
1813 | */ | |
1814 | static struct pci_driver sbridge_driver = { | |
1815 | .name = "sbridge_edac", | |
1816 | .probe = sbridge_probe, | |
9b3c6e85 | 1817 | .remove = sbridge_remove, |
eebf11a0 MCC |
1818 | .id_table = sbridge_pci_tbl, |
1819 | }; | |
1820 | ||
1821 | /* | |
1822 | * sbridge_init Module entry function | |
1823 | * Try to initialize this module for its devices | |
1824 | */ | |
1825 | static int __init sbridge_init(void) | |
1826 | { | |
1827 | int pci_rc; | |
1828 | ||
956b9ba1 | 1829 | edac_dbg(2, "\n"); |
eebf11a0 MCC |
1830 | |
1831 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | |
1832 | opstate_init(); | |
1833 | ||
1834 | pci_rc = pci_register_driver(&sbridge_driver); | |
1835 | ||
e35fca47 CG |
1836 | if (pci_rc >= 0) { |
1837 | mce_register_decode_chain(&sbridge_mce_dec); | |
eebf11a0 | 1838 | return 0; |
e35fca47 | 1839 | } |
eebf11a0 MCC |
1840 | |
1841 | sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n", | |
1842 | pci_rc); | |
1843 | ||
1844 | return pci_rc; | |
1845 | } | |
1846 | ||
1847 | /* | |
1848 | * sbridge_exit() Module exit function | |
1849 | * Unregister the driver | |
1850 | */ | |
1851 | static void __exit sbridge_exit(void) | |
1852 | { | |
956b9ba1 | 1853 | edac_dbg(2, "\n"); |
eebf11a0 | 1854 | pci_unregister_driver(&sbridge_driver); |
e35fca47 | 1855 | mce_unregister_decode_chain(&sbridge_mce_dec); |
eebf11a0 MCC |
1856 | } |
1857 | ||
1858 | module_init(sbridge_init); | |
1859 | module_exit(sbridge_exit); | |
1860 | ||
1861 | module_param(edac_op_state, int, 0444); | |
1862 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); | |
1863 | ||
1864 | MODULE_LICENSE("GPL"); | |
1865 | MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); | |
1866 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); | |
1867 | MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge memory controllers - " | |
1868 | SBRIDGE_REVISION); |